Xilinx User Guide
Xilinx User Guide
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. 20022007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The following table shows the revision history for this document. All revision publications are electronic only (PDF) unless otherwise noted. Version 01/31/02 10/14/02 12/04/02 01/23/03 1.0 2.0 2.1 2.2 (Print Edition.) Initial Xilinx release. (Print Edition.) Updated and reprinted. New Virtex-II Pro family members and packages. Revised I/O support information. Added full support for 3.3V I/O standards PCI-X, LVTTL, and LVCMOS33. Added wire-bond package FG676 for XC2VP20, 30, and 40. New package diagram (Figure 5-66) and pinout diagrams (Figure 5-11 through Figure 5-15). Revised Table 5-6. Removed pinout diagrams and other references for XC2VP40FF1517. Revised material in, and added Figure 4-4 to, section Mixed Voltage Environments, page 298. Clariified explanation of banks 4/5 VCCO settings for configuration vs. operation in section Special VCCO Requirements during Configuration and Readback, page 299. Table 3-37, Table 3-38: Corrected package type FG672 to FF672, and added package type FG676. Deleted (former) Table 3-3, Power-Up Timing Characteristics, and replaced it with a hyperlink to Data Sheet Module 3. Deleted (former) Table 1-5, Multiplier Switching Characteristics, and replaced it with a hyperlink to Data Sheet Module 3. Changed attribute CLOCK_FEEDBACK to CLK_FEEDBACK. Clarifying text added to section Phase Shift Enable - PSEN in Chapter 3. Additional implementation rule added to section DCI in Virtex-II Pro/Virtex-II Pro X Hardware in Chapter 3. Corrections made in command line, key file, and key file command line equivalent in section Creating Keys in Chapter 3. Added device-specific parameters to step 16 of Single Device Configuration Sequence in Chapter 4. Section Master SelectMAP Data Loading in Chapter 4: Corrected maximum frequency for SelectMAP configuration without BUSY handshaking to 5 MHz. Table 4-8: Corrected maximum SelectMAP frequency (FCC_SELECTMAP ) to 50 MHz. Appendix A, BitGen and PROMGen Switches and Options: Updated all commandline options to correlate with development tools and their documentation. Table 3-58: Added numerous LVDS primitives to this table, including new differential termination primitives. Added new section LVDS Input HDL Examples. Changed Figure 3-119 to show internal rather than external differential input termination. Various minor edits. Revision
04/11/03
2.3
www.xilinx.com
Revision Corrected Location Constraints syntax, multiple instances. Added Figure 3-23, page 91 and associated explanatory text. Added HDL code for resetting the DCM after configuration in section External Feedback, page 93. Modified Banking Rules in section DCI in Virtex-II Pro/Virtex-II Pro X Hardware, page 236. Added reference to Answer Record 13012 in section SSTL2_ I_DCI, SSTL2_II_DCI, page 238. Corrected command-line equivalent statements for bitstream encryption key files in section Creating Keys, page 270. Added new section SelectMAP ABORT Sequence and ABORT Recovery, page 316, to section Master SelectMAP Programming Mode. Corrected shading property of GND pin in symbol key, all diagrams, section Pinout Diagrams, page 397. Numerous additional minor edits. Figure 3-59, page 158: Added missing connection between second LUT of Slice 3 and first LUT of Slice 2. Figure 3-72, page 180: Corrected bit numbers on inputs to adder. Section Routing with BlockRAM, page 184 added. Table 3-36, page 202: Added SSO parameters for HSTL18 I/O standards. Figure 3-90, page 215: Correct VREF from 0.75V to 0.9V. Section DCI I/O Buffer Library Components, page 231, added IBUFG_LVDS components to list. Section Location Constraints, page 251: Added constraint on locating a DDR register next to an SDR register using a different clock. Appendix C, Choosing the Battery for VBATT added, with linked reference in section VBATT, page 272. Page 292: added paragraph at end of Introduction to Configuration chapter specifying a fixed voltage tie for mode pins M0-M2, and warning not to toggle these pins during or after configuration. Table 4-2, page 292: Reduced configuration bitstream lengths for all devices by 64 bits. Section Configuration Pins, page 296: Added warning and constraints regarding application of 3.3V signals to dedicated configuration pins. Table 4-3, page 297: Corrected directionality of BUSY/DOUT to Output, INIT_B to Input/Output. Updated with data from XAPP659. Former Table 4-6, Master/Slave Serial Mode Programming Switching, and former Table 4-8, SelectMAP Write Timing Characteristics, removed. See the Virtex-II Pro / Virtex-II Pro X Data Sheet, DC and Switching Characteristics for these and all other timing parameter specifications. Table 4-6, page 302: Corrected FCC_SERIAL from 66 MHz to 50 MHz. Added footnote to Figure 4-9, page 305, and Figure 4-11, page 307, clarifying that DOUT transitions on the falling edge of CCLK. Second paragraph below Figure 4-13, page 311: Corrected maximum no-handshake SelectMAP configuration speed from 5 MHz to 50 MHz. Section Master SelectMAP Data Loading, page 311: Changed wording to emphasize that if RDWR_B is toggled while CS_B is still asserted, a configuration abort will occur.
02/02/04
2.5
www.xilinx.com
Revision Section Express-Style Loading, page 308: Added new text to clarify the sequencing of signals before, during, and after data loading. Page 322: added text to TDO paragraph indicating that pin is open-drain and should be pulled up externally. Table 4-13, page 331: Updated Total No. of Bits column with new numbers. Figure 5-53, page 457; Figure 5-54, page 458; Figure 5-55, page 459; and Figure 5-56, page 460: Corrected banking assignments for pins AB12 and AB31. Now shows these pins in Banks 2 and 7 respectively. Table 5-1, page New Thermal Data Table 5-3: Changed Theta-JC to 0.5C/Watt for all FF packages. Section Crosstalk, page 488: Clarified wording of PCB trace routing guidelines to minimize crosstalk onto VREF lines. Section Digital Clock Managers (DCMs) in Chapter 3: Removed all referrals to CLK2X as an option in implementing a clock feedback loop for the DCM, including: Removed former Figures 3-25, 3-27, and 3-39, which showed schematics of CLK2X feedback implementation. Section Attributes, page 97: Removed section Feedback Input discussing the CLK_FEEDBACK attribute, which was used to designate CLK2X as the feedback clock. Table 3-9, page 114: Removed CLK_FEEDBACK from the table of attributes. Section VHDL and Verilog Instantiation, page 115: Removed BUFG_ CLK2X_SUBM, BUFG_CLK2X_FB_SUBM, and BUFG_PHASE_CLK2X_SUBM from the list of available DCM submodules. Page 179: Added registered multiplier primitive to table Table 3-26, new schematic of both multiplier primitives (Figure 3-71), and explanatory text. Table 3-36, page 202: Added LVPECL_25 and BLVDS_25 to table. Table 3-38, page 206: Added referral to XAPP689 for managing ground bounce. Section DCI I/O Buffer Library Components, page 231: Removed all LVDS_33_DCI and LVDSEXT_33_DCI components from listing. Section Creating a Bidirectional LVDS Buffer, page 264, and Creating an LVPECL Output Buffer, page 267: Added referral to Table 3-36 for SSO guidelines. Section Bitstream Encryption, page 269: Added referral to Appendix C, Choosing the Battery for VBATT. Section Creating Keys (end): Added material discussing use of CBC initial value to safeguard bitstream security. Table 4-3, page 297: Mode pins (M0, M1, M2) not to be connected to 3.3V unless through a 100 resistor. VBATT pin to be connected to GND or VCCAUX when bitstream encryption not used. Section Frame Length Register (FLR), page 333: Added minus one word to the description of the value to be loaded into this register. Former Table 4-3, Power-Up Timing Configuration Signals, removed. See the Virtex-II Pro Platform FPGA Data Sheet, DC and Switching Characteristics for these and all other timing parameter specifications. Section Test Access Port, page 321: Added mention of implementation tool pull-up, pull-down, and float options on TMS and TDI pins. Updated DS026 in Appendix B, Platform Flash Family PROMs to v5.0. Various edits and deletions in Glossary.
04/19/04
2.6
www.xilinx.com
Revision Edits throughout to synchronize/align User Guide with Data Sheet Table 1. Updated DS026 in Appendix B, Platform Flash Family PROMs to v5.0. Various edits and deletions in Glossary. Edits throughout to synchronize/align User Guide with Data Sheet Table 1.
06/02/04
2.6.1
Table 4-3, page 297: Corrected BUSY/DOUT from Input to Output. Corrected INIT_B from Input to Input/Output. Removed redundant entries for CCLK and PROG_B. Revised throughout with updated tables, text, pinout diagrams, and hyperlinks to include two new devices, Virtex-II Pro X XC2VPX20 and XC2VPX70, which feature the RocketIO X 10.3125 Gb/s MGT. Revised throughout with updated tables, text, and package diagrams to include new Pb-free packaging options FGG256, FGG456, and FGG676. Section Frequency Synthesized Clock Output - CLKFX, page 101: Added text indicating no CLKFX phase alignment when the CLKIN frequency is below 24 Mhz. Section Phase Shift Characteristics, page 105: Added substantial detailed material related to calculating and controlling the desired phase shift. Table 3-29, page 187: Added clarifying example to Footnote (2) regarding GTL/GTLP VCCO lower limit. Section Daisy-Chain Configuration, page 303: Revised text to clarify daisy-chain options for strings of different Xilinx FPGA devices. Section RDWR_B, page 305: Revised text to clarify the status of the data bus when RDWR_B is High and Low. Table 4-16, page 331: Revised step 5 to give XC2VP2 its own TDI code, and step 6 to correct the TDI code from 1 to 0. Corrected Footnote (1) to say data and instruction. Chapter 4, Configuration: This chapter has been expanded and completely updated with new material. Since most of the material is newly written, specific changes in this chapter are not recorded in the Revision History. Section BUFG Exclusivity, page 75: Corrected numbering of exclusive buffer pairs. Figure 3-23, page 91: Added note on when to reset the DCM. Section Fixed-Mode Phase Shifting in Certain Virtex-II Pro Devices, page 106: Added link to Solution Record 13349. Table 3-9, page 114: From Description for CLKIN_DIVIDE_BY_2, removed text specifying an upper frequency limit for using this attribute to divide the DCM input clock by 2. Section Embedded Multipliers, page 178: Deleted subsection Two Multipliers in a Single Primitive. Deleted references to DUAL_MULT_* templates. Section Output Drive Source Voltage (VCCO) Pins, page 199: Added text recommending that VCCO be powered for all I/O standards. Table 3-36, page 202: Corrected number of SSOs for the following standards: GTL_DCI, GTLP_DCI, HSTLII_DCI, SSTL18_II, LVPECL_25, BLVDS_25. Added the following standards: DIFF_HSTL_II, DIFF_HSTL_II_DCI, DIFF_HSTL_II_18, DIFF_HSTL_II_18_ DCI, DIFF_SSTL_II, DIFF_SSTL_II_DCI, DIFF_SSTL_II_18, DIFF_SSTL_II_18_ DCI. Section DCI in Virtex-II Pro/Virtex-II Pro X Hardware, page 236: Added step 8. Added Figure 3-109, page 242.
08/05/04
3.0
03/07/05
4.0
www.xilinx.com
Revision Code template DDR_input.v, page 253: Removed assign data_out = q1 & q2 just before endmodule. Section LVDS I/O, page 258: Replaced Table 3-58, Available LVDS Primitives with new Table 3-58, Available LVDS Standards. Section Loading Encrypted Bitstreams, page 272: Corrected reference to JTAG JSTART instruction to JTAG JPROG_B. Added new section Temperature-Sensing Diode (DXP/DXN), page 273. Corrected pinout diagram FF672 Composite Pinout Diagram (XC2VP4) (Figure 5-19, page 420). Previously, this figure had shown the composite pinout diagram for the FF672/XC2VP7 device. Section Design Examples, page 521 (Appendix C): Deleted text and illustration that incorrectly suggested different battery voltage compliance requirements for Virtex-II and Virtex-II Pro BBRAM power pin. Added new section Cascading DCMs, page 95. Feedback Clock Input CLKFB, page 96: Added information regarding when CLK_FEEDBACK must be set to NONE. Reset Input RST, page 101 andReset Input RST, page 111 : Corrected hold time from 2 ns to 3 clock cycles. Port Signals, page 108: Corrected paragraph regarding DUTY_CYCLE_CORRECTION attribute. Data Flow, page 123: Added paragraph requiring block RAM address setup/hold times to be met if port is enabled, even if data is of no interest. Table 3-54 (LVCMOS15) and Table 3-55, page 222 (LVCMOS18): Updated voltage level definitions and values. Xilinx DCI, page 224: Added material clarifying the effect on DCI outputs of leaving VRN/VRP disconnected. Xilinx DCI, page 224: Removed reference to FreezeDCI. DCI in Virtex-II Pro/Virtex-II Pro X Hardware, page 236: Modified point 3 detailing when VRP/VRN reference resistors are not required. Location Constraints, page 251: Deleted last paragraph, incorrect. Differential Termination LVDS Input HDL Examples, page 260: Replaced VHDL and Verilog instantiation examples. Chapter 4, Configuration: Corrected various typographical errors. Device Startup, page 295: Added requirement of 5-10 CCLK cycles after DONE is released. Figure 4-5: Added pull-up resistor to INIT_B signal. Deleted section Using XC17V00 PROMs. Obsolete. Table 5-3: Added Pb-free package names. Corrected errors in row/column headings. (No change to values.) Figure 5-65, Figure 5-70: Replaced FG456/FGG456 and FF1148/FFG1148 package drawings with updated versions.
03/28/07
4.1
www.xilinx.com
Revision Added footnote regarding LVDS receiver differential termination to _DT standards in Table 3-58 and Table 3-59. Table 4-28: Corrected bit assignments for MATCH_CYCLE and LOCK_CYCLE. Table 4-16: Added new Step 13. Configuration Memory Read Procedure (1149.1 JTAG), page 374: Added new steps 5(b) and 5(c); corrected step 5(g) [formerly 5(e)]. Updated legal disclaimer. Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1149.1, page 321: Updated IEEE 1149.1 compliance statement.
www.xilinx.com
Table of Contents
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block SelectRAM Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded Multiplier Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 IOB Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IOB Input Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 IOB Output Timing Model and Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 IOB 3-State Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Additional Timing Models in Other Publications: PPC405 Processor Block and RocketIO/RocketIO X Transceivers . . . . . . . . . . 65
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
IBM PPC405 Processor Block Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 RocketIO Transceiver Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 RocketIO X Transceiver Timing Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Shift Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization in VHDL and Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fully Synchronous Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static-Length Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-II Pro/Virtex-II Pro X CLB Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wide-Input Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-II Pro/Virtex-II Pro X CLB Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Twos-Complement Signed Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing with BlockRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of Supported I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx DCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCI in Virtex-II Pro/Virtex-II Pro X Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
151 153 153 156 156 157 157 158 159 160 162 162 166 166 167 167 168 168 172 172 173 174 174 178 179 179 183 183 183 184 185 186 186 187 188 190 199 207 224 224 231 236 243 243 249 249
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
11
VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization in VHDL or Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an LVDS Input/Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an LVDS Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an LVDS Output 3-State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Bidirectional LVDS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDT Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
250 250 251 251 251 252 258 258 262 263 264 265 265
Chapter 4: Configuration
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Process and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed Voltage Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System ACE CF (CompactFlash) Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash PROMs With a CPLD Configuration Controller. . . . . . . . . . . . . . . . . . . . . . . . . Embedded Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM and System ACE CF Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 293 296 298 299 300 301 302 303
12
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Programming Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Boundary Scan Interconnect Testing for Virtex-II Pro Devices. . . . . . . . . . . . . . . . . . 304 In-System Programming Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Internal Configuration Access Port (ICAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 JTAG / Boundary-Scan Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1149.1 . . . . . . . . . . . Using Boundary Scan in Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1532 . . . . . . . . . . . . Configuration Flows Using JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory: Columns and Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PPC405 and MGT Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bitstream Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing a Design for Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verifying Readback Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using ChipScope ILA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 321 329 335 337 339 341 341 342 343 356 361 367 368 379 379 382 383
Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
13
14
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
15
16
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Preface
Guide Contents
Chapter 1, The Virtex-II Pro / Virtex-II Pro X FPGA Family Chapter 2, Timing Models Chapter 3, Design Considerations Chapter 4, Configuration Chapter 5, PCB Design Considerations Appendix A, BitGen and PROMGen Switches and Options Appendix B, Platform Flash Family PROMs Appendix C, Choosing the Battery for VBATT Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
For Virtex-II Pro device specifications, refer to the Virtex-II Pro Data Sheet:
The following documents offer in-depth technical design information about the RocketIO and RocketIO X multi-gigabit transceivers and PowerPC 405 processor, which are not covered in this User Guide: RocketIO Transceiver User Guide RocketIO X Transceiver User Guide PowerPC Processor Reference Guide PowerPC 405 Processor Block Reference Guide
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
17
Additional Resources
For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource Data Sheets Description/URL Xilinx data sheets describe device-specific operating characteristics, architecture, and pinouts/packaging. http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp Xilinx user guides contain detailed, device-specific operating theory and generic design examples for various device functions. http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?categor y=User+Guides Application Notes Xilinx application notes describe design techniques and approaches to general design as well as specific applications. Many application notes feature complete reference designs including source code. http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?categor y=Application+Notes Xcell Journals Tech Tips This site contains quarterly journals for Xilinx programmable logic users. http://www.xilinx.com/xcell/xcell.htm See this site for the latest news, design tips, and patch information on the Xilinx design environment. http://www.xilinx.com/support/techsup/journals/index.htm Answers Database This database provides a current listing of solution records for Xilinx software tools. Search this database using the search function at: http://www.xilinx.com/support/searchtd.htm
User Guides
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document: Convention Courier font Meaning or Use Messages, prompts, and program files that the system displays Literal commands that you enter in a syntactical statement Commands that you select from a menu Keyboard shortcuts Example speed grade: - 100
Courier bold
Helvetica bold
18
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Convention
Meaning or Use Variables in a syntax statement for which you must supply values. (In angle brackets.)
Example
ngdbuild <design_name>
Italic font
See the Development System Reference Guide for more information. If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. ngdbuild [option_name] design_name
Emphasis in text An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required. A list of items from which you must choose one or more | Separates items in a list of choices
Square brackets
[ ]
Braces
{ }
lowpwr ={on|off} lowpwr ={on|off} IOB #1: Name = QOUT IOB #2: Name = CLKIN . . . allow block block_name loc1 loc2 ... locn;
Vertical bar
Online Document
The following conventions are used in this document: Convention Meaning or Use Cross-reference link to a location in the current document Cross-reference link to a location in another document Hyperlink to a website (URL) Example See the section Additional Resources for details. Refer to Title Formats in Chapter 1 for details. See Figure 2-5 in the Virtex-II Handbook. Go to http://www.xilinx.com for the latest speed files.
Blue text
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
19
20
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Chapter 1
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
21
system noise. The RocketIO/RocketIO X technology fulfills higher bandwidth system requirements than currently possible, with cost savings coming from faster time-tomarket, reduced printed circuit board (PCB) complexity, and lower component count. Each of the larger devices incorporates one or two small yet powerful IBM PowerPC 405 processor cores, each capable of more than 300 MHz clock frequency and 420 Dhrystone MIPS. While the processor cores occupy a small area of the die, they provide tremendous system flexibility where they are used. The PowerPC 405 cores are fully embedded within the FPGA fabric, where all processor nodes are controlled by the FPGA routing resources. This provides the utmost architectural capability, where complex applications may be efficiently divided between high-speed logic implementation and high-flexibility software implementations. For example, a packet processing application using only the FPGA logic today for high-speed packet routing may be augmented to include a slave high-performance processor for exception handling or in-system statistics monitoring. In contrast, using a separate processor externally requires hundreds of additional interface pins, which degrades system performance and significantly increases FPGA I/O requirements and overall board costs. The Virtex-II Pro/Virtex-II Pro X products are based on the most advanced FPGA fabric available: the Virtex-II architecture with IP-Immersion technology, which was developed to offer significant improvements in engineering productivity, silicon efficiency, and system flexibility. Unique features common in the Virtex-II Seriesconsisting of the Virtex-II and Virtex-II Pro familiesinclude powerful SystemIO system connectivity solutions, digitally controlled impedance (DCI) technology, comprehensive clocking solutions, high-speed Active Interconnect routing architecture, and bitstream encryption. These features together constitute the most complete Platform FPGA solution available, optimized for high performance system-level applications. The upward compatibility of the Virtex Series of products ensures benefits in engineering productivity, performance, design longevity, and continuing cost reduction.
Legacy of Leadership
Each of the Virtex families of FPGAs has been the most successful programmable product family in its class, starting with the introduction of the original Virtex family in 1998. The Virtex and Virtex-E families were recognized by the industry as the highest technology products available when they were first introduced. The Virtex-II family, which again achieved technology leadership in density, performance, and features, ushered in the era of Platform FPGAsprogrammable devices with the system-level capability and performance to implement systems functionality. The Virtex-II Pro family continues the tradition of technology leadership as the most sophisticated Platform FPGA yet, again breaking the technology barrier for the benefit of leading-edge system architects. The Virtex-II Pro/Virtex-II Pro X family is the first FPGA family to incorporate both serial transceiver technology and a hard processor core within a general-purpose FPGA device. This is significant for new high-bandwidth embedded processing applications such as packet processing, where both high device I/O bandwidth and high performance processor cores are needed together. The Virtex-II Pro/Virtex-II Pro X devices are the industry's first FPGAs in a 0.13-micron process. The nine-layer metal, all-copper, low-k process technology is among the most advanced in the semiconductor industry. The combination of advanced Active Interconnect architecture and advanced process technology makes the Virtex-II Pro/Virtex-II Pro X family the highest performance FPGA in the world. The RocketIO/RocketIO X multi-gigabit MGTs are the highest performance, most complete embedded serial transceivers available. They are user-configurable for up to
22
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
3.125 Gbps or 10.3125 Gbps baud rate per channel, which is many times the performance of other embedded transceivers at 1.25 Gbps. Each RocketIO/RocketIO X transceiver provides a complete set of common functionality available in standard SerDes transceivers. In contrast, "programmable ASSP" products with clock/data recovery (CDR) provide only the most basic transceiver capability. The IBM PowerPC 405 processor core used in the Virtex-II Pro/Virtex-II Pro X family is the highest performance embedded core available in FPGAs. The PowerPC architecture is used in many markets including communications, industrial control, test and measurement systems, and other performance-oriented markets. It is currently the most popular processor architecture in embedded applications.
Packets Everywhere
The Virtex-II Pro/Virtex-II Pro X family provides a powerful new paradigm for network processing where low latency is required, such as storage area networks, wireless infrastructure, and voice-over-IP networks. The digital convergence phenomenon drives the need for packet routing based on type and priority. For example, live voice and video data packets require significantly lower latency than data file packets. New data networking applications must now handle higher bandwidth traffic as well as more complex types of prioritized packets. In many cases, Virtex-II Pro/Virtex-II Pro X devices can offer higher overall performance than other solutions, including specialized network processors (NPs). Using the Virtex-II Pro architecture, the most common packets may be quickly read and routed using FPGA logic, without incurring the lengthy software runtime needed by NPs. The FPGA logic interrupts the PowerPC processor core only when processor instructions are needed for special packet types. For example, packets may be stored into a 16 KB dual-port memory area accessible by both the FPGA logic and the PowerPC 405 on-chip memory (OCM) port, allowing rapid change of control and packet disposition. By using the FPGA logic to process the most common packet types while the processor core handles the more specialized ones as a slave to the logic, the Virtex-II Pro architecture can provide higher overall performance than NPs, as well as more sophisticated processing capabilities than FPGA logic alone.
Bridge, Anyone?
Powerful protocol bridges for tying together disparate data stream formats are well-suited for the Virtex-II Pro/Virtex-II Pro X solution. New interface standards and protocols include PCI Express, Infiniband, Gigabit Ethernet, XAUI/10 Gigabit Ethernet, RapidIO, and HyperTransport. These must interface seamlessly to one another, as well as to other standards such as PCI, Fibre Channel, POS Phy Level 4, Flexbus 4, and others. This presents a significant challenge to system developers because of changing standards, scarcity of off-the-shelf interface components, and the inflexibility of available solutions. System designers have had to assemble their own blend of FPGAs, discrete physical transceivers, and discrete communications processors to solve their complex system challenges. Even newer "programmable ASSPs" (application-specific standard products) with built-in serial transceivers fall short, because they frequently require companion FPGAs to supplement their logic capacity. The Virtex-II Pro solution, using the powerful Xilinx SystemIO capability to fully integrate silicon, software, and IP capabilities, provides the most flexible pre-engineered protocol bridge solutions available for fast timeto-market and low development cost.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
23
Simplifying Complexity
The Virtex-II Pro/Virtex-II Pro X solution offers a powerful paradigm for complex embedded systems found in signal processing, industrial control, image processing, networking, communications, and aeronautic applications. For the first time, complex embedded systems traditionally involving sophisticated hardware and software may be developed concurrently, emulated in actual hardware at speed, debugged in-system, and re-architected for performance within weeks, rather than months or years. In addition, full systems can be remotely upgraded as easily as software-only upgrades are performed today, using Compact Flash, CDROM, Internet, wireless transmission, or other flexible means. Hardware design is simplified using powerful development software and a large soft IP library to assemble logic- and processor-based platforms. Software development may be started earlier using the actual device in preconfigured sample platforms, without waiting for the new system board to be developed. In many cases, higher density Virtex-II Pro components may be used for early system development, whereby extra resources (including additional PowerPC processor cores) may be used to easily emulate board-level components yet to be developed. This flexibility, obviously unavailable in custom ASICs or ASSPs, allows systems to be emulated at speed, rather than simulated using software simulators at 100 or 1000 times slower. In-system debugging is further enhanced by the Xilinx ChipScope Pro tool, which provides comprehensive logic analysisfrom probing internal nodes to full bus analysis with bus protocol adherence checks using an external logic analyzer via the IEEE 1149.1 (JTAG) test access port. Using ChipScope Pro can result in orders of magnitude of improvement in engineering productivity. Complex systems can be optimally repartitioned between FPGA logic and processor cores, allowing a continuum of possible trade-offs between the speed of logic and the flexibility of software code. For example, a first implementation of an echo cancellation algorithm might be all-software in compiled C code running on a PowerPC core, in order to allow the system software development to start. As the system is further optimized, part of the DSP algorithm could be retargeted using Matlab Simulink into FPGA logic to achieve a significantly faster but functionally identical system for production release. In another example, an encryption application might implement the Diffie-Hellman key exchange algorithm, whereby exponentiation and message management could be optimally partitioned into FPGA logic and an embedded processor, respectively. In this way, the programmable systems paradigm offers tremendous flexibility to allow system designers and architects to optimize the trade-offs in development time, system performance, and system costs. It is significant that the embedded systems enabled by Virtex-II Pro solutions are "all-soft," in that both logic and software code are controlled by a soft data file. Because of this, the low cost of design maintenance and degree of design reuse is greatly enhanced. Whole system upgrades, including both hardware and software, can now be accomplished with one unified soft file using System ACE configuration solutions, offering the same low cost and ease of use as software-only upgrades.
Time Is Money
The Virtex-II Series, comprising both the Virtex-II and Virtex-II Pro/Virtex-II Pro X families, offers significantly faster time-to-market and lower development costs than ASICs. Compared to a full-custom ASIC, the Virtex-II Pro solution eliminates the need for exhaustive verification during development, and allows hardware-software debug at system speeds rather than at slow software simulation speeds. In addition, the
24
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Virtex-II Pro/Virtex-II Pro X features of signal integrity, pre-engineered clocking capabilities, and an abundance of soft IP cores, significantly reduce development time. The Virtex-II Series offers significantly lower development costs than ASICs, due to lower tool costs, lower third-party IP costs, and absence of NRE costs. The Virtex-II Series also increases engineering productivity by accelerating hardware availability for software development and increasing software debug speed. In addition, the availability of powerful development tools enables straightforward retargeting of other embedded processors into the PowerPC platform. Compared to other processor architectures, the PowerPC 405 core in most cases allows higher performance and more powerful capabilities, and thus can be used to accelerate preproduction of performance-sensitive applications.
Flexibility Is Money
The flexibility inherent in the Virtex-II Series allows system architects to fine-tune their architectural partitioning after the initial prototype is developed. That is, each subsystem function can be freely implemented as hardware only, software only, or any combination within the hardware-software continuum, depending on the trade-off between performance and complexity. For example, a wireless infrastructure system might initially implement a rake filter function in hardware, and then change to a firmware implementation as more software control is necessary during later development. This repartitioning would be impossible in custom ASICs without significant time and cost penalties. The Virtex-II Series offers significantly more flexibility than fixed chip sets and ASSPs, allowing end user product differentiation and future-proofing. For a design requirement that can generally be met either by ASSPs or by Virtex-II Platform FPGAs, the initial design investment for an FPGA implementation may be higher. However, the advantages for Platform FPGA implementations include customizing of functionality, ease of design reuse, ability to fix design bugs, differentiation of user end products, and ownership and control of the entire system. These are important advantages in highly competitive markets where ASSPs have standing errata lists and unpredictable future availability. In contrast, properly developed Platform FPGA designs are soft designs that may be readily maintained and reused as needed. Therefore, FPGA methodologies can provide system manufacturers with greater competitive advantage in the short term, and greater ownership and control over their products in the long term.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
25
26
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Chapter 2
Timing Models
Summary
The following topics are covered in this chapter: CLB / Slice Timing Models Block SelectRAM Timing Model Embedded Multiplier Timing Model IOB Timing Models Pin-to-Pin Timing Models Digital Clock Manager Timing Model Additional Timing Models in Other Publications: PPC405 Processor Block and RocketIO/RocketIO X Transceivers
Introduction
Due to the large size and complexity of Virtex-II Pro/Virtex-II Pro X FPGAs, understanding the timing associated with the various paths and functional elements has become a difficult and important problem. Although it is not necessary to understand the various timing parameters in order to implement most designs using Xilinx software, a thorough timing model can assist advanced users in analyzing critical paths or planning speed-sensitive designs. The Timing Model chapter is broken up into sections consisting of three basic components: Functional Element Diagram - basic architectural schematic illustrating pins and connections. Timing Parameters - Virtex-II Pro and Virtex-II Pro X Platform FPGA Data Sheet timing parameter definitions. Timing Diagram - illustrates functional element timing parameters relative to each other.
This chapter was written with the Xilinx Timing Analyzer software (TRCE) in mind. All pin names, parameter names, and paths are consistent with Post Route Timing and PreRoute Static Timing reports. Use the models in this chapter in conjunction with both the Timing Analyzer software and the section on switching characteristics in the Virtex-II Pro Platform FPGA Data Sheet. Most of the timing parameters found in the section on switching characteristics are described in this chapter.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
27
LUT G inputs D
YQ
BX CE CLK SR
UG002_C3_017_030703
Figure 2-1:
28
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Timing Parameters
Table 2-1: General Slice Timing Parameters
Function Control Signal Description
Parameter
Combinatorial Delays TILO F/G inputs to X/Y outputs F/G inputs to F5 output F/G inputs to X output FXINA/FXINB inputs to Y output Transparent Latch input to XQ/YQ outputs Propagation delay from the F/G inputs of the slice, through the look-up tables (LUTs), to the X/Y outputs of the slice. Propagation delay from the F/G inputs of the slice, through the LUTs and MUXF5 to the F5 output of the slice. Propagation delay from the F/G inputs of the slice, through the LUTs and MUXF5 to the X output of the slice. Propagation delay from the FXINA/FXINB inputs, through MUXFX to the Y output of the slice. Incremental delay through a transparent latch to XQ/YQ outputs.
TIF5
TIF5X
TIFXY
TIFNCTL
Sequential Delays TCKO FF Clock (CLK) to XQ/YQ outputs Latch Clock (CLK) to XQ/YQ outputs Time after the clock that data is stable at the XQ/YQ outputs of the slice sequential elements (configured as a flip-flop). Time after the clock that data is stable at the XQ/YQ outputs of the slice sequential elements (configured as a latch).
TCKLO
TDICK/TCKDI
BX/BY inputs
Time before Clock (CLK) that data from the BX or BY inputs of the slice must be stable at the D-input of the slice sequential elements (configured as a flip-flop). Time before Clock (CLK) that data from the DY input of the slice must be stable at the D-input of the slice sequential elements (configured as a flip-flop). Time before Clock (CLK) that data from the DX input of the slice must be stable at the D-input of the slice sequential elements (configured as a flip-flop). Time before Clock (CLK) that the CE (Clock Enable) input of the slice must be stable at the CE-input of the slice sequential elements (configured as a flip-flop).
TDYCK/TCKDY
DY input
TDXCK/TCKDX
DX input
TCECK/TCKCE
CE input
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
29
Table 2-1:
Parameter
TRCK/TCKR
SR/BY inputs
Clock CLK TCH TCL Set/Reset TRPW Minimum Pulse Width for the SR (Set/Reset) and BY (Rev) pins. Propagation delay for an asynchronous Set/Reset of the slice sequential elements. From SR/BY inputs to XQ/YQ outputs. Toggle Frequency - Maximum Frequency that a CLB flip-flop can be clocked: 1/(TCH+TCL) Minimum Pulse Width, High. Minimum Pulse Width, Low.
TRQ
FTOG
Timing Characteristics
Figure 2-2 illustrates general timing characteristics of a Virtex-II Pro/Virtex-II Pro X slice.
1 CLK TCECK CE TDYCK DY
(DATA)
SR
(RESET)
YQ
(OUT)
Figure 2-2:
At time TCECK before Clock Event 1, the Clock-Enable signal becomes valid-high at the CE input of the slice register. At time TDYCK before Clock Event 1, data from the DY input becomes valid-high at the D input of the slice register and is reflected on the YQ pin at time TCKO after Clock Event 1*. At time TRCK before Clock Event 3, the SR signal (configured as synchronous reset in this case) becomes valid-high, resetting the slice register, and this is reflected on the YQ pin at time TCKO after Clock Event 3. Note: In most cases software uses the DX/DY inputs to route data to the slice registers when at all possible. This is the fastest path to the slice registers and saves other slice routing resources.
30
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
ADDRESS G4 G3 G2 G1
RAM
D Y
WS BY DATA_IN or Address
DI
SLICEWE[2:0]
WSGEN
WE CK MUXF5 F5 WS ADDRESS G4 G3 G2 G1 DI
RAM
D X
SR (Write Enable)
UG002_C3_019_1204 00
Figure 2-3:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
31
Timing Parameters
Table 2-2:
Parameter
Sequential Delays for Slice LUT Configured as RAM (Distributed RAM) CLK to X/Y outputs (WE active) in 16x1 mode CLK to X/Y outputs (WE active) in 32x1 mode Time after the Clock (CLK) of a WRITE operation that the data written to the distributed RAM (in 16x1 mode) is stable on the X/Y outputs of the slice. Time after the Clock (CLK) of a WRITE operation that the data written to the distributed RAM (in 32x1 mode) is stable on the X/Y outputs of the slice. Time after the Clock (CLK) of a WRITE operation that the data written to the distributed RAM is stable on the F5 output of the slice.
TSHCKO16
TSHCKO32
TSHCKOF5
Setup and Hold for Slice LUT Configured as RAM (Distributed RAM)
TxS = Setup time (before clock edge) TxH = Hold time (after clock edge) The following descriptions are for setup times only.
TDS/TDH
Time before the clock that data must be stable at the DI input of the slice LUT (configured as RAM), via the slice BX/BY inputs. Time before the clock that address signals must be stable at the F/G inputs of the slice LUT (configured as RAM). Time before the clock that the Write Enable signal must be stable at the WE input of the slice LUT (configured as RAM).
TAS/TAH
WE input (SR)
Minimum Pulse Width, High (for a Distributed RAM clock). Minimum Pulse Width, Low (for a Distributed RAM clock). Minimum clock period to meet address write cycle time.
32
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Timing Characteristics
Figure 2-4 illustrates the timing characteristics of a 16-bit distributed RAM implemented in a Virtex-II Pro/Virtex-II Pro X slice (LUT configured as RAM).
1 TWC TWPH TWPL CLK TAS 2 TDS DATA_IN 1 TWES WE DATA_OUT (X/Y Output) X TILO 0 1 0 X TILO 2 3 4 5 6 7
ADDR
UG002_C3_020_031301
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
33
SRL
D MC15 WS DI
WE CK
SRL
D MC15 XB
SR CLK
BX (DATA_IN or ADDRESS)
Shift_Out
UG002_C3_021_113000
Figure 2-5:
34
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Timing Parameters
Table 2-3:
Parameter
Sequential Delays for Slice LUT Configured as SRL (Select Shift Register) TREG CLK to X/Y outputs Time after the Clock (CLK) of a WRITE operation that the data written to the SRL is stable on the X/Y outputs of the slice. Time after the Clock (CLK) of a WRITE operation that the data written to the SRL is stable on the Shiftout or XB/YB outputs of the slice. Time after the Clock (CLK) of a WRITE operation that the data written to the SRL is stable on the F5 output of the slice.
TCKSH
CLK to Shiftout
TREGF5
CLK to F5 output
TSRLDS/ TSRLDH
Time before the clock that data must be stable at the DI input of the slice LUT (configured as SRL), via the slice BX/BY inputs. Time before the clock that the Write Enable signal must be stable at the WE input of the slice LUT (configured as SRL).
CE input (WE)
Minimum Pulse Width, High (for SRL clock). Minimum Pulse Width, Low (for SRL clock).
Timing Characteristics
Figure 2-6 illustrates the timing characteristics of a 16-bit shift register implemented in a Virtex-II Pro/Virtex-II Pro X slice (LUT configured as SRL).
1 TSRPH TSRPL 2 CLK
TWSS
0
TREG TILO
2
TILO
1 1 1 0 1 16
MSB (MC15)
UG002_C3_022_102700
Figure 2-6:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
35
36
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
DO DOP
DS031_10_102000
Figure 2-7:
Timing Parameters
Table 2-4: Block SelectRAM Timing Parameters Function Control Signal Description
Parameter
ADDR DI EN
Time before the clock that address signals must be stable at the ADDR inputs of the block RAM. Time before the clock that data must be stable at the DI inputs of the block RAM. Time before the clock that the enable signal must be stable at the EN input of the block RAM. Time before the clock that the synchronous set/reset signal must be stable at the SSR input of the block RAM. Time before the clock that the write enable signal must be stable at the WE input of the block RAM.
TBRCK/TBCKR
SSR
TBWCK/TBCKW
WE
Clock to Out
TBCKO Clock to Output CLK to DO Time after the clock that the output data is stable at the DO outputs of the block RAM.
Clock
TBPWH TBPWL Clock Clock CLK CLK Minimum pulse width, high. Minimum pulse width, low.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
37
Timing Characteristics
The timing diagram in Figure 2-8 describes a single-port block RAM in Write-First mode. The timing for Read-First and No-Change modes are similar (see Chapter 3, Design Considerations).
1 TBPWH CLK TBACK ADDR DI DO TBECK EN TBRCK SSR TBWCK WE Disabled Read Write Read Reset Disabled 00 TBDCK DDDD TBCKO MEM (00) 0F CCCC CCCC* 7E BBBB MEM (7E) 8F AAAA 0101** 20 0000 2 TBPWL 3 4 5
Figure 2-8:
38
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Timing Model
Figure 2-9 illustrates the delay paths associated with the implementation of block SelectRAM. This example takes the simplest paths on and off chip (these paths can vary greatly depending on the design). This timing model demonstrates how and where the block SelectRAM timing parameters are used.
FPGA
Block SelectRAM Data Address Write Enable Enable Synchronous Set/Reset [TIOPI + NET] + TBDCK [TIOPI + NET] + TBACK [TIOPI + NET*] + TBWCK [TIOPI + NET] + TBECK [TIOPI + NET] + TBRCK
Data
Figure 2-9:
NET = Varying interconnect delays TIOPI = Pad to I-output of IOB delay TIOOP = O-input of IOB to pad delay TGI0O = BUFGMUX delay
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
39
MULT 18 x 18 B[17:0]
P[35:0]
DS031_40_100400
Figure 2-10:
Timing Parameters
Worst-Case Propagation Delays
The TMULT timing parameter is reported by the Timing Analyzer software. These values correspond to the propagation delay through the multiplier to a specific output pin of the multiplier block. The shortest delay is to pin 0, the longest to pin 35. These parameters can be found in the table entitled Multiplier Switching Characteristics in Module 3 of the Virtex-II Pro Platform FPGA Data Sheet. The delay-to-pin ratio is essentially linear (see Figure 2-11). This implies that smaller multiply functions are faster than larger ones. This is true as long as the LSB inputs are used.
40
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Pin 35
Pin 0 Delay
Figure 2-11:
UG002_C3_023_092500
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
41
Timing Characteristics
Figure 2-12 illustrates the result (outputs) of a 4-bit x 4-bit unsigned multiply implemented in an embedded multiplier block.
Time 0 input [3..0] input [3..0]
1111
1111
TMULT (P0) P0 X TMULT (P1) P1 X TMULT (P2) P2 X TMULT (P3) P3 X TMULT (P4) P4 X TMULT (P5) P5 X TMULT (P6) P6 X TMULT (P7) P7 X 1 1 1 0 0 0 0 1
UG002_C3_024_101300
Figure 2-12:
At time 0 the two 4-bit numbers to be multiplied become valid at the A[0..3], B[0..3] inputs to the embedded multiplier. The result appears on the output pins P[0..7] in a staggered fashion. First, P0 becomes valid at time TMULT(P0), followed by each subsequent output pin, until P7 becomes valid at time TMULT (P7). In this case, the delay for this multiply function should correspond to that of Pin 7. In other words, the result is not valid until all output pins become valid.
42
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
These sections are intended to be used in conjunction with the section on switching characteristics in the Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to the Data Sheet.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
43
IOB Input Timing Model and Parameters Figure 2-13 illustrates IOB inputs.
PAD
ICE
SR
REV
SR
REV
UG002_C3_004_101300
Figure 2-13:
Timing Parameters
Table 2-5: IOB Input Timing Parameters
Function Control Signal Description
Propagation delay from the pad to I output of the IOB with no delay adder. Propagation delay from the pad to I output of the IOB with the delay adder. Propagation delay from the pad to IQ output of the IOB via transparent latch with no delay adder. Propagation delay from the pad to IQ output of the IOB via transparent latch with the delay adder.
TIOPLI
TIOPLID
44
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 2-5:
Parameter
TIOPICK/TIOICKP
Time before the clock that the input signal from the pad must be stable at the ID input of the IOB Input Register, with no delay. Time before the clock that the input signal from the pad must be stable at the ID input of the IOB Input Register, with delay. Time before the clock that the Clock Enable signal must be stable at the ICE input of the IOB Input Register. Time before the clock that the Set/Reset signal must be stable at the SR input of the IOB Input Register.
TIOPICKD/TIOICKPD
TIOICECK/TIOCKICE
ICE input
Time after the clock that the output data is stable at the IQ output of the IOB Input Register.
SR Input to IQ (asynchronous)
Time after the Set/Reset signal of the IOB is toggled that the output of the IOB input register (IQ) reflects the signal. Time after the Global Set/Reset is toggled that the output of the IOB input register (IQ) reflects the set or reset.
TGSRQ
GSR to output IQ
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
45
Timing Characteristics
Figure 2-14 illustrates IOB input register timing.
1 2 3 4 5
UG002_c3_005_112700
Figure 2-14:
Clock Event 1
At time TIOICECK before Clock Event 1, the input clock enable signal becomes validhigh at the ICE input of the input register, enabling the input register for incoming data. At time TIOPICK before Clock Event 1, the input signal becomes valid-high at the I input of the input register and is reflected on the IQ output of the input register at time TIOCKIQ after Clock Event 1.
Clock Event 4
At time TIOSRCKI before Clock Event 4, the SR signal (configured as synchronous reset in this case) becomes valid-high resetting the input register and reflected at the IQ output of the IOB at time TIOCKIQ after Clock Event 4.
46
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
TIOCKIQ TIOCKIQ
UG002_c3_006_112700
Clock Event 1
At time TIOICECK before Clock Event 1 the input clock enable signal becomes validhigh at the ICE input of both of the DDR input registers, enabling them for incoming data. Since the ICE and I signals are common to both DDR registers, care must be taken to toggle these signals between the rising edges of ICLK1 and ICLK2 as well as meeting the register setup-time relative to both clocks. At time TIOPICK before Clock Event 1 (rising edge of ICLK1) the input signal becomes valid-high at the I input of both registers and is reflected on the IQ1 output of inputregister 1 at time TIOCKIQ after Clock Event 1.
Clock Event 2
At time TIOPICK before Clock Event 2 (rising edge of ICLK2) the input signal becomes valid-low at the I input of both registers and is reflected on the IQ2 output of input-register 2 at time TIOCKIQ after Clock Event 2 (no change in this case).
Clock Event 9
At time TIOSRCKI before Clock Event 9 the SR signal (configured as synchronous reset in this case) becomes valid-high resetting input-register 1 (IQ1) at time TIOCKIQ after Clock Event 9, and input-register 2 (IQ2) at time TIOCKIQ after Clock Event 10.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
47
OTCLK2
CE CK2 SR REV
O2
Figure 2-16:
Timing Parameters
Table 2-6: IOB Output Timing Parameters
Function Control Signal Description
Propagation delay from the O input of the IOB to the pad. Propagation delay from the O input of the IOB to the pad via transparent latch.
TIOOCK/TIOCKO
O input
Time before the clock that data must be stable at the O input of the IOB Output Register. Time before the clock that the Clock Enable signal must be stable at the OCE input of the IOB Output Register.
TIOOCECK/TIOCKOCE
OCE input
48
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 2-6:
Parameter
SR input (OFF)
Time after the clock that the output data is stable at the pad.
Time after the Set/Reset input of the IOB is toggled that the pad reflects the set or reset. Time after the Global Set/Reset is toggled that the pad reflects the set or reset.
TIOGSRQ
Timing Characteristics
Figure 2-17 illustrates IOB output register timing.
1 2 3 4 5
UG002_C3_008_112700
Figure 2-17:
Clock Event 1
At time TIOOCECK before Clock Event 1, the output clock enable signal becomes validhigh at the OCE input of the output register, enabling the output register for incoming data. At time TIOOCK before Clock Event 1, the output signal becomes valid-high at the O input of the output register and is reflected on the pad at time TIOCKP after Clock Event 1.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
49
Clock Event 4
At time TIOSRCKO before Clock Event 4, the SR signal (configured as synchronous reset in this case) becomes valid-high, resetting the output register and reflected on the pad at time TIOCKP after Clock Event 4.
UG002_c3_009_112700
Figure 2-18:
Clock Event 1
At time TIOOCECK before Clock Event 1, the output clock enable signal becomes validhigh at the OCE input of both of the DDR output registers, enabling them for incoming data. Since the OCE signal is common to both DDR registers, care must be taken to toggle this signal between the rising edges of OTCLK1 and OTCLK2 as well as meeting the register setup-time relative to both clocks. At time TIOOCK before Clock Event 1 (rising edge of OTCLK1), the output signal O1 becomes valid-high at the O1 input of output register 1 and is reflected on the pad at time TIOCKP after Clock Event 1.
Clock Event 2*
At time TIOOCK before Clock Event 2 (rising edge of OTCLK2), the output signal O2 becomes valid-high at the O2 input of output register 2 and is reflected on the pad at time TIOCKP after Clock Event 2 (no change on the pad in this case).
Clock Event 9
At time TIOSRCKO before Clock Event 9, the SR signal (configured as synchronous reset in this case) becomes valid-high, resetting output-register 1 (reflected on the pad at time
50
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
TIOCKP after Clock Event 9) (no change in this case) and output-register 2 (reflected on the pad at time TIOCKP after Clock Event 10) (no change in this case).
FF LATCH TCE OTCLK1 SR Shared by all registers REV FF LATCH D2 CE OTCLK2 CK2 SR REV Q2 D1 Q1
PAD
T2
Figure 2-19:
Timing Parameters
Table 2-7: IOB 3-State Timing Parameters
Function Control Signal Description
Time after T input of the IOB is toggled that the pad goes to high-impedance. Time after the T input of the IOB is toggled that the pad goes from high-impedance to valid data. Time after the T input of the IOB via transparent latch is toggled that the pad goes to high-impedance.
TIOTON
TIOTLPHZ
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
51
Table 2-7:
Parameter
TIOTLPON
TGTS Setup and Hold With Respect to Clock at IOB 3-State Register
TxxCK = Setup time (before clock edge) TxxCKxx = Hold time (after clock edge)
TIOTCK/TIOCKT
T input
Time before the clock that the signal must be stable at the T input of the IOB 3-state Register. Time before the clock that the clock enable signal must be stable at the TCE input of the IOB 3-state Register. Time before the clock that the set/reset signal.
TIOTCECK/TIOCKTCE
TCE input
SR input (TFF)
Time after clock that the pad goes to high-impedance. Time after clock that the pad goes from high-impedance to valid data.
Time after the SR signal is toggled that the pad goes to high-impedance. Time after the SR signal is toggled that the pad goes from high-impedance to valid data.
TIOSRON
52
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Timing Characteristics
Figure 2-20 illustrates IOB 3-state register timing.
1 2 3 4 5
CLK TIOTCK T TIOTCECK TCE TIOSRCKT SR TIOCKHZ PAD DATA Z TIOCKON DATA Z DATA
UG002_c3_011_101300
Figure 2-20:
Clock Event 1
At time TIOTCECK before Clock Event 1, the 3-state clock enable signal becomes validhigh at the TCE input of the 3-state register, enabling the 3-state register for incoming data. At time TIOTCK before Clock Event 1 the 3-state signal becomes valid-high at the T input of the 3-state register, returning the pad to high-impedance at time TIOCKHZ after Clock Event 1.
Clock Event 2
At time TIOSRCKT before Clock Event 2, the SR signal (configured as synchronous reset in this case) becomes valid-high, resetting the 3-state register and returning the pad to valid data at time TIOSRON after Clock Event 2.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
53
OTCLK2 TIOTCK T1 TIOTCK T2 TIOTCECK TCE TIOSRCKT SR TIOCKHZ PAD DATA Z TIOCKON DATA Z TIOSRON DATA Z
UG002_c3_012_101300
Figure 2-21:
Clock Event 1
At time TIOTCECK before Clock Event 1, the 3-state clock enable signal becomes valid-high at the TCE input of both of the DDR 3-state registers, enabling them for incoming data. Since the TCE signal is common to both DDR registers, care must be taken to toggle this signal between the rising edges of OTCLK1 and OTCLK2 as well as meeting the register setup-time relative to both clocks.
Clock Event 2
At time TIOTCK before Clock Event 2 (rising edge of OTCLK2), the 3-state signal T2 becomes valid-high at the T2 input of 3-state register 2, switching the pad to highimpedance at time TIOCKHZ after Clock Event 2.
Clock Event 3
At time TIOTCK before Clock Event 3 (rising edge of OTCLK1), the 3-state signal T1 becomes valid-high at the T1 input of 3-state register 1, keeping the pad at high-impedance for another half clock cycle (half the period of OTCLK1 or 2).
Clock Event 4
At time TIOTCK before Clock Event 4 (rising edge of OTCLK2), the 3-state signal T2 becomes valid-low at the T2 input of 3-state register 2, switching the pad to valid data at time TIOCKON after Clock Event 4. This is repeated for 3-state signal T1 at the following clock event (5) maintaining valid data on the pad until Clock Event 8.
54
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Clock Event 8
At time TIOTCK before Clock Event 8 (rising edge of OTCLK2), the 3-state signal T2 becomes valid-high at the T2 input of 3-state register 2, switching the pad to highimpedance at time TIOCKHZ after Clock Event 8.
Clock Event 9
At time TIOSRCKT before Clock Event 9 (rising edge of OTCLK1), the SR signal (configured as synchronous reset in this case) becomes valid-high at the SR input of 3-state Register 1, returning the pad to valid data at time TIOSRON after Clock Event 9.
The former describes the delay from the Global Clock pin (with and without the DCM) to an output pin via an Output flip-flop. The latter describes the set-up time for an Input flipflop from an input pin relative to the Global Clock pin (with and without the DCM). The values reported in the switching characteristics section of the Virtex-II Pro Platform FPGA Data Sheet are for LVCMOS_25 12 mA I/O standards. For different I/O standards, adjust these values with those shown in the "IOB Switching Characteristics Standard Adjustments" tables. This section is intended to be used in conjunction with the section on switching characteristics in the Virtex-II Pro Platform FPGA Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to the Virtex-II Pro Platform FPGA Data Sheet.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
55
DCM BUFGMUX
Timing Parameters
Table 2-8: Global Clock Input to Output Timing Parameters
Description Time after the Global Clock (pin), using the DCM, that the output data from an IOB Output flip-flop is stable at the output pin. Time after the Global Clock (pin), without the DCM, that the output data from an IOB Output flip-flop is stable at the output pin.
56
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Timing Characteristics
The waveforms depicted in Figure 2-23 demonstrate the relation of the Global Clock pin, the output data, and the use of the timing parameters.
Global Clock Pin (No DCM) D-input of IOB Output Register TICKOF Output Pin
Global Clock Pin (With DCM) D-input of IOB Output Register TICKOFDLL Output Pin
UG002_C3_015_101300
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
57
IOB
Input Pin
DCM
BUFGMUX
Figure 2-24:
Timing Parameters
Setup and Hold for Input Registers Relative to the Global Clock (pin):
TPSDLL / TPHDLL - Time before the Global Clock (pin), with DCM, that the input signal must be stable at the D-input of the IOB input register. TPSFD / TPHFD - Time before the Global Clock (pin), without DCM, that the input signal must be stable at the D-input of the IOB input register. Note: TPSFD = Setup time (before clock edge) and TPHFD = Hold time (after clock edge). The
previous descriptions are for setup times only.
58
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Timing Characteristics
The waveforms depicted in Figure 2-25 demonstrate the relation of the Global Clock pin, the input data, and the use of the timing parameters.
UG002_C3_016_101300
Figure 2-25:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
59
For a detailed description of input clock tolerance, jitter, and phase offset see the waveforms at the end of this section.
DCM
CLKIN (CLKIN_FREQ_(DLL & FX)_(LF & HF)) CLKFB CLK0 - CLKOUT_FREQ_1X_(LF & HF) CLK90 - CLKOUT_FREQ_1X_LF CLK180 - CLKOUT_FREQ_1X_(LF & HF) CLK270 - CLKOUT_FREQ_1X_LF CLK2X - CLKOUT_FREQ_2X_LF CLK2X180 - CLKOUT_FREQ_2X_LF CLKDV - CLKOUT_FREQ_DV_(LF & HF) CLKFX - CLKOUT_FREQ_FX_(LF & HF) CLKFX180 - CLKOUT_FREQ_FX_(LF & HF) PSDONE
LOCKED STATUS
ug002_c1_004_112800
60
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Timing Parameters
Table 2-9: Operating Frequency Range Parameters
Parameter Low Frequency Mode CLKOUT_FREQ_1X_LF The minimum and maximum frequency for the CLK0, CLK90, CLK180, CLK270 outputs of the DCM in lowfrequency mode. The minimum and maximum frequency for the CLK2X and CLK2X180 outputs of the DCM in low-frequency mode. The minimum and maximum frequency for the CLKDV output of the DCM in low-frequency mode. The minimum and maximum frequency for the CLKFX and CLKFX180 outputs of the DCM in low-frequency mode. The minimum and maximum frequency for the CLKIN input to the DCM in low-frequency mode when using the delay-locked loop (DLL) outputs. The minimum and maximum frequency for the CLKIN input to the DCM in low-frequency mode when using the FX outputs. The minimum and maximum frequency for the PSCLK input to the DCM in low-frequency mode. Description
CLKIN_FREQ_FX_LF (2)
The minimum and maximum frequency for the CLK0, CLK180 outputs of the DCM in high-frequency mode. The minimum and maximum frequency for the CLKDV output of the DCM in high-frequency mode. The minimum and maximum frequency for the CLKFX and CLKFX180 outputs of the DCM in high-frequency mode. The minimum and maximum frequency for the CLKIN input to the DCM in high-frequency mode when using the DLL outputs. The minimum and maximum frequency for the CLKIN input to the DCM in high-frequency mode when using the FX outputs. The minimum and maximum frequency for the PSCLK input to the DCM in high-frequency mode.
CLKIN_FREQ_FX_HF
PSCLK_FREQ_HF
Notes:
1. Delay-locked loop (DLL) outputs include: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. FX outputs include: CLKFX and CLKFX180
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
61
CLKIN_PULSE
CLKFB_DELAY_VAR_EXT
Low Frequency Mode CLKIN_CYC_JITT_DLL_LF The maximum cycle-to-cycle jitter the CLKIN input to the DCM can have when using the DLL outputs in lowfrequency mode. The maximum cycle-to-cycle jitter the CLKIN input to the DCM can have when using the FX outputs in lowfrequency mode. The maximum period jitter the CLKIN input to the DCM can have when using the DLL outputs in low-frequency mode. The maximum period jitter the CLKIN input to the DCM can have when using the FX outputs in low-frequency mode.
CLKIN_CYC_JITT_FX_LF
CLKIN_PER_JITT_DLL_LF
CLKIN_PER_JITT_FX_LF
High Frequency Mode CLKIN_CYC_JITT_DLL_HF The maximum cycle-to-cycle jitter the CLKIN input to the DCM can have when using the DLL outputs in highfrequency mode. The maximum cycle-to-cycle jitter the CLKIN input to the DCM can have when using the FX outputs in highfrequency mode. The maximum period jitter the CLKIN input to the DCM can have when using the DLL outputs in high-frequency mode. The maximum period jitter the CLKIN input to the DCM can have when using the FX outputs in high-frequency mode.
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_DLL_HF
CLKIN_PER_JITT_FX_HF
Notes:
1. The frequencies applicable to CLKIN_PULSE range from 1 to >400 MHz. These frequencies also apply to PSCLK_PULSE. Since PSCLK can be less than 1 MHz, the pulse width under this condition is specified for PSCLK only.
62
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
63
The waveforms in Figure 2-27 demonstrate the relationship between clock tolerance, jitter, and phase.
Period Tolerance: the allowed input clock period change in nanoseconds.
TCLKIN
Output Jitter: the difference between an ideal reference clock edge and the actual design.
Ideal Period Actual Period +/- Jitter + Maximum Phase Difference + Phase Offset
ds022_24_112800
Figure 2-27:
Output jitter is period jitter measured on the DLL output clocks, excluding input clock jitter. Phase offset between CLKIN and CLKFB is the worst-case fixed time difference between rising edges of CLKIN and CLKFB, excluding output jitter and input clock jitter. Phase offset between clock outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL outputs, excluding output jitter and input clock jitter. Maximum phase difference between CLKIN an CLKFB is the sum of output jitter and phase offset between CLKIN and CLKFB, or the greatest difference between CLKIN and CLKFB rising edges due to DLL alone (excluding input clock jitter). Maximum phase difference between clock outputs on the DLL is the sum of output jitter and phase offset between any DLL clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
+ Jitter
64
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Additional Timing Models in Other Publications: PPC405 Processor Block and RocketIO/RocketIO X Transceivers
Due to their length and complexity, timing models for the IBM PPC405 Processor Block and the RocketIO/RocketIO X Multi-Gigabit Transceivers are not included in this User Guide. They can be found in the publications described below, which cover in detail the operation and implementation of these Virtex-II Pro/Virtex-II Pro X components:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
65
66
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Chapter 3
Design Considerations
Summary
This chapter covers the following topics: RocketIO and RocketIO X Transceivers Processor Block Global Clock Networks Digital Clock Managers (DCMs) Block SelectRAM Memory Distributed SelectRAM Memory Look-Up Tables as Shift Registers (SRLs) Large Multiplexers Sum of Products (SOP) Logic Embedded Multipliers Single-Ended SelectIO-Ultra Resources Digitally Controlled Impedance (DCI) Double-Data-Rate (DDR) I/O LVDS I/O LVPECL I/O Bitstream Encryption CORE Generator System
Introduction
This chapter describes how to take advantage of the many special features of Virtex-II Pro /Virtex-II Pro X architecture to achieve maximum density and performance. In many cases, the functions described can be automatically generated using the Xilinx CORE Generator tool. This is noted throughout the chapter, in the following sections specifically: Block SelectRAM Memory Distributed SelectRAM Memory Look-Up Tables as Shift Registers (SRLs) Large Multiplexers Embedded Multipliers
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
67
Processor Block
Two additional user manuals detail the hardware and software design aspects of the processor block. The PowerPC 405 Processor Block Reference Guide provides information on input/output signals, timing relationships between signals, and the mechanisms software can use to control the interface operation. The PowerPC Processor User Manual serves as a stand-alone reference for application and system programmers of the PPC405 processor core. For the most up-to-date information on the PPC405 processor core, refer to the current revisions of these manuals on the Xilinx website at www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides.
68
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Figure 3-1 illustrates placement of these clock resources in Virtex-II Pro/Virtex-II Pro X devices (the XC2VP20/XC2VPX20 through the XC2VP70/XC2VPX70) that have eight DCMs.
8 GCLK Pads User I/Os IBUFG 8 BUFGMUX DCM DCM DCM DCM IBUFG User I/Os
BRAM Multiplier
CLB
BRAM Multiplier
CLB
BRAM Multiplier
BRAM Multiplier
CLB
BRAM Multiplier
BRAM Multiplier
CLB
BRAM Multiplier
DCM
DCM
DCM
User I/Os
UG002_C2_092_120100
Figure 3-1:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
69
The simple scheme to distribute an external clock in the device is to implement a clock pad with an IBUFG input buffer connected to a BUFG global buffer, as shown in Figure 3-2 and Figure 3-3. The primary (GCLKP) and secondary (GCLKS) clock pads have no relationship with the P-side and N-side of differential clock inputs. In banks 0 and 1, the GCLKP corresponds to the N-side, and the GCLKS corresponds to the P-side of a differential clock input. In banks 4 and 5, this correspondence is reversed.
IBUFG BUFG I
GCLK
PAD
Clock Distribution
Clock Input IBUFGDS GCLKS GCLKP P N I O IB (Bank 0 and 1 Scheme) I O Clock Distribution BUFG
UG002_C2_105_080601
Figure 3-2:
GCLK
PAD
Clock Distribution
Clock Input
BUFG I
Clock Distribution
Figure 3-3:
.
Major synthesis tools automatically infer the IBUFG and BUFG when the corresponding input signal is used as a clock in the VHDL or Verilog code. A high frequency or adapted (frequency, phase, and so forth) clock distribution with low skew is implemented by using a DCM between the output of the IBUFG and the input of the BUFG, as shown in Figure 3-4. Digital Clock Managers (DCMs), page 89 provides details about DCMs and their use.
70
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
GCLK
Pad
CLKIN CLKFB
CLK0
Clock Distribution
UG002_C2_085_050503
Figure 3-4: Clock Distribution with DCM Clock distribution from internal sources is also possible with a BUFG only or with a DCM, as shown in Figure 3-5.
BUFG
Logic
Clock Distribution
DCM
BUFG
Logic CLKIN CLKFB CLKO
Clock Distribution
UG002_C2_086_050503
Figure 3-5:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
71
Table 3-1:
BUFGCE (CE)
NA NA General interconnect General interconnect NA NA
BUFGMUX (S)
NA NA General interconnect General interconnect NA NA
DCM (CLKIN)
Same edge General interconnect(3) General interconnect(3) General interconnect(3) Global clock net Global clock net
External Clock via IBUFG(O) DCM Clock Outputs Internal Logic User I/O Pad via IBUF(O) (not IBUFG) BUFG(O) BUFGMUX(O)
Notes:
1. Not all IBUFGs in the quadrant have a dedicated connection to a specific BUFG. Others would require general interconnect to be hooked up. 2. Same edge (top or bottom) enables use of dedicated routing resources. 3. Pad to DCM input skew is not compensated.
All BUFG (BUFGCE, BUFGMUX) outputs are available at the quadrant boundaries. The output of the global clock buffer can be routed to non-clock pins.
No hardware difference exists between a primary and a secondary clock multiplexer. However, some restrictions apply to primary/secondary multiplexers, because they share input connections, as well as access to a quadrant. Each Virtex-II Pro/Virtex-II Pro X device is divided into four quadrants: North-West, South-West, North-East, and South-East. Each quadrant has two primary and two secondary clock multiplexers. The clock multiplexers are indexed 0 to 7, with one primary and one secondary for each index, alternating on the top and on the bottom (i.e., clock multiplexer 0P at the bottom is facing clock multiplexer 0S at the top). In each device, the eight top/bottom clock multiplexers are divided into four primary and four secondary, indexed 0 to 7, as shown in Figure 3-6.
72
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
7P
6S
5P
4S
3P
2S
1P
0S
BUFGMUX
NW
NE
SW
SE
7S
6P
5S
4P
3S
2P
1S
0P
BUFGMUX
UG002_C2_087_113000
Figure 3-6:
Primary/Secondary: Rule 1
Considering two facing clock multiplexers (BUFG#P and BUFG#S), one or the other of these clock outputs can enter any quadrant of the chip to drive a clock within that quadrant, as shown in Figure 3-7. Note that the clock multiplexers xP and xS compete for quadrant access. For example, BUFG0P output cannot be used in the same quadrant as BUFG0S.
1P
0S
NW
NE
SW
SE
1S
0P
UG002_C2_088_113000
Figure 3-7:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
73
Primary/Secondary: Rule 2
In a BUFGCE or BUFGMUX configuration, shared inputs have to be considered. Any two adjacent clock multiplexers share two inputs, as shown in Figure 3-8. The clock multiplexer 1P and 0S have common I0/I1 and I1/I0 inputs.
I1 S BUFGMUX 1P O
I0 S
I1 BUFGMUX 0S O
I0
UG002_C2_089_113000
Figure 3-8:
Table 3-2 lists the clock multiplexer pairs in any Virtex-II Pro/Virtex-II Pro X device. The primary multiplexer inputs I1/I0 are common with the corresponding secondary multiplexer inputs I0/I1 (i.e., Primary I1 input is common with secondary I0 input, and primary I0 input is common with secondary I1 input). Table 3-2: Top Clock Multiplexer Pairs 1P 0S 3P 2S 5P 4S 7P 6S
Primary/Secondary Usage
For up to eight global clocks, it is safe to use the eight primary global multiplexers (1P, 3P, 5P, 7P on the top and 0P, 2P, 4P, 6P on the bottom). Because of the shared inputs, a maximum of eight independent global clock multiplexers can be used in a design, as shown in Figure 3-9.
74
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
GCLK7P
GCLK5P
GCLK3P
GCLK1P
IBUFG/IBUFGDS
7P
5P
3P
1P
NW
NE
8 clocks 8 8
8 clocks
SW
SE 6P 4P 2P 0P
IBUFG/IBUFGDS
GCLK6P
GCLK4P
GCLK2P
GCLK0P
UG002_C2_090_113000
Figure 3-9:
DCM Clocks
The four clock pins (IBUFG) in a quadrant can feed all DCMs on the same edge of the device. The clock-to-out and setup times are identical for all DCMs. Up to four clock outputs per DCM can be used to drive any clock multiplexer on the same edge (top or bottom), as shown in Figure 3-10.
BUFG Exclusivity
Each DCM has a restriction on the number of BUFGs it can drive on its (top or bottom) edge. Pairs of buffers with shared dedicated routing resources exist such that only one buffer from each dedicated pair can be driven by a single DCM. The exclusive pairs for each edge are: 0:4, 1:5, 2:6, and 3:7.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
75
GCLK7P
GCLK6S
GCLK5P
GCLK4S
GCLK3P
GCLK2S
GCLK1P
GCLK0S
IBUFG
IBUFG
DCM
DCM
DCM
DCM
DCM
DCM
4 8 8
BUFGMUX
7P
6S
5P
4S
3P
2S
1P
0S
BUFGMUX
UG002_C2_091_080601
Figure 3-10:
DCM Clocks
Clock Output
The clock distribution is based on eight clock trees per quadrant. Each clock multiplexer output is driving one global clock net. The Virtex-II Pro/Virtex-II Pro X device has eight dedicated low-skew clock nets. The device is divided into four quadrants (NW, NE, SW and SE) with eight global clocks available per quadrant. Eight clock buffers are in the middle of the top edge and eight are in the middle of the bottom edge. Any of these 16 clock buffer outputs can be used in any quadrant, up to a maximum of eight clocks per quadrant, as illustrated in Figure 3-11, provided there is not a primary vs. secondary conflict.
8 BUFGMUX
NW
NE
8
NW
8 BUFGMUX
NE
8 max
16 Clocks
8
16 Clocks
SW
8 BUFGMUX
SE
SW
SE
8 BUFGMUX
DS031_45_120200
76
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Designs with more than eight clocks must be floorplanned manually or automatically, distributing the clocks in each quadrant. As an example, a design with 16 clocks can be floorplanned as shown in Figure 3-12.
CLK_ A B C D E F G H
NW
7P 5P CLK_C 6S 6S CLK_B 2S CLK_F 0P CLK_P 5 clocks CLK_K 5S CLK_D 8 clocks CLK_O 4S 1S CLK_N 2P CLK_B CLK_E 3P CLK_A CLK_I 7S CLK_H 0S
NE
7P
0S CLK_H CLK_M
3S
5P CLK_C CLK_J
6P
SW
CLK_ I J K L M N O P
SE
UG002_C2_079_120200
Figure 3-12:
16-Clock Floorplan
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
77
The clock nets and clock buffers in this example are associated as shown in Table 3-4. Table 3-4: Clock Net Association With Clock Buffers
Clock Net (top edge) BUFG Clock Net (bottom edge) BUFG Quadrant NW Quadrant SW Quadrant NE Quadrant SE
CLK_A is used in three quadrants, and the other clocks are used in one or two quadrants, regardless of the position of the clock buffers (multiplexers), as long as they are not competing to access the same quadrant. That is, CLK_A (BUFG7P) cannot be used in the same quadrant with CLK_I (BUFG7S). Refer to Primary/Secondary: Rule 1, page 73.) In other words, two buffers with the same index (0 to 7) cannot be used in the same quadrant. Each register, block RAM, registered multiplier, or DDR register (IOB) can be connected to any of the eight clock nets available in a particular quadrant. Note that if a global clock (primary buffer) is used in four quadrants, the corresponding secondary buffer is not available.
Power Consumption
Clock trees have been designed for low skew and low-power operation. Any unused branch is disconnected, as shown in Figure 3-13.
8 BUFGMUX
NW
6 4
2 2
2 2
16 Clocks 1
SW
SE
8 BUFGMUX
ug002_c2_093_113000
Figure 3-13:
78
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Also available to reduce overall power consumption are the BUFGCE feature, for dynamically driving a clock tree only when the corresponding module is used, and the BUFGMUX feature, for switching from a high-frequency clock to a low-frequency clock. The frequency synthesizer capability of the DCM can generate the low (or high) frequency clock from a single source clock, as illustrated in Figure 3-14. (See Digital Clock Managers (DCMs), page 89.)
DCM BUFGMUX 250 MHz CLKIN CLKFB (10) CLKDV 25 MHz I1 S BUFG
UG002_C2_094_121101
CLK0
250 MHz
I0 Clock Tree
Figure 3-14:
Refer to Single-Ended SelectIO-Ultra Resources, page 186 for a list of the attributes available for IBUFG and Refer to LVDS I/O, page 258 for a list of the attributes available for IBUFGDS. The submodules in Table 3-6 are available with the input, output, and control pins listed. Table 3-6: Clock Submodules Input I I Output O O Control CE CE
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
79
Primitive Functions
IBUFG
IBUFG is an input clock buffer with one clock input and one clock output.
IBUFGDS
IBUFGDS is a differential input clock buffer with two clock inputs (positive and negative polarity) and one clock output.
BUFG
All Virtex-II Pro/Virtex-II Pro X devices have 16 global clock buffers (each of which can be used as BUFG, BUFGMUX, or BUFGCE). BUFG is a global clock buffer with one clock input and one clock output, driving a lowskew clock distribution network. The output follows the input, as shown in Figure 3-15.
BUFG(I) BUFG(O)
UG002_C2_099_120100
Figure 3-15:
BUFG Waveforms
BUFGMUX I0 I1 S
DS083-2_63_121701
Figure 3-16:
80
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
selected clock; that is, prior to the rising edge of the BUFGMUX output O. Violating this setup time requirement can result in an undefined runt pulse output. Figure 3-17 shows a switch-over from CLK0 to CLK1.
Wait for Low S CLK 0 Switch CLK1 Out
DS083-2_46_121701
If CLK0 is currently High, the multiplexer waits for CLK0 to go Low. Once CLK0 is Low, the multiplexer output stays Low until CLK1 transitions High to Low. When CLK1 transitions from High to Low, the output switches to CLK1. No glitches or short pulses can appear on the output.
DS083-2_46a_121701
Figure 3-18:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
81
The current clock is CLK0. S is activated High. If CLK0 is currently Low, the multiplexer waits for CLK0 to go High. Once CLK0 is High, the multiplexer output stays High until CLK1 transitions Low to High. When CLK1 transitions from Low to High, the output switches to CLK1. No glitches or short pulses can appear on the output.
Submodules
BUFGCE and BUFGCE_1
BUFGCE and BUFGCE_1 are submodules based on BUFGMUX and BUFGMUX_1, respectively. BUFGCE and BUFGCE_1 are global clock buffers incorporating a smart enable function that avoids output glitches or runt pulses. The select signal must meet the setup time for the clock. BUFGCE is the preferred circuit for clocking on the rising edge, while BUFGCE_1 is preferred when clocking on the falling edge.
BUFGCE I CE
DS031_62_101200
Figure 3-19:
If the CE input is inactive (Low) prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. Any level change of CE during the incoming clock High time has no effect. CE must not change during a short setup window just prior to the rising clock edge on the BUFGCE_1 input I. Violating this setup time requirement can result in an undefined runt pulse output. This means the output stays Low when the clock is disabled, but it completes the clockHigh pulse when the clock is being disabled, as shown in Figure 3-20.
BUFGCE(I) BUFGCE(CE) BUFGCE(O)
Wait Low
UG002_C2_100_120100
Figure 3-20:
BUFGCE Waveforms
82
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Figure 3-21:
BUFGCE_1 Waveforms
When BUFGCE (or BUFGCE_1) is used with DCM outputs, a second BUFG can be used for clock feedback. Buffer sharing the inputs with BUFGCE is the preferred solution.
Summary
Table 3-7 shows the maximum resources available per Virtex-II Pro/Virtex-II Pro X device. Table 3-7: Resources per Device (from XC2VP2 to XC2VP100) Resource Single-ended IBUFG (pads) Differential IBUFGDS (pairs) BUFG (Global Clock Buffer) BUFGCE (or BUFGCE_1) BUFGMUX (or BUFGMUX_1) Maximum Number 16 8 16 8 8
Characteristics
The following are characteristics of global clocks in Virtex-II Pro/Virtex-II Pro X devices: Low-skew clock distribution. Synchronous glitch-free multiplexer that avoids runt pulses. Switching between two asynchronous clock sources is usually considered unsafe, but it is safe with the Virtex-II Pro/Virtex-II Pro X global clock multiplexer. Any level change on S must meet a setup time requirement with respect to the signal on the output O (rising edge for BUFGMUX, falling edge for BUFGMUX_1). Any level change on CE must meet a setup time requirement with respect to the signal on the Input I (rising edge for BUFGCE, falling edge for BUFGCE_1). Two BUFGMUX (or BUFGMUX_1) resources can be cascaded to create a 3 to 1 clock multiplexer.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
83
Location Constraints
BUFGMUX and BUFGMUX_1 (primitives) and IBUFG (IBUFGDS) instances can have LOC properties attached to them to constrain placement. The LOC properties use the following form to constrain a clock net:
INST clock_buffer_instance_name LOC=BUFGMUX#P/S;
Each clock pad (or IBUFG) has a direct connection with a specific global clock multiplexer (input I0). A placement that does not conform to this rule causes the software to send a warning. If the clock pad (or IBUFG) has LOC properties attached, the DCM allows place and route software maximum flexibility, as compared to a direct connection to the global clock buffer (BUFG).
As examples, the BUFGMUX_INST.vhd, BUFGMUX_1_INST.vhd, BUFGCE_SUBM.vhd, and BUFGCE_1_SUBM.vhd VHDL templates are shown. In addition, the BUFGMUX_INST.v, BUFGMUX_1_INST.v, BUFGCE_1_SUBM.v, and BUFGCE_SUBM.v Verilog templates are shown.
VHDL Template
-- Module: BUFGMUX_INST -- Description: VHDL instantiation template -- Global Clock Multiplexer (Switch Low) -- Device: Virtex-II Pro Family ---------------------------------------------------------------------- Component Declarations: -component BUFGMUX port ( I0 : in std_logic; I1 : in std_logic;
84
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
S O
); end component; --- Architecture section: --- Global Clock Buffer Instantiation U_BUFGMUX: BUFGMUX port map ( I0 => , -- insert clock input used when select (S) is Low I1 => , -- insert clock input used when select (S) is High S => , -- insert Mux-Select input O => -- insert clock output ); ----------------------------------------------------------------------- Module: BUFGMUX_1_INST -- Description: VHDL instantiation template -- Global Clock Multiplexer (Switch High) --- Device: Virtex-II Pro Family ---------------------------------------------------------------------- Component Declarations: component BUFGMUX_1 port ( I0 : in std_logic; I1 : in std_logic; S : in std_logic; O : out std_logic ); end component; --- Architecture section: --- Global Clock Buffer Instantiation U_BUFGMUX_1: BUFGMUX_1 port map ( I0 => , -- insert clock input used when select (S) is Low I1 => , -- insert clock input used when select (S) is High S => , -- insert Mux-Select input O => -- insert clock output ); ----------------------------------------------------------------------- Module: BUFGCE_SUBM -- Description: VHDL instantiation template -- Global Clock Buffer with Clock Enable: -- Input Clock Buffer to BUFGMUX - Clock disabled = Low -- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on --
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
85
entity BUFGCE_SUBM is port ( I: in std_logic; CE: in std_logic; O: out std_logic ); end BUFGCE_SUBM; -architecture BUFGCE_SUBM_arch of BUFGCE_SUBM is --- Component Declarations: component BUFGMUX port ( I0 : in std_logic; I1 : in std_logic; S : in std_logic; O : out std_logic ); end component; --- signal declarations signal GND : std_logic; signal CE_B : std_logic; -begin GND <= '0'; -CE_B <= not CE; --- Global Clock Buffer Instantiation U_BUFGMUX: BUFGMUX port map ( I0 => I, I1 => GND, S => CE_B, O => O ); -end BUFGCE_SUBM_arch; ---------------------------------------------------------------------- Module: BUFGCE_1_SUBM -- Description: VHDL instantiation template -- Global Clock Buffer with Clock Enable: -- Input Clock Buffer to BUFGMUX_1 - Clock disabled = High -- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -entity BUFGCE_1_SUBM is port ( I: in std_logic; CE: in std_logic; O: out std_logic
86
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
); end BUFGCE_1_SUBM; -architecture BUFGCE_1_SUBM_arch of BUFGCE_1_SUBM is --- Component Declarations: component BUFGMUX_1 port ( I0 : in std_logic; I1 : in std_logic; S : in std_logic; O : out std_logic ); end component; --- signal declarations signal VCC : std_logic; -signal CE_B : std_logic; -begin VCC <= '1'; -CE_B <= not CE; --- Global Clock Buffer Instantiation U_BUFGMUX_1: BUFGMUX_1 port map ( I0 => I, I1 => VCC, S => CE_B, O => O ); -end BUFGCE_1_SUBM_arch;
Verilog Template
//------------------------------------------------------------------// Module: BUFGMUX_INST // Description: Verilog Instantiation Template // Global Clock Multiplexer (Switch Low) // // // Device: Virtex-II Pro Family //------------------------------------------------------------------// //BUFGMUX Instantiation BUFGMUX U_BUFGMUX (.I0(), // insert clock input used when select(S) is Low .I1(), // insert clock input used when select(S) is High .S(), // insert Mux-Select input .O() // insert clock output ); //------------------------------------------------------------------// Module: BUFGMUX_1_INST // Description: Verilog Instantiation Template // Global Clock Multiplexer (Switch High) //
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
87
// // Device: Virtex-II Pro Family //------------------------------------------------------------------// //BUFGMUX_1 Instantiation BUFGMUX_1 U_BUFGMUX_1 (.I0(), // insert clock input used when select(S) is Low .I1(), // insert clock input used when select(S) is High .S(), // insert Mux-Select input .O() // insert clock output ); //------------------------------------------------------------------// Module: BUFGCE_SUBM // Description: Verilog Submodule // Global Clock Buffer with Clock Enable: // Input Clock Buffer to BUFGMUX - Clock disabled = Low // // Device: Virtex-II Pro Family //------------------------------------------------------------------module BUFGCE_SUBM (I, CE, O); input I, CE; output O;
wire GND; assign GND = 1'b0; BUFGMUX U_BUFGMUX (.I0(I), .I1(GND), .S(~CE), .O(O) ); // endmodule //------------------------------------------------------------------// Module: BUFGCE_1_SUBM // Description: Verilog Submodule // Global Clock Buffer with Clock Enable: // Input Clock Buffer to BUFGMUX_1 - Clock disabled = High // // Device: Virtex-II Pro Family //------------------------------------------------------------------module BUFGCE_1_SUBM (I, CE, O); input I, CE; output O;
88
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
89
Phase Shift Overflow (STATUS[0]) CLKIN Stopped (STATUS[1]) CLKFX Stopped (STATUS[2])
When using DCMs it is important to observe the VCCAUX recommended operating noise specification in the Data Sheet. Power distribution design details are available in Xilinx Application Note XAPP623.
Clock De-Skew
The Virtex-II Pro/Virtex-II Pro X Digital Clock Manager (DCM) offers a fully digital, dedicated on-chip de-skew circuit providing zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These features can be used to implement several circuits that improve and simplify system level design. Any four of the nine outputs of the DCM can be used to drive a global clock network. All DCM outputs can drive general interconnect at the same time; for example, DCM output can be used to generate board-level clocks. The well-buffered global clock distribution network minimizes clock skew caused by loading differences. By monitoring a sample of the output clock (CLK0), the de-skew circuit compensates for the delay on the routing network, effectively eliminating the delay from the external input port to the individual clock loads within the device. Figure 3-22 shows all of the inputs and outputs relevant to the DCM de-skew feature.
DCM
CLKIN CLKFB RST CLK0
Figure 3-22:
The de-skew feature can also act as a clock mirror. By driving the CLK0 output off-chip and then back in again, the de-skew feature can be used to de-skew a board-level clock serving multiple devices. Figure 3-23 shows an example.
90
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Virtex-II Pro Device IBUFG CLKIN CLKFB IBUFG DCM CLK0 CLK90 CLK180 CLK270 OBUF
CLK2X CLKDV
(1)
CLK2X CLKDV
(1)
RST
LOCKED
Non-Virtex-II Pro Chip Non-Virtex-II Pro Chip Other Non-Virtex-II Pro Chips
x132_10_020205
Figure 3-23:
Notes:
1. For a discussion of when to reset the DCM, see section External Feedback, page 93.
By taking advantage of the de-skew circuit to remove on-chip clock delay, the designer can greatly simplify and improve system level design involving high-fanout, highperformance clocks.
Operation
A de-skew circuit in its simplest form consists of variable delay line and control logic. The delay line produces a delayed version of the input clock (CLKIN). The clock distribution network routes the clock to all internal registers and to the clock feedback CLKFB pin. The control logic samples the input clock, as well as the feedback clock, and adjusts the delay line. For optimum performance, the Virtex-II Pro/Virtex-II Pro X DCM uses a discrete digital delay line, which is a series of buffer elements each with an intrinsic delay of less than DCM_TAP (see AC Characteristics in the Data Sheet). A de-skew circuit works by inserting delay between the input clock and the feedback clock until the two rising edges align, putting the two clocks 360 degrees out of phase, which means they are in phase. When the edges from the input clock line up with the edges from the feedback clock, the DCM achieves lock. The two clocks have no discernible
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
91
difference. Thus, the DCM output clock compensates for the delay in the clock distribution network, effectively removing the delay between the source clock and its loads.
92
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Output Clocks
Some restrictions apply regarding the connectivity of the output pins. The DCM clock outputs can each drive an OBUF, a global clock buffer BUFGMUX, or they can route directly to the clock input of a synchronous element. To use the dedicated routing, the DCM clock outputs should drive BUFGMUXs that are on the same edge (top or bottom) of the device. If the DCM and BUFGMUX are not on the same edge, local routing is used and the DCM might not deskew properly. Do not use the DCM output clock signals until after activation of the LOCKED signal. Prior to the activation of the LOCKED signal, the DCM output clocks are not valid and can exhibit glitches, spikes, or other spurious movement.
External Feedback
To ensure consistent locking, if a DCM is configured with external feedback, applying a reset after configuration is strongly recommended. For an optimum locking process, a DCM configured with external feedback requires both CLKIN and CLK0 to be present and stable when the DCM begins to lock. During configuration with external feedback, it is not possible to provide CLKFB in the beginning of the locking process. At the end of configuration, the DCM begins to lock once the device enters the startup sequence. Because a global 3-state signal (GTS) is still asserted during this time, the output I/O pins remain in a 3-state condition, effectively putting the CLKFB signal into a 3-state condition. When CLKFB eventually appears (after the GTS is deasserted), the DCM proceeds with the lock. However, it might not lock at the optimal point and can introduce slightly more jitter (as well as greater clock cycle latency) through the DCM. In addition, if CLKFB is coupling with another signal when it is put into a 3-state condition (a PCB signal integrity issue), the DCM might sense this invalid clock as CLKFB and use it to proceed with a lock. This second possibility can cause the DCM to not lock properly once the GTS deasserts and the true CLKFB signal is present. Use of reset after configuration guarantees that the locking process starts with a valid CLKIN and CLKFB signal and ensures consistent locking.
Notes:
1. The default value is -g LCK_cycle:NoWait and -g GTS_cycle:5. When these settings are used, the startup sequence does not wait for the DCM to lock. 2. If the startup sequence is altered (for example, using the BitGen option), the LCK_cycle (wait for DCM to lock) must not be placed before the GTS_cycle (de-assert GTS); otherwise, the DCM never locks and configuration does not complete. 3. HDL example code to reset the DCM after configuration are shown below. This example requires that GTS_cycle be set before GWE_cycle in the BitGen options (the default). This ensures that the DCM is reset after the I/O pins are activated.
Verilog Example: // DCM instantiation to show the reset connection DCM u_dcm1 (.CLKIN(clkin), .CLKFB(clkfb), .CLK0(clk0), .RST(rstin), .LOCKED(locked)); // rstin connects to RST pin of DCM assign rstin = (user_reset || config_rst);
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
93
// This is the actual reset circuit that outputs config_rst. It is a four-cycle shift register. FDS flop1 (.D(1'b0), .C(clkin), .Q(out1), .S(1'b0)); FD flop2 (.D(out1), .C(clkin), .Q(out2)); FD flop3 (.D(out2), .C(clkin), .Q(out3)); FD flop4 (.D(out3), .C(clkin), .Q(out4)); //config_rst will be asserted for 3 clock cycles. assign config_rst = (out2 | out3 | out4); VHDL Example: -- DCM instantiation to show the reset connection u_dcm1: DCM port map ( CLKIN => clkin, CLKFB => clkfb, CLK0 => clk0, RST => rstin, LOCKED => locked); -- rstin connects to RST pin of DCM rstin <= user_reset or config_rst; -- This is the actual reset circuit that outputs config_rst. It is a four-cycle shift register. flop1: FDS port map (D => '0', C => clkin, Q => out1, S => '0'); flop2: FD port map (D => out1, C => clkin, Q => out2); flop3: FD port map (D => out2, C => clkin, Q => out3); flop4: FD port map (D => out3, C => clkin, Q => out4); -- config_rst will be asserted for 3 clock cycles. config_rst <= out2 or out3 or out4;
94
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Cascading DCMs
Xilinx does not recommend cascading DCMs because jitter accumulates as a resultin other words, the output clock jitter of the second-stage DCM is worse than the output clock jitter of the first-stage DCM. If possible, use two DCMs in parallel instead of in series. If it is absolutely necessary to cascade DCMs, the following rules must be observed: The output jitter specifications for DLL outputs are provided in the data sheet. Use the Jitter Calculator to determine the jitter for CLKFX. If possible, avoid cascading CLKFX to CLKFX in high-frequency mode. In general, jitter accumulates based on the following equation:
Total Jitter =
( Jitter1 ) 2 + ( Jitter2 ) 2
The input and output frequency and jitter specifications for each DCM must be met. If the frequency of the DCM inputs allows it, use feedback for both DCMs. Use the LOCKED output from DCM1 to create a Reset for DCM2. The recommended length of a Reset pulse is three CLKIN cycles. The LOCKED signal from DCM1 could be inverted to LOCKED and used as the input to an SRL16, with the output of the SRL16 providing the Reset input to DCM2. Connect the output of DCM1 to CLKIN of DCM2 through a BUFG. Figure 3-24 illustrates this approach.
BUFG BUFG
DCM_BASE
DCM_BASE
CLKIN
CLKIN
Reset
CLK0 CLK90 DCM1 CLK180 CLK270 CLK2X CLKFB CLK2X180 CLKDV CLKFX CLKFX180 RESET LOCKED
INV
BUFG
srl_module
D CLK Q LOCKED
CLK0 CLK90 DCM2 CLK180 CLK270 CLK2X CLKFB CLK2X180 CLKDV CLKFX CLKFX180 RESET LOCKED CLKIN
CLKFX
BUFG
LOCK
UG012_c3_052_032807
Figure 3-24:
Cascading DCMs
It is recommended that R1 > R2, where: R1 = R2 = M/D ratio for DCM1 M/D ratio for DCM2
Port Signals
Source Clock Input CLKIN
The CLKIN pin provides the user source clock (the clock signal on which the de-skew circuit operates) to the DCM. The CLKIN frequency must fall in the ranges specified in the Data Sheet. The clock input signal can be provided by one of the following: IBUF Input buffer
IBUFG Global clock input buffer on the same edge of the device (top or bottom) BUFGMUX Internal global clock buffer
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
95
Note: When IBUF is used as the clock input, the PAD to DCM input skew is not compensated.
Refer to Table 3-1, page 72 for more information.
Status - STATUS
The STATUS output is an 8-bit output, of which STATUS[1] reveals the loss of the input clock, CLKIN to the DCM.
96
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Attributes
The following attributes provide access to some of the Virtex-II Pro/Virtex-II Pro X series de-skew features, (for example, clock division and duty cycle correction).
Frequency Mode
The de-skew feature of the DCM is achieved with a delay-locked loop (DLL). This attribute specifies either the high or low-frequency mode of the DLL. The default is low-frequency mode. In high-frequency mode, the only outputs available from the DLL are the CLK0, CLK180, CLKDV, and LOCKED. (CLK90, CLK270, CLK2X, and CLK2X180 are not available in high-frequency mode.) The frequency ranges for both frequency modes are specified in the Data Sheet. To set the DLL to high-frequency mode, attach the DLL_FREQUENCY_MODE=HIGH attribute in the source code or schematic.
Startup Delay
The default value of the STARTUP_WAIT attribute is FALSE. When STARTUP_WAIT is set to TRUE, and the LCK_cycle BitGen option is used, then the configuration startup sequence waits in the specified cycle until the DCM locks. For details, see Chapter 4, Configuration and Appendix A, BitGen and PROMGen Switches and Options.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
97
Legacy Support
The Virtex/Virtex-E library primitives/sub modules are supported in Virtex-II Pro/ Virtex-II Pro X for legacy purposes. The following are supported primitives/submodules: CLKDLL CLKDLLE CLKDLLHF BUFGDLL
Library Primitive
Only a single library primitive is available for the DLL, a part of the DCM. It is labeled the 'DCM' primitive.
Submodules
BUFGMUX clk_in CLKIN CLK0 clko_w clk1x
IO
DCM
CLKFB
UG002_C2_061_112800
Figure 3-25:
clk_in clk_in_w
BUFG_CLK0_SUBM
CLKIN
CLK0
clk1x_ext
clkfb clkfb_w
DCM0_ext
CLKFB
clk1x_int_w
DCM1_int
CLKFB "1"
UG002_C2_063_100901
Figure 3-26:
BUFG_CLK0_FB_SUBM
98
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
DCM
clkdiv_w CLKFB
"1" clk_div
IO
"1"
UG002_C2_065_110700
Figure 3-27:
BUFG_CLKDV_SUBM
Frequency Synthesis
The DCM provides several flexible methods for generating new clock frequencies. Each method has a different operating frequency range and different AC characteristics. The CLK2X and CLK2X180 outputs double the clock frequency. The CLKDV output provides divided output clocks with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16. The DCM also offers a fully digital, dedicated Frequency Synthesizer output (CLKFX) and its opposite phase (CLKFX180). The output frequency can be any function of the input clock frequency described by M D, where M is the multiplier (numerator) and D is the divisor (denominator). The two counter-phase frequency synthesized outputs can drive global clock routing networks within the device. The well-buffered global clock distribution network minimizes clock skew due to differences in distance or loading. See Figure 3-28.
DCM
CLKIN CLKFB RST CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED STATUS[7:0] clock signal control signal
ug002__c2_081_101101
Figure 3-28:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
99
Operation
The DCM clock output CLKFX is any M/D product of the clock input to the DCM. Specifications for M and D, as well as input and output frequency ranges for the frequency synthesizer, are provided in the Data Sheet. The frequency synthesizer output is phase aligned to the clock output, CLK0, only if feedback is provided to the CLKFB input of the DCM. The internal operation of the frequency synthesizer is complex and beyond the scope of this document. The frequency synthesizer multiplies the incoming frequencies by the precalculated quotient M/D and generates the correct output frequencies as long as it is within the range specified in the Data Sheet. For example, assume input frequency = 50 MHz, M = 25, and D = 8 (note that M and D values have no common factors and hence cannot be reduced). The output frequency is correctly 156.25 MHz, although 25 x 50 MHz = 1.25 GHz and 50 MHz / 8 = 6.25 MHz, and both of these values are far outside the range of the input frequency.
Port Signals
Source Clock Input CLKIN
The CLKIN pin provides the user source clock to the DCM. The CLKIN frequency must fall in the ranges specified in the Data Sheet. The clock input signal can be provided by one of the following: IBUF Input buffer IBUFG Global clock input buffer BUFGMUX Internal global clock buffer Note: When IBUF is used as the clock input, the PAD to DCM input skew is not compensated.
Refer to Table 3-1, page 72 for more information.
100
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
This feature provides automatic duty cycle correction such that the CLKDV output pin has a 50/50 duty cycle always in low-frequency mode, as well as for all integer values of the division factor N in high-frequency mode.
Status - STATUS
The STATUS output is an 8-bit output: STATUS[1] indicates the loss of the input clock, CLKIN, only when CLKFB is connected. STATUS[2] indicates loss of CLKFX and CLKFX180 even though LOCKED might still be High. Note that this CLKFX stopped status functions only when CLKIN is present.
Attributes
The following attributes provide access to some of the Virtex-II Pro/Virtex-II Pro X series frequency synthesis features, (for example, clock multiplication, clock division).
Clock Divide
The CLKDV_DIVIDE attribute specifies how the signal on the CLKDV pin is frequency divided with respect to the CLK0 pin. The values allowed for this attribute are 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, or 16; the default value is 2.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
101
To set the frequency synthesizer to high-frequency mode, attach the DFS_FREQUENCY_MODE=HIGH attribute in the source code or schematic.
Multiply/Divide Attribute
The M and D values can be set using the CLKFX_MULTIPLY and the CLKFX_DIVIDE attributes. The default settings are M = 4 and D = 1.
Startup Delay
The default value of the STARTUP_WAIT attribute is FALSE. When STARTUP_WAIT is set to TRUE, and the LCK_cycle BitGen option is used, then the configuration startup sequence waits in the specified cycle until the DCM locks. For details, see Chapter 4, Configuration and Appendix A, BitGen and PROMGen Switches and Options.
Submodules
clkfx_w clkfx
clk_in rst
CLKIN RST
CLKFX
DCM
CLKFX180 LOCKED clkfx180_w lock
"1" clkfx180
"1"
UG002_C2_074_110800
Figure 3-29:
BUFG_DFS_SUBM
clk_in
CLKIN
CLK0
clk1x_w
clk1x
"1"
CLKFB CLKFX clkfx_w clkfx
DCM
"1" rst
RST CLKFX180
clkfx180_w
clkfx180
UG002_C2_075_110800
102
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Phase Shifting
The DCM can also provide coarse and fine-grained phase shifting. The CLK0, CLK90, CLK180, and CLK270 outputs are each phase shifted by of the input clock period relative to each other, providing coarse phase control. Note that CLK90 and CLK270 are not available in high-frequency mode.
Operation
Figure 3-31 shows a block diagram of the DCM and all of the outputs affected by the circuitry of the phase shift feature.
DCM
CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV
Figure 3-31:
Fine-phase adjustment affects all nine DCM output clocks. When activated, the phase shift between the rising edges of CLKIN and CLKFB is a specified fraction of the input clock period. In variable mode, the PHASE_SHIFT value can also be dynamically incremented or decremented as determined by PSINCDEC synchronously to PSCLK, when the PSEN input is active. Figure 3-32 illustrates the effects of fine-phase shifting.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
103
CLKIN CLKOUT_PHASE_SHIFT CLKFB = FIXED (PS/256) x PERIODCLKIN (PS negative) (PS/256) x PERIODCLKIN (PS positive)
CLKFB
Figure 3-32:
The PHASE_SHIFT attribute is the numerator in the following equation: Phase Shift (ns) = (PHASE_SHIFT/256) * PERIODCLKIN The full range of this attribute is always -255 to +255, but its practical range varies with CLKIN frequency, as constrained by the FINE_SHIFT_RANGE component, which represents the total delay achievable by the phase shift delay line. Total delay is a function of the number of delay taps used in the circuit. Across process, voltage, and temperature, this absolute range is guaranteed to be as specified in the DCM Timing Parameters section of the Data Sheet. Absolute range (fixed mode) = FINE_SHIFT_RANGE Absolute range (variable mode) = FINE_SHIFT_RANGE/2 The reason for the difference between fixed and variable modes is as follows. For variable mode to allow symmetric, dynamic sweeps from -255/256 to +255/256, the DCM sets the "zero phase skew" point as the middle of the delay line, thus dividing the total delay line range in half. In fixed mode, since the PHASE_SHIFT value never changes after configuration, the entire delay line is available for insertion into either the CLKIN or CLKFB path (to create either positive or negative skew). Taking both of these components into consideration, the following are some usage examples: If PERIODCLKIN = two times FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 128, and in variable mode it is limited to 64. If PERIODCLKIN = FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 255, and in variable mode it is limited to 128. If PERIODCLKIN half of the FINE_SHIFT_RANGE, then PHASE_SHIFT is limited to 255 in either mode.
In variable mode, the phase factor can be changed by activating PSEN for one period of PSCLK. Increments or decrements to the phase factor can be made by setting the
104
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
PSINCDEC pin to a High or Low, respectively. When the de-skew circuit has completed an increment or decrement operation, the signal PSDONE goes High for a single PSCLK cycle. This indicates to the user that the next change may be made. The user interface and the physical implementation are different. The user interface describes the phase shift as a fraction of the clock period (N/256). The physical implementation adds the appropriate number of buffer stages (each DCM_TAP) to the clock delay. The DCM_TAP granularity limits the phase resolution at higher clock frequencies.
1/256
Therefore, assuming a typical DCM_TAP of 45 ps, at ~90 Mhz with an 11.11 ns period, the * CLKIN_Period is ~45 ps. At a frequency < approximately 90 MHz, 1/256 * CLKIN_Period > 45 ps; hence the minimum step size is limited by #1 above. At a frequency > approximately 90 MHz, 1/256 * CLKIN_Period < 45 ps; hence the minimum step size is limited by #2 above.
At any condition, regardless of the CLKIN frequency, the PHASE_SHIFT (PS) value is determined by the following equation: "desired phase shift" = (PS/256) * (CLKIN period) From this PS value, the DPS function of DCM will select the appropriate tap setting. This tap setting will vary across process, voltage, and temperature (PVT). For example, if CLKIN = 150 Mhz (6.67 ns period), and the "desired phase shift" = 680 ps: 0.680 = PS/256 * 6.67 PS = 26 (This will be the PHASE_SHIFT value.) The DCM_TAP of ~45 ps is only an approximation. The actual tap value can range from 30 ps to 60 ps at any given time, depending upon PVT. Hence, 10 tap steps does not always mean 10 * 45 ps = 450 ps. In addition, the DCM might not adjust to a new phase shift at every 1/256 phase shift increment if 1/256 * CLK_Period < DCM_TAP, because 1/256 is not equal to 1 tap. For example, when you change the PS value from "3" to "4", the DCM may not increment the phase shift if the current phase shift is closer to the ideal value when compared to the next tap at the PVT. In this case, the design consideration is that at any time, the DCM will find the closest phase shift given the PHASE_SHIFT attribute value. The error at this PHASE_SHIFT for a
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
105
simple case of using CLK0 will be CLKOUT_PER_JITT_0 + CLKIN_CLKFB_PHASE. This is specified in the datasheet. The DCM_TAP value is included in the output jitter specs along with random jitter introduced by the DCM and by the FPGA. Using a FIXED phase shift will allow the design to be within 5-10% of the desired phase shift point. If more accuracy is needed, use the VARIABLE mode to dial it in.
CLK0
BUFGMUX I0 I1 S RST
ug002_c2_106_102802
Figure 3-33:
Note: PAR might report a warning that the IBUFG (CLKIN)-to-BUFGMUX connection is not an
optimal connection and so does not use the fast connection between the two components. This warning can be safely ignored; in this case, a dedicated connection is not necessary for the IBUFG-BUFGMUX connection.
106
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Verilog Example:
//DCM instantiation DCM U_DCM ( .CLKIN(clkin), .CLKFB(clk0_new), .RST(rst), .CLK0(clk0), .LOCKED(locked) ); //BUFGMUX instantiation BUFGMUX U_BUFGMUX ( .O(clk0_new), .I0(clk0), .I1(clkin), .S(rst) );
VHDL Example:
-- DCM instantiation -U_DCM: DCM port map ( CLKIN => clkin, CLKFB => clk0_new, DSSEN => '0', PSCLK => '0', PSINCDEC => '0', RST => rst, CLK0 => clk0, LOCKED => locked); -- BUFGMUX instantiation -U_BUFGMUX: BUFGMUX( I0 => clk0 I1 => clkin, O => clk0_new);
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
107
10 ns
For frequency 100 MHz (period 10 ns), CLK0 PHASE_SHIFT = 0 255 covers the whole range of period. For frequency between 50-100 MHz (period 10-20 ns). At 50 MHz, use CLK0 PHASE_SHIFT= 0 127 for the first 10 ns. Use CLK180 with PHASE_SHIFT= 0 127 for the next 10 ns. For frequency between 25-50 MHz (period 20-40 ns). At 25 MHz, use CLK0 PHASE_SHIFT= 0 63 for the first 10 ns. Use CLK90 with PHASE_SHIFT= 0 63 for the next 10 ns. Use CLK180 with PHASE_SHIFT= 0 63 for the next 10 ns. Use CLK270 with PHASE_SHIFT= 0 63 for the last 10 ns. CLK0(100Mhz)
10 ns
10 ns
10 ns
CLK0(50Mhz)
CLK180(50Mhz)
CLK0(25Mhz)
CLK90(25Mhz)
CLK180(25Mhz)
CLK270(25Mhz)
ug002_c2_107_020705
Figure 3-34:
Port Signals
1x Clock Outputs CLK[0|90|180|270]
The 1x clock output pin CLK0 represents a delay-compensated version of the source clock (CLKIN) signal. In low-frequency mode, the DCM provides three phase-shifted versions of the CLK0 signal (CLK90, CLK180, and CLK270), whereas in high-frequency mode, only the 180 phase-shifted version is provided. All four (including CLK0) of the phase shifted outputs can be used simultaneously in low-frequency mode. The relationship between phase shift and the corresponding period shift appears in Table 3-8. The timing diagrams in Figure 3-35 illustrate the DLL clock output characteristics. Table 3-8: Relationship of Phase-Shifted Output Clock to Period Shift % Period Shift 0% 25% 50% 75% 0 90 180 270
Phase (degrees)
108
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Setting DUTY_CYCLE_CORRECTION=FALSE dectivates duty cycle correction for the DCM outputs listed above. It is strongly recommended to always set the DUTY_CYCLE_CORRECTION attribute to TRUE (default value). Note that setting this attribute to FALSE does not necessarily produce output clocks with the same duty cycle as the source clock. The DCM clock outputs can drive an OBUF, a BUFGMUX, or they can route directly to the clock input of a synchronous element.
0 90 180 270 0 90 180 270
t CLKIN CLK2X CLKDV_DIVIDE=2 CLKDV DUTY_CYCLE_CORRECTION=FALSE CLK0 CLK90 CLK180 CLK270 DUTY_CYCLE_CORRECTION=TRUE CLK0 CLK90 CLK180 CLK270
x132_07_092599
Figure 3-35:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
109
110
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Status - STATUS
STATUS[0] indicates the overflow of the phase shift numerator (when DCM is phase shifted beyond +255 or -255) and that the absolute delay range of the phase shift delay line is exceeded.
Attributes
The following attributes provide access to the Virtex-II Pro/Virtex-II Pro X fine-phase adjustment capability.
PHASE_SHIFT
This attribute specifies the phase shift numerator as any value from -255 to 255. This attribute can be used with both fixed and variable phase shift mode. If used with variable mode, the attribute sets the starting phase shift. .
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
111
Submodules
DCM
clk_in CLKIN CLK0 clk0_w
IO
PSCLK
PSDONE
psdone
ioUG002_C2_076_112900
clk_in
DCM
CLKIN CLKFB rst RST LOCKED CLK0
clk0_w
clk1x
"1" lock
psindec
PSINCDEC
psen
Figure 3-37:
BUFG_PHASE_CLK0_SUBM
112
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
clk_in
DCM
CLKIN CLKFB rst RST CLKDV CLK0
clk0_w
clk1x
"1" clk_div
psindec
PSINCDEC
psen
PSEN
LOCKED
lock psdone
UG002_C2_073_101201
PSCLK PSDONE
Figure 3-38:
BUFG_PHASE_CLKDV_SUBM
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
113
CLKFX_DIVIDE CLKFX_MULTIPLY CLKIN_PERIOD This specifies the source clock period to help DCM adjust for optimum CLKFX/CLKFX180 outputs. This attribute allows for the input clock frequency to be divided in half when such a reduction is necessary to meet the DCM input clock frequency requirements. This controls the use of the PHASE_SHIFT value. This affects the amount of delay in the feedback path, and should be used for source-synchronous interfaces. [See the Clock De-Skew section.] This specifies the frequency mode of the frequency synthesizer. This specifies the DLLs frequency mode. CLK90, CLK270, CLK2X, and CLK2X180 are not available in high-frequency mode.
1 4 0.0
CLKIN_DIVIDE_BY_2
FALSE
CLKOUT_PHASE_SHIFT DESKEW_ADJUST
String: NONE or FIXED or VARIABLE String: SYSTEM_SYNCHRONOUS or SOURCE_SYNCHRONOUS or 0 to 15 String: LOW or HIGH
NONE SYSTEM_SYNCHRONOUS
DFS_FREQUENCY_MODE
LOW
DLL_FREQUENCY_MODE
LOW
114
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-9:
DUTY_CYCLE_CORRECTION This controls the DCM of 1X outputs (CLK0, CLK90, CLK180, and CLK270), such that they exhibit a 50/50 duty cycle. Leave this attribute set at the default value (TRUE). DSS_MODE FACTORY_JF PHASE_SHIFT STARTUP_WAIT Unsupported feature. Leave the value at default. This attribute is fixed unless recommended otherwise. This specifies the phase shift numerator. When this attribute is set to TRUE, the configuration startup sequence waits in the specified cycle until the DCM locks.
For more information on applying these attributes in UCF, VHDL, or Verilog code, refer to the Constraints Guide at: http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm.
The corresponding submodules must be synthesized with the design. The BUFG_CLK0_SUBM submodule is provided in VHDL and Verilog as an example.
VHDL Template
-- Module: BUFG_CLK0_SUBM -- Description: VHDL submodule
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
115
-- DCM with CLK0 deskew -- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -entity BUFG_CLK0_SUBM is port ( CLK_IN : in std_logic; RST : in std_logic; CLK1X : out std_logic; LOCK : out std_logic ); end BUFG_CLK0_SUBM; -architecture BUFG_CLK0_SUBM_arch of BUFG_CLK0_SUBM is -- Components Declarations: component BUFG port ( I : in std_logic; O : out std_logic ); end component; component DCM -- pragma translate_off generic ( DLL_FREQUENCY_MODE : string := "LOW"; DUTY_CYCLE_CORRECTION : boolean := TRUE; STARTUP_WAIT : boolean := FALSE ); -- pragma translate_on port ( CLKIN : in std_logic; CLKFB : in std_logic; DSSEN : in std_logic; PSINCDEC : in std_logic; PSEN : in std_logic; PSCLK : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector(7 downto 0) ); end component; -- Attributes attribute DLL_FREQUENCY_MODE : string;
116
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
attribute DUTY_CYCLE_CORRECTION : string; attribute STARTUP_WAIT : string; attribute DLL_FREQUENCY_MODE of U_DCM: label is "LOW"; attribute DUTY_CYCLE_CORRECTION of U_DCM: label is "TRUE"; attribute STARTUP_WAIT of U_DCM: label is "FALSE"; -- Signal Declarations: signal GND : std_logic; signal CLK0_W: std_logic; signal CLK1X_W: std_logic; begin GND <= '0'; CLK1X <= CLK1X_W; -- DCM Instantiation U_DCM: DCM port map ( CLKIN => CLK_IN, CLKFB => CLK1X_W, DSSEN => GND, PSINCDEC => GND, PSEN => GND, PSCLK => GND, RST => RST, CLK0 => CLK0_W, LOCKED => LOCK ); -- BUFG Instantiation U_BUFG: BUFG port map ( I => CLK0_W, O => CLK1X_W ); end BUFG_CLK0_SUBM_arch;
Verilog Template
// Module: BUFG_CLK0_SUBM // Description: Verilog Submodule // DCM with CLK0 deskew // // Device: Virtex-II Pro Family //------------------------------------------------------------------module BUFG_CKL0_SUBM ( CLK_IN, RST, CLK1X, LOCK ); input CLK_IN; input RST; output CLK1X; output LOCK; wire CLK0_W; wire GND; assign GND = 1'b0;
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
117
//BUFG Instantiation // BUFG U_BUFG (.I(CLK0_W), .O(CLK1X) ); // Attributes for functional simulation// // synopsys translate_off defparam U_DCM.DLL_FREQUENCY_MODE = "LOW"; defparam U_DCM.DUTY_CYCLE_CORRECTION = "TRUE"; defparam U_DCM.STARTUP_WAIT = "FALSE"; // synopsys translate_on // Instantiate the DCM primitive// DCM U_DCM ( .CLKFB(CLK1X), .CLKIN(CLK_IN), .DSSEN(GND), .PSCLK(GND), .PSEN(GND), .PSINCDEC(GND), .RST(RST), .CLK0(CLK0_W), .LOCKED(LOCK) ); // synthesis attribute declarations /* synopsys attribute DLL_FREQUENCY_MODE "LOW" DUTY_CYCLE_CORRECTION "TRUE" STARTUP_WAIT "FALSE" */ endmodule
118
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
DCM Waveforms
The DCM waveforms shown below are the results of functional simulation using Model Technology's ModelSim EE/Plus 5.3a_p1 simulator. Note that the time scale for these simulations were set to 1ns/1ps. It is important to set the unused inputs of the DCM to logic 0 and to set the attribute values to the correct data types. For example, the PHASE_SHIFT, CLKFX_DIVIDE, and CLKFX_MULTIPLY attributes are integers and should be set to values as shown.
defparam U_DCM.DFS_FREQUENCY_MODE = LOW; defparam U_DCM.CLKFX_DIVIDE = 1; (this values range is specified under Frequency Synthesis in the Virtex-II Pro Data Sheet) defparam U_DCM.CLKFX_MULTIPLY = 4; (this values range is specified under Frequency Synthesis in the Virtex-II Pro Data Sheet) defparam U_DCM.CLKOUT_PHASE_SHIFT = FIXED; defparam U_DCM.PHASE_SHIFT = 150; (Any value from 1 to 255) defparam U_DCM.STARTUP_WAIT = FALSE;
The input clock, 'clk_in' (CLKIN input of DCM) in all these waveforms is 50 MHz. The DCM_DLL waveforms in Figure 3-39 shows four DCM outputs, namely, clk1x (CLK0 output of DCM), clk2x (CLK2X output of DCM), clk90 (CLK90 output of DCM), and clk180 (CLK180 output of DCM).
ug002_c2_095_113000
Figure 3-39:
DCM_DLL Waveforms
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
119
The DCM_DFS Waveforms in Figure 3-40 shows four DCM outputs namely, clk1x (CLK0 output of DCM), clk2x (CLK2X output of DCM), clkfx (CLKFX output of DCM), and clkfx180 (CLKFX180 output of DCM). In this case the attributes, CLKFX_DIVIDE = 1, and the CLKFX_MULTIPLY = 3.
ug002_c2_096_113000
Figure 3-40:
DCM_DFS Waveforms
120
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The DCM_DPS waveforms in Figure 3-41 shows four DCM outputs, namely, clk1x (CLK0 output of DCM), clk2x (CLK2X output of DCM), clk90 (CLK90 output of DCM), and clk180 (CLK180 output of DCM). In this case, the attribute PHASE_SHIFT = 150 which translates to a phase shift of (150 x 20 ns)/256 = 11.719 ns, where 20 ns is the clock period.
Figure 3-41:
DCM_DPS Waveforms
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
121
The DCM_DPS_DFS waveforms in Figure 3-42 shows four DCM outputs namely, clk1x (CLK0 output of DCM), clk90 (CLK90 output of DCM), clkfx (CLKFX output of DCM), and clkfx180 (CLKFX180 output of DCM). In this case, the attributes, CLKFX_DIVIDE = 1, and the CLKFX_MULTIPLY = 4. The attribute, PHASE_SHIFT = 150 which translates to a phase shift of (150 x 20 ns)/256 = 11.719 ns, where 20 ns is the clock period..
ug002_c2_098_113000
Figure 3-42:
DCM_DPS_DFS Waveforms
122
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Port A
DOA DOPA
DOB DOPB
Port B
Figure 3-43:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
123
As described below, there are three options for the behavior of the data output during a write operation on its port. There is no dedicated monitor to arbitrate the result of identical addresses on both ports. It is up to the user to time the two clocks appropriately. However, conflicting simultaneous writes to the same location never cause any physical damage. When a block RAM port is enabled, all address transitions must meet the setup/hold time of the ADDR inputs with respect to the port clock, as listed in the Virtex-II Pro Data Sheet. The requirement must be met even when the read data output is of no interest and ignored by the user.
Operating Modes
To maximize utilization of the True Dual-Port memory at each clock edge, the block SelectRAM memory supports three different write modes for each port. The read during write mode offers the flexibility of using the data output bus during a write operation on the same port. Output behavior is determined by the configuration. This choice increases the efficiency of block SelectRAM memory at each clock cycle and allows designs that use maximum bandwidth.
Read Operation
The read operation uses one clock edge. The read address is registered on the read port, and the stored data is loaded into the output latches after the RAM access interval passes.
Write Operations
A write operation is a single clock-edge operation. The write address is registered on the write port, and the data input is stored in memory. Three different modes are used to determine data available on the output latches after a write clock edge.
aa
bb
cc
dd
MEM(aa)
1111
2222
MEM(dd)
DS031_19_040400
Figure 3-44:
124
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
aa
bb
cc
dd
MEM(aa)
old MEM(bb)
old MEM(cc)
MEM(dd)
DS031_18_040400
Figure 3-45:
NO_CHANGE Mode
In NO_CHANGE mode, the output latches remain unchanged during a write operation. As shown in Figure 3-46, data output is still the last read data and is unaffected by a write operation on the same port. Mode selection is set by configuration. One of these three modes is set individually for each port by an attribute. The default mode is WRITE_FIRST.
aa
bb
cc
dd
MEM(aa)
MEM(dd)
DS031_17_040400
Figure 3-46:
Conflict Resolution
Virtex-II Pro/Virtex-II Pro X block SelectRAM memory is a True Dual-Port RAM that allows both ports to simultaneously access the same memory cell. When one port writes to a given memory cell, the other port must not address that memory cell (for a write or a
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
125
read) within the clock-to-clock setup window. Figure 3-47 describes this asynchronous operation.
B A B A READ Port
aa bb
WRITE Port
MEM(aa)= 3333
MEM(bb)= 4444
MEM(cc)= 2222
UG002_C2_026_081800
Figure 3-47:
READ-WRITE Conditions
If port A and port B are configured with different widths, only the overlapping bits are invalid when conflicts occur.
Asynchronous Clocks
The first CLK_A clock edge violates the clock-to-clock setup parameter, because it occurs too soon after the last CLK_B clock edge. The write operation on port B is valid, and the read operation on port A is invalid. At the second rising edge of the CLK_B pin, the write operation is valid. The memory location (bb) contains 4444. The second rising edge of CLK_A reads the new data at the same location (bb), which now contains 4444. The clock-to-clock setup timing parameter is specified together with other block SelectRAM switching characteristics in the Data Sheet.
Synchronous Clocks
When both clocks are synchronous or identical, the result of simultaneous accesses from both ports to the same memory cell is best described in words: If both ports read simultaneously from the same memory cell: Both Data_out ports will have the same data. If both ports write simultaneously into the same memory cell: The data stored in that cell becomes invalid (unless both ports write identical data). If one port writes and the other port reads from the same memory cell: The write operation succeeds, and the data to be read out from the read port will be determined by the read output mode (write_first, read_first, or no_change). If the write port is in read_first mode, the read port's Data_out represents the previous content of the memory cell. If the write port is in write_first mode or in no_change
126
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
mode, the read port's Data_out becomes invalid. Obviously, the read port's mode setting does not affect this operation.
Characteristics
A write operation requires only one clock edge. A read operation requires only one clock edge. All inputs are registered with the port clock and have a setup-to-clock timing specification. All outputs have a read-through function or one of three read-during-write functions, depending on the state of the WE pin. The outputs relative to the port clock are available after the clock-to-out timing interval. Block SelectRAM cells are true synchronous RAM memories and do not have a combinatorial path from the address to the output. The ports are completely independent of each other (that is, clocking, control, address, read/write functions, initialization, and data width) without arbitration. Output ports are latched with a self-timed circuit, guaranteeing glitch-free reads. The state of the output port does not change until the port executes another read or write operation. Data input and output signals are always buses; that is, in a 1-bit width configuration, the data input signal is DI[0] and the data output signal is DO[0].
Library Primitives
The input and output data buses are represented by two buses for 9-bit width (8+1), 18-bit width (16+2), and 36-bit width (32+4) configurations. The ninth bit associated with each byte can store parity or error correction bits. No specific function is performed on this bit. The separate bus for parity bits facilitates some designs. However, other designs safely use a 9-bit, 18-bit, or 36-bit bus by merging the regular data bus with the parity bus. Read/write and storage operations are identical for all bits, including the parity bits.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
127
Figure 3-48 shows the generic dual-port block RAM primitive. DIA, DIPA, ADDRA, DOA, DOPA, and the corresponding signals on port B are buses.
RAMB16_S#_S# DIA[#:0] DIPA[#:0] ADDRA[#:0] WEA ENA SSRA CLKA DOA[#:0] DOPA[#:0]
DS031_20_040500
Figure 3-48:
128
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-10 lists the available dual-port primitives for synthesis and simulation. Table 3-10: Dual-Port Block RAM Primitives Port A Width 1 Port B Width 1 2 4 (8+1) (16+2) (32+4) 2 2 4 (8+1) (16+2) (32+4) 4 4 (8+1) (16+2) (32+4) (8+1) (8+1) (16+2) (32+4) (16+2) (16+2) (32+4) (32+4) (32+4)
Primitive RAMB16_S1_S1 RAMB16_S1_S2 RAMB16_S1_S4 RAMB16_S1_S9 RAMB16_S1_S18 RAMB16_S1_S36 RAMB16_S2_S2 RAMB16_S2_S4 RAMB16_S2_S9 RAMB16_S2_S18 RAMB16_S2_S36 RAMB16_S4_S4 RAMB16_S4_S9 RAMB16_S4_S18 RAMB16_S4_S36 RAMB16_S9_S9 RAMB16_S9_S18 RAMB16_S9_S36 RAMB16_S18_S18 RAMB16_S18_S36 RAMB16_S36_S36
Figure 3-49 shows the generic single-port block RAM primitive. DI, DIP, ADDR, DO, and DOP are buses.
RAMB16_S# DI[#:0] DIP[#:0] ADDR[#:0] WE EN SSR CLK DO[#:0] DOP[#:0]
DS031_21_040500
Figure 3-49:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
129
Table 3-11 lists all of the available single-port primitives for synthesis and simulation. Table 3-11: Single-Port Block RAM Primitives Primitive RAMB16_S1 RAMB16_S2 RAMB16_S4 RAMB16_S9 RAMB16_S18 RAMB16_S36 Port Width 1 2 4 (8+1) (16+2) (32+4)
Port Signals
Each block SelectRAM port operates independently of the other while accessing the same set of 18K-bit memory cells.
Clock - CLK[A|B]
Each port is fully synchronous with independent clock pins. All port input pins have setup time referenced to the port CLK pin. The data bus has a clock-to-out time referenced to the CLK pin. Clock polarity is configurable (rising edge by default).
Enable - EN[A|B]
The enable pin affects the read, write, and set/reset functionality of the port. Ports with an inactive enable pin keep the output pins in the previous state and do not write data to the memory cells. Enable polarity is configurable (active High by default).
130
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Set/Reset - SSR[A|B]
The SSR pin forces the data output latches to contain the value SRVAL (see Attributes, page 132). The data output latches are synchronously asserted to 0 or 1, including the parity bit. In a 36-bit width configuration, each port has an independent SRVAL[A|B] attribute of 36 bits. This operation does not affect RAM memory cells and does not disturb write operations on the other port. Like the read and write operation, the set/reset function is active only when the enable pin of the port is active. Set/reset polarity is configurable (active High by default).
Unused Inputs
Non-connected Data and/or address inputs should be connected to logic 1.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
131
GSR
The global set/reset (GSR) signal of a Virtex-II Pro/Virtex-II Pro X device is an asynchronous global signal that is active at the end of device configuration. The GSR can also restore the initial state at any time. The GSR signal initializes the output latches to the INIT, or to the INIT_A and INIT_B value (see Attributes). A GSR signal has no impact on internal memory contents. Because it is a global signal, the GSR has no input pin at the functional level (block SelectRAM primitive).
Address Mapping
Each port accesses the same set of 18,432 memory cells using an addressing scheme dependent on the width of the port. The physical RAM locations addressed for a particular width are determined using the following formula (of interest only when the two ports use different aspect ratios): END = ((ADDR + 1) * Width) -1 START= ADDR * Width Table 3-13 shows low-order address mapping for each port width. Table 3-13: Port Address Mapping
Data Locations 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 15 7 3 2 1 0 1 0 0 3 1 0 14 13 6 12 11 5 2 10 9 4 8 7 3 1 0 6 11 5 2 10 9 8 7 6 5 4 3 2 1 0 4 3 1 0 2 1 0 0
Attributes
Content Initialization - INIT_xx
INIT_xx attributes define the initial memory contents. By default block SelectRAM memory is initialized with all zeros during the device configuration sequence. The 64 initialization attributes from INIT_00 through INIT_3F represent the regular memory contents. Each INIT_xx is a 64-digit hex-encoded bit vector. The memory contents can be partially initialized and are automatically completed with zeros. The following formula is used for determining the bit positions for each INIT_xx attribute. Given yy = conversion hex-encoded to decimal (xx), INIT_xx corresponds to the memory cells as follows: from [(yy + 1) * 256] -1 to (yy) * 256
For example, for the attribute INIT_1F, the conversion is as follows: yy = conversion hex-encoded to decimal X1F = 31 from [(31+1) * 256] -1 = 8191 to 31 * 256 = 7936
132
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
More examples are given in Table 3-14. Table 3-14: Block SelectRAM Initialization Attributes Memory Cell Attribute from
INIT_00 INIT_01 INIT_02 INIT_0E INIT_0F INIT_10 INIT_1F INIT_20 INIT_2F INIT_30 .. INIT_3F 255 511 767 3839 4095 4351 8191 8447 12287 12543 16383
to
0 256 512 3584 3840 4096 7936 8192 12032 12288 16128
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
133
Table 3-15:
Location Constraints
Block SelectRAM instances can have LOC properties attached to them to constrain placement. Block SelectRAM placement locations differ from the convention used for naming CLB locations, allowing LOC properties to transfer easily from array to array. The LOC properties use the following form: LOC = RAMB16_X#Y# The RAMB16_X0Y0 is the bottom-left block SelectRAM location on the device.
Applications
Creating Larger RAM Structures
Block SelectRAM columns have specialized routing to allow cascading blocks with minimal routing delays. Wider or deeper RAM structures are achieved with a smaller timing penalty than is encountered when using normal routing resources. The CORE Generator program offers the designer a painless way to generate wider and deeper memory structures using multiple block SelectRAM instances. This program outputs VHDL or Verilog instantiation templates and simulation models, along with an EDIF file for inclusion in a design.
134
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The following are dual-port templates: SelectRAM_A1_B1 SelectRAM_A1_B2 SelectRAM_A1_B4 SelectRAM_A1_B9 SelectRAM_A1_B18 SelectRAM_A1_B36 SelectRAM_A2_B2 SelectRAM_A2_B4 SelectRAM_A2_B9 SelectRAM_A2_B18 SelectRAM_A2_B36 SelectRAM_A4_B4 SelectRAM_A4_B9 SelectRAM_A4_B18 SelectRAM_A4_B36 SelectRAM_A9_B9 SelectRAM_A9_B18 SelectRAM_A9_B36 SelectRAM_A18_B18 SelectRAM_A18_B36 SelectRAM_A36_B36
VHDL Template
As an example, the XC2V_RAMB_1_PORT.vhd file uses the SelectRAM_A36 template:
-- Module: XC2V_RAMB_1_PORT -- Description: 18Kb Block SelectRAM example -- Single Port 512 x 36 bits -- Use template SelectRAM_A36.vhd" --- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all;
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
135
--- Syntax for Synopsys FPGA Express -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -entity XC2V_RAMB_1_PORT is port ( DATA_IN : in std_logic_vector (35 downto 0); ADDRESS : in std_logic_vector (8 downto 0); ENABLE: in std_logic; WRITE_EN : in std_logic; SET_RESET : in std_logic; CLK : in std_logic; DATA_OUT : out std_logic_vector (35 downto 0) ); end XC2V_RAMB_1_PORT; -architecture XC2V_RAMB_1_PORT_arch of XC2V_RAMB_1_PORT is --- Components Declarations: -component BUFG port ( I : in std_logic; O : out std_logic ); end component; --- Syntax for Synopsys FPGA Express component RAMB16_S36 -- pragma translate_off generic ( -- "Read during Write" attribute for functional simulation WRITE_MODE : string := "READ_FIRST" ; -- WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE -- Output value after configuration INIT : bit_vector(35 downto 0) := X"000000000"; -- Output value if SSR active SRVAL : bit_vector(35 downto 0) := X"012345678"; -- Plus bits initial content INITP_00 : bit_vector(255 downto 0) := X"000000000000000000000000000000000000000000000000FEDCBA9876543210"; INITP_01 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; -- Regular bits initial content
136
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
INIT_00 : bit_vector(255 downto 0) := X"000000000000000000000000000000000000000000000000FEDCBA9876543210"; INIT_01 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; ... (cut) INIT_3E : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- pragma translate_on port ( DI : in std_logic_vector (31 downto 0); DIP : in std_logic_vector (3 downto 0); ADDR : in std_logic_vector (8 downto 0); EN : in STD_LOGIC; WE : in STD_LOGIC; SSR : in STD_LOGIC; CLK : in STD_LOGIC; DO : out std_logic_vector (31 downto 0); DOP : out std_logic_vector (3 downto 0) ); end component; --- Attribute Declarations: attribute WRITE_MODE : string; attribute INIT: string; attribute SRVAL: string; -attribute INITP_00: string; attribute INITP_01: string; attribute INITP_02: string; attribute INITP_03: string; attribute INITP_04: string; attribute INITP_05: string; attribute INITP_06: string; attribute INITP_07: string; -attribute INIT_00: string; attribute INIT_01: string; attribute INIT_02: string; (cut) attribute INIT_3E: string; attribute INIT_3F: string; --- Attribute "Read during Write mode" = WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE attribute WRITE_MODE of U_RAMB16_S36: label is "READ_FIRST"; attribute INIT of U_RAMB16_S36: label is "000000000"; attribute SRVAL of U_RAMB16_S36: label is "012345678"; --- RAMB16 memory initialization for Alliance -- Default value is "0" / Partial initialization strings are padded -- with zeros to the left attribute INITP_00 of U_RAMB16_S36: label is "000000000000000000000000000000000000000000000000FEDCBA9876543210";
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
137
attribute INITP_01 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_02 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_03 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_04 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_05 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_06 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_07 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; -attribute INIT_00 of U_RAMB16_S36: label is "000000000000000000000000000000000000000000000000FEDCBA9876543210"; attribute INIT_01 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_02 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; ... (cut) attribute INIT_3E of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3F of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; ---- Signal Declarations: --- signal VCC : std_logic; -- signal GND : std_logic; signal CLK_BUFG: std_logic; signal INV_SET_RESET : std_logic; -begin -- VCC <= '1'; -- GND <= '0'; --- Instantiate the clock Buffer U_BUFG: BUFG port map ( I => CLK, O => CLK_BUFG ); --- Use of the free inverter on SSR pin INV_SET_RESET <= NOT SET_RESET; -- Block SelectRAM Instantiation U_RAMB16_S36: RAMB16_S36 port map ( DI => DATA_IN (31 downto 0), -- insert 32 bits data-in bus (<31 downto 0>) DIP => DATA_IN (35 downto 32), -- insert 4 bits parity datain bus (or <35 downto 32>) ADDR => ADDRESS (8 downto 0), -- insert 9 bits address bus EN => ENABLE, -- insert enable signal WE => WRITE_EN, -- insert write enable signal
138
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
SSR => INV_SET_RESET, -- insert set/reset signal CLK => CLK_BUFG, -- insert clock signal DO => DATA_OUT (31 downto 0), -- insert 32 bits data-out bus (<31 downto 0>) DOP => DATA_OUT (35 downto 32) -- insert 4 bits parity dataout bus (or <35 downto 32>) ); -end XC2V_RAMB_1_PORT_arch; ---------------------------------------------------------------------
Verilog Template
// Module: XC2V_RAMB_1_PORT // Description: 18Kb Block SelectRAM-II example // Single Port 512 x 36 bits // Use template "SelectRAM_A36.v" // // Device: Virtex-II Pro Family //------------------------------------------------------------------module XC2V_RAMB_1_PORT (CLK, SET_RESET, ENABLE, WRITE_EN, ADDRESS, DATA_IN, DATA_OUT);
input CLK, SET_RESET, ENABLE, WRITE_EN; input [35:0] DATA_IN; input [8:0] ADDRESS; output [35:0] DATA_OUT; wire CLK_BUFG, INV_SET_RESET; //Use of the free inverter on SSR pin assign INV_SET_RESET = ~SET_RESET;
// initialize block ram for simulation // synopsys translate_off defparam //Read during Write attribute for functional simulation U_RAMB16_S36.WRITE_MODE = READ_FIRST, //WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE //Output value after configuration U_RAMB16_S36.INIT = 36'h000000000, //Output value if SSR active U_RAMB16_S36.SRVAL = 36'h012345678, //Plus bits initial content U_RAMB16_S36.INITP_00 = 256'h0123456789ABCDEF000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
139
U_RAMB16_S36.INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000, //Regular bits initial content U_RAMB16_S36.INIT_00 = 256'h0123456789ABCDEF000000000000000000000000000000000000000000000000, U_RAMB16_S36.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000, ...<cut> U_RAMB16_S36.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on //Instantiate the clock Buffer BUFG U_BUFG ( .I(CLK), .O(CLK_BUFG)); //Block SelectRAM Instantiation RAMB16_S36 U_RAMB16_S36 ( .DI(DATA_IN[31:0]), .DIP(DATA_IN-PARITY[35:32]), .ADDR(ADDRESS), .EN(ENABLE), .WE(WRITE_EN), .SSR(INV_SET_RESET), .CLK(CLK_BUFG), .DO(DATA_OUT[31:0]), .DOP(DATA_OUT-PARITY[35:32])); // synthesis attribute declarations /* synopsys attribute WRITE_MODE "READ_FIRST" INIT "000000000" SRVAL "012345678" INITP_00 "0123456789ABCDEF000000000000000000000000000000000000000000000000" INITP_01 "0000000000000000000000000000000000000000000000000000000000000000" INITP_02 "0000000000000000000000000000000000000000000000000000000000000000" INITP_03 "0000000000000000000000000000000000000000000000000000000000000000" INITP_04 "0000000000000000000000000000000000000000000000000000000000000000" INITP_05 "0000000000000000000000000000000000000000000000000000000000000000" INITP_06 "0000000000000000000000000000000000000000000000000000000000000000" INITP_07 "0000000000000000000000000000000000000000000000000000000000000000"
140
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
INIT_00 "0123456789ABCDEF000000000000000000000000000000000000000000000000" INIT_01 "0000000000000000000000000000000000000000000000000000000000000000" INIT_02 "0000000000000000000000000000000000000000000000000000000000000000" ...<cut> INIT_3E "0000000000000000000000000000000000000000000000000000000000000000" INIT_3F "0000000000000000000000000000000000000000000000000000000000000000" */ endmodule
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
141
As illustrated in the Figure 3-50, the dual port has one read/write port and an independent read port.
Single-Port RAM D Address R/W Port D Address Dual-Port RAM R/W Port SPO
Write
WCLK
Read Write
WCLK Read Port Address DPO
Read
Read
ug002_c2_001_061400
Figure 3-50:
Any read/write operation can occur simultaneously with and independently of a read operation on the other port.
Write Operations
The write operation is a single clock-edge operation, with a write enable that is active High by default. When the write enable is Low, no data is written into the RAM. When the write enable is High, the clock edge latches the write address and writes the data on D into the RAM.
Read Operation
The read operation is a combinatorial operation. The address port (single or dual port) is asynchronous with an access time equivalent to the logic delay.
142
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
WCLK
DATA_IN
ADDRESS WRITE_EN
tread
aa
twrite MEM(aa) d
tread
DATA_OUT
Previous Data
New Data
DS031_27_041300
Figure 3-51:
Characteristics
A write operation requires only one clock edge. A read operation requires only the logic access time. Outputs are asynchronous and dependent only on the logic delay. Data and address inputs are latched with the write clock and have a setup-to-clock timing specification. There is no hold time requirement. For dual-port RAM, one address is the write and read address, the other address is an independent read address.
Library Primitives
Seven library primitives from 16 x 1-bit to 128 x 1-bit are available. Four primitives are single-port RAM and three primitives are True Dual-Port RAM, as shown in Table 3-16. Table 3-16: Single-Port and Dual-Port Distributed SelectRAM RAM Size 16 bits 32 bits 64 bits 128 bits 16 bits 32 bits 64 bits Type single-port single-port single-port single-port dual-port dual-port dual-port Address Inputs A3, A2, A1, A0 A4, A3, A2, A1, A0 A5, A4, A3, A2, A1, A0 A6, A5, A4, A3, A2, A1, A0 A3, A2, A1, A0 A4, A3, A2, A1, A0 A5, A4, A3, A2, A1, A0
The input and output data are 1-bit wide. However, several distributed SelectRAM memories can be used to implement wide memory blocks.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
143
Figure 3-52 shows generic single-port and dual-port distributed SelectRAM primitives. The A and DPRA signals are address buses.
RAMyX1S
D WE WCLK O D WE WCLK
RAMyX1D
SPO
RAMyX8S
D[7:0] WE WCLK O[7:0]
A[..]+
ug002_c2_003_101600
Figure 3-52:
As shown in Table 3-17, wider library primitives are available for 2-bit, 4-bit, and 8-bit RAM. Table 3-17: Primitive RAM16x2S RAM32X2S RAM64X2S RAM16X4S RAM32X4S RAM16X8S RAM32X8S Wider Library Primitives RAM Size 16 x 2-bit 32 x 2-bit 64 x 2-bit 16 x 4-bit 32 x 4-bit 16 x 8-bit 32 x 8-bit Data Inputs D1, D0 D1, D0 D1, D0 D3, D2, D1, D0 D3, D2, D1, D0 D <7:0> D <7:0> Address Inputs A3, A2, A1, A0 A4, A3, A2, A1, A0 A5, A4, A3, A2, A1, A0 A3, A2, A1, A0 A4,A3, A2, A1, A0 A3, A2, A1, A0 A4,A3, A2, A1, A0 Data Outputs O1, O0 O1, O0 O1, O0 O3, O2, O1, O0 O3, O2, O1, O0 O <7:0> O <7:0>
144
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Ports Signals
Each distributed SelectRAM port operates independently of the other while reading the same set of memory cells.
Clock - WCLK
The clock is used for the synchronous write. The data and the address input pins have setup time referenced to the WCLK pin.
Enable - WE
The enable pin affects the write functionality of the port. An inactive Write Enable prevents any writing to memory cells. An active Write Enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs.
Data In - D
The data input provides the new data value to be written into the RAM.
GSR
The global set/reset (GSR) signal does not affect distributed SelectRAM modules.
Attributes
Content Initialization - INIT
With the INIT attributes, users can define the initial memory contents after configuration. By default distributed SelectRAM memory is initialized with all zeros during the device configuration sequence. The initialization attribute INIT represents the specified memory contents. Each INIT is a hex-encoded bit vector. Table 3-18 shows the length of the INIT attribute for each primitive.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
145
Table 3-18:
INIT Attributes Length Template SelectRAM_16S SelectRAM_32S SelectRAM_64S SelectRAM_128S SelectRAM_16S SelectRAM_32S SelectRAM_64S INIT Attribute Length 4 digits 8 digits 16 digits 32 digits 4 digits 8 digits 16 digits
Location Constraints
The CLB has four slices S0, S1, S2 and S3. As an example, in the bottom left CLB, the slices have the coordinates shown below: Slice S3 X1Y1 Slice S2 X1Y0 Slice S1 X0Y1 Slice S0 X0Y0
Distributed SelectRAM instances can have LOC properties attached to them to constrain placement. The RAM16X1S primitive fits in any LUT of slices S0 or S1. For example, the instance U_RAM16 is placed in slice X0Y0 with the following LOC properties:
INST "U_RAM16" LOC = "SLICE_X0Y0";
The RAM16X1D primitive occupies half of two slices, as shown in Figure 3-53. The first slice (output SPO) implements the read/write port with the same address A[3:0] for read and write. The second slice implements the second read port with the address DPRA[3:0] and is written simultaneously with the first slice to the address A[3:0].
146
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
RAM16X1D
SPO Reg
DPRA[3:0]
DPO Reg
A[3:0]
Reg
Reg
Figure 3-53:
RAM16X1D Placement
In the same CLB module, the dual-port RAM16X1D either occupies half of slices S0 (X0Y0) and S2 (X1Y0), or half of slices S1 (X0Y1) and S3 (X1Y1). If a dual-port 16 x 2-bit module is built, the two RAM16X1D primitives occupy two slices, as long as they share the same clock and write enable, as illustrated in Figure 3-54.
RAM16X1D Bit 0
D[0]
SPO[0]
Reg
DPO[0]
Reg
D[1]
SPO[1]
Reg
DPO[1]
Reg
Slice S0
Figure 3-54:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
147
A4
Reg
ug002_c2_006_061300
Figure 3-55:
RAM32X1S Placement
Following the same rules, a RAM32X1D primitive fits in two slices, with one slice implementing the read/write port and the second slice implementing the second read port. The RAM64X1S primitive occupies two slices and the RAM64X1D primitive occupies four slices (one CLB element), with two slices implementing the read/write port and two other slices implementing the second read port. The RAM64X1S read path is built on the MUXF5 and MUXF6 multiplexers. The RAM128X1S primitive occupies four slices, equivalent to one CLB element. Distributed SelectRAM placement locations use the slice location naming convention, allowing LOC properties to transfer easily from array to array.
Applications
Creating Larger RAM Structures
The memory compiler program generates wider and/or deeper memory structures using distributed SelectRAM instances. Along with an EDIF file for inclusion in a design, this program produces VHDL and Verilog instantiation templates and simulation models. Table 3-19 shows the generic VHDL and Verilog distributed SelectRAM examples provided to implement n-bit-wide memories. Table 3-19: VHDL and Verilog Submodules Primitive RAM16X1S RAM32X1S RAM64X1S RAM128X1S RAM16X1D RAM32X1D RAM64X1D Size 16 words x n-bit 32 words x n-bit 64 words x n-bit 128 words x n-bit 16 words x n-bit 32 words x n-bit 64 words x n-bit Type single-port single-port single-port single-port dual-port dual-port dual-port
148
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
By using the read/write port for the write address and the second read port for the read address, a FIFO that can read and write simultaneously is easily generated. Simultaneous access doubles the effective throughput of the memory.
VHDL Template
-- Module: SelectRAM_16S --- Description: VHDL instantiation template -Distributed SelectRAM -Single Port 16 x 1 -can be used also for RAM16X1S_1 --- Device: Virtex-II Pro Family ------------------------------------------------------------------------ Components Declarations: -component RAM16X1S -- pragma translate_off generic ( -- RAM initialization (0 by default) for functional simulation: INIT : bit_vector := X"0000" ); -- pragma translate_on port ( D : in std_logic; WE : in std_logic; WCLK : in std_logic; A0 : in std_logic; A1 : in std_logic;
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
149
A2 : in std_logic; A3 : in std_logic; O : out std_logic ); end component; ------------------------------------------------------------------------ Architecture section: --- Attributes for RAM initialization ("0" by default): attribute INIT: string; -attribute INIT of U_RAM16X1S: label is "0000"; --- Distributed SelectRAM Instantiation U_RAM16X1S: RAM16X1S port map ( D => , -- insert input signal WE => , -- insert Write Enable signal WCLK => , -- insert Write Clock signal A0 => , -- insert Address 0 signal A1 => , -- insert Address 1 signal A2 => , -- insert Address 2 signal A3 => , -- insert Address 3 signal O => -- insert output signal ); ----------------------------------------------------------------------
Verilog Template
// // Module: SelectRAM_16S // // Description: Verilog instantiation template // Distributed SelectRAM // Single Port 16 x 1 // can be used also for RAM16X1S_1 // // Device: Virtex-II Pro Family // //------------------------------------------------------------------// // // Syntax for Synopsys FPGA Express // synopsys translate_off defparam //RAM initialization (0 by default) for functional simulation: U_RAM16X1S.INIT = 16'h0000; // synopsys translate_on
//Distributed SelectRAM Instantiation RAM16X1S U_RAM16X1S ( .D(), // insert input signal .WE(), // insert Write Enable signal
150
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
// insert Write Clock signal // insert Address 0 signal // insert Address 1 signal // insert Address 2 signal // insert Address 3 signal // insert output signal
In addition, cascadable shift registers (SRLC16) support synchronous shift-out output of the last (16th) bit. This output has a dedicated connection to the input of the next SRLC16 inside the CLB resource. Two primitives are illustrated in Figure 3-56.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
151
SRLC16E
D Address
SRL16E
CE CLK D Address Q Q15
CE CLK D Address
SRLC16E
CE CLK Q15
UG002_C2_007_061400
Figure 3-56:
Shift Operation
The shift operation is a single clock-edge operation, with an active High clock enable feature. When enable is High, the input (D) is loaded into the first bit of the shift register, and each bit is shifted to the next highest bit position. In a cascadable shift register configuration (such as SRLC16), the last bit is shifted out on the Q15 output. The bit selected by the 4-bit address appears on the Q output.
152
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
CLK
CE
D
tshift
Q15
Address
10
Q
taccess
Position (7)
Position (10)
taccess
Figure 3-57:
Characteristics
A shift operation requires one clock edge. Dynamic-length read operations are asynchronous (Q output). Static-length read operations are synchronous (Q output). The data input has a setup-to-clock timing specification. In a cascadable configuration, the Q15 output always contains the last bit value. The Q15 output changes synchronously after each shift operation.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
153
Table 3-20 lists all of the available primitives for synthesis and simulation. Table 3-20: Shift Register Primitives Length 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits Control CLK CLK, CE CLK CLK, CE CLK CLK, CE CLK CLK, CE Address Inputs A3,A2,A1,A0 A3,A2,A1,A0 A3,A2,A1,A0 A3,A2,A1,A0 A3,A2,A1,A0 A3,A2,A1,A0 A3,A2,A1,A0 A3,A2,A1,A0 Output Q Q Q Q Q, Q15 Q, Q15 Q, Q15 Q, Q15
In addition to the 16-bit primitives, three submodules that implement 32-bit, 64-bit, and 128-bit cascadable shift registers are provided in VHDL and Verilog code. Table 3-21 lists available submodules. Table 3-21: Shift Register Submodules Length 32 bits 64 bits 128 bits Control CLK, CE CLK, CE CLK, CE Address Inputs A4,A3,A2,A1,A0 A5, A4, A3,A2,A1,A0 A6, A5, A4, A3,A2,A1,A0 Output Q, Q31 Q, Q63 Q, Q127
The submodules are based on SRLC16E primitives, which are associated with dedicated multiplexers (MUXF5, MUXF6, and so forth). This implementation allows a fast static- and dynamic-length mode, even for very large shift registers. Figure 3-58 represents the cascadable shift registers (32-bit and 64-bit) implemented by the submodules in Table 3-21.
154
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
A5, A4
A5
A4
D 4
D A[3:0] CE
D 4
D A[3:0] CE
Q15
Q15
SRLC16E
Q MUXF5 D 4 A[3:0] CE Q 4 D
SRLC16E
MUXF5 Q
A[3:0] CE
Q15
Q31
Q15
SRLC16E
SRLC16E
Q
Q15
SRLC16E
MUXF5 D 4 A[3:0] CE Q
Q15
Q63
SRLC16E
Figure 3-58:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
155
A 128-bit shift register is built on the same scheme and uses MUXF7 (address input A6). All clock enable (CE) and clock (CLK) inputs are connected to one global clock enable and one clock signal per submodule. If a global static- or dynamic-length mode is not required, the SRLC16E primitive can be cascaded without multiplexers.
Port Signals
Clock - CLK
Either the rising edge or the falling edge of the clock is used for the synchronous shift-in. The data and clock enable input pins have set-up times referenced to the chosen edge of CLK.
Data In - D
The data input provides new data (one bit) to be shifted into the shift register.
Data Out - Q
The data output Q provides the data value (1 bit) selected by the address inputs.
156
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
GSR
The global set/reset (GSR) signal has no impact on shift registers.
Attributes
Content Initialization - INIT
The INIT attribute defines the initial shift register contents. The INIT attribute is a hexencoded bit vector with four digits (0000).The left-most hexadecimal digit is the most significant bit. By default the shift register is initialized with all zeros during the device configuration sequence, but any other configuration value can be specified.
Location Constraints
Each CLB resource has four slices: S0, S1, S2, and S3. As an example, in the bottom left CLB resource, each slice has the coordinates shown in Table 3-22. Table 3-22: Slice Coordinates in the Bottom-Left CLB Resource Slice S2 X1Y0 Slice S1 X0Y1 Slice S0 X0Y0
Slice S3 X1Y1
To constrain placement, shift register instances can have LOC properties attached to them. Each 16-bit shift register fits in one LUT. A 32-bit shift register in static or dynamic address mode fits in one slice (two LUTs and one MUXF5). This shift register can be placed in any slice. A 64-bit shift register in static or dynamic address mode fits in two slices. These slices are either S0 and S1, or S2 and S3. Figure 3-59 illustrates the position of the four slices in a CLB resource. The dedicated CLB shift chain runs from the top slice to the bottom slice. The data input pin must either be in slice S1 or in S3. The address selected as the output pin (Q) is the MUXF6 output. A 128-bit shift register in static or dynamic address mode fits in a four-slice CLB resource. The data input pin has to be in slice S3. The address selected as the output pin (Q) is the MUXF7 output.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
157
D LUT F5
F8
LUT Slice S3
F6 LUT
F5 LUT Slice S2
CLB
UG002_C2_009_012604
Figure 3-59:
158
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
SRLC16E
UG002_C2_010_101600
Figure 3-60:
This configuration provides a better timing solution and simplifies the design. Because the flip-flop must be considered to be the last register in the shift-register chain, the static or dynamic address should point to the desired length minus one. If needed, the cascadable output can also be registered in a flip-flop.
"0111" 4
UG002_C2_012_032901
Figure 3-61:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
159
The following are templates for submodules: SHIFT_REGISTER_32_C (submodule: SRLC32E_SUBM) SHIFT_REGISTER_64_C (submodule: SRLC64E_SUBM) SHIFT_REGISTER_128_C (submodule: SRLC128E_SUBM)
The corresponding submodules have to be synthesized with the design. Templates for the SHIFT_REGISTER_16_C module are provided in VHDL and Verilog code as an example.
VHDL Template:
-- Module: SHIFT_REGISTER_C_16 -- Description: VHDL instantiation template -- CASCADABLE 16-bit shift register with enable (SRLC16E) -- Device: Virtex-II Pro Family ---------------------------------------------------------------------- Components Declarations: -component SRLC16E -- pragma translate_off generic ( -- Shift Register initialization ("0" by default) for functional simulation: INIT : bit_vector := X"0000" ); -- pragma translate_on port ( D : in std_logic; CE : in std_logic; CLK : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic;
160
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Q Q15
); end component; -- Architecture Section: --- Attributes for Shift Register initialization (0 by default): attribute INIT: string; -attribute INIT of U_SRLC16E: label is 0000; --- ShiftRegister Instantiation U_SRLC16E: SRLC16E port map ( D => , -- insert input signal CE => , -- insert Clock Enable signal (optional) CLK => , -- insert Clock signal A0 => , -- insert Address 0 signal A1 => , -- insert Address 1 signal A2 => , -- insert Address 2 signal A3 => , -- insert Address 3 signal Q => , -- insert output signal Q15 => -- insert cascadable output signal );
Verilog Template:
// Module: SHIFT_REGISTER_16 // Description: Verilog instantiation template // Cascadable 16-bit Shift Register with Clock Enable (SRLC16E) // Device: Virtex-II Pro Family //------------------------------------------------------------------// Syntax for Synopsys FPGA Express // synopsys translate_off defparam //Shift Register initialization ("0" by default) for functional simulation: U_SRLC16E.INIT = 16'h0000; // synopsys translate_on //SelectShiftRegister-II Instantiation SRLC16E U_SRLC16E ( .D(), .A0(), .A1(), .A2(), .A3(), .CLK(), .CE(), .Q(), .Q15() ); // synthesis attribute declarations /* synopsys attribute INIT "0000" */
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
161
Large Multiplexers
Introduction
Virtex-II Pro/Virtex-II Pro X slices contain dedicated two-input multiplexers (one MUXF5 and one MUXFX per slice). These multiplexers combine the 4-input LUT outputs or the outputs of other multiplexers. Using the multiplexers MUXF5, MUXF6, MUXF7 and MUXF8 allows to combine 2, 4, 8 and 16 LUTs. Specific routing resources are associated with these 2-input multiplexers to guarantee a fast implementation of any combinatorial function built upon LUTs and MUXFX. The combination of the LUTs and the MUXFX offers a unique solution to the design of wide-input functions. This section illustrates the implementation of large multiplexers up to 32:1. Any slice can implement a 4:1 multiplexer, any CLB can implement a 16:1 multiplexer, and 2 CLBs can implement a 32:1 multiplexer. Such multiplexers are just one example of wide-input combinatorial function taking advantage of the MUXFX feature. Many other logic functions can be mapped in the LUT and MUXFX features. This section provides generic VHDL and Verilog reference code implementing multiplexers. These submodules are built from LUTs and the dedicated MUXF5, MUXF6, MUXF7, and MUXF8 multiplexers. To automatically generate large multiplexers using these dedicated elements, use the CORE Generator Bit Multiplexer and Bus Multiplexer modules. For applications like comparators, encoder-decoders or case statement in VHDL or Verilog, these resources offer an optimal solution.
MUXFX
4
LUT
Reg
OUT_F5
MUXF5
4
LUT
Reg
S_F5
Any Slice
Figure 3-62: LUTs and MUXF5 in a Slice
UG002_C2_016_081500
Each Virtex-II Pro/Virtex-II Pro X CLB contains 4 slices. The second MUXFX implements a MUXF6, MUXF7 or MUXF8 according to the position of the slice in the CLB. These MUXFX are designed to allow LUTs combination up to 16 LUTs in two adjacent CLBs.
162
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Figure 3-63 shows the relative position of the slices in the CLB.
Figure 3-63: Slice Positions in a CLB Slices S0 and S2 have a MUXF6, designed to combine the outputs of two MUXF5 resources. Figure 3-64 illustrates any single combinatorial function up to 6 inputs, or in some functions up to 18 inputs, in slices S0 and S1, or in slices S2 and S3.
LUT
Reg
MUXF5
4
LUT
Reg
S_F6 OUT_F6
MUXF6
4
LUT
Reg
MUXF5
4
LUT
Reg
S_F5
UG002_C2_018_081800
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
163
The slice S1 has a MUXF7, designed to combine the outputs of two MUXF6. Figure 3-65 illustrates any single combinatorial function up to 7 inputs, or in some functions up to 35 inputs, in a Virtex-II CLB.
Slice S3 MUXF8
4
LUT MUXF5
Reg
4 S_F5
LUT
Reg
S_F6
Slice S2 MUXF6
LUT MUXF5
Reg
4 S_F5
LUT
Reg
S_F7
LUT
MUXF5
4 S_F5
LUT
Reg
S_F6
Slice S0 MUXF6
LUT MUXF5
Reg
4 S_F5
LUT
Reg
UG002_C2_019_081600
Figure 3-65:
164
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The slice S3 of each CLB has a MUXF8. Any single combinatorial functions of up to 8 inputs, or some functions up to 68 inputs, fit in two CLBs as shown in Figure 3-66. The outputs of two MUXF7 are combined through dedicated routing resources between two adjacent CLBs in a column.
MUXF8
Slice S3
MUXF6
Slice S2
MUXF7
Slice S1
MUXF6
Slice S0
CLB
MUXF8
OUT_F8
Slice S3
MUXF6
Slice S2
MUXF7
Slice S1
MUXF6
Slice S0
CLB
UG002_C2_020_081600
Figure 3-66:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
165
Wide-Input Multiplexers
Each LUT can implement a 2:1 multiplexer. In each slice, the MUXF5 and two LUTs can implement a 4:1 multiplexer. As shown in Figure 3-67, the MUXF6 and two slices can implement a 8:1 multiplexer. The MUFXF7 and the four slices of any CLB can implement a 16:1 and the MUXF8 and two CLBs can implement a 32:1 multiplexer.
DATA[7:0] F5
S1
16:1 output F7
8:1 Output
S0
SELECT[2:0] SELECT[3]
CLB
8:1 MUX
Figure 3-67: 8:1 and 16:1 Multiplexers
16:1 MUX
UG002_C2_015_081800
Characteristics
Implementation in one level of logic (LUT) and dedicated MUXFX Full combinatorial path
166
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
In addition to the primitives, five submodules that implement multiplexers from 2:1 to 32:1 are provided in VHDL and Verilog code. Synthesis tools can automatically infer the above primitives (MUXF5, MUXF6, MUXF7, and MUXF8); however, the submodules described in this section used instantiation of the new MUXFX to guarantee an optimized result. Table 3-24 lists available submodules: Table 3-24: Available Submodules Multiplexer 2:1 4:1 8:1 16:1 32:1 Control SELECT_I SELECT_I[1:0] SELECT_I[2:0] SELECT_I[3:0] SELECT_I[4:0] Input DATA_I[1:0] DATA_I[3:0] DATA_I[8:0] DATA_I[15:0] DATA_I[31:0] Output DATA_O DATA_O DATA_O DATA_O DATA_O
Port Signals
Data In - DATA_I
The data input provides the data to be selected by the SELECT_I signal(s).
Control In - SELECT_I
The select input signal or bus determines the DATA_I signal to be connected to the output DATA_O. For example, the MUX_4_1_SUBM multiplexer has a 2-bit SELECT_I bus and a 4-bit DATA_I bus. Table 3-25 shows the DATA_I selected for each SELECT_I value. Table 3-25: Selected Inputs DATA_O DATA_I[0] DATA_I[1] DATA_I[2] DATA_I[3]
SELECT_I[1:0] 00 01 10 11
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
167
Applications
Multiplexers are used in various applications. These are often inferred by synthesis tools when a case statement is used (see the example below). Comparators, encoder-decoders and wide-input combinatorial functions are optimized when they are based on one level of LUTs and dedicated MUXFX resources of the Virtex-II Pro/Virtex-II Pro X CLBs.
The corresponding submodules have to be synthesized with the design The submodule MUX_16_1_SUBM in VHDL and Verilog are provided as example.
VHDL Template
-- Module: MUX_16_1_SUBM -- Description: Multiplexer 16:1 --- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; -- Syntax for Synopsys FPGA Express
168
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
-- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on entity MUX_16_1_SUBM is port ( DATA_I: in std_logic_vector (15 downto 0); SELECT_I: in std_logic_vector (3 downto 0); DATA_O: out std_logic ); end MUX_16_1_SUBM; architecture MUX_16_1_SUBM_arch of MUX_16_1_SUBM is -- Component Declarations: component MUXF7 port ( I0: in std_logic; I1: in std_logic; S: in std_logic; O: out std_logic ); end component; --- Signal Declarations: signal DATA_MSB : std_logic; signal DATA_LSB : std_logic; -begin --- If synthesis tools support MUXF7 : --SELECT_PROCESS: process (SELECT_I, DATA_I) --begin --case SELECT_I is -- when "0000" => DATA_O <= DATA_I (0); -- when "0001" => DATA_O <= DATA_I (1); -- when "0010" => DATA_O <= DATA_I (2); -- when "0011" => DATA_O <= DATA_I (3); -- when "0100" => DATA_O <= DATA_I (4); -- when "0101" => DATA_O <= DATA_I (5); -- when "0110" => DATA_O <= DATA_I (6); -- when "0111" => DATA_O <= DATA_I (7); -- when "1000" => DATA_O <= DATA_I (8); -- when "1001" => DATA_O <= DATA_I (9); -- when "1010" => DATA_O <= DATA_I (10); -- when "1011" => DATA_O <= DATA_I (11); -- when "1100" => DATA_O <= DATA_I (12); -- when "1101" => DATA_O <= DATA_I (13); -- when "1110" => DATA_O <= DATA_I (14); -- when "1111" => DATA_O <= DATA_I (15); -- when others => DATA_O <= 'X'; --end case; --end process SELECT_PROCESS; --- If synthesis tools DO NOT support MUXF7 : SELECT_PROCESS_LSB: process (SELECT_I, DATA_I) begin case SELECT_I (2 downto 0) is when "000" => DATA_LSB <= DATA_I (0);
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
169
when "001" => DATA_LSB <= DATA_I (1); when "010" => DATA_LSB <= DATA_I (2); when "011" => DATA_LSB <= DATA_I (3); when "100" => DATA_LSB <= DATA_I (4); when "101" => DATA_LSB <= DATA_I (5); when "110" => DATA_LSB <= DATA_I (6); when "111" => DATA_LSB <= DATA_I (7); when others => DATA_LSB <= 'X'; end case; end process SELECT_PROCESS_LSB; -SELECT_PROCESS_MSB: process (SELECT_I, DATA_I) begin case SELECT_I (2 downto 0) is when "000" => DATA_MSB <= DATA_I (8); when "001" => DATA_MSB <= DATA_I (9); when "010" => DATA_MSB <= DATA_I (10); when "011" => DATA_MSB <= DATA_I (11); when "100" => DATA_MSB <= DATA_I (12); when "101" => DATA_MSB <= DATA_I (13); when "110" => DATA_MSB <= DATA_I (14); when "111" => DATA_MSB <= DATA_I (15); when others => DATA_MSB <= 'X'; end case; end process SELECT_PROCESS_MSB; --- MUXF7 instantiation U_MUXF7: MUXF7 port map ( I0 => DATA_LSB, I1 => DATA_MSB, S => SELECT_I (3), O => DATA_O ); -end MUX_16_1_SUBM_arch; --
Verilog Template
// Module: MUX_16_1_SUBM // // Description: Multiplexer 16:1 // Device: Virtex-II Pro Family //------------------------------------------------------------------// module MUX_16_1_SUBM (DATA_I, SELECT_I, DATA_O); input [15:0]DATA_I; input [3:0]SELECT_I; output DATA_O; wire [2:0]SELECT; reg DATA_LSB; reg DATA_MSB; assign SELECT[2:0] = SELECT_I[2:0];
170
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
/* //If synthesis tools supports MUXF7 : always @ (DATA_I or SELECT_I) case (SELECT_I) 4'b0000 : DATA_O <= 4'b0001 : DATA_O <= 4'b0010 : DATA_O <= 4'b0011 : DATA_O <= 4'b0100 : DATA_O <= 4'b0101 : DATA_O <= 4'b0110 : DATA_O <= 4'b0111 : DATA_O <= 4'b1000 : DATA_O <= 4'b1001 : DATA_O <= 4'b1010 : DATA_O <= 4'b1011 : DATA_O <= 4'b1100 : DATA_O <= 4'b1101 : DATA_O <= 4'b1110 : DATA_O <= 4'b1111 : DATA_O <= default : DATA_O <= endcase */
DATA_I[0]; DATA_I[1]; DATA_I[2]; DATA_I[3]; DATA_I[4]; DATA_I[5]; DATA_I[6]; DATA_I[7]; DATA_I[8]; DATA_I[9]; DATA_I[10]; DATA_I[11]; DATA_I[12]; DATA_I[13]; DATA_I[14]; DATA_I[15]; 1'bx;
always @ (SELECT or DATA_I) case (SELECT) 3'b000 : DATA_LSB <= DATA_I[0]; 3'b001 : DATA_LSB <= DATA_I[1]; 3'b010 : DATA_LSB <= DATA_I[2]; 3'b011 : DATA_LSB <= DATA_I[3]; 3'b100 : DATA_LSB <= DATA_I[4]; 3'b101 : DATA_LSB <= DATA_I[5]; 3'b110 : DATA_LSB <= DATA_I[6]; 3'b111 : DATA_LSB <= DATA_I[7]; default : DATA_LSB <= 1'bx; endcase always @ (SELECT or DATA_I) case (SELECT) 3'b000 : DATA_MSB <= DATA_I[8]; 3'b001 : DATA_MSB <= DATA_I[9]; 3'b010 : DATA_MSB <= DATA_I[10]; 3'b011 : DATA_MSB <= DATA_I[11]; 3'b100 : DATA_MSB <= DATA_I[12]; 3'b101 : DATA_MSB <= DATA_I[13]; 3'b110 : DATA_MSB <= DATA_I[14]; 3'b111 : DATA_MSB <= DATA_I[15]; default : DATA_MSB <= 1'bx; endcase // MUXF7 instantiation MUXF7 U_MUXF7 (.I0(DATA_LSB), .I1(DATA_MSB), .S(SELECT_I[3]),
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
171
.O(DATA_O) ); endmodule // */
4 0 LUT
MUXCY 1 Slice
4 LUT 0
MUXCY 1
4 0 LUT
MUXCY 1
VCC
UG002_c2_51_120400
Figure 3-68:
172
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The output from the chain of AND gates is passed as one of the inputs of the dedicated OR gate, ORCY. To calculate the SOP, these AND chains can be cascaded vertically across several CLBs, depending on the width of the input data. Figure 3-69 illustrates how the AND outputs are then passed in through the ORCY gates in a horizontal cascade, the sum of which is the Sum of Products.
ORCY 4 4
ORCY SOP
LUT
MUXCY
LUT
MUXCY
Slice 3 4 LUT
MUXCY
Slice 3 4 LUT
MUXCY
LUT
MUXCY
LUT
MUXCY
Vcc
Vcc
LUT
MUXCY
LUT
MUXCY
Slice 1 4 LUT
MUXCY
Slice 1 4 LUT
MUXCY
LUT
MUXCY
LUT
MUXCY
Slice 0 4 LUT
MUXCY
Vcc
Vcc
CLB
UG002_c2_42_120400
Figure 3-69:
VHDL Parameters
AND_WIDTH Parameter
The width of each AND gate used in the cascade.
PROD_TERM Parameter
The number of AND gates used along each vertical cascade.
AND_IN Parameter
Data input to the AND gates. The total width of data is calculated from the product of AND_WIDTH and PROD_TERM
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
173
SOP_OUT Parameter
The Sum of Products (SOP) output data from the cascade chain.
Applications
These logic gates can be used in various applications involving very wide AND gates and Sum of Products (SOP) functions.
VHDL Templates
-- Module : AND_CHAIN -- Description : 16 input AND gate --- Device : Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --library UNISIM; --use UNISIM.VCOMPONENTS.ALL; entity AND_CHAIN is generic ( input_width : integer); --must be a 4x value port ( data_in : in std_logic_vector( input_width-1 downto 0); carry_in : in std_logic; out_andor_chain : out std_logic); end AND_CHAIN; architecture AND_CHAIN_arch of AND_CHAIN is component ORCY port( i : std_logic; ci : in std_logic; o : out std_logic); end component; component AND_LOGIC port( sel_data : in std_logic_vector(3 downto 0); data_cin : in std_logic; data_out : out std_logic); end component;
174
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
signal VCC, GND : std_logic; signal cout : std_logic_vector(input_width/4 downto 0); signal out_and_chain : std_logic; begin VCC <= '1'; GND <= '0'; --initialization of first input for MUXCY cout(0) <= VCC; and_chain_x : for i in (input_width/4) - 1 downto 0 generate AND_LOGIC_inst : AND_LOGIC port map ( sel_data => data_in((4 * i + 3) downto (4 * i)), data_cin => cout(i), data_out => cout(i + 1)); end generate; out_and_chain <= cout(input_width/4); orcy_inst : ORCY port map( i => out_and_chain, ci => carry_in, o => out_andor_chain); end AND_CHAIN_arch; ---------------------------------------------------------------------- Module AND_LOGIC -- Description : 4-input AND gate --- Device : Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --library UNISIM; --use UNISIM.VCOMPONENTS.ALL; entity AND_LOGIC port( sel_data : signal for MUXCY data_cin : data_out : end AND_LOGIC; is in std_logic_vector(3 downto 0); -- data for select from LUT in std_logic; -- result from previous stage out std_logic);
architecture AND_LOGIC_arch of AND_LOGIC is component MUXCY port( DI : in std_logic; CI : in std_logic; s : in std_logic; o : out std_logic); end component;
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
175
signal GND : std_logic; signal sel:std_logic; begin GND <= '0'; sel <= sel_data(0) and sel_data(1) and sel_data(2) and sel_data(3); --Wide AND gate using MUXCY MUX : MUXCY port map ( DI => GND, CI => data_cin, s => sel, o => data_out); end AND_LOGIC_arch; ---------------------------------------------------------------------- Module : SOP_SUBM -- Description : Implementing SOP using MUXCY and ORCY --- Device : Virtex-II Pro Family --------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; --library UNISIM; --use UNISIM.VCOMPONENTS.ALL; entity SOP_SUBM is generic( and_width : integer :=16 ; prod_term : integer := 4 ); port( and_in : in std_logic_vector(and_width * prod_term - 1 downto 0); sop_out : out std_logic); end SOP_SUBM; architecture SOP_SUBM_arch of SOP_SUBM is component AND_CHAIN generic ( input_width : integer); --must be a 4x value port ( data_in : in std_logic_vector( input_width-1 downto 0); carry_in : in std_logic; out_andor_chain : out std_logic); end component; signal VCC, GND : std_logic; signal carry : std_logic_vector(prod_term downto 0); begin VCC <= '1'; GND <= '0'; carry(0) <= GND; andor_inst : for i in 0 to (prod_term - 1) generate
176
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
and_chainx : AND_CHAIN generic map( input_width => and_width) port map( data_in => and_in((and_width * i + (and_width -1)) downto (and_width * i)), carry_in => carry(i), out_andor_chain => carry(i + 1)); end generate; sop_out <= carry(prod_term); end SOP_SUBM_arch;
Verilog Templates
// Module : AND_CHAIN // Description : 16 input AND gate // // Device : Virtex-II Family //------------------------------------------------------------------module AND_CHAIN(data_in, carry_in, out_andor_chain); input [15:0] data_in; input carry_in; output out_andor_chain; wire VCC = 1'b1; wire out_and_chain; wire dat_out1, data_out2, data_out3; AND_LOGIC_OR u4(.sel_data(data_in[15:12]), .data_cin(data_out3), .carry_in(carry_in), .data_out(out_andor_chain)); AND_LOGIC u3(.sel_data(data_in[11:8]), .data_cin(data_out2), .data_out(data_out3)); AND_LOGIC u2(.sel_data(data_in[7:4]), .data_cin(data_out1), .data_out(data_out2)); AND_LOGIC u1(.sel_data(data_in[3:0]), .data_cin(VCC), .data_out(data_out1)); endmodule //------------------------------------------------------------------// Module AND_LOGIC // Description : 4-input AND gate // // Device : Virtex-II Family //------------------------------------------------------------------// Module : init_and // module AND_LOGIC(sel_data, data_cin, data_out); input[3:0] sel_data; input data_cin; output data_out; wire GND = 1'b0; wire VCC = 1'b1; wire and_out; assign and_out = sel_data[3] & sel_data[2] & sel_data[1] & sel_data[0]; MUXCY muxcy_inst (.DI(GND), .CI(data_cin), .S(and_out), .O(data_out)); endmodule // Module AND_LOGIC + ORCY module AND_LOGIC_OR(sel_data, data_cin, carry_in, data_out);
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
177
input[3:0] sel_data; input data_cin; input carry_in; output data_out; wire data_mux_out; wire GND = 1'b0; wire VCC = 1'b1; wire and_out; assign and_out = sel_data[3] & sel_data[2] & sel_data[1] & sel_data[0]; MUXCY muxcy_inst (.DI(GND), .CI(data_cin), .S(and_out), .O(data_mux_out)) /* synthesis RLOC="x0y0" */; ORCY u5(.I(carry_in), .CI(data_mux_out), .O(data_out)) /* synthesis RLOC="x0y0" */; endmodule
//------------------------------------------------------------------// Module : SOP_SUBM // Description : Implementing SOP using MUXCY and ORCY // // Device : Virtex-II Family //------------------------------------------------------------------module SOP_SUBM(and_in, sop_out); input [63:0] and_in; output sop_out; wire out_andor_chain1, out_andor_chain2, out_andor_chain3; wire GND = 1'b0; AND_CHAIN u4(.data_in(and_in[63:48]), .carry_in(out_andor_chain3), .out_andor_chain(sop_out)); AND_CHAIN u3(.data_in(and_in[47:32]), .carry_in(out_andor_chain2), .out_andor_chain(out_andor_chain3)); AND_CHAIN u2(.data_in(and_in[31:16]), .carry_in(out_andor_chain1), .out_andor_chain(out_andor_chain2)); AND_CHAIN u1(.data_in(and_in[15:0]), .carry_in(GND), .out_andor_chain(out_andor_chain1)); endmodule
Embedded Multipliers
Introduction
Virtex-II Pro/Virtex-II Pro X devices feature a large number of embedded 18-bit X 18-bit twos-complement embedded multipliers. The embedded multipliers offer fast, efficient means to create 18-bit signed by 18-bit signed multiplication products. The multiplier blocks share routing resources with the Block SelectRAM memory, allowing for increased efficiency for many applications. Cascading of multipliers can be implemented with additional logic resources in local Virtex-II Pro/Virtex-II Pro X slices. Applications such as signed-signed, signed-unsigned, and unsigned-unsigned multiplication, logical, arithmetic, and barrel shifters, twos-complement and magnitude return are easily implemented. Using the CORE Generator, the designer can quickly generate multipliers that make use of the embedded 18-bit x 18-bit twos-complement multipliers (V2.0 or later) of the Multiplier core for Virtex-II Pro/Virtex-II Pro X devices.
178
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
A
18
36
MULT18X18
UG012_c3_047_040504
Figure 3-70:
Embedded Multiplier
Primitive
MULT18X18 MULT18X18S
Signed/Unsigned
Signed (Twos complement) Signed (Twos complement)
Output
Combinatorial Registered
The registered version of the multiplier adds a clock input C, an active-High clock enable CE, and a synchronous reset R (see Figure 3-71). The registers are implemented in the multiplier itself and do not require any other resources. The control inputs C, CE, and R all have built-in programmable polarity. The data inputs, clock enable, and reset all must meet a setup time before the clock edge, and the data on the P outputs changes after the clock-tooutput delay.
A[17:0] A[17:0] P[35:0] B[17:0] B[17:0] C CE R P[35:0]
MULT18X18
MULT18X18S
UG012_c3_046_040504
Figure 3-71:
The pin names used in the Xilinx implementation tools, such as the FPGA Editor, are identical to those used in the library primitives.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
179
In addition to the primitive, 15 submodules that implement various widths of signed and unsigned multipliers and twos-complement return functions are provided in VHDL and Verilog code. Multipliers using cascaded MULT18X18 primitives are included with registers between stages causing three cycles of latency. Multipliers that make use of the embedded Virtex-II Pro/Virtex-II Pro X 18-bit by 18-bit twos complement multipliers can be easily generated using V2.0 of the CORE Generator Multiplier module. Table 3-27 lists cascaded multiplier submodules. Table 3-27: Embedded Multiplier Submodules - Cascaded MULT18X18 A Width 35 34 B Width 35 34 P Width 70 68 Signed/Unsigned Signed Unsigned
Figure 3-72 represents the cascaded scheme used to implement a 35-bit by 35-bit signed multiplier utilizing four embedded multipliers and two adders.
A[34:17] B[34:17]
A B P
36
36
MULT 18 x 18
36 0,A[16:0] 0,B[16:0] A B P 34 34 34
69:34
33:0
MULT 18 x 18
+ A[34:17] 0,B[16:0] A B P
70
70
36
36
0 0 0 0 69 53 52:17 16 0
MULT 18 x 18
+ 0,A[16:0] B[34:17] A B P
36
36
36
MULT 18x18
UG002_C2_021_040604
Figure 3-72:
MULT35X35_S Submodule
The fixed adder is 53 bits wide (17 LSBs are always 0 on one input). The 34-bit by 34-bit unsigned submodule is constructed in a similar manner with the most significant bit on each operand being tied to logic low. Table 3-28 lists multipliers and twos-complement return functions that utilize one MULT18X18 primitive and are not registered.
180
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-28:
Embedded Multiplier Submodules - Single MULT18X18 A width 17 8 8 4 4 6 5 5 6 5 5 4 7 4 3 18 9 18 B width 17 8 8 4 4 6 5 5 6 5 5 4 7 4 3 P width 34 16 16 8 8 12 10 10 12 10 10 8 14 8 6 18 9 17 Signed/Unsigned Unsigned Signed Unsigned Signed Unsigned Signed Unsigned Signed Unsigned Unsigned Unsigned Signed Unsigned Signed Signed -
Submodule MULT17X17_U MULT8X8_S MULT8X8_U MULT4X4_S MULT4X4_U MULT_6X6S_5X5U MULT_5X5S_6X6U MULT_5X5U_5X5U MULT_4X4S_7X7U MULT_4X4S_3X3S TWOS_CMP18 TWOS_CMP9 MAGNTD_18
Multipliers of form MULT_aXaS_bXbU use one embedded multiplier to implement two multipliers with separate outputs. The submodules listed above use optimized pin assignments to achieve shortest possible through-delay. Figure 3-73 and Figure 3-74 represent 4-bit by 4-bit signed multiplier and 4-bit by 4-bit unsigned multiplier implementations, respectively.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
181
0 0 A3 A3 A3 A3 A[3:0]
17 8 7 6 A 5 4 [3:0] P
35:8 7:0
NC P[7:0]
0 0 B3 B3 B3 B3 B[3:0]
17 8 7 6 B 5 4 [3:0]
MULT 18 x 18
UG002_C2_022_012604
Figure 3-73:
MULT4X4_S Submodule
0 0 A 3:0
17 4 3:0
35:8 7:0
NC P 7:0
0 0 B 3:0
17 4 3:0
MULT 18 x 18
UG002_C2_023_012604
Figure 3-74:
MULT4X4_U Submodule
Submodule MAGNTD_18 performs a magnitude return (i.e., absolute value) of a twoscomplement number. An incoming negative number returns with a positive number, while an incoming positive number remains unchanged. Submodules TWOS_CMP18 and TWOS_CMP9 perform a twos-complement return function. The incoming number in twos-complement form (either signed or unsigned) is complemented when the DO_COMP pin is asserted High. Additional slice logic can be used with these submodules
182
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
to efficiently convert sign-magnitude to twos-complement or vice-versa. Figure 3-75 shows the connections to a MULT18X18 to create the submodule TWOS_CMP9.
X000 A [8:0]
[17:9]
A
[8:0] [35:9]
NC P [8:0]
P
X000 X111
[17:9] [8:0]
[8:0]
B MULT18X18
UG002_C2_027_081800
Figure 3-75:
TWOS_CMP9 Submodule
Port Signals
Data In - A
The data input provides new data (up to 18 bits) to be used as one of the multiplication operands.
Data In - B
The data input provides new data (up to 18 bits) to be used as one of the multiplication operands.
Data Out - P
The data output bus P provides the data value (up to 36 bits) of twos-complement multiplication for operands A and B.
Location Constraints
Each embedded multiplier has location coordinates of the form XrowYcolumn. To constrain placement, multiplier instances can have LOC properties attached to MULT18X18 embedded multiplier instances can have LOC properties attached to them to constrain placement. MULT18X18 placement locations differ from the convention used for naming CLB locations, allowing LOC properties to transfer easily from array to array. The LOC properties use the following form: LOC = MULT18X18_X#Y#
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
183
If the above BlockRAM and multiplier pins do not have common source, the implementation tools will not place the blocks adjacently.
184
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The following are templates for submodules: SIGNED_MULT_35X35 (submodule: MULT35X35_S) UNSIGNED_MULT_34X34 (submodule: MULT34X34_U) UNSIGNED_MULT_17X17 (submodule: MULT17X17_U) SIGNED_MULT_8X8 (submodule: MULT8X8_S) UNSIGNED_MULT_8X8 (submodule: MULT8X8_U) SIGNED_MULT_4X4 (submodule: MULT4X4_S) UNSIGNED_MULT_4X4 (submodule: MULT4X4_U) TWOS_COMPLEMENTER_18BIT (submodule: TWOS_CMP18) TWOS_COMPLEMENTER_9BIT (submodule: TWOS_CMP9) MAGNITUDE_18BIT (submodule: MAGNTD_18)
The corresponding submodules have to be synthesized with the design. Templates for the SIGNED_MULT_18X18 module are provided in VHDL and Verilog code as an example.
VHDL Template:
-- Module: SIGNED_MULT_18X18 -- Description: VHDL instantiation template -- 18-bit X 18-bit embedded signed multiplier (asynchronous) --- Device: Virtex-II Pro Family ---------------------------------------------------------------------- Components Declarations component MULT18X18 port( A : in std_logic_vector (17 downto 0); B : in std_logic_vector (17 downto 0); P : out std_logic_vector (35 downto 0) ); end component; --- Architecture Section -U_MULT18X18 : MULT18X18 port map ( A => , -- insert input signal #1 B => , -- insert input signal #2 P => -- insert output signal );
Verilog Template:
// Module: SIGNED_MULT_18X18
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
185
// Description: Verilog instantiation template // 18-bit X 18-bit embedded signed multiplier (asynchronous) // // Device: Virtex-II Pro Family //------------------------------------------------------------------// Instantiation Section // MULT18X18 U_MULT18X18 ( .A () , // insert input signal #1 .B () , // insert input signal #2 .P () // insert output signal );
Introduction
As FPGAs continue to grow in size and capacity, the larger and more complex systems designed for them demand an increased variety of I/O standards. Furthermore, as system clock speeds continue to increase, the need for high-performance I/O becomes more important. Chip-to-chip delays have an increasingly substantial impact on overall system speed. The task of achieving the desired system performance is becoming more difficult with the proliferation of low-voltage I/O standards. SelectIO-Ultra resolves this potential problem by providing a highly configurable, high-performance alternative to I/O resources used in more conventional programmable devices. Virtex-II Pro/Virtex-II Pro X SelectIO-Ultra blocks can support up to 22 single-ended I/O standards. Supporting such a variety of I/O standards allows support for a wide variety of applications. Each Input/Output Block (IOB) includes six registers, two each from the input, output, and 3-state signals within the IOB. These registers are optionally configured as either a D-type flip-flop or as a level-sensitive latch. The purpose of having six registers is to allow designers to design double-data-rate (DDR) logic in the I/O blocks. Each pair of the flipflop (FF) has different clocks so that the flip-flops can be driven by two clocks with a 180degree phase shift to achieve DDR. All I/O flip-flops still share the same reset/preset line. The input buffer has an optional delay element used to guarantee a zero hold time requirement for input signals registered within the IOB. Virtex-II Pro/Virtex-II Pro X SelectIO-Ultra features also provide dedicated resources for input reference voltage (VREF) and input output source voltage (VCCO), along with a convenient banking system that simplifies board design. Virtex-II Pro/Virtex-II Pro X CMOS inputs and outputs are powered from VCCO. Differential amplifier inputs, such as GTL and SSTL, are powered from VCCAUX.
186
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Fundamentals
Modern bus applications, pioneered by the largest and most influential components in the digital electronics industry, are commonly introduced with a new I/O standard tailored specifically to the needs of that application. The bus I/O standards provide specifications to other vendors who create products designed to interface with these applications. Each standard often has its own specifications for current, voltage, I/O buffering, and termination techniques. The ability to provide the flexibility and time-to-market advantages of programmable logic is increasingly dependent on the capability of the programmable logic device to support an ever increasing variety of I/O standards. SelectIO-Ultra resources feature highly configurable input and output buffers that provide support for a wide variety of I/O standards. An input buffer can be configured as either a simple buffer or as a differential amplifier input. An output buffer can be configured as either a push-pull output or as an open drain output. Table 3-29 illustrates all of the supported single-ended I/O standards in Virtex-II Pro/Virtex-II Pro X devices. Each buffer type can support a variety of current and voltage requirements. Table 3-29: Supported Single-Ended I/O Standards
Input Reference Voltage (VREF) N/A N/A N/A N/A N/A N/A N/A N/A 0.8 1.0 0.75 0.75 0.9 0.9 0.9 0.9 1.08 1.08 1.25 1.25 Input Source Output Source Board Termination Voltage (VCCO) Voltage (VCCO) Voltage (VTT) 3.3 3.3 2.5 1.8 1.5
Note (1) Note (1) Note (1) Note (2) Note (2)
I/O Standard LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 PCI66_3 PCI-X GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I_18 HSTL_II_18 HSTL_III _18 HSTL_IV_18 SSTL2_I SSTL2_II
N/A N/A N/A N/A N/A N/A N/A N/A 1.2 1.5 0.75 0.75 1.5 1.5 0.9 0.9 1.8 1.8 1.25 1.25
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
1.5 1.5 1.5 1.5 1.8 1.8 1.8 1.8 2.5 2.5
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
187
Table 3-29:
1. For PCI and PCI-X standards, refer to XAPP653. 2. VCCO of GTL or GTLP should not be lower than the termination voltage or the voltage seen at the I/O pad. For example, connect VCCO to 1.5V if the pin High level is 1.5V 3. SSTL18_I is not a JEDEC-supported standard.
188
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
189
Library Symbols
The Xilinx library includes an extensive list of symbols designed to provide support for the variety of SelectIO-Ultra features. Most of these symbols represent variations of the five generic SelectIO-Ultra symbols. IBUF (input buffer) IBUFG (clock input buffer) OBUF (output buffer) OBUFT (3-state output buffer) IOBUF (input/output buffer)
IBUF
Signals used as inputs to a Virtex-II Pro/Virtex-II Pro X device must source an input buffer (IBUF) via an external input port. The generic IBUF symbol is shown in Figure 3-76. The extension to the base name defines which I/O standard the IBUF uses. The assumed standard is LVCMOS when the generic IBUF has no specified extension.
IBUF I O
x133_01_111699
Figure 3-76:
Table 3-30 details variations of the IBUF symbol for single-ended Virtex-II Pro/ Virtex-II Pro X I/O standards: Table 3-30: IBUF IBUF_LVCMOS15 IBUF_LVCMOS18 IBUF_LVCMOS25 IBUF_LVCMOS33 Variations of the IBUF Symbol IBUF_GTL IBUF_GTLP IBUF_HSTL_I IBUF_HSTL_II IBUF_HSTL_III IBUF_HSTL_IV When the IBUF symbol supports an I/O standard that requires a differential amplifier input, the IBUF is automatically configured as a differential amplifier input buffer. The low-voltage I/O standards with a differential amplifier input require an external reference voltage input VREF. The voltage reference signal is banked within the Virtex-II Pro/Virtex-II Pro X device on a half-edge basis, such that, for all packages, there are eight independent VREF banks internally. For a representation of the I/O banks, see Figure 3-77 and Figure 3-78. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IBUF_SSTL2_I IBUF_SSTL2_II IBUF_PCI33_3 IBUF_PCI66_3 IBUF_PCIX
190
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
IBUF placement restrictions require that any differential amplifier input signals within a bank be of the same standard. How to specify a specific location for the IBUF via the LOC property is described below. Table 3-31 summarizes compatibility requirements of Virtex-II Pro/Virtex-II Pro X input standards. An optional delay element in the input data path is associated with each IBUF. When the IBUF drives a flip-flop within the IOB, the delay element is activated by default to ensure a zero hold-time requirement at the device input pin. The IOBDELAY = NONE property overrides this default, reducing the input set-up time, but risking a hold-time requirement. When the IBUF does not drive a flip-flop within the IOB, the delay element is deactivated by default to provide a shorter input set-up time. To delay the input signal, activate the delay element with the IOBDELAY = BOTH property.
Bank 1 Bank 2
Bank 0 Bank 7
Bank 3
Bank 4
Bank 5
ds031_66_112900
Figure 3-77:
Bank 0 Bank 7
Bank 1 Bank 2
Bank 6
Bank 5
Bank 4
ug002_c2_014_112900
Figure 3-78: I/O Banks: Top View for Wire-Bond Package (FG) Table 3-31: Rule 1 Rule 2 Xilinx Input Standard Compatibility Requirements Standards with the same VCCO, and VREF can be placed within the same bank. Standards that don't require a VREF can be placed within the same bank with the standards that have the same VCCO values
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
Bank 3
Bank 6
191
Each bank has its own VCCO and VREF voltage. Details on compatible input standards for each VCCO / VREF voltage combination are available in the Data Sheet.
OBUF
An OBUF must drive outputs through an external output port. Figure 3-79 shows the generic output buffer (OBUF) symbol.
OBUF I O
x133_04_111699
Figure 3-79:
The extension to the base name defines which I/O standard the OBUF uses. With no extension specified for the generic OBUF symbol, the assumed standard is slew rate limited LVCMOS25 with 12mA drive strength. The LVCMOS OBUFs can additionally support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients, when switching non-critical signals. LVCMOS output buffers have selectable drive strengths. The format for these OBUF symbol names is as follows:
OBUF_<slew_rate>_<drive_strength> <slew_rate> is either F (fast) or S (slow) and <drive_strength> is specified in
milliamperes. For LVCMOS25, the supported drive strengths are 2, 4, 6, 8, 12, 16, and 24. For LVCMOS15 and LVCMOS18, the supported drive strengths are 2, 4, 6, 8, 12, and 16. Table 3-32 details variations of the OBUF symbol. Table 3-32: OBUF OBUF_S_2 OBUF_S_4 OBUF_S_6 OBUF_S_8 OBUF_S_12 OBUF_S_16 OBUF_S_24 OBUF_F_2 OBUF_F_4 OBUF_F_6 OBUF_F_8 OBUF_F_12 Variations of the OBUF Symbol OBUF_LVCMOS18 OBUF_LVCMOS18_S_2 OBUF_LVCMOS18_S_4 OBUF_LVCMOS18_S_6 OBUF_LVCMOS18_S_8 OBUF_LVCMOS18_S_12 OBUF_LVCMOS18_S_16 OBUF_LVCMOS18_F_2 OBUF_LVCMOS18_F_4 OBUF_LVCMOS18_F_6 OBUF_LVCMOS18_F_8 OBUF_LVCMOS18_F_12 OBUF_LVCMOS18_F_16 OBUF_LVCMOS25_F_24 OBUF_LVCMOS33_S_4 OBUF_LVCMOS33_S_6 OBUF_LVCMOS33_S_8 OBUF_LVCMOS33_S_12 OBUF_LVCMOS33_S_16 OBUF_LVCMOS33_S_24 OBUF_LVCMOS33_F_2 OBUF_LVCMOS33_F_4 OBUF_LVCMOS33_F_6 OBUF_LVCMOS33_F_8 OBUF_LVCMOS33_F_12 OBUF_LVCMOS33_F_16
192
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Variations of the OBUF Symbol (Continued) OBUF_LVCMOS25 OBUF_LVCMOS25_S_2 OBUF_LVCMOS25_S_4 OBUF_LVCMOS25_S_6 OBUF_LVCMOS25_S_8 OBUF_LVCMOS25_S_12 OBUF_LVCMOS25_S_16 OBUF_LVCMOS25_S_24 OBUF_LVCMOS25_F_2 OBUF_LVCMOS25_F_4 OBUF_LVCMOS25_F_6 OBUF_LVCMOS25_F_8 OBUF_LVCMOS25_F_12 OBUF_LVCMOS25_F_16 OBUF_LVCMOS33_F_24 OBUF_PCI33_3 OBUF_PCI66-3 OBUF_PCIX OBUF_GTL OBUF_GTLP OBUF_HSTL_I OBUF_HSTL_II OBUF_HSTL_III OBUF_HSTL_IV OBUF_SSTL18_I OBUF_SSTL18_II OBUF_SSTL2_I OBUF_SSTL2_II
OBUF_LVCMOS15 OBUF_LVCMOS15_S_2 OBUF_LVCMOS15_S_4 OBUF_LVCMOS15_S_6 OBUF_LVCMOS15_S_8 OBUF_LVCMOS15_S_12 OBUF_LVCMOS15_S_16 OBUF_LVCMOS15_F_2 OBUF_LVCMOS15_F_4 OBUF_LVCMOS15_F_6 OBUF_LVCMOS15_F_8 OBUF_LVCMOS15_F_12 OBUF_LVCMOS15_F_16
OBUF placement restrictions require that within a given VCCO bank each OBUF share the same output source drive voltage. Input buffers with the same VCCO and output buffers that do not require VCCO can be placed within any VCCO bank. Table 3-33 summarizes Virtex-II Pro/Virtex-II Pro X output compatibility requirements. The LOC property can specify a location for the OBUF. Table 3-33: Rule 1 Rule 2 Output Standards Compatibility Requirements
Only outputs with standards which share compatible VCCO can be used within the same bank. There are no placement restrictions for outputs with standards that do not require a VCCO
Each bank has its own VCCO voltage. Details on compatible output standards for each VCCO voltage combination are available in the Data Sheet.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
193
OBUFT
The generic 3-state output buffer OBUFT, shown in Figure 3-80, typically implements 3-state outputs or bidirectional I/O.
T I
OBUFT O
x133_05_111699
Figure 3-80:
The extension to the base name defines which I/O standard OBUFT uses. With no extension specified for the generic OBUFT symbol, the assumed standard is slew rate limited LVCMOS with 12mA drive strength. The LVCMOS OBUFT additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients, when switching non-critical signals. LVCMOS 3-state buffers have selectable drive strengths. The format for these OBUFT symbol names is as follows:
OBUFT_<slew_rate>_<drive_strength> <slew_rate> is either F (fast) or S (slow) and <drive_strength> is specified in
milliamperes. For LVCMOS25, the supported drive strengths are 2, 4, 6, 8, 12, 16, and 24. For LVCMOS15 and LVCMOS18, the supported drive strengths are 2, 4, 6, 8, 12, and 16. Table 3-34 details variations of the OBUFT symbol. Table 3-34: OBUFT OBUFT_S_2 OBUFT_S_4 OBUFT_S_6 OBUFT_S_8 OBUFT_S_12 OBUFT_S_16 OBUFT_S_24 OBUFT_F_2 OBUFT_F_4 OBUFT_F_6 OBUFT_F_8 OBUFT_F_12 OBUFT_F_16 Variations of the OBUFT Symbol OBUFT_LVCMOS18 OBUFT_LVCMOS18_S_2 OBUFT_LVCMOS18_S_4 OBUFT_LVCMOS18_S_6 OBUFT_LVCMOS18_S_8 OBUFT_LVCMOS18_S_12 OBUFT_LVCMOS18_S_16 OBUFT_LVCMOS18_F_2 OBUFT_LVCMOS18_F_4 OBUFT_LVCMOS18_F_6 OBUFT_LVCMOS18_F_8 OBUFT_LVCMOS18F_12 OBUFT_LVCMOS18_F_16 OBUFT_LVCMOS25 OBUFT_LVCMOS25_F_24 OBUFT_LVCMOS33 OBUFT_LVCMOS33_S_2 OBUFT_LVCMOS33_S_4 OBUFT_LVCMOS33_S_6 OBUFT_LVCMOS33_S_8 OBUFT_LVCMOS33_S_12 OBUFT_LVCMOS33_S_16 OBUFT_LVCMOS33_S_24 OBUFT_LVCMOS33_F_2 OBUFT_LVCMOS33_F_4 OBUFT_LVCMOS33_F_6 OBUFT_LVCMOS33_F_8 OBUFT_LVCMOS33_F_12
194
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-34:
Variations of the OBUFT Symbol (Continued) OBUFT_LVCMOS25_S_2 OBUFT_LVCMOS25_S_4 OBUFT_LVCMOS25_S_6 OBUFT_LVCMOS25_S_8 OBUFT_LVCMOS25_S_12 OBUFT_LVCMOS25_S_16 OBUFT_LVCMOS25_S_24 OBUFT_LVCMOS25_F_2 OBUFT_LVCMOS25_F_4 OBUFT_LVCMOS25_F_6 OBUFT_LVCMOS25_F_8 OBUFT_LVCMOS25_F_12 OBUFT_LVCMOS25_F_16 OBUFT_LVCMOS33_F_16 OBUFT_LVCMOS33_F_24 OBUFT_PCI33_3 OBUFT_PCI66-3 OBUFT_PCIX OBUFT_GTL OBUFT_GTLP OBUFT_HSTL_I OBUFT_HSTL_II OBUFT_HSTL_III OBUFT_HSTL_IV OBUFT_SSTL2_I OBUFT_SSTL2_II
OBUFT_F_24 OBUFT_LVCMOS15 OBUFT_LVCMOS15_S_2 OBUFT_LVCMOS15_S_4 OBUFT_LVCMOS15_S_6 OBUFT_LVCMOS15_S_8 OBUFT_LVCMOS15_S_12 OBUFT_LVCMOS15_S_16 OBUFT_LVCMOS15_F_2 OBUFT_LVCMOS15_F_4 OBUFT_LVCMOS15_F_6 OBUFT_LVCMOS15_F_8 OBUFT_LVCMOS15_F_12 OBUFT_LVCMOS15_F_16
OBUFT placement restrictions require that within a given VCCO bank each OBUFT share the same output source drive voltage. Input buffers with the same VCCO and output buffers that do not require VCCO can be placed within any VCCO bank. The LOC property can specify a location for the OBUFT. 3-state output buffers and bidirectional buffers can have either a weak pull-up resistor, a weak pull-down resistor, or a weak keeper circuit. Control this feature by adding the appropriate symbol to the output net of the OBUFT (PULLUP, PULLDOWN, or KEEPER). The weak keeper circuit requires the input buffer within the IOB to sample the I/O signal. Thus, OBUFTs programmed for an I/O standard that requires a VREF have automatic placement of a VREF in the bank with an OBUFT configured with a weak keeper typically implement a bidirectional I/O. In this case, the IBUF (and the corresponding VREF) are placed explicitly.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
195
IOBUF
Use the IOBUF symbol for bidirectional signals that require both an input buffer and a 3-state output buffer with an active High 3-state pin. Figure 3-81 shows the generic input/output IOBUF buffer.
T I
IOBUF IO
x133_06_111699
Figure 3-81:
The extension to the base name defines which I/O standard the IOBUF uses. With no extension specified for the generic IOBUF symbol, the assumed standard is LVCMOS input buffer and slew rate limited LVCMOS with 12mA drive strength for the output buffer. The LVCMOS IOBUF can additionally support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients, when switching non-critical signals. LVCMOS output buffers have selectable drive strengths. The format for these IOBUF symbol names is as follows:
IOBUF_<slew_rate>_<drive_strength> <slew_rate> is either F (fast) or S (slow) and <drive_strength> is specified in
milliamperes. For LVCMOS25, the supported drive strengths are 2, 4, 6, 8, 12, 16, and 24. For LVCMOS15 and LVCMOS18, the supported drive strengths are 2, 4, 6, 8, 12, and 16. Table 3-35 details variations of the IOBUF symbol. Table 3-35: IOBUF IOBUF_S_2 IOBUF_S_4 IOBUF_S_6 IOBUF_S_8 IOBUF_S_12 IOBUF_S_16 IOBUF_S_24 IOBUF_F_2 IOBUF_F_4 IOBUF_F_6 Variations of the IOBUF Symbol IOBUF_LVCMOS18 IOBUF_LVCMOS18_S_2 IOBUF_LVCMOS18_S_4 IOBUF_LVCMOS18_S_6 IOBUF_LVCMOS18_S_8 IOBUF_LVCMOS18_S_12 IOBUF_LVCMOS18_S_16 IOBUF_LVCMOS18_F_2 IOBUF_LVCMOS18_F_4 IOBUF_LVCMOS18_F_6 IOBUF_LVCMOS18_F_8 IOBUF_LVCMOS33 IOBUF_LVCMOS33_S_2 IOBUF_LVCMOS33_S_4 IOBUF_LVCMOS33_S_6 IOBUF_LVCMOS33_S_8 IOBUF_LVCMOS33_S_12 IOBUF_LVCMOS33_S_16 IOBUF_LVCMOS33_S_24 IOBUF_LVCMOS33_F_2 IOBUF_LVCMOS33_F_4 IOBUF_LVCMOS33_F_6
196
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Variations of the IOBUF Symbol (Continued) IOBUF_LVCMOS18F_12 IOBUF_LVCMOS18_F_16 IOBUF_LVCMOS25 IOBUF_LVCMOS25_S_2 IOBUF_LVCMOS25_S_4 IOBUF_LVCMOS25_S_6 IOBUF_LVCMOS25_S_8 IOBUF_LVCMOS25_S_12 IOBUF_LVCMOS25_S_16 IOBUF_LVCMOS25_S_24 IOBUF_LVCMOS25_F_2 IOBUF_LVCMOS25_F_4 IOBUF_LVCMOS25_F_6 IOBUF_LVCMOS25_F_8 IOBUF_LVCMOS25_F_12 IOBUF_LVCMOS25_F_16 IOBUF_LVCMOS25_F_24 IOBUF_LVCMOS33_F_8 IOBUF_LVCMOS33_F_12 IOBUF_LVCMOS33_F_16 IOBUF_LVCMOS33_F_24 IOBUF_PCI33_3 IOBUF_PCI66-3 IOBUF_PCIX IOBUF_GTL IOBUF_GTLP IOBUF_HSTL_I IOBUF_HSTL_II IOBUF_HSTL_III IOBUF_HSTL_IV IOBUF_SSTL18_I IOBUF_SSTL18_II IOBUF_SSTL2_I IOBUF_SSTL2_II
IOBUF_F_12 IOBUF_F_16 IOBUF_F_24 IOBUF_LVCMOS15 IOBUF_LVCMOS15_S_2 IOBUF_LVCMOS15_S_4 IOBUF_LVCMOS15_S_6 IOBUF_LVCMOS15_S_8 IOBUF_LVCMOS15_S_12 IOBUF_LVCMOS15_S_16 IOBUF_LVCMOS15_F_2 IOBUF_LVCMOS15_F_4 IOBUF_LVCMOS15_F_6 IOBUF_LVCMOS15_F_8 IOBUF_LVCMOS15_F_12 IOBUF_LVCMOS15_F_16
When the IOBUF symbol supports an I/O standard that requires a differential amplifier input, IOBUF is automatically configured as a differential amplifier input buffer. Low-voltage I/O standards with a differential amplifier input require an external reference voltage input VREF. The voltage reference signal is banked within the Virtex-II Pro/Virtex-II Pro X device on a half-edge basis, such that for all packages there are eight independent VREF banks internally. For a representation of the I/O banks, see Figure 3-78. Within each bank approximately one of every twelve I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IOBUF placement restrictions require any differential amplifier input signals within a bank be of the same standard. Additional restrictions on Virtex-II Pro/Virtex-II Pro X SelectIO-Ultra IOBUF placement require that within a given VCCO bank each IOBUF share the same output source drive voltage. Input buffers with the same VCCO and output buffers that do not require VCCO can be placed within any VCCO bank. The LOC property can specify a location for the IOBUF. An optional delay element is associated with the input path in each IOBUF. When the IOBUF drives an input flip-flop within the IOB, the delay element is activated by default to ensure the zero hold-time requirement. Override this default with the IOBDELAY = NONE property.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
197
In the case when the IOBUF does not drive an input flip-flop within the IOB, the delay element is deactivated by default to provide higher performance. To delay the input signal, activate the delay element with the IOBDELAY = BOTH property. 3-state output buffers and bidirectional buffers can have a weak pull-up resistor, a weak pull-down resistor, or a weak keeper circuit. Control this feature by adding the appropriate symbol to the output net of the IOBUF (PULLUP, PULLDOWN, or KEEPER).
SelectIO-Ultra Properties
Access to some SelectIO-Ultra features (for example, location constraints, input delay, output drive strength, and slew rate) is available through properties associated with these features.
Alternatively, the IOB = TRUE property can be placed on a register to force the mapper to place the register in an IOB. The two registers for each path makes designing double-data-rate (DDR) logic much simpler. Each pair of the registers has separate clock inputs, which can be driven by either the positive edge or the negative edge of the clock. Users can use both edges of the clocks to clock data in and out from the IOB. For details on DDR, see Double-Data-Rate (DDR) I/O, page 243.
Location Constraints
Specify the location of each SelectIO-Ultra symbol with the location constraint LOC attached to the SelectIO-Ultra symbol. The external port identifier indicates the value of the location constrain. The format of the port identifier depends on the package chosen for the specified design. The LOC properties use the following form: LOC=A42; LOC=P37;
198
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Design Considerations
Reference Voltage (VREF) Pins
Low-voltage I/O standards with a differential amplifier input buffer require an input reference voltage (VREF). Provide the VREF as an external signal to the device. The voltage reference signal is banked within the Virtex-II Pro/Virtex-II Pro X device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 3-78 for a representation of the I/O banks. Within each bank approximately one of every twelve I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. Within each VREF bank, any input buffers that require a VREF signal must be of the same type. Output buffers that have the same VCCO values as the input buffers can be placed within the same VREF bank.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
199
It is recommended to power VCCO even for non-VCCO dependent input standards such as LVDS, LVPECL, SSTL, HSTL, and GTL. The input clamp diodes, which are always present regardless of I/O standard, become forward-biased if pin voltage exceeds VCCO by the diode threshold voltage (~0.5V). Leaving VCCO disconnected, or setting it to an excessively low voltage, can lead to a distorted input signal. To avoid this, VCCO should be greater than the input high voltage (plus any overshoot), less the 0.5V diode voltage. Furthermore, if a bank is unused, tie VCCO to VCCAUX or any available VCCO. Do not leave it floating or connected to ground.
Termination Techniques
A variety of termination techniques reduce the impact of transmission line effects. The following are output termination techniques: None Series Parallel (Shunt) Series and Parallel (Series-Shunt)
200
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
These termination techniques can be applied in any combination. A generic example of each combination of termination methods appears in Figure 3-82.
Unterminated
Z=50
Z=50 VREF
Z=50 VREF
Z=50 VREF
Series-Parallel Terminated Output Driving a Parallel Terminated Input Series Terminated Output
Z=50 Z=50 VREF VREF
x133_07_111699
VTT
VTT
Figure 3-82:
New ---------- RR Value New SSO Limit = ------------ SSO Limit for 50 50
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
201
Example: If using the LVDCI_18 driver with 65 reference resistors, the LVDCI_18 SSO limit for 50 impedance is first taken from the table. The SSO limit for LVDCI_18 at 50 is 11 per power/ground pin pair. Therefore, the SSO limit for LVDCI_18 at 65 is (65 / 50) 11 = 14 per power/ground pin pair. Since some of the ground pins are shared inside the package, the effective power/ground pairs per bank may be fewer than the physical power/ground pair pins. The following tables show the number of equivalent power/ground pairs. Table 3-36: Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair (1) Standard LVTTL_S2 LVTTL_S4 LVTTL_S6 LVTTL_S8 LVTTL_S12 LVTTL_S16 LVTTL_S24 LVTTL_F2 LVTTL_F4 LVTTL_F6 LVTTL_F8 LVTTL_F12 LVTTL_F16 LVTTL_F24 LVDCI_15 50 impedance LVDCI_DV2_15 25 impedance LVCMOS15_S2 LVCMOS15_S4 LVCMOS15_S6 LVCMOS15_S8 LVCMOS15_S12 LVCMOS15_S16 LVCMOS15_F2 LVCMOS15_F4 LVCMOS15_F6 LVCMOS15_F8 Package: FG, FF 68 41 29 22 15 11 7 40 24 17 13 10 8 5 10 5 51 31 22 17 11 8 30 18 13 10
202
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-36: Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair (1) (Continued) Standard LVCMOS15_F12 LVCMOS15_F16 LVDCI_18, 50 impedance LVDCI_DV2_18, 25 impedance LVCMOS18_S2 LVCMOS18_S4 LVCMOS18_S6 LVCMOS18_S8 LVCMOS18_S12 LVCMOS18_S16 LVCMOS18_F2 LVCMOS18_F4 LVCMOS18_F6 LVCMOS18_F8 LVCMOS18_F12 LVCMOS18_F16 LVDCI_25, 50 impedance LVDCI_DV2,_25 25 impedance LVCMOS25_S2 LVCMOS25_S4 LVCMOS25_S6 LVCMOS25_S8 LVCMOS25_S12 LVCMOS25_S16 LVCMOS25_S24 LVCMOS25_F2 LVCMOS25_F4 LVCMOS25_F6 LVCMOS25_F8 LVCMOS25_F12 LVCMOS25_F16 LVCMOS25_F24 LVDCI_33, 50 impedance Package: FG, FF 8 6 11 5 58 35 25 19 13 10 34 20 15 11 9 7 13 6 68 41 29 22 15 11 7 40 24 17 13 10 8 5 13
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
203
Table 3-36: Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair (1) (Continued) Standard LVDCI_DV2_33, 25 impedance LVCMOS33_S2 LVCMOS33_S4 LVCMOS33_S6 LVCMOS33_S8 LVCMOS33_S12 LVCMOS33_S16 LVCMOS33_S24 LVCMOS33_F2 LVCMOS33_F4 LVCMOS33_F6 LVCMOS33_F8 LVCMOS33_F12 LVCMOS33_F16 LVCMOS33_F24 PCI_33, PCI_66, PCIX GTL GTL_DCI GTLP GTLP_DCI HSTLI HSTLI_DCI HSTLII HSTLII_DCI HSTLIII HSTLIII_DCI HSTLIV HSTLIV_DCI SSTL18_I SSTL18_I_DCI SSTL18_II SSTL18_II_DCI SSTL2_I Package: FG, FF 6 68 41 29 22 15 11 7 40 24 17 13 10 8 5 8 4 4 4 4 20 20 10 6 8 8 4 4 20 20 13 6 15
204
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-36: Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair (1) (Continued) Standard SSTL2_I_DCI SSTL2_II SSTL2_II_DCI HSTL_I_18 HSTL_I_DCI_18 HSTL_II_18 HSTL_II_DCI_18 HSTL_III_18 HSTL_III_DCI_18 HSTL_IV_18 HSTL_IV_DCI_18 LVPECL_25 BLVDS_25 DIFF_HSTL_II DIFF_HSTL_II_DCI DIFF_HSTL_II_18 DIFF_HSTL_II_18_DCI DIFF_SSTL_II DIFF_SSTL_II_DCI DIFF_SSTL_II_18 DIFF_SSTL_II_18_DCI
Notes:
1. The maximum number of simultaneously switching outputs per power/ground pair may be less than the number given in this table if the external bypass capacitor solution has a high series inductance. This table presumes the use of ultra-low inductance bypass capacitors. Refer to VCC Decoupling, page 483.
Package: FG, FF 15 10 5 16 16 8 6 6 6 3 3 8 8 10 6 8 6 10 6 12 6
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
205
Table 3-37 shows the number of pairs in banks 0, 1, 4, and 5 (top and bottom edges of the die), while Table 3-38 shows the numbers in banks 2, 3, 6, and 7. This is because MGTs reside on the top and bottom edge only. Table 3-37: Equivalent Pwr/Gnd Pairs per Bank, Top/Bottom
For Banks 0, 1, 4, and 5 (Top/Bottom Sides): Package
2VP2 2VP4 2VP7 2VP20 2VP30 2VP40 2VP50 2VP70 2VP100
FG256/FGG256 FG456/FGG456 FG676/FGG676 FF672 FF896 FF1152 FF1148 FF1517 FF1704 FF1696 Table 3-38:
2 3
2 3 3 5 5 5
6 6 9 9 9 9 11 11 11 11 13 15 15 16 16
Package
2VP2 2VP4 2VP7 2VP20 2VP30 2VP40 2VP50 2VP70 2VP100
FG256/FGG256 FG456/FGG456 FG676/FGG676 FF672 FF896 FF1152 FF1148 FF1517 FF1704 FF1696
2 2
2 4 4 5 5 5
6 9 11 11 11 11 11 12 11 12 15 15 16 16 16
Refer to XAPP689 for further details on managing ground bounce in large FPGAs.
206
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Application Examples
Creating a design with the SelectIO-Ultra feature requires either assignment of the IOSTANDARD attribute in the constraint file or instantiation of the desired library symbol within the design code. To enter the IOSTANDARD attribute in the constraint file (UCF file), the following syntax can be used:
NET <pad net name> IOSTANDARD=<the name of the standard>
To instantiate a library symbol in the HDL code, use the proper input or output buffer name, and follow the standard syntax of instantiation. For example, to instantiate a GTL input buffer in VHDL, the following syntax can be used:
GTL_buffer : IBUF_GTL port map (I=>data_in, O=>data_gtl_in);
At the board level, designers need to know the termination techniques required for each I/O standard. This section describes some common application examples illustrating the termination techniques recommended by each of the single-ended standard supported by the SelectIO-Ultra features.
Termination Examples
Circuit examples involving typical termination techniques for each of the SelectIO-Ultra standards follow. For a full range of accepted values for the DC voltage specifications for each standard, refer to the table associated with each figure. The resistors used in each termination technique example and the transmission lines depicted represent board level components and are not meant to represent components on the device.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
207
GTL
A sample circuit illustrating a valid termination technique for GTL is shown in Figure 3-83.
VTT = 1.2V VCCO = N/A 50 VTT = 1.2V 50
Z = 50
VREF = 0.8V
UG012_C2_008_121101
Figure 3-83: Table 3-39 lists DC voltage specifications. Table 3-39: GTL Voltage Specifications
GTL Terminated
Parameter VCCO VREF = N VTT (1) VTT VIH VREF + 0.05 VIL VREF 0.05 VOH VOL IOH at VOH (mA) IOLat VOL (mA) at 0.4V IOLat VOL (mA) at 0.2V
Notes:
1. N must be greater than or equal to 0.653 and less than or equal to 0.68.
208
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
GTL +
Figure 3-84 shows a sample circuit illustrating a valid termination technique for GTLP.
VTT = 1.5V 50 VCCO = N/A VTT = 1.5V 50
Z = 50
VREF = 1.0V
UG012_C2_009_121101
GTLP Terminated
GTLP Voltage Specifications Parameter Min 0.88 1.35 0.98 0.3 36 Typ 1.0 1.5 1.1 0.9 0.45 Max 1.12 1.65 1.02 0.6 48
VCCO VREF = N VTT (1) VTT VIH VREF + 0.1 VIL VREF 0.1 VOH VOL IOH at VOH (mA) IOLat VOL (mA) at 0.6V IOLat VOL (mA) at 0.3V
Notes:
1. N must be greater than or equal to 0.653 and less than or equal to 0.68.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
209
HSTL Class I
Figure 3-85 shows a sample circuit illustrating a valid termination technique for HSTL_I.
VCCO = 1.5V VTT = 0.75V 50
Z = 50
VREF = 0.75V
UG012_C2_010_121101
Figure 3-85:
Table 3-41 lists DC voltage specifications. Table 3-41: HSTL Class I Voltage Specification MIN 1.40 0.68 VREF + 0.1 VCCO 0.4 8 8 TYP 1.50 0.75 VCCO 0.5 MAX 1.60 0.90 VREF 0.1 0.4 -
Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
210
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
HSTL Class II
Figure 3-86 shows a sample circuit illustrating a valid termination technique for HSTL_II.
VCCO = 1.5V VTT = 0.75V 50 VTT = 0.75V 50
Z = 50
VREF = 0.9V
UG012_C2_013a_020204
Figure 3-86:
Table 3-42 lists DC voltage specifications. Table 3-42: HSTL Class II Voltage Specification MIN 1.40 VREF + 0.1 VCCO 0.4 16 16 TYP 1.50 0.75 VCCO 0.5 MAX 1.60 VREF 0.1 0.4 -
Parameter VCCO VREF (1) VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Notes:
1. Per EIA/JESD8-6, The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
211
VREF = 0.9V
UG012_C2_011_121101
Figure 3-87:
Table 3-43 lists DC voltage specifications. Table 3-43: HSTL Class III Voltage Specification MIN 1.40 VREF + 0.1 VCCO 0.4 8 24 TYP 1.50 0.90 VCCO MAX 1.60 VREF 0.1 0.4 -
Parameter VCCO VREF (1) VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Notes:
1. Per EIA/JESD8-6, The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.
212
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
HSTL Class IV
Figure 3-88 shows a sample circuit illustrating a valid termination technique for HSTL_IV.
VCCO = 1.5V VTT = 1.5V 50 VTT = 1.5V 50
Z = 50
VREF = 0.9V
UG012_C2_012_121101
Figure 3-88:
Table 3-44 lists DC voltage specifications. Table 3-44: HSTL Class IV Voltage Specification MIN 1.40 VREF + 0.1 VCCO 0.4 8 48 TYP 1.50 0.90 VCCO MAX 1.60 VREF 0.1 0.4 -
Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Notes:
1. Per EIA/JESD8-6, The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
213
VREF = 0.9V
UG012_C2_010a_121101
Figure 3-89: Terminated HSTL Class I (1.8V) Table 3-45 lists DC voltage specifications. Table 3-45: HSTL Class I (1.8V) Voltage Specification MIN 1.7 0.8 VREF + 0.1 VCCO 0.4 8 8 TYP 1.8 0.9 VCCO 0.5 MAX 1.9 1.1 VREF 0.1 0.4 -
Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
214
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
VREF = 0.9V
UG012_C2_013a_020204
Figure 3-90:
Table 3-46 lists DC voltage specifications. Table 3-46: HSTL Class II (1.8V) Voltage Specification MIN 1.7 VREF + 0.1 VCCO 0.4 16 16 TYP 1.8 0.9 VCCO 0.5 MAX 1.9 VREF 0.1 0.4 -
Parameter VCCO VREF (1) VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Notes:
1. Per EIA/JESD8-6, The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
215
VREF = 1.1V
UG012_C2_011a_121101
Figure 3-91:
Table 3-47 lists DC voltage specifications. Table 3-47: HSTL Class III (1.8V) Voltage Specification MIN 1.7 VREF + 0.1 VCCO 0.4 8 24 TYP 1.8 1.1 VCCO MAX 1.9 VREF 0.1 0.4 -
Parameter VCCO VREF (1) VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Notes:
1. Per EIA/JESD8-6, The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.
216
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
VREF = 1.1V
UG012_C2_012a_121101
Figure 3-92:
Table 3-48 lists DC voltage specifications. Table 3-48: HSTL Class IV (1.8V) Voltage Specification MIN 1.7 VREF + 0.1 VCCO 0.4 8 48 TYP 1.8 1.1 VCCO MAX 1.9 VREF 0.1 0.4 -
Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Notes:
1. Per EIA/JESD8-6, The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
217
SSTL2_I
Figure 3-93 shows a sample circuit illustrating a valid termination technique for SSTL2_I.
VCCO = 2.5V 25
Z = 50
VTT = 1.25V 50
VREF = 1.25V
UG012_C2_015_121101
Terminated SSTL2_I
SSTL2_I Voltage Specifications Parameter Min 2.3 1.13 1.11 1.3 0.3(3) 1.74 0.52 8.1 8.1 Typ 2.5 1.25 1.25 1.43 1.07 1.84 0.66 Max 2.7 1.38 1.39 3.0(2) 1.2 1.99 0.77 -
VCCO VREF = 0.5 VCCO VTT = VREF + N(1) VIH VREF + 0.18 VIL VREF 0.18 VOH VREF + 0.61 (4) VOL VREF 0.61 (4) IOH at VOH (mA) IOLat VOL (mA)
Notes:
1. 2. 3. 4.
N must be greater than or equal to -0.04 and less than or equal to 0.04. VIH maximum is VCCO + 0.3. VIL minimum does not conform to the formula. VOH and VOL will be different for SSTL2_I_DCI, because it uses a controlled-impedance driver.
218
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
SSTL2_II
Figure 3-94 shows a sample circuit illustrating a valid termination technique for SSTL2_II.
VCCO = 2.5V 25
Z = 50
VTT = 1.25V 50
VTT = 1.25V 50
VREF = 1.25V
UG012_C2_016_121101
Figure 3-94:
Terminated SSTL2_II
Table 3-50 lists DC voltage specifications. Table 3-50: SSTL2_II Voltage Specifications Parameter VCCO VREF = 0.5 VCCO VTT = VREF + N(1) VIH VREF + 0.15 VIL VREF 0.15 VOH VREF + 0.8 (4) VOL VREF 0.8 (4) IOH at VOH (mA) IOLat VOL (mA)
Notes:
1. 2. 3. 4. N must be greater than or equal to 0.04 and less than or equal to 0.04. VIH maximum is VCCO + 0.3. VIL minimum does not conform to the formula. VOH and VOL will be different for SSTL2_II_DCI, because it uses a controlled-impedance driver.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
219
SSTL18_II
Figure 3-95 shows a sample circuit illustrating a valid termination technique for SSTL18_II.
VCCO = 1.8V 20
Z = 50
VTT = 0.90V 50
VTT = 0.90V 50
VREF = 0.90V
UG012_C2_017_100302
Figure 3-95:
Terminated SSTL18_II
Table 3-51 lists DC voltage specifications. Table 3-51: SSTL18_II Voltage Specifications (JESD8-15) Parameter VCCO VREF = 0.5 VCCO VTT = VREF + N(1) VIH VREF + 0.15 VIL VREF 0.15 VOH VREF + 0.8 (4) VOL VREF 0.8 (4) IOH at VOH (mA) IOLat VOL (mA) -13.4 13.4 Min 1.7 0.833 0.793 0.958 -0.3 1.396 0.406 Typ 1.8 0.9 0.9 Max 1.9 0.969 1.009 2.2 0.844
220
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
LVTTL
Table 3-53 lists DC voltage specifications. Table 3-53: LVTTL Voltage Specifications Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA)
Notes:
1. VOLand VOH for lower drive currents are sample tested.
Typ 3.3 -
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
221
LVCMOS15
Table 3-54 lists DC voltage specifications. Table 3-54: LVCMOS15 Voltage Specifications Parameter VCCO VREF VTT VIH = 0.65 VCCO VIL = 0.35 VCCO VOH = VCCO 0.4 VOL IOH at VOH (mA) IOLat VOL (mA) Min 0.93 0.3 16 16 Typ 1.5 1.1 Max VCCO + 0.3 0.55 0.4 -
LVCMOS18
Table 3-55 lists DC voltage specifications. Table 3-55: LVCMOS18 Voltage Specifications Parameter VCCO VREF VTT VIH = 0.7 VCCO VIL = 0.3 VCCO VOH = VCCO 0.4 VOL IOH at VOH (mA) IOLat VOL (mA) 1.19 0.3 16 16 Min Typ 1.8 1.4 VCCO + 0.3 0.57 0.4 Max
222
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
LVCMOS25
Table 3-56 lists DC voltage specifications. Table 3-56: LVCMOS25 Voltage Specifications Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA) Min 2.3 1.7 0.5 1.9 24 24 Typ 2.5 Max 2.7 2.7 0.7 0.4 -
LVCMOS33
Table 3-57 lists DC voltage specifications. Table 3-57: LVCMOS33 Voltage Specifications Parameter VCCO VREF VTT VIH VIL VOH VOL IOH at VOH (mA) IOLat VOL (mA) Min 3.0 2.0 0.5 2.6 24 24 Typ 3.3 Max 3.6 3.6 0.8 0.4 -
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
223
Xilinx DCI
DCI uses two multi-purpose reference pins in each bank to control the impedance of the driver or the parallel termination value for all of the I/Os of that bank. The N reference pin (VRN) must be pulled up to VCCO by a reference resistor, and the P reference pin (VRP) must be pulled down to ground by another reference resistor. The value of each reference resistor should be equal to the characteristic impedance of the PC board traces, or should be twice that value (configuration option). When VRN/VRP is not connected and is isolated, DCI will attempt to match to "infinite impedance" (open circuit). For LVDCI and LVDCI_DV2 standards, the output is effectively set to high-Z. For most HSTL_DCI, SSTL_DCI, and GTL_DCI standards, the on-chip terminations are turned completely off. (The exceptions are HSTL_IV_DCI, GTL_DCI, and GTLP_DCI, for which a small part of the termination is turned on as part of the bit stream; that portion remains on even when the VRN and VRP pins are disconnected.) When using DCI, leaving VRN/VRP disconnected does not damage the device though it does dissipate more power than, for example, a case where the DCI is not turned on, because the DCI control logic would still be active. Additionally, if a VRN/VRP pin is not isolated, it could couple with another signal. In this case, DCI attempts to match to the
224
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
coupling signal. Disconnecting the VRN/VRP pins after configuration increases the impedance of on-chip terminations, but it does not turn the DCI off completely. When the polarity is reversed (VRP is mistakenly connected to VCCO and VRN to GND), the termination effect is the same as described above and the device will not be damaged. When a DCI I/O standard is used on a particular bank, the two multi-purpose reference pins cannot be used as regular I/Os. However, if DCI I/O standards are not used in the bank, these pins are available as regular I/O pins. Check the Virtex-II Pro/Virtex-II Pro X pinout for detailed pin descriptions. DCI adjusts the impedance of the I/O by selectively turning transistors in the I/Os on or off. The impedance is adjusted to match the external reference resistors. The impedance adjustment process has two phases. The first phase, which compensates for process variations, is done during the device startup sequence. The second phase, which maintains the impedance in response to temperature and supply voltage changes, begins immediately after the first phase and continues indefinitely, even while the part is operating. By default, the DONE pin does not go High until the first phase of the impedance adjustment process has completed. If users do not wish to have the second phase enabled, the DCIUpdateMode option in BitGen should be set to "Quiet". For controlled impedance output drivers, the impedance can be adjusted either to match the reference resistors or half the resistance of the reference resistors. For on-chip termination, the termination is always adjusted to match the reference resistors. DCI can configure output drivers to be the following types: 1. 2. Controlled Impedance Driver (Source Termination) Controlled Impedance Driver with Half Impedance (Source Termination)
It can also configure inputs to have he following types of on-chip terminations: 1. 2. Input termination to VCCO (Single Termination) Input termination to VCCO/2 (Split Termination, Thevenin equivalent) Driver with termination to VCCO (Single Termination) Driver with termination to VCCO/2 (Split Termination, Thevenin equivalent)
For bidirectional operation, both ends of the line can be DCI-terminated permanently: 1. 2.
Alternatively, bidirectional point-to-point lines can use controlled-impedance drivers (with 3-state buffers) on both ends.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
225
R Z0
Virtex-II Pro DCI
UG012_C2_047_121101
Figure 3-96:
R/2 Z0
Virtex-II Pro DCI
UG012_C2_052_121101
Figure 3-97:
226
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
VCCO
Z0 VREF
UG012_C2_053_121101
Figure 3-98:
DCI can provide this termination to VCCO using single termination. The termination resistance is set by the reference resistors. For GTL and HSTL standards, they should be controlled by 50-ohm reference resistors. The DCI I/O standards that support single termination are: GTL_DCI, GTLP_DCI, HSTL_III_DCI, HSTL_III_DCI_18, HSTL_IV_DCI., and HSTL_IV_DCI_18. Figure 3-99 illustrates single termination inside a Virtex-II Pro/Virtex-II Pro X device.
VCCO R
Figure 3-99:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
227
VCCO /2 R
Z0
VREF
UG012_C2_055_121101
Figure 3-100:
This is equivalent to having a split termination composed of two resistors. One terminates to VCCO, the other to ground. The resistor values are 2R. DCI provides termination to VCCO/2 using split termination. The termination resistance is set by the external reference resistors, i.e., the resistors to VCC and ground are each twice the reference resistor value. If users are planning to use HSTL or SSTL standards, the reference resistors should be 50ohms. The DCI I/O standards that support split termination are: HSTL_I_DCI, HSTL_I_DCI_18, HSTL_II_DCI, HSTL_II_DCI_18, SSTL2_I_DCI, and SSTL2_II_DCI. Figure 3-101 illustrates split termination inside a Virtex-II Pro/Virtex-II Pro X device.
VCCO 2R
Figure 3-101:
228
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
VCCO R
Z0
UG012_C2_057_121101
Figure 3-102:
DCI can provide this termination to VCCO using single termination. In this case, DCI only controls the impedance of the termination, but not the driver. If users are planning to use GTL or HSTL standards, the external reference resistors should be 50-ohms. The DCI I/O standards that support a driver with single termination are: GTL_DCI, GTLP_DCI, HSTL_IV_DCI, and HSTL_IV_DCI_18. Figure 3-103 illustrates a driver with single termination inside a Virtex-II Pro/ Virtex-II Pro X device
VCCO R
Z0
Virtex-II Pro
UG012_C2_058_121101
Figure 3-103: Driver with Termination to VCCO Using DCI Single Termination
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
229
VCCO /2 R
Z0
UG012_C2_059_121101
Figure 3-104:
DCI can provide this termination to VCCO/2 using split termination. It only controls the impedance of the termination, but not the driver. For HSTL or SSTL standards, the external reference resistors should be 50-ohms. The DCI I/O standards that support a Driver with split termination are: HSTL_II_DCI, HSTL_II_DCI_18, and SSTL2_II_DCI. Figure 3-105 illustrates a driver with split termination inside a Virtex-II Pro/ Virtex-II Pro X device.
VCCO
2R
Z0 2R Virtex-II Pro
UG012_C2_060_121101
Figure 3-105:
230
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Software Support
This section lists the valid DCI I/O buffer library components and describes how to use DCI in the Xilinx software.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
231
The following are DCI output buffer library components: OBUF_GTLP_DCI OBUF_GTL_DCI OBUF_HSTL_I_DCI OBUF_HSTL_II_DCI OBUF_HSTL_III_DCI OBUF_HSTL_IV_DCI OBUF_HSTL_I_DCI_18 OBUF_HSTL_II_DCI_18 OBUF_HSTL_III_DCI_18 OBUF_HSTL_IV_DCI_18 OBUF_LVDCI_15 OBUF_LVDCI_18 OBUF_LVDCI_25 OBUF_LVDCI_33 OBUF_LVDCI_DV2_15 OBUF_LVDCI_DV2_18 OBUF_LVDCI_DV2_25 OBUF_SSTL2_I_DCI OBUF_SSTL2_II_DCI
The following are DCI 3-state output buffer library components: OBUFT_GTLP_DCI OBUFT_GTL_DCI OBUFT_HSTL_I_DCI OBUFT_HSTL_II_DCI OBUFT_HSTL_III_DCI OBUFT_HSTL_IV_DCI OBUFT_HSTL_I_DCI_18 OBUFT_HSTL_II_DCI_18 OBUFT_HSTL_III_DCI_18 OBUFT_HSTL_IV_DCI_18 OBUFT_LVDCI_15 OBUFT_LVDCI_18 OBUFT_LVDCI_25 OBUFT_LVDCI_33 OBUFT_LVDCI_DV2_15 OBUFT_LVDCI_DV2_18
232
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The following are DCI I/O buffer library components: IOBUF_GTLP_DCI IOBUF_GTL_DCI IOBUF_HSTL_II_DCI IOBUF_HSTL_IV_DCI IOBUF_SSTL2_II_DCI IOBUF_HSTL_II_DCI_18 IOBUF_HSTL_IV_DCI_18 IOBUF_LVDCI_15 IOBUF_LVDCI_18 IOBUF_LVDCI_25 IOBUF_LVDCI_33 IOBUF_LVDCI_DV2_15 IOBUF_LVDCI_DV2_18 IOBUF_LVDCI_DV2_25
IOSTANDARD Attribute
The IOSTANDARD attribute can be entered through the NCF or UCF file. The syntax is as follows: NET <net name> IOSTANDARD = LVDCI_25; Where <net name> is the name between the IPAD and IBUF or OPAD or OBUF. For HDL designs, this name is the same as the port name. The following are valid DCI attributes for output drivers: LVDCI_15 LVDCI_18 LVDCI_25 LVDCI_33 LVDCI_DV2_15 LVDCI_DV2_18 LVDCI_DV2_25
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
233
The following are valid DCI attributes for terminations: GTL_DCI GTLP_DCI HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 SSTL2_I_DCI SSTL2_II_DCI
VHDL Example
Instantiating DCI input and output buffers is the same as instantiating any other I/O buffers. Users must make sure that the correct I/O buffer names are used and follow the standard syntax of instantiation. For example, to instantiate a HSTL Class I output DCI buffer, the following syntax can be used: HSTL_DCI_buffer: OBUF_HSTL_I_DCI port map (I=>data_out, O=>data_out_DCI); Below is an example VHDL code that instantiates four 2.5V LVDCI drivers and four HSTL Class I outputs.
-- Module: DCI_TEST --- Description: VHDL example for DCI SelectIO-Ultra -- Device: Virtex-II Pro Family --------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dci_test is port (clk, reset, ce, control : in std_logic; A, B : in std_logic_vector (3 downto 0); Dout : out std_logic_vector (3 downto 0); muxout : out std_logic_vector (3 downto 0)); end dci_test; architecture dci_arch of dci_test is --DCI output buffer component declaration component OBUF_LVDCI_25 port (I : in std_logic; O : out std_logic); end component; attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of OBUF_LVDCI_25 : component is true; attribute black_box_pad_pin of OBUF_LVDCI_25 : component is "O"; --HSTL Class I DCI output buffer component declaration
234
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
component OBUF_HSTL_I_DCI port (I : in std_logic; O: out std_logic); end component; attribute syn_black_box of OBUF_HSTL_I_DCI : component is true; attribute black_box_pad_pin of OBUF_HSTL_I_DCI : component is "O"; signal muxout_int : std_logic_vector (3 downto 0); signal dout_int : std_logic_vector (3 downto 0); begin process (clk, reset) begin if (reset = '1') then dout_int<="0000"; elsif (clk'event and clk='1') then dout_int<=dout_int+1; end if; end process; process (controls, A, B, DOUT_INT) begin if (control='1') then muxout_int<=A and B; else muxout_int<=Dout_int; end if; end process; U0 : OBUF_LVDCI_25 port map( I=>dout_int(0), O=>dout(0)); U1 : OBUF_LVDCI_25 port map( I=>dout_int(1), O=>dout(1)); U2 : OBUF_LVDCI_25 port map( I=>dout_int(2), O=>dout(2)); U3 : OBUF_LVDCI_25 port map( I=>dout_int(3), O=>dout(3)); K0 : OBUF_HSTL_I_DCI port map( I=>muxout_int(0), O=>muxout(0)); K1 : OBUF_HSTL_I_DCI port map( I=>muxout_int(1), O=>muxout(1)); K2 : OBUF_HSTL_I_DCI port map( I=>muxout_int(2), O=>muxout(2)); K3 : OBUF_HSTL_I_DCI port map( I=>muxout_int(3), O=>muxout(3)); end dci_arch;
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
235
The following DCI outputs do not require reference resistors on VRP/VRN: HSTL_I_DCI HSTL_III_DCI HSTL_I_DCI_18 HSTL_III_DCI_18 SSTL3_I_DCI SSTL2_I_DCI
The following inputs do not require reference resistors on VRP/VRN: LVDCI_15 LVDCI_18 LVDCI_25 LVDCI_33 LVDCI_DV2_15 LVDCI_DV2_18 LVDCI_DV2_25 LVDCI_DV2_33
4.
The value of the external reference resistors should be selected to give the desired output impedance. If using GTL_DCI, HSTL_DCI, or SSTL_DCI I/O standards, then they should be 50. The values of the reference resistors must be within the supported range (20 100). Follow the DCI I/O banking rules: a. b. c. VREF must be compatible for all of the inputs in the same bank. VCCO must be compatible for all of the inputs and outputs in the same bank. No more than one DCI I/O standard using Single Termination type is allowed per bank.
5. 6.
236
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
d. No more than one DCI I/O standard using Split Termination type is allowed per bank. e. 7. Single Termination and Split Termination, Controlled Impedance Driver, and Controlled Impedance Driver with Half Impedance can co-exist in the same bank. The D0-D7, INIT, or DOUT pins are used as I/O after configuration One (or more) of those pins is a DCI input or output The programming file option "DCIUpdateMode" is set to "Quiet"
Otherwise, these I/Os will not function properly. In the case of an output, the I/O will be put into a 3-state condition, or will not have the correct termination. In the case of an input, the I/O will not have the correct termination. This does not affect the RDWR_B and CS_B signals, which are also dual-purpose configuration pins. 8. "Quiet" mode set in programming file option "DCIUpdateMode" is not compatible with encrypted bitstream.
The behavior of DCI 3-state outputs is as follows: If a LVDCI or LVDCI_DV2 driver is in 3-state, the driver is 3-stated. If a Driver with Single or Split Termination is in 3-state, the driver is 3-stated but the termination resistor remains. The following section lists any special care actions that must be taken for each DCI I/O standard.
GTL_DCI
GTL does not require a VCCO voltage. However, for GTL_DCI, VCCO must be connected to 1.2V. GTL_DCI provides single termination to VCCO for inputs or outputs.
GTLP_DCI
GTLP does not require a VCCO voltage. However, for GTLP_DCI, VCCO must be connected to 1.5V. GTLP_DCI provides single termination to VCCO for inputs or outputs.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
237
LVDS_25_DCI, LVDSEXT_25_DCI
LVDS_25_DCI and LVDSEXT_25_DCI provide split termination for the P and N inputs only. VRP and VRN should connect to 50 resistors. Equivalently, it provides 100 differential impedance between the LVDS inputs.
238
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
VCCO/2
VCCO/2 R Z0
VCCO/2 R Z0
VCCO R
VCCO R Z0
VCCO R
Conventional
R Z0
VCCO/2
VCCO R
VCCO R
R Z0
VCCO
VCCO/2 R Z0
VCCO 2R Z0 Virtex-II Pro DCI VCCO R 2R Virtex-II Pro DCI VCCO R Z0 Virtex-II Pro DCI VCCO R
VCCO 2R
VCCO 2R Z0 Virtex-II Pro DCI Virtex-II Pro DCI VCCO R 2R Virtex-II Pro DCI VCCO R Z0 Virtex-II Pro DCI VCCO R
VCCO 2R Z0
VCCO R
VCCO R Z0
Bidirectional
N/A
N/A
Virtex-II Pro DCI
Reference Resistor
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
Recommended Z0
DS083-2_65a_061603
Figure 3-106:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
239
SSTL2_I or SSTL18_I
VCCO/2 R
SSTL2_II or SSTL18_II
VCCO/2 R
VCCO/2 R Z0
Conventional
R/2
Z0 R/2
VCCO/2
VCCO 25(1) 2R Z0 2R
VCCO/2 R
VCCO
VCCO/2 R Z0 R/2
VCCO 2R
25(1)
VCCO 2R Z0 25(1)
VCCO 2R
VCCO 25(1) 2R Z0
Bidirectional
N/A
Reference Resistor
VRN = VRP = R = Z0 50
VRN = VRP = R = Z0 50
DS083-2_65b_011603
Recommended Z0(2)
Notes: 1. The SSTL-compatible 25 series resistor is accounted for in the DCI buffer, and it is not DCI controlled. 2. Z0 is the recommended PCB trace impedance.
Figure 3-107:
240
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Z0
Conventional
2R
Z0
VCCO 2R
Z0
Reference Resistor
VRN = VRP = R = Z0
Figure 3-108:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
241
GTL/GTLP DCI
VCCO
VCCO R Z0
Conventional
VCCO R
VCCO R Z0
VCCO R
VCCO
VCCO R Z0
VCCO R
VCCO R Z0
Bidirectional
Virtex-II Pro DCI
Reference Resistor
VRN = VRP = R = Z0 50
Recommended Z0
Figure 3-109:
242
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Data Flow
Input DDR
Input DDR is accomplished via a single input signal driving two registers in the IOB. Both registers are clocked on the rising edge of their respective clocks. With proper clock forwarding, alternating bits from the input signal are clocked in on the rising edge of the two clocks, which are 180 degrees out of phase. Figure 3-110 depicts the input DDR registers and the signals involved.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
243
D CE
CLK0
Q0
CK
DATA
SET/ PRESET
RESET/ CLR
CE
D CE
CLK1
Q1
CK
SET/ PRESET
RESET/ CLR
SET/PRE RESET/CLR
UG002_C2_036_031301
Figure 3-110:
Input DDR
CLK0 and CLK1 are 180 degrees out of phase. Both registers share the SET/PRE and RESET/CLR lines. As shown in Figure 3-111, alternating bits on the DATA line are clocked in via Q0 and Q1 while CE is High. The clocks are shifted out of phase by the DCM (CLK0 and CLK180 outputs) or by the inverter available on the CLK1 clock input.
244
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
CLK0
CLK1
CE
DATA
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
OUTPUT Q0 OUTPUT Q1
D0A
D2A
D4A
D6A
D1A
D3A
D5A
UG002_C2_037_032201
Output DDR
Output DDR registers are used to clock output from the chip at twice the throughput of a single rising-edge clocking scheme. Clocking for output DDR is the same as input DDR. The clocks driving both registers are 180 degrees out of phase. The DDR MUX selects the register outputs. The output consists of alternating bits from DATA_1 and DATA_2. Figure 3-112 depicts the output DDR registers and the signals involved.
DATA2
D CE
Q2
CLK2
CK
SET/ PRESET RESET/ CLR
CE
DDR MUX
DATA1
OUT
D CE
Q1
CLK1
CK
SET/ PRESET RESET/ CLR
SET/PRE RESET/CLR
UG002_C2_038_101300
Figure 3-112:
Output DDR
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
245
Both registers share the SET/PRE and RESET/CLR line. Both registers share the CE line which must be High for outputs to be seen on Q1 and Q2. Figure 3-113 shows the data flow for the output DDR registers.
1 CLK1 2 3 4 5 6
CLK2
DATA_1
D1A
D1B
D1C
DATA_2
D2A
D2B
D2C
OUT
D1A
D2A
D1B
D2B
D1C
UG002_C2_039_101300
Figure 3-113:
246
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
D CE CK
SET/ PRESET
Q2
RESET/ CLR
CET
DDR MUX
TRI1
D CE CK
SET/ PRESET
Q1
RESET/ CLR
DATA1
D CE
Q1
CLK1
CK
CLK2
SET/ PRESET
RESET/ CLR
DDR MUX
OUT
CE
DATA2
D CE CK
SET/ PRESET
Q2
RESET/ CLR
SET/PRE RESET/CLR
UG012_C2_040_020205
Figure 3-114:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
247
All four registers share the SET/PRESET and RESET/CLEAR lines. Two registers are required to accomplish the DDR task and two registers are required for the 3-state control. There are two Clock Enable signals, one for output DDRs performing the DDR function and another for the output DDRs performing the 3-state control function. Two 180 degree out of phase clocks are used. CLK1 clocks one of the DDR registers and a 3-state register. CLK2 clocks the other DDR register and the other 3-state register. The DDR registers and 3-state registers are associated by the clock that is driving them. Therefore, the DDR register that is clocked by CLK1 is associated to the 3-state register being clocked by CLK1. The remaining two registers are associated by CLK2. If both 3-state registers are driving a logic High, the output sees a high impedance. If both 3-state registers are driving a logic Low, the output sees the values from the DDR MUX see Figure 3-115).
CLK1
CLK2
DATA_1
D1A
D1B
D1C
D1D
DATA_2
D2A
D2B
D2C
D2D
TRI 1 TRI 2
OUT
D1A
D2A
D1B
D2B
D1C
ZZZ
UG002_C2_041_101300
Figure 3-115:
When the 3-state registers are not driving the same logic value, the 3-state register being clocked by CLK1 is called TREG1. The other 3-state register TREG2 is clocked by CLK2. Similarly, the DDR register being clocked by CLK1 is called DREG1, and the other DDR register DREG2 is clocked by CLK2. If TREG1 is driving a logic High and TREG2 is driving a logic Low, the output sees a high impedance when CLK1 is High and the value out of DREG2 when CLK2 is High. If TREG2 is driving a logic High and TREG1 is driving a logic Low, the output sees a high impedance when CLK2 is High and the value out of DREG1 when CLK1 is High.
248
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Characteristics
All registers in an IOB share the same SET/PRE and RESET/CLR lines. The 3-State and Output DDR registers have common clocks (OTCLK1 & OTCLK2). All signals can be inverted (with no added delay) inside the IOB. DDR MUXing is handled automatically within the IOB. There is no manual control of the MUX-select. This control is generated from the clock. When several clocks are used, and when using DDR registers, the floorplan of a design should take into account that the input clock to an IOB is shared with a pair of IOBs.
Library Primitives
Input DDR registers are inferred, and dedicated output DDR registers have been provided as primitives for Virtex-II Pro/Virtex-II Pro X designs. Input DDR registers consist of two inferred registers that clock in a single data line on each edge. Generating 3-state output with DDR registers is as simple as instantiating a primitive.
S D0 D1 CE FDDRRSE Q
C0 C1 R
UG002_C2_034_032201
Figure 3-116: FDDRRSE Symbol: DDR Flip-Flop With Clock Enable and Synchronous Reset and Set
PRE D0 D1 CE FDDRCPE Q
C0 C1 CLR
UG002_C2_035_101300
Figure 3-117: FDDRCPE Symbol: DDR Flip-Flop With Clock Enable and Asynchronous PRESET and CLR
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
249
Port Signals
FDDRRSE
Data Inputs - D0 and D1
D0 and D1 are the data inputs into the DDR flip-flop. Data on the D0 input is loaded into the flip-flop when R and S are Low and CE is High during a Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when R and S are Low and CE is High during a Low-to-High C1 clock transition.
Clock Enable - CE
The enable pin affects the loading of data into the DDR flip-flop. When Low, new data is not loaded into the flip-flop. CE must be High to load new data into the flip-flop.
Clocks - C0 and C1
These two clocks are phase shifted 180 degrees (via the DLL) and allow selection of two separate data inputs (D0 and D1).
Data Output - Q
When power is applied, the flip-flop is asynchronously cleared and the output is Low. During normal operation, The value of Q is either D0 or D1. The Data Inputs description above states how the value of Q is chosen.
FDDRCPE
Data Inputs - D0 and D1
D0 and D1 are the data inputs into the DDR flip-flop. Data on the D0 input is loaded into the flip-flop when PRE and CLR are Low and CE is High during a Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when PRE and CLR are Low and CE is High during a Low-to-High C1 clock transition.
250
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Clock Enable - CE
The enable pin affects the loading of data into the DDR flip-flop. When Low, clock transitions are ignored and new data is not loaded into the flip-flop. CE must be High to load new data into the flip-flop.
Clocks - C0 and C1
These two clocks are phase shifted 180 degrees (via the DLL) and allow selection of two separate data inputs (D0 and D1).
Data Output - Q
When power is applied, the flip-flop is asynchronously cleared and the output is Low. During normal operation, The value of Q is either D0 or D1. The Data Inputs description above states how the value of Q is chosen.
Location Constraints
DDR instances can have LOC properties attached to them to constrain pin placement. The LOC constraint uses the following form.
NET <net_name> LOC=A8;
where A8 is a valid I/O pin location. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. If two adjacent IOBs using DDR registers do not share the same clock signals on their clock pins (ICLK1, ICLK2, OTCLK1, and OTCLK2), or a DDR register locates next to a single data rate register that uses a different clock, one of the clock signals will be unroutable.
Applications
DDR SDRAM
The DDR SDRAM is an enhancement to the Synchronous DRAM by effectively doubling the data throughput of the memory device. Commands are registered at every positive clock edge. Input data is registered on both edges of the data strobe, and output data is referenced to both edges of the data strobe, as well as both edges of the clock.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
251
Clock Forwarding
DDR can be used to forward a copy of the clock on the output. This can be useful for propagating a clock along with double-data-rate data that has an identical delay. It is also useful for multiple clock generation, where there is a unique clock driver for every clock load.
Input DDR
To implement an Input DDR application, paste the following template in your code.
DDR_input.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DDR_Input is Port ( clk : in std_logic; d : in std_logic; rst : in std_logic; q1 : out std_logic; q2 : out std_logic ); end DDR_Input; --Describe input DDR registers (behaviorally) to be inferred architecture behavioral of DDR_Input is begin q1reg : process (clk, d, rst) begin if rst='1' then --asynchronous reset, active high q1 <= '0'; elsif clk'event and clk='1' then --Clock event - posedge q1 <= d; end if; end process; q2reg : process (clk, d, rst) begin if rst='1' then --asynchronous reset, active high q2 <= '0'; elsif clk'event and clk='0' then --Clock event - negedge q2 <= d; end if;
252
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
------------
NOTE: You must include the following constraints in the .ucf file when running back-end tools, in order to ensure that IOB DDR registers are used: INST "q2_reg" IOB=TRUE; INST "q1_reg" IOB=TRUE; Depending on the synthesis tools you use, it may be required to check the edif file for modifications to original net names...in this case, Synopsys changed the names: q1 and q2 to q1_reg and q2_reg
DDR_input.v
module DDR_Input (data_in , q1, q2, clk, rst); input data_in, clk, rst; output q1, q2; reg q1, q2;
//Describe input DDR registers (behaviorally) to be inferred always @ (posedge clk or posedge rst) //rising-edge DDR reg. and asynchronous reset begin if (rst) q1 = 1'b0; else q1 = data_in; end always @ (negedge clk or posedge rst) //falling-edge DDR reg. and asynchronous reset begin if (rst) q2 = 1'b0; else q2 = data_in; end endmodule /* NOTE: You must include the following constraints in the .ucf file when running back-end tools, \ in order to ensure that IOB DDR registers are used: INST "q2_reg" IOB=TRUE; INST "q1_reg" IOB=TRUE;
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
253
Depending on the synthesis tools you use, it may be required to check the edif file for modifications to original net names...in this case, Synopsys changed the names: q1 and q2 to q1_reg and q2_reg */
Output DDR
To implement an Output DDR application, paste the following template in your code.
DDR_out.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- pragma translate_off LIBRARY UNISIM; use UNISIM.VCOMPONENTS.ALL; --pragma translate_on entity DDR_Output is Port( clk : in std_logic; --clk and clk180 can be outputs from the DCM or clk180 can be the clk180 : in std_logic; --logical inverse of clk (the inverter is located in the IOB and will be inferred. d0 : in std_logic; --data in to fddr d1 : in std_logic; --data in to fddr ce : in std_logic; --clock enable rst : in std_logic; --reset set : in std_logic; --set q : out std_logic --DDR output ); end DDR_Output; architecture behavioral of DDR_Output is component FDDRRSE port( Q : out std_logic; D0 : in std_logic; D1 : in std_logic; C0 : in std_logic; C1 : in std_logic; CE : in std_logic; R : in std_logic; S : in std_logic ); end component; begin U0: FDDRRSE port map ( Q => q, D0 => d0, D1 => d1, C0 => clk,
254
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
end behavioral;
DDR_out.v
module DDR_Output (d0 , d1, q, clk, clk180, rst, set, ce); input d0, d1, clk, clk180, rst, set, ce; output q;
//Synchronous Output DDR primitive instantiation FDDRRSE U1 ( .D0(d0), .D1(d1), .C0(clk), .C1(clk180), .CE(ce), .R(rst), .S(set), .Q(q) );
endmodule
DDR_3state.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- pragma translate_off LIBRARY UNISIM; use UNISIM.VCOMPONENTS.ALL; --pragma translate_on entity DDR_3state is Port( clk : in std_logic; --clk and clk180 can be outputs from the DCM or clk180 can be the clk180 : in std_logic; --logical inverse of clk (the inverter is located in the IOB and will be inferred. d0 : in std_logic; --data in to fddr d1 : in std_logic; --data in to fddr ce : in std_logic; --clock enable set : in std_logic; --set rst : in std_logic; --reset en0 : in std_logic; --enable signal en1 : in std_logic; --enable signal data_out : out std_logic --data seen at pad
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
255
); end DDR_3state; architecture behavioral of DDR_3state is signal ddr_out, tri : std_logic; component FDDRRSE port ( Q : out std_logic; D0 : in std_logic; D1 : in std_logic; C0 : in std_logic; C1 : in std_logic; CE : in std_logic; R : in std_logic; S : in std_logic ); end component;
begin --Instantiate Ouput DDR registers U0: FDDRRSE port map(Q => tri, D0 => en0, D1 => en1, C0 => clk, C1 => clk180, CE => ce, R => rst, S => set ); --Instantiate three-state DDR registers U1: FDDRRSE port map( Q => ddr_out, D0 => d0, D1 => d1, C0 => clk, C1 => clk180, CE => ce, R => rst, S => set ); --inferr the 3-State buffer process(tri, ddr_out) begin if tri = '1' then data_out <= 'Z'; elsif tri = '0' then data_out <= ddr_out; end if; end process; end behavioral;
DDR_3state.v
256
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
module DDR_3state (d0 , d1, data_out, en_0, en_1, clk, clk180, rst, set, ce); input d0, d1, clk, clk180, rst, set, ce, en_0, en_1; output data_out; reg data_out; wire q, q_tri; //Synchronous Output DDR primitive instantiation FDDRRSE U1 ( .D0(d0), .D1(d1), .C0(clk), .C1(clk180), .CE(ce), .R(rst), .S(set), .Q(q) );
//Synchronous 3-State DDR primitive instantiation FDDRRSE U2 ( .D0(en_0), .D1(en_1), .C0(clk), .C1(clk180), .CE(ce), .R(rst), .S(set), .Q(q_tri) );
//3-State buffer description always @ (q_tri or q) begin if (q_tri) data_out = 1'bz; else data_out = q; end endmodule
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
257
LVDS I/O
Introduction
Low Voltage Differential Signaling (LVDS) is a very popular and powerful high-speed interface in many system applications. Virtex-II Pro/Virtex-II Pro X I/Os are designed to comply with the EIA/TIA electrical specifications for LVDS to make system and board design easier. With the addition of an LVDS current-mode driver in the IOBs, which eliminates the need for external source termination in point-to-point applications, and with the choice of an extended mode, Virtex-II Pro/Virtex-II Pro X devices provide the most flexible solution for doing an LVDS design in an FPGA. Table 3-58 lists all LVDS standards that are available for Virtex-II Pro/Virtex-II Pro X devices. Table 3-58: Available LVDS Standards
Input (IBUFDS) Output (OBUFDS) 3-State (OBUFTDS) Clock (IBUFGDS) Bi-Directional (IOBUF)
IOSTANDARD LVDS_25 LVDSEXT_25 (1) LVDS_25_DCI LVDSEXT_25_DCI (1) BLVDS_25 LDT_25 LVPECL_25 ULVDS_25 LDT_25_DT (2) LVDSEXT_25_DT (1,2) LVDS_25_DT (2) ULVDS_25_DT (2) Notes:
1. LVDSEXT = Extended mode LVDS buffer. This buffer provides a higher drive capability and voltage swing (350 - 750 mV), which makes it ideal for long-distance or cable LVDS links. The output AC characteristics of this LVDS Extended Mode driver are not within the EIA/TIA specifications. This LVDS Extended Mode driver is intended for situations that require higher drive capabilities in order to produce an LVDS signal that is within EIA/TIA specification at the receiver. 2. On-chip termination option is available. See LVDS Receiver Termination, page 260 for more instantiation details.
258
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
IBUFDS_LVDS*/IBUFGDS_LVDS* I IB
UG002_C2_031_100200
LVDS Input and Clock Buffer Primitives LVDS Inputs LVDS Clocks IBUFGDS IBUFGDS_LVDS_25 IBUFGDS_LVDSEXT_25 IBUFGDS_LVDS_25_DCI IBUFGDS_LVDSEXT_25_DCI
IBUFDS IBUFDS_LVDS_25 IBUFDS_LVDSEXT_25 IBUFDS_LVDS_25_DCI IBUFDS_LVDSEXT_25_DCI IBUFDS_BLVDS_25 IBUFDS_LDT_25 IBUFDS_LVPECL_25 IBUFDS_ULVDS_25 IBUFDS_LDT_25_DT (1) IBUFDS_LVDSEXT_25_DT (1) IBUFDS_LVDS_25_DT (1) IBUFDS_ULVDS_25_DT (1)
Notes:
1. On-chip termination option is available. See LVDS Receiver Termination, page 260 for more instantiation details.
To create an LVDS input, instantiate the desired mode (2.5V or Extended) LVDS input buffer. Notice that the P and N channels are included in the primitive (I = P, IB = N). Software automatically uses the appropriate pin from an adjacent IOB for the N channel. The same applies to LVDS clocks: Use IBUFGDS_LVDS*
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
259
Verilog Instantiation
IBUFDS_LVDS_25 U1 ( .I(data_in_P), .IB(data_in_N), .O(data_in) );
Port Signals
I = P-channel data input to the LVDS input buffer IB = N-channel data input to the LVDS input buffer O = Non-differential input data from LVDS input buffer
Location Constraints
NET "data_in_P" LOC= "<pin_location>";
Figure 3-119 is an example of a typical termination for an LVDS receiver on a board with 50 transmission lines.
LVDS Line Driver P
Z = 50
Data out Z = 50 N
0
100
Data in
IBUFDS_LVDS
UG012_C2_028_051603
260
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Verilog Instantiation
IBUFDS # (.IOSTANDARD("LVDS_25_DT")) U1 ( .O(data_in), .I(data_in_P), .IB(data_in_N) );
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
261
The pin names used are the same as those used in the HDL library primitives.
OBUFDS_LVDS*
O OB
UG002_C2_032_100200
Figure 3-120: LVDS Output Buffer Primitives To create an LVDS output, instantiate the desired mode (2.5 or Extended) LVDS output buffer. Notice that the P and N channels are included in the primitive (O = P, OB = N). Software automatically uses the appropriate pin from an adjacent IOB for the N channel.
Verilog Instantiation
OBUFDS_LVDS_25 U1 ( .I(data_out), .O(data_out_P), .OB(data_out_N) );
Port Signals
I = data input to the LVDS input buffer O = P-channel data output OB = N-channel data output
Location Constraints
NET "data_out_P" LOC= "<pin_location>";
262
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
compliant) LVDS signal. Figure 3-121 illustrates an LVDS transmitter on a board with 50 transmission lines.
Data out
100
UG012_C2_029_121101
Figure 3-121:
The pin names used are the same as those used in the HDL library primitives.
OBUFTDS_LVDS* T
O OB
UG002_C2_033_100200
Figure 3-122:
To create an LVDS 3-State output, instantiate the desired mode (2.5V or Extended) LVDS 3-state buffer. Notice that the P and N channels are included in the primitive (O = P, OB = N). Software automatically uses the appropriate pin from an adjacent IOB for the N channel.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
263
Verilog Instantiation
OBUFTDS_LVDS_25 U1 ( .I(data_out), .T(tri), .O(data_out_P), .OB(data_out_N)
);
Port Signals
I = data input to the 3-state output buffer T = 3-State control signal O = P-channel data output OB = N-channel data output
Location Constraints
NET "data_out_P" LOC = "<pin_location>";
+ 100 + -
+ -
OBUFTDS_LVDS*
OBUFTDS_LVDS*
LVDS Receiver
UG012_C2_030_121101
Figure 3-123:
264
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
VHDL Instantiation
blvds_io: IOBUFDS_BLVDS_25 port map ( I => data_out, O => data_in, T => tri, IO => data_IO_P, IOB => data_IO_N );
Verilog Instantiation
IOBUFDS_BLVDS_25 blvds_io ( .I(data_out), .O(data_in), .T(tri), .IO(data_IO_P), .IOB(data_IO_N)
);
Port Signals
I = data output: internal logic to LVDS I/O buffer T = 3-State control to LVDS I/O buffer IO = P-channel data I/O to or from BLVDS pins IOB = N-channel data I/O to or from BLVDS pins O = Data input: off-chip data to LVDS I/O buffer
Location Constraints
Only the P or N channel must be constrained. Software automatically places the corresponding channel of the pair on the appropriate pin.
LDT
Lightning Data Transport (LDT) is a high speed interface and protocol introduced by Advanced Micro Devices. LDT is a differential signaling based interface that is very similar to LVDS. Virtex-II Pro/Virtex-II Pro X IOBs are equipped with LDT buffers. These buffers also have corresponding software primitives as follows: IBUFDS_LDT_25 IBUFGDS_LDT_25 OBUFDS_LDT_25 OBUFTDS_LDT_25
LDT Implementation
LDT implementation is the same as LVDS with DDR, so follow all of the rules and guidelines set forth earlier in this chapter for LVDS-DDR, and replace the LVDS buffer with the corresponding LDT buffer. For more information on Virtex-II Pro/Virtex-II Pro X LDT electrical specification, refer to the Data Sheet.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
265
LVPECL I/O
Introduction
Low Voltage Positive Emitter-Coupled Logic (LVPECL) is a very popular and powerful high-speed interface in many system applications. Virtex-II Pro/Virtex-II Pro X I/Os are designed to comply with the EIA/TIA electrical specifications for 2.5V LVPECL to make system and board design easier. Table 3-60 lists all LVPECL primitives that are available for Virtex-II Pro/Virtex-II Pro X devices. Table 3-60: Available LVPECL Primitives
Output
OBUFDS_LVPECL_25
Input
IBUFDS_LVPECL_25
3-State
OBUFTDS_LVPECL_25
Clock
IBUFGDS_LVPECL_25
Bi-Directional
IBUFDS_LVPECL*/IBUFGDS_LVPECL* I IB
ug012_c2_067_082902
Figure 3-124:
To create an LVPECL input, instantiate the 2.5V LVPECL input buffer. Notice that the P and N channels are included in the primitive (I = P, IB = N). Software automatically uses the appropriate pin from an adjacent IOB for the N channel. The same applies to LVPECL clocks: Use IBUFGDS_LVPECL*.
266
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Verilog Instantiation
IBUFDS_LVPECL_25 U1 ( .I(data_in_P), .IB(data_in_N), .O(data_in) );
Port Signals
I = P-channel data input to the LVPECL input buffer IB = N-channel data input to the LVPECL input buffer O = Non-differential input data from LVPECL input buffer
Location Constraints
NET "data_in_P" LOC= "<pin_location>";
Z0 = 50
IN
Data out Z 0 = 50 N
Data in
INX
IBUFDS_LVPECL
UG012_C2_068_082902
Figure 3-125:
The pin names used are the same as those used in the HDL library primitives.
OBUFDS_LVPECL*
O OB
ug012_c2_069_082902
Figure 3-126:
To create an LVPECL output, instantiate the desired mode LVPECL output buffer. Notice that the P and N channels are included in the primitive (O = P, OB = N). Software
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
267
automatically uses the appropriate pin from an adjacent IOB for the N channel. Refer to Table 3-36 for simultaneous switiching output guideline for LVPECL drivers.
Verilog Instantiation
OBUFDS_LVPECL_25U1 ( .I(data_out), .O(data_out_P), .OB(data_out_N) );
Port Signals
I = data input to the LVPECL input buffer O = P-channel data output OB = N-channel data output
Location Constraints
NET "data_out_P" LOC= "<pin_location>";
RS
ug012_c2_66_082902
Figure 3-127:
268
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Bitstream Encryption
Virtex-II Pro/Virtex-II Pro X devices have an on-chip decryptor that can be enabled to make the configuration bitstream (and thus the whole logic design) secure. The user can encrypt the bitstream in the Xilinx software, and the FPGA then performs the reverse operation, decrypting the incoming bitstream, and internally recreating the intended configuration. This method provides a very high degree of design security. Without knowledge of the encryption/decryption key or keys, potential pirates cannot use the externally intercepted bitstream to analyze, or even to clone the design. System manufacturers can be sure that their Virtex-II Pro/Virtex-II Pro X implemented designs cannot be copied and reverse engineered. The Virtex-II Pro/Virtex-II Pro X devices store the internal decryption keys in a few hundred bits of dedicated RAM, backed up by a small externally connected battery. At <100 nA load, the endurance of the battery is only limited by its shelf life. Refer to Appendix C, Choosing the Battery for VBATT for suggestions on choosing a backup battery. The method used to encrypt the data is Data Encryption Standard (DES). This is an official standard supported by the National Institute of Standards and Technology (NIST) and the U. S. Department of Commerce. DES is a symmetric encryption standard that utilizes a 56-bit key. Because of the increased sophistication and speed of todays computing hardware, single DES is no longer considered to be secure. However, the Triple Data Encryption Algorithm (TDEA), otherwise known as triple DES, is authorized for use by U. S. federal organizations to protect sensitive data and is used by many financial institutions to protect their transactions. Triple DES has yet to be cracked. Both DES and triple DES are available in Virtex-II Pro/Virtex-II Pro X devices.
What DES Is
DES and triple DES are symmetric encryption algorithms. This means that the key to encrypt and the key to decrypt are the same. The security of the data is kept by keeping the key secret. This contrasts to a public key system, like RSA or PGP. One thing to note is that Virtex-II Pro/Virtex-II Pro X devices use DES in Cipher Block Chaining mode. This means that each block is combined with the previous encrypted block for added security. DES uses a single 56-bit key to encrypt 64-bit blocks one at a time.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
269
For a popular description of the origin and the basic concept of DES and many other older and newer encryption schemes, see the recent best-seller: The Code Book by Simon Singh, Doubleday 1999, ISBN 0-385-49531-5
Creating Keys
For Virtex-II Pro/Virtex-II Pro X, DES or triple DES (TDEA) can be used. DES uses a single 56-bit key, where triple-DES always uses three such keys. All of the keys can be chosen by the BitGen program at random, or can be explicitly specified by the user. Virtex-II Pro/Virtex-II Pro X devices can have six separate keys programmed into the device. A particular device can store two sets of triple-DES keys and can thus accept alternate bitstreams from two competing IP vendors, without providing access to each other's design. However, all of the keys must be programmed at once. An encrypted bitstream is created by the BitGen program. Keys and key options can be chosen in two ways: by command-line arguments to BitGen, or by specifying a KeyFile (with the g KeyFile command-line option). The BitGen options relevant to encryption are listed in Table 3-62. Table 3-62: Option Encrypt Key0 Key1 Key2 Key3 Key4 Key5 KeyFile Keyseq0 Keyseq1 Keyseq2 Keyseq3 Keyseq4 BitGen Encryption Options Description Whether to encrypt the bitstream DES Key 0 DES Key 1 DES Key 2 DES Key 3 DES Key 4 DES Key 5 Location of separate key definition file Set the key sequence for key 0 (S = single, F = first, M = middle, L = last) Set the key sequence for key 1 Set the key sequence for key 2 Set the key sequence for key 3 Set the key sequence for key 4 Values (default first where appropriate) No, Yes pick, <hex string> pick, <hex string> pick, <hex string> pick, <hex string> pick, <hex string> pick, <hex string> <string> S,F,M,L S,F,M,L S,F,M,L S,F,M,L S,F,M,L
270
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
BitGen Encryption Options Description Set the key sequence for key 5 Key number to start decryption Constant Block Chaining start value Values (default first where appropriate) S,F,M,L 0,3 pick, <string>
The key sequence (Keyseq) is set to S for single key encryption, F for first key in multi-key encryption, M for middle key in multi-key encryption, and L for last key in multi-key encryption. When the KeyFile option is specified, BitGen looks in that file for all other DES key options listed above. An example for the input KeyFile using triple DES is:
# Comment for key file Key 0 0x9ac28ebeb2d83b; Key 1 pick; Key 2 string for my key; Key 3 0x00000000000000; Key 4 8774eb3ebb4f84; Keyseq 0 F; Keyseq 1 M; Keyseq 2 L; Keyseq 3 F; Keyseq 4 M; Keyseq 5 L; Key StartCBC 503f2f655b1b2f82; StartKey 0;
Every key is given in the output key file, with unused key locations set to "0x0000000000000000. The proper key sequence prefix is added for all used keys. The prefix is preserved for unused keys, if the user specified a value. The output key file has the same base file name as the .bit file, but with a .nky file extension. The command line equivalent of the input key file above is as follows:
bitgen -g security:level1 -g Encrypt:Yes -g Key0: 0x9ac28ebeb2d83b -g Key1:pick -g Key2:- string for my key- -g Key30x00000000000000 -g Key4:8774eb3ebb4f84 -g Keyseq0:F, -g Keyseq1:M, -gKeyseq2:L -g Keyseq3:F -g Keyseq4:M -g Keyseq5:L -g StartCBC:503f2f655b1b2f82 -g StartKey:0 myinput.ncd
The output key file from either of the above inputs looks something like this:
Device 2VP4FG456; Key 0 0x9ac28ebeb2d83b; Key 1 0xdb1adb5f08b972; Key 2 0x5452032773c286; Key 3 0x00000000000000; Key 4 0x8774eb3ebb4f84; Key 5 0x00000000000000; Keyseq 0 F; Keyseq 1 M; Keyseq 2 L; Keyseq 3 F; Keyseq 4 M;
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
271
In the case of the string for Key2, if the keyvalue is a character string, BitGen encodes the string into a 56-bit hex string. The same character string gives the same 56-bit hex string every time. This enables passwords or phrases to be used instead of hex strings. The above keys are all specified as 64 bits each. The first 8 bits are used by Xilinx as header information and the following 56 bits as the key. BitGen accepts 64 bit keys, but automatically overrides the header, if necessary. Because of security issues, the g Compress option cannot be used with bitstream encryption. Also, partial reconfiguration is not allowed. In order to guarantee security of a bitstream, the Constant Block Chaining (CBC) initial value should be different for each design. The actual value of the CBC is not important, only that it be a different value for every different bitstream that is encrypted with the same key or every re-encryption of the same bitstream with a different key.
Loading Keys
DES keys can only be loaded through JTAG. The iMPACT tools have the capability to take a .nky file and program the device with the keys. In order to program the keys, a keyaccess mode is entered. When this mode is entered, all of the FPGA memory, including the keys and configuration data, is cleared. Once the keys are programmed, they cannot be reprogrammed without clearing the entire device. This key access mode is completely transparent to most users. Keys are programmed using the ISC_PROGRAM instruction, as detailed in the JTAG 1532 specification. SVF generation is also supported, if keys are to be programmed using a different method, such as a microprocessor or JTAG test software.
VBATT
VBATT is a separate battery voltage to allow the keys to remain programmed in the Virtex-II Pro/Virtex-II Pro X device. VBATT draws very little current (on the order of nA) to keep the keys programmed. A small watch battery is suitable. Refer to VBATT DC Characteristics in the Data Sheet and the batterys specifications to estimate its lifetime. For a detailed discussion of battery types suitable for use as a VBATT source, see Appendix C, Choosing the Battery for VBATT.
272
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
While the auxiliary voltage (VCCAUX) is applied, VBATT does not draw any current, and the battery can be removed or exchanged.
Refer to the "PC Board Layout" section of these data sheets for important design considerations. 2. National Semiconductor LM83 or LM86 Triple-Diode Input and Local Digital Temperature Sensors with Two-Wire Interface. For general information on these devices, go to the National Semiconductor website at http://www.national.com. Specifically, the data sheets for these devices can be found at:
http://www.national.com/ds/LM/LM83.pdf http://www.national.com/ds/LM/LM86.pdf
Refer to the "Application Hints" section of these data sheets for important design considerations.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
273
274
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
ug002_c2_068b_100901
Figure 3-128:
Smart-IP Technology
Smart-IP technology leverages Xilinx FPGA architectural features, such as look-up tables (LUTs), distributed RAM, segmented routing and floorplanning information, as well as relative location constraints and expert logic mapping to optimize the performance of every core instance in a given Xilinx FPGA design. In the context of Virtex-II Pro/ Virtex-II Pro X cores, Smart-IP technology includes the use of the special high-performance Virtex-II Pro/Virtex-II Pro X architectural features, such as embedded 18x18 multipliers, block memory, shift register look-up tables (SRL16s), and special wide mux elements. Smart-IP technology delivers: Physical layouts optimized for high performance Predictable high performance and efficient resource utilization Reduced power requirements through compact design and interconnect minimization Performance independent of device size Ability to use multiple cores without deterioration of performance Reduced compile time over competing architectures
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
275
Netlist Constraints
Netlist
Design Implementation
ug002_c2_069_101001
Figure 3-129:
Notes:
1. The outputs produced by the CORE Generator consist of an implementation Netlist and optional schematic symbol, HDL template files, and HDL simulation model wrapper files.
Core Types
Parameterized Cores
The CORE Generator System supplies a wide assortment of parameterized IP cores that can be customized to meet specific Virtex-II Pro/Virtex-II Pro X design needs and size constraints. See Figure 3-130. For each parameterized core, the CORE Generator System supplies: A customized EDIF implementation netlist (.EDN) A parameterized Verilog or VHDL behavioral simulation model (.V, .VHD) and corresponding wrapper file (also .V, .VHD) Verilog or VHDL templates (.VEO, .VHO) An ISE Foundation or Viewlogic schematic symbol
The EDIF implementation netlist is used by the Xilinx tools to implement the core. The other design files generated depend on the Design Entry settings specified (target CAE vendor, and design flow type -- schematic or HDL). Schematic symbol files are generated when a schematic design flow is specified for the project. Parameterized HDL simulation models are provided in two separate HDL simulation libraries, one for Verilog functional simulation support, and the other for VHDL functional simulation support. The libraries, which are included as part of the Xilinx installation, are in the following locations:
276
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
$XILINX/verilog/src/XilinxCoreLib $XILINX/vhdl/src/XilinxCoreLib
ug002_c2_070a_100501
Figure 3-130:
If using a compiled simulator, these libraries must be precompiled before performing a functional simulation of the cores. An analyze_order file describing the required compile order of these models is included with each XilinxCoreLib library, one for Verilog (verilog_analyze_order) and one for VHDL (vhdl_analyze_order). For an HDL design flow, Verilog and VHDL templates (.VEO and .VHO files) are also provided to facilitate the integration of the core into the design for the purposes of functional simulation, synthesis, and implementation. The Verilog (.V) and VHDL (.VHD) wrapper files are also generated. The wrapper files for a particular core are compiled like normal simulation models. They convey custom parameter values to the corresponding generic, parameterized behavioral model for that core in the XilinxCoreLib library. The custom parameter values are used to tailor the behavior of the customized core. The following is a sample VHO template:
component adder8 port ( a: IN std_logic_VECTOR(7 downto 0); b: IN std_logic_VECTOR(7 downto 0); c: IN std_logic; ce: IN std_logic; ci: IN std_logic; clr: IN std_logic; s: OUT std_logic_VECTOR(8 downto 0)); end component;
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
277
-- Synplicity black box declaration attribute black_box : boolean; attribute black_box of test: component is true; -- COMP_TAG_END ------ End COMPONENT Declaration ------------- The following code must appear in the VHDL architecture -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG your_instance_name : adder8 port map ( a => a, b => b, c => c, ce => ce, ci => ci, clr => clr, s => s); -----INST_TAG_END ------ End INSTANTIATION Template -----------You must compile the wrapper file test.vhd when simulating the core, test. When compiling the wrapper file, be sure to reference the XilinxCoreLib VHDL simulation library. For detailed instructions, please refer to the "Core Generator Guide".
Examples include the fixed netlist Xilinx FFTs and most AllianceCORE products. Since the HDL behavioral models for fixed netlist cores are not parameterized, the corresponding .VEO and .VHO template files are correspondingly simple. They do not need to pass customizing parameter values to a library behavioral model.
278
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
When installing the CORE Generator software, the designer gains immediate access to dozens of cores supplied by the LogiCORE Program. In addition, data sheets are available for all AllianceCORE products, and additional, separately licensed, advanced function LogiCORE products are also available. New and updated Virtex-II Pro/Virtex-II Pro X IP for the CORE Generator can be downloaded from the IP Center and added to the CORE Generator catalog.
LogiCORE Program
LogiCORE products are designed, sold, licensed, and supported by Xilinx. LogiCORE products include a wide selection of generic, parameterized functions, such as muxes, adders, multipliers, and memory cores which are bundled with the Xilinx CORE Generator software at no additional cost to licensed software customers. System-level cores, such as PCI, Reed-Solomon, ADPCM, HDLC, POS-PHY, and Color Space Converters are also available as optional, separately licensed products. Probably, the most common application of the CORE Generator is to use it to quickly generate Virtex-II Pro/ Virtex-II Pro X block and distributed memories. A more detailed listing of available LogiCORE products is available in Table 3-63 and on the Xilinx IP Center website (www.xilinx.com/ipcenter). Types of IP currently offered by the Xilinx LogiCORE program include: Basic Elements: logic gates, registers, multiplexers, adders, multipliers Communications and Networking: ADPCM modules, HDLC controllers, ATM building blocks, forward error correction modules, and POS-PHY Interfaces DSP and Video Image Processing: cores ranging from small building blocks (e.g., Time Skew Buffers) to larger system-level functions (e.g., FIR Filters and FFTs) System Logic: accumulators, adders, subtracters, complementers, multipliers, integrators, pipelined delay elements, single and dual-port distributed and block RAM, ROM, and synchronous and asynchronous FIFOs Standard Bus Interfaces: PCI 64/66 (64-bit, 66 MHz), 64/33 (64-bit, 33 MHz), and 32/33 (32-bit, 3 3MHz) Interfaces
AllianceCORE Program
The AllianceCORE program is a cooperative effort between Xilinx and third-party IP developers to provide additional system-level IP cores optimized for Xilinx FPGAs. To ensure a high level of quality, AllianceCORE products are implemented and verified in a Xilinx device as part of the certification process. Xilinx develops relationships with AllianceCORE partners who can complement the Xilinx LogiCORE product offering. Where Xilinx does not offer a LogiCORE for a particular function, Xilinx partners with an AllianceCORE partner to offer that function. A large percentage of Xilinx AllianceCORE partners focus on data and telecommunication applications, as well as processor and processor peripheral designs. Together, Xilinx and the AllianceCORE partners are able to provide an extensive library of cores to accelerate the design process. AllianceCORE products include customizable cores which can be configured to exact needs, as well as fixed netlist cores targeted toward specific applications. In many cases, partners can provide cores customized to meet the specific design needs if the primary offerings do not fit the requirements. Additionally,
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
279
source code versions of the cores are often available from the partners at additional cost for those who need maximum flexibility. The library of Xilinx and AllianceCORE IP cores allows designers to leverage the expertise of experienced designers who are well-versed in optimizing designs for Virtex-II Pro/ Virtex-II Pro X and other Xilinx architectures. This enables designers to obtain high performance and density in the target device with a faster time to market.
Reference Designs
Xilinx offers two types of reference designs; application notes (XAPPs) developed by Xilinx, and reference designs developed through the Xilinx Reference Design Alliance Program. Both types are extremely valuable to customers looking for guidance when designing systems. Reference designs can often be used as starting points for implementing a broad spectrum of functions in Xilinx programmable logic. Application notes developed by Xilinx usually include supporting design files. They are supplied free of charge, without technical support or warranty. To see currently available reference designs, visit the Xilinx website. Reference designs developed through the Xilinx Reference Design Alliance Program are developed, owned, and controlled by the partners in the program. The goal of the program is to form strategic engineering and marketing partnerships with other semiconductor manufacturers and design houses so as to assist in the development of high quality, multicomponent reference designs that incorporate Xilinx devices and demonstrate how they can operate at the system level with other specialized and general purpose semiconductors. The reference designs in the Xilinx Reference Design Alliance Program are fully functional and applicable to a wide variety of digital electronic systems, including those used for networking, communications, video imaging, and DSP applications. Visit the Xilinx website to see a list of designs currently available through this program.
XPERTS Program
Xilinx established the XPERTS Program to provide customers with access to a worldwide network of certified design consultants proficient with Xilinx Platform FPGAs, software, and IP core integration. All XPERT members are certified and have extensive expertise and experience with Xilinx technology in various vertical applications, such as communications and networking, DSP, video and image processing, system I/O interfaces, and home networking. XPERTS partners are an integral part of Xilinx strategy to provide customers with costefficient design solutions, while accelerating time to market. For more information on Xilinx XPERTS Program, visit the Xilinx website.
280
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Xilinx
LogiCORE
Xilinx
LogiCORE
Bus Infrastructure: OPB Arbiter PLB Arbiter PLB-OPB Bridge OPB-PLB Bridge OPB IPIF Modules: IPIF-Slave Attachment IPIF-Master Attachment IPIF-Address Decode IPIF-Interrupt Control Xilinx Xilinx Xilinx Xilinx LogiCORE LogiCORE LogiCORE LogiCORE Device driver included Device driver included Device driver included Device driver included Xilinx Xilinx Xilinx Xilinx LogiCORE LogiCORE LogiCORE LogiCORE Device driver included Device driver included Device driver included Device driver included
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
281
Table 3-63:
IPIF-Read Packet FIFOs IPIF-Write Packet FIFOs IPIF-DMA IPIF-Scatter Gather Memory Interfaces: PLB External Memory Controller OPB External Memory Controller Memory Interfaces (continued): PLB DDR Controller OPB BRAM Controller OPB ZBT Controller Peripherals: Interrupt Controller UART-16550 UART-16450 IIC Master & Slave SPI Master & Slave Ethernet 10/100 MAC ATM Utopia Level 2 Slave TimeBase/Watch Dog Timer Timer/Counter UART - Lite GPIO Basic Elements: BUFE-based Multiplexer Slice BUFT-based Multiplexer Slice Binary Counter Binary Decoder Bit Bus Gate Bit Gate Bit Multiplexer Bus Gate
Xilinx
LogiCORE
SRAM & FLASH interface including Flash device driver SRAM & FLASH interface including Flash device driver
Xilinx
LogiCORE
Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx
LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE
Device driver included Device driver included Device driver included Device driver included Device driver included Device driver included Device driver included Device driver included Device driver included Device driver included Device driver included
1-256 bits wide 1-256 bits wide 2-256 bits output width 2-256 bits output width 1-256 bits wide 1-256 bits wide 1-256 bits wide 1-256 bits wide
282
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-63:
Bus Multiplexer Comparator FD-based Parallel Register FD-based Shift Register LD-based Parallel Latch RAM-based Shift Register Communication & Networking: 3G FEC Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder 3GPP Turbo Decoder 8b/10b Decoder
Viterbi Decoder, Turbo Codec, Convolutional Enc 3GPP specs, 2 Mb/s, BER=10-6 for 1.5dB SNR Compliant w/ 3GPP, puncturing 3GPP/UMTS compliant, IMT-2000, 2Mb/s data Industry std 8b/10b en/decode for serial data transmission Industry std 8b/10b en/decode for serial data transmission G.721, 723, 726, 726a, 727, 727a, u-law, a-law G.721, 723, 726, 726a, 727, 727a, u-law, a-law
3G Wireless Infrastructure 3G Wireless Infrastructure 3G Wireless Infrastructure Error correction, wireless Physical layer of Fiber Channel Physical layer of Fiber Channel DECT, VOIP, cordless telephony DECT, VOIP, cordless telephony
8b/10b Encoder
Xilinx
LogiCORE
ADPCM 1024 Channel ADPCM 256 Channel ADPCM 512 Channel ADPCM 768 Channel ADPCM Speech Codec, 32 Channel (DO-DI-ADPCM32) ADPCM Speech Codec, 64 Channel (DO-DI-ADPCM64) BOOST LITE Bluetooth Baseband Processor
G.721, 723, 726, 726a, 727, 727a, u-law, a-law G.726, G.727, 32 duplex channels G.726, G.727, 64 duplex channels Compliant to Bluetooth v1.1, BQB qualified software for L2CAP, LHP, HC1, voice support Compliant to Bluetooth v1.1, BQB qualified software for L2CAP, LHP, HC1, voice support
DECT, VOIP, cordless telephony DECT, VOIP, Wireless local loop, DSLAM, PBX DECT, VOIP, wireless local loop, DSLAM, PBX Bluetooth applications
Xilinx
LogiCORE
NewLo gic
AllianceC ORE
NewLo gic
AllianceC ORE
Bluetooth applications
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
283
Table 3-63:
Convolutional Encoder
iCODI NG
AllianceC ORE
DVB-RCS compliant, 9 Mb/s data rate, switchable code rates and frame sizes
Flexbus 4 Interface Core, 16-Channel (DO-DI-FLX4C16) Flexbus 4 Interface Core, 4-Channel (DO-DI-FLX4C4) Flexbus 4 Interface Core, 1-Channel (DO-DI-FLX4C1) HDLC Controller Core, 32 Channels
Xilinx
LogiCORE
Xilinx
LogiCORE
Xilinx
LogiCORE
Xilinx
LogiCORE
Xilinx
LogiCORE
16/32-bit frame seq, 8/16bit addr insert/delete, flag/zerop insert/detect Convolutional, width up to 256 bits, 256 branches
Interleaver/De-interleaver
Xilinx
LogiCORE
Alcatel
AllianceC ORE
802.3 compliant, Supports single & multimode fiber optic devices, M11 interfaces, RMON and Etherstate statistics
POS-PHY Level 3 Link Layer Interface Core, 48 Channel (DO-DI-POSL3LINK48A) POS-PHY L3 Link Layer Interface, 16-Ch (DO-DIPOSL3LINK16) POS-PHY L3 Link Layer Interface, 4-Ch (DO-DIPOSL3LINK4) POS-PHY L3 Link Layer Interface, 2-Ch (DO-DIPOSL3LINK2)
Xilinx
LogiCORE
Xilinx
LogiCORE
Line card: terabit routers & optical switches Line card: terabit routers & optical switches Line card: terabit routers & optical switches
Xilinx
LogiCORE
Xilinx
LogiCORE
284
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-63:
POS-PHY L3 Link Layer Interface, Single Channel POS-PHY L4 Multi-Channel Interface (DO-DI-POSL4MC) Reed-Solomon Decoder
TILAB Xilinx
parameterizable, RTL available Std or cust coding, 3-12 bit width, up to 4095 symbols with 256 check symb.
SDLC Controller
CAST
AllianceC ORE
Like Intel 8XC152 Global Serial Channel, Serial Comm., HDLC apps, telecom Solution requires SPEEDAnalyzer ASIC, 2.5 Gb/s fdx wire speed; net processor (NPV) 3GPP/UMTS compliant, 2 Mb/s data rate 3GPP/UMTS compliant, upto 4 interleaver laws 3GPP/UMTS compliant, >2 Mb/s data rate Puncturing, serial & parallel architecture,
IP
AllianceC ORE
Turbo Decoder - 3GPP Turbo Encoder TURBO_DEC Turbo Decoder Viterbi Decoder
Xilinx
LogiCORE
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
285
Table 3-63:
Digital Signal Processing: 1024-Point Complex FFT IFFT for Virtex-II 16-Point Complex FFT IFFT for Virtex-II 256-Point Complex FFT IFFT for Virtex-II 32 Point Complex FFT/IFFT 64-Point Complex FFT IFFT for Virtex-II Bit Correlator Cascaded Integrator Comb (CIC) Direct Digital Synthesizer Xilinx LogiCORE 16 bit complex data, 2s comp, forward and inverse transform 16 bit complex data, 2s comp, forward and inverse transform 16 bit complex data, 2s comp, forward and inverse transform
Xilinx
LogiCORE
Xilinx
LogiCORE
Xilinx Xilinx
LogiCORE LogiCORE 16 bit complex data, 2s comp, forward and inverse transform 4096 taps, serial/parallel input, 4096 bits width 32 bits data width, rate change from 8 to 16384 8-65K samples, 32-bits output precision, phase dithering/offset 32-bit input/coeff width, 1024 taps, 1-8 chan, polyphase, online coeff reload 2 Virtex-II, Spartan-II FPGAs, 1 CPLD, Matlab I/F 168 input widths, SRL16/register implementation DSP prototyping
Xilinx
LogiCORE
GVA-300 Virtex-II DSP Hardware Accelerator LFSR, Linear Feedback Shift Register Math Functions: Accumulator Adder Subtracter DFP2INT Floating Point to Integer Converter DFPADD Floating Point Adder DFPCOMP Floating Point Comparator DFPDIV Floating Point Divider
GV Xilinx
LogiCORE LogiCORE AllianceC ORE AllianceC ORE AllianceC ORE AllianceC ORE
1-256s bit wide 1-256s bit wide Full IEEE-754 compliance, 4 pipelines, Single precision real format support Full IEEE-754 compliance, 4 pipelines, Single precision real format support Full IEEE-754 compliance, 4 pipelines, Single precision real format support Full IEEE-754 compliance, 15 pipelines, Single precision real format support DSP, Math, Arithmetic apps DSP, Math, Arithmetic apps DSP, Math, Arithmetic apps DSP, Math, Arithmetic apps
Digital
Digital
Digital
286
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-63:
DFPSQRT Floating Point Square Root DINT2FP Integer to Floating Point Converter
Digital
Digital
Xilinx
LogiCORE
Multiply Generator
Xilinx
LogiCORE
Pipelined Divider Sine Cosine Look Up Table Twos Complementer Memories & Storage Elements: Asynchronous FIFO
Xilinx
LogiCORE
1-256 bits, 15-65535 words, DRAM or BRAM, independent I/O clock domains 1-512 bits, 2-10K words, SRL16 1-1024 bit, 16-65536 word, RAM/ROM/SRL16, opt output regs and pipelining 1-256 bits, 2-13K words 1-256 bits, 2-128K words 1-256 bits, 16-256 words, distributed/block RAM
Xilinx Xilinx
LogiCORE LogiCORE
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
287
Table 3-63:
Microprocessors, Controllers & Peripherals: 10/100 Ethernet MAC Xilinx LogiCORE Interfaces through OPB to MicroBlaze 44 opcode, 64-K word data, program, Harvard arch. Microchip 16C5X PIC like MC68000 Compatible Hitachi SH-3 CPU Zilog Z80 compatible, 8-bit processor DDR SDRAM burst length support for 2,4,8 per access, supports data 16,32, 64, 72. PIC 12c4x like, 2X faster, 12bit wide instruction set, 33 instructions S/W compatible with PIC16C55X, 14-bit instruction set, 35 instructions PIC 12c4x like, 2X faster, 12bit wide instruction set, 33 instructions I2C-like, multi master, fast/std. modes I2C-like, Slave I2C-like, Slave 80C31 instruction set, RISC architecture 6.7X faster than standard 8051 80C31 instruction set, high speed multiplier, RISC architecture 6.7X faster than standard 8051 80C31 instruction set, high speed mult/div ,RISC 6.7X faster than standard 8051 Networking, comm., processor applications Control functions, State mach, Coprocessor Embedded systems, telecom Embedded systems, pro audio, video Embedded systems Embedded systems, Communications Digital video, embedded computing , networking Embedded systems, telecom, audio and video Embedded systems, telecom, audio and video Embedded systems, telecom, audio and video Embedded systems Embedded Embedded Systems Embedded systems, telecom, video Embedded systems, telecom, video
Loarant
AllianceC ORE AllianceC ORE AllianceC ORE AllianceC ORE AllianceC ORE AllianceC ORE
C165X MicroController C68000 Microprocessor CPU FPGA (Virtex-II) MicroEngine Cards CZ80CPU Microprocessor DDR SDRAM Controller Core
Digital
Digital
DFPIC165X Fast RISC MicroController DI2CM I2C Bus Controller Master DI2CM I2C Bus Controller Slave DI2CSB I2C Bus Controller Slave Base DR8051 RISC MicroController
Digital
AllianceC ORE AllianceC ORE AllianceC ORE AllianceC ORE AllianceC ORE AllianceC ORE
Digital
Digital
AllianceC ORE
288
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 3-63:
Flip805x-PS Microprocessor
IIC Master and Slave LavaCORE Configurable Java Processor Core LavaCORE Configurable Java Processor Core Lightfoot 32-bit Java Processor Core
MicroBlaze Soft RISC Processor OPB Arbiter OPB GPIO OPB Interrupt Controller OPB Memory Interface (Flash, SRAM) OPB Timer/Counter OPB UART (16450, 16550) OPB UART Lite OPB WDT PF3100 PC/104-Plus Reconfigurable Module SPI
Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Xilinx Derivat ion Xilinx
LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE AllianceC ORE LogiCORE
MemecCore
AllianceCORE
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
289
Table 3-63:
Standard Bus Interfaces: PCI32 Virtex Interface Design Kit (DO-DI-PCI32-DKT) Xilinx LogiCORE Includes PCI32 board, drive development kit, and customer education 3-day training class v2.2 comp, assured PCI timing, 3.3/5-V, 0waitstate, CPCI hot swap friendly v2.2 comp, assured PCI timing, 3.3/5-V, 0waitstate, CPCI hot swap friendly v2.2 comp, assured PCI timing, 3.3/5-V, 0waitstate, CPCI hot swap friendly v2.2 comp, assured PCI timing, 3.3/5-V, 0waitstate, CPCI hot swap friendly RapidIO Interconnect v1.1 compliant, verified with Motorolas RapidIO bus functional model v1.4 PC add-in boards, CPCI, Embedded
Xilinx
LogiCORE
PCI64 & PCI32, IP Only (DO-DI-PCI-AL) PCI64 Virtex Interface Design Kit (DO-DI-PCI64-DKT)
Xilinx
LogiCORE
PC boards, CPCI, Embedded, hiperf video, gb ethernet PC boards, CPCI, Embedded, hiperf video, gb ethernet PC boards, CPCI, Embedded, hiperf video, gb ethernet Routers, switches, backplane, control plane, data path, embedded sys, high speed interface to memory and encryption engines, high end video Scanners, Printers, Handhelds, Mass Storage
Xilinx
LogiCORE
Xilinx
LogiCORE
Xilinx
LogiCORE
Memec -Core
AllianceC ORE
Compliant with USB1.1 spec., Supports VCI bus, Performs CRC, Supports 1.5 Mb/s & 12 Mb/s
Video & Image Processing: 1-D Discrete Cosine Transform 2-D DCT/IDCT Forward/Inverse Discrete Cosine Transform FASTJPEG_BW Decoder Xilinx Xilinx LogiCORE LogiCORE 8-24 bits for coeff & input, 864 pts image, video phone, color laser printers Conforms to ISO/IEC Baseline 10918-1, GrayScale Conforms to ISO/IEC Baseline 10918-1, color, multi-scan, Gray-Scale Video editing, digital camera, scanners Video editing, digital camera, scanners
FASTJPEG_C Decoder
290
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Chapter 4
Configuration
Summary
This chapter covers the following topics: Introduction Configuration Solutions Software Support and Data Files Serial Programming Modes SelectMAP Programming Modes JTAG / Boundary-Scan Programming Modes Configuration Details Readback
Introduction
Virtex-II Pro devices are configured by loading application-specific configuration data into internal memory. Configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be reused as general-purpose inputs and outputs after configuration is complete. Depending on the system design, several configuration modes are selectable via mode pins. The mode pins M2, M1, and M0 are dedicated pins. An additional pin, HSWAP_EN, is used in conjunction with the mode pins to select whether user I/O pins have pull-up resistors during configuration. By default, HSWAP_EN is tied High (internal pull-up resistor), which shuts off pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, the pull-up resistors are on and therefore, the user I/Os have pull-up resistors during configuration. Other dedicated pins are: CCLK - the configuration clock pin DONE - configuration status pin TDI, TDO, TMS, TCK - boundary-scan pins PROG_B - configuration reset pin
Depending on the configuration mode selected, CCLK can be an output generated by the Virtex-II Pro FPGA or an input accepting externally generated clock data. For correct operation, these pins require a VCCAUX of 2.5V to permit LVCMOS operations.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
291
Chapter 4: Configuration
All dual-function configuration pins are contained in banks 4 and 5. Bank 4 contains pins used in serial configuration modes, banks 4 and 5 contain pins used for SelectMAP modes. A persist option is available, which can be used to force pins to retain their configuration function even after device configuration is complete. If the persist option is not selected, then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used for user I/O in normal operation. The persist option does not apply to boundary-scan related pins. The persist feature is valuable in applications that employ partial reconfiguration, dynamic reconfiguration, or readback. The M2, M1, and M0 mode pins are intended to be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied directly to ground or VCCAUX. The mode pins are not to be toggled (changed) during and after configuration.
Configuration Modes
Virtex-II Pro supports the following configuration modes: Master-Serial Slave-Serial (default) Master SelectMAP Slave SelectMAP Boundary-Scan (IEEE 1532 and IEEE 1149)
Table 4-1 shows Virtex-II Pro configuration mode pin settings. Table 4-1: Virtex-II Pro Configuration Mode Pin Settings
Configuration Mode (1) M2 M1 M0 CCLK Direction Data Width Serial Dout (2) Master Serial Slave Serial Master SelectMAP Slave SelectMAP Boundary Scan 0 1 0 1 1 0 1 1 1 0 0 1 1 0 1 Out In Out In N/A 1 1 8 8 1 Yes Yes No No No
Notes: 1. The HSWAP_EN pin controls the pull-ups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls whether or not the pull-ups are used. 2. Daisy chaining is possible only in modes where Serial Dout is used. For example, in SelectMAP modes, the first device does NOT support daisy chaining of downstream devices.
Table 4-2 lists the total number of bits required to configure each device: Table 4-2: Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 Virtex-II Pro Bitstream Sizes Default Bitstream Size 1,305,376 3,006,496 4,485,408 8,214,560 8,214,560 11,589,920 Device XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Default Bitstream Size 15,868,192 19,021,344 26,098,976 26,098,976 34,292,768
292
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
No PROG_b = Low
Yes
Yes
No INIT_ B = High?
Yes
Sample Mode Pins Master Serial/ Master SelectMAP CCLK Begins Load Configuration Data Frames
CRC Correct?
No
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
293
Chapter 4: Configuration
Power Up
The VCCINT power pins must be supplied with a 1.5V source. (Refer to the Virtex-II Pro and Virtex-II Pro X Platform FPGA Data Sheet for DC characteristics.) The IOB voltage input for Bank 4 (VCCO_4) and the auxiliary voltage input (VCCAUX) are also used as a logic input to the Power-On-Reset (POR) circuitry. Even if this bank is not being used, VCCO_4 must be connected to a 1.5V or greater source.
VCC
TPOR
PROG_B
TPL
INIT_B
TICCK
CCLK OUTPUT or INPUT
VALID
ds022_020_101904
Figure 4-2:
Initialization
For the initialization phase, the INIT_B pin is released, the mode pins are sampled, the appropriate pins become active, and the configuration process begins. It is possible to delay configuration by externally holding INIT_B Low.
Delaying Configuration
The INIT_B pin can also be held Low externally to delay configuration of the FPGA. The FPGA samples its mode pins on the rising edge of INIT_B. After INIT_B transitions to High, configuration can begin. No additional time-out or waiting periods are required, but configuration does not need to commence immediately after the transition of INIT_B. The configuration logic does not begin processing data until the synchronization word from the bitstream is loaded.
294
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
After the last data frame is loaded, the global set/reset (GSR) signal is pulsed (see the "GRESTORE" description in Table 4-25, page 347). The GSR signal initializes all registers in the device prior to entering the startup sequence, which is the next configuration phase.
Device Startup
Device startup brings the FPGA out of the configuration process and into normal device operation. The Startup Sequence is controlled by an eight-phase state machine that: Deasserts GTS, activating I/Os Asserts GWE, allowing RAMs and flip-flops to toggle Releases the DONE pin Asserts the End-Of-Startup signal (EOS) during the final phase. The EOS signal is an internal flag that can be read through the Status Register (see Status Register (STAT), page 349).
Figure 4-3 depicts the default start-up sequence. The order of the start-up events is user-programmable according to the BitGen startup options (see Appendix A, BitGen and PROMGen Switches and Options). Delays can be inserted in the start-up sequence to allow DCMs to lock and DCI to match. The startup sequencer always waits for the DONE pin on the FPGA to go High during the Done cycle. The DONE pin does not necessarily go High when it is "released" by the device, since the pin may be held Low externally by other devices. The DONE pin can be configured as an open-drain output, in which case the DONE pin is "released" to a highimpedance state. Alternatively, it can be configured as an active driver, in which case the DONE pin is "released" to an active High level. The BitGen DRIVE DONE (bitgen -g drivedone:yes) setting determines whether the active driver is enabled on the DONE pin. This feature allows several FPGAs with connected DONE pins become active simultaneously.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
295
Chapter 4: Configuration
Default Cycles
Start-upCLK Phase 0 1 2 3 4 5 6 7
DONE GTS
GWE
Sync to DONE
Start-upCLK Phase 0 1 2 3 4 5 6 7
GWE
x138_01_071100
Figure 4-3:
The DONE pin may be held low for many CCLK cycles after being released by the device, but when the transition from logic 0 to logic 1 begins, it must finish within one CCLK cycle. If many devices are connected to the same DONE signal, the last device may not be able to drive DONE high within one CCLK cycle. In this case an external pull-up resistor may be needed on the DONE signal. If the risetime on the DONE signal cannot be reduced to one CCLK period, set the DONE PIPE option (bitgen -g donepipe:yes) to allow an additional CCLK cycle. In addition, five to ten CCLK cycles are required after the DONE pin is released to get the device through the start-up sequence.
Configuration Pins
Dedicated configuration pins (CCLK, PROG_B, DONE, M2, M1, and M0) are powered by VCCAUX at 2.5V. They should not be exposed to 3.3V signals. However, in cases where they must be connected to 3.3V, it is highly recommended that they connect through 100 series resistors to 3.3V, or that no more than 3 mA of current be allowed to pass through these pins at any time. Dual-function pins (D0/DIN, D1:D7, CS_B, RDWR_B, BUSY/DOUT and INIT_B) powered by VCCO are designated for configuration and other user functions after configuration. Table 4-3 is the list of all dedicated, dual-function, and user pins. Before and during configuration, all configuration I/O pins are set for the LVCMOS25 (12mA, fast slew rate) standard when VCCO is 2.5V. It becomes LVCMOS33 (16mA, fast slew rate) when VCCO is 3.3V. The configuration clock pin CCLK is set for the LVCMOS25 (12mA, slow slew rate).
296
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 4-3:
Pin Name
Comments
Pin is supplied by VCCAUX. Input should not be driven by a 3.3V signal unless a 100 series resistor is used. Output is LVCMOS25 and compatible with LVTTL. Pin is supplied by VCCAUX (must be 2.5V). It should not be pulled up to 3.3V unless a 100 series resistor is used. Pin is supplied by VCCAUX (must be 2.5V). It should not be pulled up to 3.3V unless a 470 series resistor is used. Pins are supplied by VCCAUX (must be 2.5V). They should not be pulled up to 3.3V unless 100 series resistors are used. Pin is supplied by VCCAUX (must be 2.5V). It should not be pulled up to 3.3V unless a 100 series resistor is used. Pin is supplied by VCCAUX (3.3V tolerant). Pin is supplied by VCCAUX (3.3V tolerant). Pin is supplied by VCCAUX (3.3V tolerant). Pin is open-drain and can be pulled up to 3.3V. The external pullup resistor should be stronger than 200. There is no internal pullup. Pin is supplied by VCCAUX (2.5V). It has an internal pull-up. Do not pull up externally to 3.3V unless a 100 series resistor is used. This pin does not support the power-down feature. Pins are supplied by VCCO . Pin is supplied by VCCO . Pin is supplied by VCCO . Pin is supplied by VCCO . Pin is supplied by VCCO . Reference resistor pulled down to GND. Reference resistor pulled up to VCCO . Depends on the I/O standard used. These pins are the cathode and anode of the temperature diode. Battery supply for the encryption keys. Connect this pin to either VCCAUX or GND when bitstream encryption is not used. All regular user I/Os support the following 3.3V signaling standards: LVTTL, LVCMOS, PCI33, PCI66, PCIX, LVDCI33
CCLK
Input/Output
Input Open-drain Output Input Input Input Input Input Open-drain Output
PWRDWN_B D0/DIN, D1-D7 CS_B RDWR_B BUSY/DOUT INIT_B VRP VRN VREF DXN, DXP VBATT User I/O
Input
2.5
Input/Output Input Input Output Input/Output Input Input Input N/A Input Input/Output
2.5/3.3 2.5/3.3 2.5/3.3 2.5/3.3 2.5/3.3 N/A 2.5/3.3 2.5/3.3 N/A 3.0 Various
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
297
Chapter 4: Configuration
SelectIO-Ultra is separated into eight banks of I/O groups. Each bank can be configured with one of several I/O standards. Refer to Chapter 3, Design Considerations for I/O banking rules and available I/O standards. Before and during configuration, all I/O banks are set for the LVCMOS25 (12mA) standard. All dedicated configuration pins are powered by VCCAUX. All dual-function configuration pins are located within banks 4 and 5. As described under Configuration Process and Flow, the VCCO_4 input voltage is used as a logic input to the power-on-reset (POR) circuitry if the VCCO_4 voltage level is monitored by the power-on-reset (POR) circuitry. If it drops below the minimum allowed voltage, the POR circuit will reset the entire device, clearing configuration memory and causing DONE to go Low. Table 4-4 summarizes the configuration VCCO requirements discussed in the following sections. Table 4-4: Configuration Modes and VCCO Voltages Pins Used
Dedicated pins Dedicated pins plus DOUT, DIN, and INIT Dedicated pins plus dual-function pins
Configuration Mode
JTAG Serial SelectMAP Notes:
VCCO_4
1.5V min (1) 2.5V/3.3V 2.5V/3.3V
VCCO_5
not a concern not a concern 2.5V/3.3V
1. VCCO_4 is monitored by the POR circuit. See section Power Up, page 294.
298
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The DO pin of the PROM is at LVCMOS25 levels, and the DIN pin of the Virtex-II Pro is at LVTTL levels. Therefore, they are compatible. Figure 4-4 shows the Virtex-II Pro FPGA and the Platform Flash PROM in master serial configuration.
VCCO = 2.5V/3.3V VCCO = 2.5V/3.3V VCCAUX = 2.5V
CLK DO CE
4.7k
CCLK DIN
Virtex-II Pro
INIT_B
300
RESET/OE
DONE M0 M1 M2
GND
ug012_c3_048_031505
Figure 4-4:
In Slave serial mode, the VCCO of the FPGA can be either 2.5V or 3.3V. However, make sure the CCLK pin of the FPGA is not exposed to more than 2.5V, since this is a 2.5V pin powered by VCCAUX .
Configuration Solutions
Several configuration solutions are available to support Virtex-II Pro devices, each targeted to specific application requirements. Guidance and support (application notes, reference designs, and so forth) is also available for designers looking to develop and implement their own configuration solution for Virtex FPGAs.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
299
Chapter 4: Configuration
[Microprocessor]
8/16-bit Bus ACE CompactFlash ATA Bus Configuration 1 Configuration 2 Configuration 3 JTAG Test Port TDI TCK TMS ACE TDO Controller INIT_B PROG_B
VCC 200
VCC 200
VCC 200
VCC 4.7k
UG012_C3_041_021807
Figure 4-5:
The CompactFlash card stores an unlimited number of bitstreams, and supports densities up to 2 GB for FAT16 file formats. This card is capable of storing one large bitstream or several smaller bitstreams. If several bitstreams are used, the system can be set up so that individual bitstreams are callable as needed, allowing for dynamic reconfiguration of the Virtex-II Pro device and other Xilinx FPGAs in the JTAG chain. The ACE Controller drives bits through the FPGA JTAG chain and has three other ports: A port for interfacing with a microprocessor or a network A port for interfacing with the CompactFlash card A port that provides access to the FPGA JTAG chain for FPGA testing or configuration via automatic test equipment or via desktop or third-party programmers
For further information on any System ACE product, visit the www.xilinx.com/systemace website.
Configuration PROMs
Using Platform Flash PROMs
The Platform Flash family of in-system programmable (ISP) configuration PROMs provides the flexibility of reprogrammability and the efficiency of small-footprint packages, combined with both serial and SelectMAP (parallel) FPGA configurability. The family offers single devices ranging in density from 1 Mb to 32 Mb, and PROMs can be cascaded to support even larger bitstreams. Data throughput rates of up to 264 Mb/s can be attained, and FPGA reconfiguration can be triggered via a JTAG command. These PROMs are programmable using Xilinx iMPACT software via cable, HW-130, or standard third-party programmers. Platform Flash PROMs are available in VO20, VO48, and FS48 packages. See Table 4-5, page 303 to determine which PROMs go with which Virtex-II Pro FPGAs. Package drawings are avaialble in Appendix B, Platform Flash Family PROMs.
300
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
EPROM CPLD
ADDRESS[18:0] DATAOUT[7:0] /CE
VCC 4.7k
FPGA (Master)
FPGA (Slave)
/OE
DONE
DONE
PROG_B VCC
PROG_B
4.7k
Control Signal
X079_05_011105
Figure 4-6: Configuring Virtex-II Pro Devices Using a CPLD and Parallel PROM XAPP137, Configuring Virtex FPGAs From Parallel EPROMs With a CPLD (www.xilinx.com/bvdocs/appnotes/xapp137.pdf) describes an architecture that configures one or more Virtex-II Pro devices using the Slave SelectMAP mode. See Figure 4-7 for an example of FPGA configuration using a CPLD and a parallel EPROM.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
301
Chapter 4: Configuration
D[0:7]
EPROM or FLASH
(1M X 8) DONE0 DONE1 INIT BUSY A[0:19] OE/CE A[0:19] OE/CE CCLK
BUSY
Virtex-II Pro
CS_B RDWR_B PROG_B CCLK
M2 VCC
M1
M0
M2
M1
M0
VCC VCC
Figure 4-7:
Embedded Solutions
Using an Embedded Microcontroller
XAPP058, Xilinx In-System Programming Using an Embedded Microcontroller (www.xilinx.com/bvdocs/appnotes/xapp058.pdf) describes a compact and robust process that (re)configures Virtex-II Pro devices directly from a microprocessor through the JTAG test port of the Virtex-II Pro device. The process additionally supports (re)configuration of XC18V00 ISP PROMs and CPLDs that reside on the JTAG scan chain. Portable, reference C-code is provided with the application note for rapid implementation.
302
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Virtex-II Pro Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 (2) Notes:
1. Requires XCCACE-TQ144 CompactFlash Controller 2. Assumes compression is used. Without compression, Xilinx recommends the System ACE configuration solution for this larger-density device. Storing configuration data by cascading multiple independent PROMs is an option, but requires careful signal integrity and power supply planning.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
303
Chapter 4: Configuration
iMPACT
To program Virtex-II Pro and other Xilinx devices with a personal computer, Xilinx provides iMPACT as a part of the ISE software package. A free version of iMPACT is also available through the WebPACK software suite. More information on WebPACK is available at: http://www.support.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack
Programming Cables
iMPACT supports several Xilinx programming cables that are compatible with Virtex-II Pro devices, including the Parallel-Cable III, Parallel-Cable IV, and Platform Cable USB. For more information on these cables, or to order programming cables online, please visit: http://www.support.xilinx.com/xlnx/xil_prodcat_product.jsp?title=csd_cables
304
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
M0
M1
PROM
DATA CLK CE RESET/OE VCC (Low Reset Option Used) Optional Pull-up on DONE1
VCC 4.7k
PROG_B
ug012_c3_011_011105
Figure 4-8:
Notes:
1. If the Virtex-II Pro device has not selected the DriveDONE option, then an external pull-up resistor of 330 should be added to the DONE pin. This pull-up resistor is not needed if DriveDONE = Yes.
PROG_B
INIT_B
Master CLK Begins Here(1)
CCLK DIN
BIT 0
BIT 1
BIT n
BIT n+1
DOUT
Data bits clocked in on rising edge of CCLK
BIT n-64
BIT n-63
ug012_c3_004a_070903
Figure 4-9:
Notes:
1. For Master configurations, the CCLK does not transition until after initialization as indicated by arrow. 2. DOUT transitions on the falling edge of CCLK.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
305
Chapter 4: Configuration
Daisy-Chain Configuration
Virtex-II Pro devices can be daisy-chained with the Virtex, Spartan-II, Virtex-E, Spartan-IIE, Virtex-II, Spartan-3, and Virtex-4 families. There are three important design considerations when designing a mixed-serial daisy chain: 1. Many older devices cannot accept as fast a CCLK frequency as (for example) a Virtex-4 device can generate. Select a configuration CCLK speed supported by all devices in the chain. Newer devices should be grouped at the beginning of the serial daisy chain, with older devices located at the end of the chain. There is a limit to the number of configuration bits a device can pass through its DOUT pin. As shown in Table 4-6, this limit varies for different families. The sum of the bitstream lengths for all downstream devices must not exceed the number in this table for each family.
VCC
2. 3.
M0
M1
M0 M2 DOUT DIN
M1
PROM
DATA CLK CE RESET/OE (Low Reset Option Used)
M2 DIN CCLK
DOUT
CCLK
VCC 4.7k
DONE
INIT_B
PROGRAM
ug012_c3_003_011105
Figure 4-10:
Notes:
1. If none of the devices have been selected to DriveDONE, then an external pull-up resistor of 330 should be added to the common DONE line. This pull-up resistor is not needed if DriveDONE = Yes. If used, DriveDONE should be enabled only for the last device in the configuration chain.
306
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 4-6:
Maximum Number of Configuration Bits, Various Device Families Architecture Maximum DOUT Bits 32 x( 227 1) = 4,294,967,264 32 x( 227 1) = 4,294,967,264 32 x (227 1) = 4,294,967,264 32 x (220 1) = 33,554,216
The separate bitstreams for the FPGAs in a daisy chain must be combined into a single PROM file, by using either iMPACT or the PROMGen utility (see Appendix A, BitGen and PROMGen Switches and Options). Separate .bit files cannot be simply concatenated together to form a daisy-chain bitstream. The first device in the chain is the first to be configured. No data is passed onto the DOUT pin until all the data frames, start-up command, and CRC check have been loaded. CRC checks only include the data for the current device, not for any others in the chain. After finishing the first stream, data for the next device is loaded. The data for the downstream device appears on DOUT typically about 80 CCLK cycles after being loaded into DIN. This is due to internal packet processing. Each daisy-chained bitstream carries its own synchronization word. Nothing of the first bitstream is passed to the next device in the chain other than the daisy-chained configuration data. The DONE_cycle must be set before GTS, or during the same cycle to guarantee each Virtex-II Pro device to move to the operation state when all the DONE pins have been released. When daisy-chaining multiple devices, either set the last device in the chain to DriveDONE, or add external pull-up resistors to counteract the combined capacitive loading on DONE. If non-Virtex devices are included in the daisy chain, it is important to set their bitstreams to SyncToDONE with BitGen options. For more information on Virtex BitGen options, see Appendix A, BitGen and PROMGen Switches and Options.
PROG_B
INIT_B
CCLK DIN
BIT 0
BIT 1
BIT n
BIT n+1
DOUT
Data bits clocked in on rising edge of CCLK
BIT n-64
BIT n-63
ug012_c3_004b_091902
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
307
Chapter 4: Configuration
D[0:7]
Bidirectional
Dual-Function
RDWR_B
Input
Dual-Function
CS_B
Input
Dual-Function
BUSY
Three-State Output
Dual-Function
M[2:0]
Input
Dedicated
308
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 4-7:
Pin Name
CCLK PROG_B
Dedicated or Dual-Function
Dedicated Dedicated
Description
Configuration clock for all modes other than JTAG. Input for Slave SelectMAP mode; output for Master SelectMAP mode. Active-Low asynchronous full-chip reset. Has permanent weak pull-up. Before MODE pins are sampled, INIT_B is an input that can be held Low to delay configuration. After MODE pins are sampled, INIT_B is an opendrain, active Low output indicating whether a CRC error occurred during configuration: 0 = CRC error 1 = No CRC error After configuration, the INIT_B pin becomes user I/O unless the bitgen -g persist:yes setting is used. Active High signal indicating configuration is complete: 0 = FPGA not configured 1 = FPGA configured Pin has optional internal pull-up.
INIT_B
Bi-directional Open-Drain
Dual-Function
DONE
Input or Output
Dedicated
Daisy-chaining is not possible for SelectMAP mode, however multiple devices can be connected on the same SelectMAP bus as shown in Figure 4-14, page 312. To connect devices on a SelectMAP bus, the DATA pins (D0:D7), CCLK, RDWR_B, BUSY, PROG_B, DONE, and INIT_B are connected in common between all devices. The CS_B (Chip Select) inputs are kept separate so that each device can be accessed individually. External control logic is required to arbitrate between devices by asserting and deasserting the CS_B signals as necessary. Alternatively, it is possible to simultaneously configure multiple devices using the same bitstream, provided that readback is not required. In this arrangement the CS_B pins are connected together, along with the remaining configuration pins, so that the SelectMAP ports on all devices are enabled simultaneously.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
309
Chapter 4: Configuration
Xilinx PROM
DATA[0:7] CCLK CF
CE RESET/OE
ug012_50_031605
Figure 4-12:
Notes: 1. The DONE pin is by default an open-drain output requiring an external pull-up resistor. In this arrangement, the active DONE driver can be enabled, eliminating the need for an external pullup resistor. 2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up is required. 3. The BitGen startup clock setting must be set for CCLK for SelectMAP configuration. 4. The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial PROMs can be cascaded to increase the overall configuration storage capacity. 5. The .bit file must be reformatted into a PROM file before it can be stored on the serial PROM. Refer to Appendix A, BitGen and PROMGen Switches and Options. 6. On XC17V00 devices, the reset polarity is programmable. RESET should be set for active Low when using an XC17V00 device in this setup. 7. The Xilinx PROM must be set for parallel mode. (This mode is not available for all devices.) 8. When configuring a Virtex-II Pro device in SelectMAP mode from a Xilinx configuration PROM, the RDWR_B and CS_B signals can be tied Low (see section Master SelectMAP Data Loading). 9. The BUSY signal does not need to be monitored for this setup and can be left unconnected (see section Master SelectMAP Data Loading).
RDWR_B
When asserted Low, the RDWR_B signal indicates that data is being written to the data bus. When High, the RDWR_B signal indicates that data is being read from the data bus.
310
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
CS_B
The Chip Select input (CS_B) enables the SelectMAP data bus. To write or read data onto or from the bus, the CS_B signal must be asserted Low. When CS_B is High, Virtex-II Pro devices do not drive onto or read from the bus.
CCLK
The CCLK pin is a clock output in the Master SelectMAP interface. It synchronizes all loading and reading of the data bus for configuration and readback. The CCLK pin is driven by the FPGA.
INIT_B
CCLK
CS_B
RDWR_B DATA[0:7]
Byte 0
Byte 1
Byte n
Byte n
Byte n+1
BUSY
Device Ready Byte 0 Loaded
BUSY
Byte n Ignored
Byte n Loaded
x138_06_063003
Figure 4-13:
The first byte can be loaded on the first rising CCLK edge that INIT_B is High, and when both CS_B and RDWR_B are asserted Low. CS_B and RDWR_B can be asserted anytime before or after INIT_B has gone High. However, the SelectMAP interface is not active until after INIT_B has gone High. If RDWR_B toggles while CS_B is asserted, an ABORT occurs. Extra processing time is needed when the bitstream is encrypted. Because of this, BUSY handshaking is required for encrypted bitstreams at a lower speed than for non-encrypted bitstreams. The maximum speed at which a Virtex-II Pro/Virtex-II Pro X device can be configured via SelectMAP without BUSY handshaking is 50 MHz.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
311
Chapter 4: Configuration
must not be tied together. External control of the CS_B signal is required and is usually provided by a microprocessor or CPLD.
DATA[0:7] CCLK RDWR_B BUSY VCC VCC
M1 M0
M2
M1 M0
M2
ug012_c3_005a_011205
Figure 4-14:
Notes:
1. If none of the Virtex-II Pro devices have been selected to DriveDONE, add an external 330 pull-up resistor to the common DONE line. This pull-up resistor is not needed if DriveDONE = Yes. If used, DriveDONE should be selected only for the last device in the configuration chain.
If Readback is going to be performed on the device after configuration, the RDWR_B and BUSY signals must be handled appropriately. (For details, refer to Readback, page 367.) Figure 4-14 does not show a control module for the SelectMAP interface. The SelectMAP interface is typically driven by a processor, microcontroller, FPGA or CPLD.
Refer to Toggling between Read and Write Control below for details.
312
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
When the SelectMAP port is set for write control (RDWR_B=0), the device samples the D0:7 inputs on each rising CCLK edge. The BUSY signal must be monitored during readback and when bitstream encryption is used during configuration.
There are several ways to control configuration data loading using Slave SelectMAP mode: 1. Continuous Data Loading (Free-Running CCLK). After the INIT_B signal goes High, the device registers the D[0:7] inputs on every rising CCLK edge while the SelectMAP interface is enabled (CS_B=0) and set for write control (RDWR_B=0). Configuration data are loaded continuously, without pauses. This method is depicted in Figure 4-15.
PROG_B
(4)
INIT_B
CCLK
(1) (6) (13)
CS_B
(2) (5) (14)
RDWR_B
(8) (9) Byte 1 (10) Byte n (11)
DATA[0:7]
(3) High-Z (7)
Byte 0
BUSY DONE
(12)
ug071_25_121903
Figure 4-15:
Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
CS_B signal can be tied Low if there is only one device on the SelectMAP bus. If CS_B is not tied Low, it can be asserted at any time. RDWR_B can be tied Low if readback is not needed. RDWR_B should not be toggled after CS_B has been asserted, as this triggers an ABORT. (See SelectMAP ABORT Sequence and ABORT Recovery.) If CS_B is tied Low, BUSY is driven Low before INIT_B toggles High. The MODE pins are sampled when INIT_B goes High. RDWR_B should be asserted before CS_B to avoid causing an ABORT. CS_B is asserted, enabling the SelectMAP interface. BUSY remains in high-Z state until CS_B is asserted. The first byte is loaded on the first rising CCLK edge after CS_B is asserted. The configuration bitstream is loaded one byte per rising CCLK edge. After the last byte is loaded the device enters the startup sequence. The startup sequence lasts a minimum of eight CCLK cycles. The DONE pin goes High during the startup sequence. Additional CCLKs could be required to complete the startup sequence. After configuration has finished, the CS_B signal can be deasserted. After the CS_B signal is deasserted, RDWR_B can be deasserted.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
313
Chapter 4: Configuration
2.
SelectMAP Data Loading Controlled by the CS_B signal (Non-Contiguous Data Strobe). In some cases configuration will need to be paused while the next byte of configuration data is presented on the D[0:7] pins. One way of pausing SelectMAP configuration is to disable the SelectMAP interface (CS_B=0). When the SelectMAP interface is disabled, the D[0:7] and BUSY pins are placed in a high-Z state, and all inputs are ignored. The D[0:7] signals are sampled on the next rising CCLK edge after the SelectMAP interface is enabled. See Figure 4-16.
PROG_B
(2)
INIT_B
(5) (6) (7) (8) (9) (10) (11) (12) (13) (14)
CCLK
(3)
CS_B DATA[0:7]
(1)
RDWR_B
(4)
BUSY
High-Z
High-Z
High-Z
ug071_26_121903
Figure 4-16:
Notes:
1.
RDWR_B is driven Low by the user, setting the D[0:7] pins as inputs for configuration. RDWR_B can be tied Low if readback is not needed. RDWR_B should not be toggled after CS_B has been asserted, as this triggers an ABORT. (See SelectMAP ABORT Sequence and ABORT Recovery.) Device is ready for configuration after INIT_B toggles High. The user asserts CS_B Low, enabling SelectMAP data bus. CS_B signal can be tied Low if there is only one device on the SelectMAP bus. If CS_B is not tied Low, it can be asserted at any time. BUSY goes Low shortly after CS_B is asserted. If CS_B is tied Low, BUSY is driven Low before INIT_B toggles High. Byte loaded on rising CCLK edge. Byte loaded on rising CCLK edge. The user deasserts CS_B; byte ignored. The user deasserts CS_B; byte ignored. Byte loaded on rising CCLK edge. Byte loaded on rising CCLK edge. The user deasserts CS_B; byte ignored. Byte loaded on rising CCLK edge. Byte loaded on rising CCLK edge. Byte loaded on rising CCLK edge.
314
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
3.
Data Loading Controlled by Gating CCLK (Controlled CCLK). An alternate way to control SelectMAP data loading is to gate (halt) the CCLK signal. If needed, the RDWR_B signal can be toggled during this time, as long as it is returned to its prior value before the next rising CCLK edge. If the RDWR_B signal is driven high (set for read control) while the SelectMAP interface is enabled (CS_B=0), the D[0:7] pins will become outputs, and will be driven actively by the device. The D[0:7] signals will retain their state while CCLK is paused. See Figure 4-17.
(4) (5) (6)
CCLK
(3)
CS_B
(2)
RDWR_B
(1)
DATA[0:7]
Byte 0
Byte 1
Byte n
ug071_27_080204
Figure 4-17:
Notes:
1. 2. 3. 4. 5. 6.
D[0:7] pins are in High-Z state while CS_B is deasserted. RDWR_B has no effect on the device while CS_B is deasserted. CS_B is asserted by the user. Device begins loading configuration data on rising CCLK edges. Byte loaded on rising CCLK edge. Byte loaded on rising CCLK edge. Byte loaded on rising CCLK edge.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
315
Chapter 4: Configuration
When switching to write control (writing data to the FPGA), the device begins sampling data on the D[0:7] pins after it deasserts the BUSY signal. Similarly, when switching to read control, the device presents valid data on the D[0:7] pins after it deasserts the BUSY signal. This procedure is illustrated in Figure 4-18.
CS_B
RDWR_B
WRITE READ Byte n Byte 0 Byte n
DATA[0:7]
Byte 0
CCLK BUSY
High-Z
High-Z
High-Z
UG071_48_102504
Figure 4-18:
Triggering an ABORT
An ABORT occurs when the device registers a new RDWR_B state while CS_B remains asserted and a rising CCLK edge occurs.
5.
316
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
CCLK
CS_B
RDWR_B
HI-Z HI-Z
DATA[0:7]
WRITE
A0
A1
A2
A3
ABORT
BUSY
HI-Z
ug012_c3_044_062703
CCLK
CS_B
RDWR_B
HI-Z HI-Z ABORT
DATA[0:7]
READ
BUSY
HI-Z
ug012_c3_045_062703
Figure 4-20:
Note that ABORTs during readback are not followed by a status word if the RDWR_B signal remains set for write control.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
317
Chapter 4: Configuration
Bit Number
The ABORT sequence lasts for four CCLK cycles. The status byte reflects data alignment, ABORT status, and whether readback is in progress. An example sequence is given in Table 4-9. Table 4-9: ABORT Sequence Example D[0:7] 11111011 11110011 11110001 11111001 DALIGN 1 1 0 0 IN_ABORT_B 1 0 0 1
Byte Number 0 1 2 3
After the last cycle, the synchronization word can be reloaded to establish data alignment.
ABORT Recovery
There are two procedures for recovering from an ABORTone simple, the other more complex. These procedures apply to both read- and write-ABORT recovery.
318
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
10. Read 1 frame from the device 11. Toggle the SelectMAP interface to Write control
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
319
Chapter 4: Configuration
O [7:0] BUSY
Figure 4-21:
ICAP_VIRTEX2 Primitive
The ports on the ICAP primitive correspond to ports on the SelectMAP interface as shown in Table 4-10. The ICAP ports behave exactly as do the equivalent SelectMAP ports. Table 4-10: ICAP Ports and Equivalent SelectMAP Ports Equivalent SelectMAP Port Name BUSY O[0:7] CE CLK I[0:7] WRITE Direction Output Output Input Input Input Input BUSY D[0:7] when SMAP port is set for read control CS_B CCLK D[0:7] when SMAP port is set for write control RDWR_B
ICAP Port
The following restrictions govern the use of ICAP: ICAP and SelectMAP cannot be used together after configuration.
After the DONE pin goes High, the ICAP port will be disabled if the PERSIST bit is set. A design that instantiates the ICAP port can be configured via SelectMAP, provided that the PERSIST bit is not set.
Care must be taken when using the JTAG interface on a design that also accesses the ICAP port.
The JTAG CFG_IN, CFG_OUT, JSTART, and JSHUTDOWN instructions must not be sent to the device while configuration or readback operations are being performed through the ICAP port. After finishing a configuration or readback operation on the JTAG interface, the configuration logic should be desynchronized before performing any operations using the ICAP port. Conversely, after finishing an operation on the ICAP port, the configuration logic should be desynchronized before performing any operations using the JTAG interface.
320
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
There are three input pins and one output pin to control the 1149.1 boundary-scan TAP controller. There are optional control pins, such as TRST (Test Reset) and enable pins, which might be found on devices from other manufacturers. It is important to be aware of these optional signals when interfacing Xilinx devices with parts from different vendors, because they might need to be driven. The TAP controller is a 16-state state machine shown in Figure 4-22. The four mandatory TAP pins are outlined below.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
321
Chapter 4: Configuration
TMS - This pin determines the sequence of states through the TAP controller on the rising edge of TCK. TMS has an internal resistive pull-up to provide a logic High if the pin is not driven. TCK - This pin is the JTAG test clock. It sequences the TAP controller and the JTAG registers in the Virtex-II Pro devices. TDI - This pin is the serial input to all JTAG instruction and data registers. The state of the TAP controller and the current instruction held in the instruction register determine which register is fed by the TDI pin for a specific operation. TDI has an internal resistive pull-up to provide a logic High to the system if the pin is not driven. TDI is applied into the JTAG registers on the rising edge of TCK. TDO - This pin is the serial output for all JTAG instruction and data registers. The state of the TAP controller and the current instruction held in the instruction register determine which register (instruction or data) feeds TDO for a specific operation. TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device. This pin is an open-drain output and should be pulled up by an external resistor to the appropiate level (typically 3.3V). Note: As specified by the IEEE Standard, the TMS and TDI pins all have internal pull-up
resistors by default. These internal pull-up resistors of 50-150 k are active, regardless of the mode selected. User can select a pull-up, pull-down, or float option in the implementation tools.
For JTAG configuration mode, JTAG inputs are independent of VCCO and work between 2.5V and 3.3V TTL levels (VIL max = .8V, VIH min = 2.0V). The JTAG input pins are 3.3V tolerant. The JTAG output (TDO) is an open-drain output and must be pulled up to the appropriate voltage level (typically 3.3V) through an external resistor. The value of the external pull-up resistor depends on the capacitive loading on the TDO pin and the operating frequency, but it should not be less than 200. The optimal TDO pull-up value can be determined through IBIS simulation.
TAP Controller
Figure 4-22, page 323 diagrams a 16-state finite state machine. The four TAP pins control how data is scanned into the various registers. The state of the TMS pin at the rising edge of TCK determines the sequence of state transitions. There are two main sequences, one for shifting data into the data register and the other for shifting an instruction into the instruction register.
322
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
CAPTURE-IR 0
SHIFT-IR 1 EXIT1-IR 0 1
0 0
EXIT2-DR 1 UPDATE-DR 1 0
NOTE: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK.
x139_01_112399
Boundary Scan Command EXTEST SAMPLE USER1 USER2 CFG_OUT CFG_IN INTEST USERCODE IDCODE HIGHZ JSTART JSHUTDOWN BYPASS JPROG_B RESERVED
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
323
Chapter 4: Configuration
The mandatory IEEE 1149.1 commands are supported in Virtex-II Pro devices, as well as several Xilinx vendor-specific commands. Virtex-II Pro devices have a powerful command set. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS, IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports two internal user-defined registers (USER1 and USER2) and configuration/readback of the device. The Virtex-II Pro boundary-scan operations are independent of mode selection. The boundary-scan mode in Virtex-II Pro devices overrides other mode selections. For this reason, boundary-scan instructions using the boundary-scan register (SAMPLE/PRELOAD, INTEST, EXTEST) must not be performed during configuration. All instructions except USER1 and USER2 are available before a Virtex-II Pro device is configured. After configuration, all instructions are available. JSTART and JSHUTDOWN are instructions specific to the Virtex-II Pro architecture and configuration flow. As described in Table 4-12, the JSTART and JSHUTDOWN instructions clock the startup sequence when the appropriate bitgen option is selected. The instruction does not work correctly without the correct bitgen option selected.
bitgen -g startupclk:jtagclk designName.ncd
For details on the standard boundary-scan instructions EXTEST, INTEST, and BYPASS, refer to the IEEE Standard. The user-defined registers (USER1/USER2) are described in USER1, USER2 Registers, page 327.
Boundary-Scan Architecture
Virtex-II Pro device registers include all registers required by the IEEE 1149.1 Standard. In addition to the standard registers, the family contains optional registers for simplified testing and verification (Table 4-13). Table 4-13: Virtex-II Pro JTAG Registers Register Length Device specific 3 bits per I/O 1 bit 32 bits 64 bits 32 bits Description Holds current instruction OPCODE and captures internal device status. Controls and observes input, output, and output enable. Device bypass. Captures device ID. Allows access to the configuration bus when using the CFG_IN or CFG_OUT instructions. Captures user-programmable code
Register Name Instruction register Boundary scan register Bypass register Identification register JTAG configuration register USERCODE register
Boundary-Scan Register
The test primary data register is the boundary-scan register. Boundary-scan operation is independent of individual IOB configurations. Each IOB, bonded or un-bonded, starts as bidirectional with 3-state control. Later, it can be configured to be an input, output, or 3-state only. Therefore, three data register bits are provided per IOB (Figure 4-23). When conducting a data register (DR) operation, the DR captures data in a parallel fashion during the CAPTURE-DR state. The data is then shifted out and replaced by new data during the SHIFT-DR state. For each bit of the DR, an update latch is used to hold the input
324
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
data stable during the next SHIFT-DR state. The data is then latched during the UPDATEDR state when TCK is Low. The update latch is opened each time the TAP Controller enters the UPDATE-DR state. Care is necessary when exercising an INTEST or EXTEST to ensure that the proper data has been latched before exercising the command. This is typically accomplished by using the SAMPLE/PRELOAD instruction. Consider internal pull-up and pull-down resistors when developing test vectors for testing opens and shorts. The boundary-scan mode determines if the IOB has a pull-up resistor. Figure 4-23 is a representation of Virtex-II Pro Boundary-Scan Architecture.
TDI
1x 01 00
sd
INTEST
LE 1
IOB.I
0 1x 01 00 sd D Q D Q
LE 1
IOB.O IOB.T
1x 01 00 sd D Q D Q
0 0 1
LE
UPDATE
Figure 4-23:
Bit Sequence
The order in each non-TAP IOB is described in this section. The input is first, then the output, and finally the 3-state IOB control. The 3-state IOB control is closest to the TDO. The input-only pins contribute only the input bit to the boundary-scan I/O data register. The bit sequence of the device is obtainable from the Boundary-Scan Description Language Files (BSDL files) for the Virtex family. These files can be obtained from the Xilinx software download area. The bit sequence is independent of the design. It always has the same bit order and the same number of bits.
Bypass Register
The other standard data register is the single flip-flop BYPASS register. It passes data serially from the TDI pin to the TDO pin during a bypass instruction. This register is initialized to zero when the TAP controller is in the CAPTURE-DR state.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
325
Chapter 4: Configuration
Instruction Register
The instruction register loads the OPCODE necessary for the Virtex-II Pro boundary-scan instruction set. This register loads the current OPCODE and captures internal device status. The width of this register is device size specific.
Identification Register
Virtex devices have a 32-bit identification register, commonly referred to as the IDCODE register. This register is based upon IEEE Standard 1149.1 and allows easy identification of the part being tested or programmed via boundary scan.
where v is the revision code f is the 7-bit family code, 0001001 for Virtex-II Pro a is the number of array rows plus columns in the part, expressed in 9 bits: XC2VP2 rows + columns XC2VP4 rows + columns XC2VP7 rows + columns XC2VP20 rows + columns XC2VP30 rows + columns XC2VP40 rows + columns XC2VP50 rows + columns XC2VP70 rows + columns XC2VP100 rows + columns = = = = = = = = = 16 + 22 40 + 22 40 + 34 56 + 46 80 + 46 88 + 58 88 + 70 104 + 82 120 + 94 = = = = = = = = = 38 62 74 = = = 0x026 0x03E 0x04A 0x066 0x07E 0x092 0x09E 0x0BA 0x0D6
c is the company code = 00001001001. Since the last bit of the JTAG IDCODE is always one, the last three hex digits appear as 0x093. Examples of how the binary digits translate into hex codes appear in Table 4-14.
326
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 4-14:
fffa
0010 2 0010 2 0010 2
aaaa
0100 4 1001 9 1101 D
aaaa
1010 A 0010 2 0110 6
cccc
0000 0 0000 0 0000 0
cccc
1001 9 1001 9 1001 9
ccc1
0011 3 0011 3 0011 3
XC2VP7
XC2VP40
XC2VP100
ID Codes assigned to Virtex-II Pro FPGAs are shown in Table 4-15. Table 4-15: Virtex-II Pro Device ID Codes IDCODE (1) <v>1226093 <v>123E093 <v>124A093 <v>1266093 <v>127E093 FPGA XC2VP40 XC2VP50 XC2VP70 XC2VP100 IDCODE <v>1292093 <v>129E093 <v>12BA093 <v>12D6093
1. The <v> in the IDCODE stands for the devices revision code (in hex).
USERCODE Register
USERCODE is supported in the Virtex family as well. This register allows a user to specify a design-specific identification code. The USERCODE can be programmed into the device and read back for verification at a later time. The USERCODE is embedded into the bitstream during bitstream generation (bitgen -g UserID option) and is valid only after configuration.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
327
Chapter 4: Configuration
Note that these are user-defined registers. The example (Figure 4-24) is one of many implementations. For HDL, the BSCAN_VIRTEX2 macro needs to be instantiated in the design.
cap0 SHIFT 0 TDI 1 D Q 0 1 D Q 0 1 TDO1 cap1 cap2
R DRCK1
RESET D CE R SEL1 UPDATE Internal Symbol Logic CLOCKDR BSCAN_VIRTEX2 UPDATE SHIFT RESET TDI SEL1 DRCK1 SEL2 DRCK2 CAPTURE SEL1 DRCK1 Q D CE R Q D CE R Q
SEL2
DRCK2
TDO1 TDO2
x139_04_020304
Figure 4-24:
328
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
TCK
TTCKTDO
Data Valid
Data Valid
139 05 020300
Figure 4-25:
For further information on the Startup sequence, bitstream, and internal configuration registers referenced here, refer to Readback, page 367.
Also, when using iMPACT software, verify that the most current version is being used. Table 4-16 describes the TAP controller commands required to configure a Virtex-II Pro device. Refer to Figure 4-22, page 323 for TAP controller states. These TAP controller commands are issued automatically if configuring the part with the iMPACT software.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
329
Chapter 4: Configuration
Power Up
INIT_B = High?
No
Shutdown Sequence
No
Abort Startup
No
ug012_c3_043_031105
Figure 4-26:
330
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 4-16:
Single Device Configuration Sequence Set & Hold TDI X X X X TMS 1 0 1 0 # of Clocks TCK 5 1 2 2
TAP Controller Step and Description 1. On power-up, place a logic one on the TMS and clock the TCK five times. This ensures starting in the TLR (Test-Logic-Reset) state. Move into the RTI state. Move into the SELECT-IR state. Enter the SHIFT-IR state. Start loading the CFG_IN instruction, LSB first: XC2VP2 XC2VP7: XC2VP20 XC2VP100: 6. Load the MSB of CFG_IN instruction when exiting SHIFT-IR, as defined in the IEEE standard. Enter the SELECT-DR state. Enter the SHIFT-DR state. Shift in the Virtex-II Pro bitstream. Bitn (MSB) is the first bit in the bitstream (1). Shift in the last bit of the bitstream. Bit0 (LSB) shifts on the transition to EXIT1-DR. Reset TAP by clocking five 1s on TMS. Move to the Run-Test-Idle state. Enter the SELECT-IR state. Move to the SHIFT-IR state.
2. 3. 4. 5.
0 0 1 1 0 0 1 1 1 0 1 0
9 13 1 2 2 (bits in bitstream)-1 1 1 5 1 2 2
7. 8. 9. 10.
16. Start loading the JSTART instruction. The JSTART instruction initializes the startup sequence. XC2VP2 XC2VP7: XC2VP20 XC2VP100: 17. 18. 19. Load the last bit of the JSTART instruction. Move to the UPDATE-IR state. Move to RTI and clock the STARTUP sequence by applying a minimum of 12 clock cycles to the TCK. Move to the TLR state. The device is now functional. 111_001100 111_1111_001100 1 X X 0 0 1 1 0 9 13 1 1 12
20.
Notes:
1. In the Configuration Register, data is shifted in from the right (TDI) to the left (TDO).
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
331
Chapter 4: Configuration
Refer to the State Diagram in Figure 4-22 for the following TAP controller steps. 1. 2. 3. 4. 5. 6. 7. On power-up, place a logic 1 on the TMS and clock the TCK 5 times. This ensures starting in the TLR (Test-Logic-Reset) state. Load the CFG_IN instruction into the target device (and BYPASS in all other devices).Go through RTI (RUN-TEST/IDLE). Load in the configuration bitstream per step 7 through step 11 in Table 4-16. Repeat step 2 and step 3 for each device. Reset all TAPs by clocking five 1s on TMS. Load the JSTART command into all devices. Go to RTI and clock TCK 12 times. All devices are active at this point.
JTAG Header
TDO
Device 0
Device 1
Device 2
ug012_c3_049_011205
Figure 4-27:
Notes:
332
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
3. 4. 5. 6.
Load JSHUTDOWN. Go to RTI and clock TCK at least 12 times to clock the shutdown sequence. Proceed to SHIFT-IR state and load the CFG_IN instruction again. Go to SHIFT-DR state and load the configuration bits. Make sure the configuration bits contain AGHIGH command, which asserts the global signal GHIGH_B. This prevents contention while writing configuration data.
0011 0000 0000 0000 1000 0000 0000 0001 Header: Write to CMD 0000 0000 0000 0000 0000 0000 0000 1000 AGHIGH command asserts GHIGH_B
7. 8. 9.
When all configuration bits have been loaded, reset the TAP by clocking five 1s on TMS. Go to SHIFT-IR state and load the JSTART instruction. Go to RTI and clock TCK at least 12 times to clock the startup sequence.
Debugging Configuration
To verify successful configuration, there are several options. Some of the most helpful verification steps include using TAP pins and the readback command. Using the Virtex-II Pro TAP controller and status pins is discussed first. When using TAP controller pins, TDO is driven only in the SHIFT-DR and SHIFT-IR state. If the output of the TDO can be changed via an external pull-up resistor, the TAP is not in SHIFT-IR or SHIFT-DR. If the TAP can be controlled precisely, use this to test the application. In JTAG configuration, the status pin (DONE) functions the same as in the other configuration modes. The DONE pin can be monitored to determine if a bitstream has been completely loaded into the device. If DONE is Low, the entire bitstream has not been sent or the start-up sequence is not finished. If DONE is High, the entire bitstream has been received correctly. The INIT_B pin functions similar to a normal INIT_B but does not indicate a configuration error in boundary-scan configuration. In addition to external pin monitoring, an internal test can be conducted. The second method includes the following steps to capture the internal device status register contents:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
333
Chapter 4: Configuration
1. 2. 3.
Move the TAP to TLR state. Go to SHIFT-IR state and load in the CFG_IN instruction. Go to SHIFT-DR state and shift in the following 64-bit pattern with the MSB (left-most bit), shifted in first.
1111 1010 0010 0000 0000 0000
1.
Pad word Synchronization word Read STATus Register (1) flush pipe flush pipe flush pipe
Notes:
Since an odd number of words (1) is sent to the device for this JTAG read operation, it must end with exactly three pad words. This is because all JTAG read command sequences must consist of an even number of words (see Packet Processor, page 343 for details).
4. 5.
After shifting in the pattern, load the CFG_OUT instruction in the SHIFT-IR state. Move to SHIFT-DR state and clock TCK 32 times while reading TDO. The data seen on TDO is the content of the status register. The last bit out is a one if a CRC error occurred. If successful, it should read as follows.
0000 0000 0000 0000 0001 1MMM 1110 11101(1,2) Notes:
1. 2. 3. MMM is the mode pins value. Assuming that the device is in normal operation mode. Refer to Status Register (STAT), page 349 for a detailed explanation of the bits in the Status Register.
6. 7.
Go to SHIFT-IR state and load the CFG_IN instruction again. Move to SHIFT-DR state and shift in the following bit pattern:
0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0001 Header: Write to CMD register 0000 0000 0000 0000 0000 0111 RCRC command 0000 0000 0000 0000 0000 0000 flush pipe 0000 0000 0000 0000 0000 0000 flush pipe
8.
The device status register also gives the status of the DONE and INIT_B signals. For information on the status register, refer to Figure 4-38, page 349.
334
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Unprogrammed (0,0)
ISC_Accessed (1,X)
Any non-test inst.but ISC_DISABLE loaded and ISC_DONE is clear ISC_Done is clear
Power UP
ISC_Done is set
ISC_ENABLE executed
Operational (0,1)
Any non-test inst.but ISC_DISABLE loaded and ISC_DONE is set
ISC_DISABLE loaded
(ISC_Enabled, ISC_Done)
UG002_01_082600
Figure 4-28:
Once the device is powered up, it goes to an Unprogrammed state. The I/Os are all either 3-stated or pulled up. When ISC_ENABLE is successfully executed, the ISC_Enabled signal is asserted, and the device moves to ISC_Accessed state. When the device moves to ISC_Accessed state from Operational state, the shutdown sequence is executed. The I/Os are all either 3-stated or pulled up. The StartUp sequence is executed when in the ISC_Accessed state. At the end of the StartUp Sequence, ISC_Enabled is cleared and the device moves to ISC_Complete. The minimum clock cycle requirement is the number of clock cycles required to complete the StartUp sequence. At the completion of the minimum required clock cycles, ISC_Enabled is deasserted. Whether the StartUp sequence is successful or not is determined by CRC or configuration error status from the configuration processor. If the startup is completed, ISC_Done is asserted; otherwise, ISC_Done stays Low. The I/Os are either 3-stated or pulled up. When ISC_Done is set in ISC_Complete state, the device moves to the Operational state. Otherwise, if ISC_Done is clear, the device moves to an Unprogrammed state. However, if the TAP controller goes to TLR state while the device is in ISC_Accessed state and if ISC_Done is set, then the device moves to the Operational state. However, the I/O is not active yet because the Startup sequence has not been performed. The Startup sequence has to be performed in the Operational state to bring the I/O active.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
335
Chapter 4: Configuration
336
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
PROG_B
PROG_B No
No
Clear Configuration memory once more
End of Data Yes CRC correct Yes No Pull INIT_B Low STOP
JTAG Available(1)
INIT_B = High?
No
(1) The JTAG interface becomes available after configuration memory is cleared. It is possible to shift in JTAG instructions for boundary scan operation, or configure the device through JTAG, while holding INIT_B Low to prevent the sampling of the Mode pins.
Load ISC_DISABLE
Load ISC_ENABLE
Reconfigure Yes
No
Load ISC_PROGRAM
A
UG002_c4_38_101300
Figure 4-29:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
337
Chapter 4: Configuration
TAP Instr.
IDCODE
ISC_ENABLE
ISC_DISABLE
BYPASS
ISC_Enabled
Modal State
Unprog.
ISC_Accessed
ISC_Complete
Operational
System Output
Active
UG002_C3_028_113000
Figure 4-30:
TAP Instr.
IDCODE
ISC_ENABLE
ISC_DISABLE
BYPASS
ISC_Enabled
Modal State
Operational
ISC_Accessed
ISC_Complete
Operational
System Output
Disabled Start-up
Active
UG002_C3_029_113000
Figure 4-31: Signal Diagram for Successful ISC Partial and Full Reconfiguration
338
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Configuration Details
All user programmable features inside a Virtex-II Pro device are controlled by memory cells that are volatile and must be configured on power-up. These memory cells are known as the configuration memory, and define the LUT equations, signal routing, IOB voltage standards, and all other aspects of the user design. To program configuration memory, instructions for the configuration control logic and data for the configuration memory are provided in the form of a bitstream, which is delivered to the device through one of the JTAG, SelectMAP, or Serial configuration interfaces. The composition of the bitstream is largely independent of the configuration method; however, certain operations such as readback can only be performed via the SelectMAP and JTAG interfaces.
Virtex-II Pro Frame Count, Frame Length, and Bitstream Size Frames 884 884 1,320 1,756 1,756 1,756 2,192 2,628 3,064 3,064 3,500 Frame Length (32-bit Words) 46 106 106 146 146 206 226 226 266 266 306 Configuration Bits (1) 1,301,248 2,998,528 4,477,440 8,204,032 8,204,032 11,575,552 15,852,544 19,005,696 26,080,768 26,080,868 34,272,000 Default Bitstream Size (2) 1,305,376 3,006,496 4,485,408 8,214,560 8,214,560 11,589,920 15,868,192 19,021,344 26,098,976 26,098,976 34,292,768
Virtex-II Pro devices do not "expect" a bitstream of any particular size. The length of the bitstream can vary according to Bitgen settings.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
339
Chapter 4: Configuration
Configuration frames are grouped into six column types that correspond roughly to physical device resources. All Virtex-II Pro devices have the same configuration column types: IOB, IOI, CLB, GCLK, BlockRAM, and BlockRAM Interconnect. All Virtex-II Pro devices have the same number of IOB, IOI, and GCLK columns. However,the number of CLB, BRAM, and BRAM Interconnect columns varies by device size. The number of frames per column type remains constant for all devices. Table 4-18 shows the number of columns per device and the number of frames per column. Table 4-18: Column Type:
Columns per Device:
IOI
Frames per Column:
CLB
Columns per Device: Frames per Column:
BRAM
Columns per Device: Frames: per Column
BRAM Interconnect
Columns per Device: Frames per Column:
GCLK
Columns per Device: Frames per Column:
Device: XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
2 2 2 2 2 2 2 2 2 2 2
4 4 4 4 4 4 4 4 4 4 4
2 2 2 2 2 2 2 2 2 2 2
22 22 22 22 22 22 22 22 22 22 22
22 22 34 46 46 46 58 70 82 82 94
22 22 22 22 22 22 22 22 22 22 22
4 4 6 8 8 8 10 12 14 14 16
64 64 64 64 64 64 64 64 64 64 64
4 4 6 8 8 8 10 12 14 14 16
22 22 22 22 22 22 22 22 22 22 22
1 1 1 1 1 1 1 1 1 1 1
4 4 4 4 4 4 4 4 4 4 4
IOB Columns
IOB columns configure the voltage standard for the I/Os on the left and right edges of the device. IOBs on the top and bottom edges of the device are configured by the CLB Columns with which they are vertically aligned. There are two IOB columns per device.
IOI Columns
IOI columns configure the IOB registers, multiplexers, and 3-state buffers in the IOBs on the left and right edges of the device. IOBs on the top and bottom edges of the device are configured by the CLB columns with which they are vertically aligned. There are two IOI columns per device.
CLB Columns
The CLB columns program the configurable logic blocks, routing, and most interconnect. IOBs on the top and bottom edges of the device are also programmed by CLB configuration columns. The number of CLB configuration columns matches the number of physical CLB columns in the device.
340
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
BlockRAM Columns
BlockRAM configuration columns program only the BlockRAM user memory space. BlockRAMs are accessed by the configuration control logic in the same way that user designs access BlockRAMs: via the address and data pins that are available on the BlockRAM primitive. Consequently, the user design is not able to access BlockRAM while BlockRAM columns are being addressed by the configuration logic. For this reason, active reconfiguration and readback on BlockRAMs should not be attempted. The number of BlockRAM configuration columns matches the number of physical BlockRAM columns in the device.
GCLK Column
The global clock column configures most global clock resources, including clock buffers and DCMs. There is one global clock column per device.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
341
Chapter 4: Configuration
BA
MJA
MNA
Byte Number
Virtex-II Pro configuration memory is divided into three independently addressable blocks: Block Address 0 (BA 00) contains all GCLK, IOB, IOI, and CLB configuration columns Block Address 1 (BA 01) contains all BRAM columns Block Address 2 (BA 10) contains all BRAM Interconnect columns
Figure 4-33 illustrates the Virtex-II Pro configuration memory map. The MJA for each block type is a function of the device size, and is determined by the number of CLB columns (n) and the number of BlockRAM columns (m) in a device. During configuration, frames are programmed in order of increasing block, major, and minor address (i.e., from left to right in Figure 4-33).
BRAM INT BRAM INT
BRAM
CLB
CLB
CLB
CLB
IOB
BA MJA
0 0 0 0 0 0
0 0 0
IOB
IOI
IOI
Column Type
BRAM
GCLK
0 1 2 3 4 5 n n n 0 m 0 m + + + 2 3 4
ug002_c3_035_030405
Figure 4-33:
Notes:
1. n = number of device CLB columns; m = number of device BRAM/BRAM Int columns. Refer to Table 4-18, page 340 for these numbers. 2. Virtex-II Pro configuration control logic allows access to nonexistent memory locations; therefore, attempts to write to invalid addresses have no effect, and attempts to read from invalid addresses yield a static value. The configuration logic does not issue an error of any kind when attempting to perform operations on invalid memory addresses.
Bitstream Packets
The Virtex-II Pro bitstream is composed of a 32-bit synchronization word (0xAA995566) and numerous data packets. The purpose of the synchronization word is to align the device configuration logic with the beginning of the first packet in the bitstream. Each packet targets a specific configuration register to set configuration options, program configuration memory, or toggle internal signals. Bitstream data packets consist of a 32-bit header and a body of variable length. There are two packet types: Type 1, used for smaller packets (up to 211 1 words) Type 2, used for larger packets (up to 227 1 words)
Figure 4-34 and Figure 4-35 describe the Type 1 and Type 2 packet headers.
342
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Type
W R R D
Register Address
RSVD
Word Count
Both packet types specify read or write access and the size of the packet in words. However, only Type 1 packet headers can specify a register address. The register set by an earlier Type 1 packet header remains active when a Type 2 packet header is processed; therefore, all Type 2 packets appear as a part of a "Type 1, Type 2 combination. Table 4-19 gives an example of a Type 1, Type 2 packet combination. Note that the register address is entirely different than the frame address described earlier. Table 4-19: Type 1, Type 2 Packet Combination Explanation Type 1 Packet Header: Write 0 words to FDRI Type 2 Packet Header: Write 10530 words to the active register (FDRI) 10530 data words
Packet Processor
After power-on, the packet processor waits for the synchronization word to appear on the configuration interface before interpreting any data. Once the device is synchronized, the packet processor waits for a valid packet header; when one is received it drives incoming data into the targeted configuration register until the word count specified by the packet header reaches zero. At the end of a packet the processor waits for a new packet header. All packet headers pass through a 64-bit buffer before reaching the packet processor; the packet processor itself interprets all commands in 32-bit words. To flush the last command in a sequence from the packet buffer, a sequence of configuration commands must end with least four 32-bit NOOP commands. Typically, this is found at the end of a bitstream, as shown in Table 4-20.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
343
Chapter 4: Configuration
This means that read command sequences must end with exactly two or exactly three NOOPs, depending on the number of words sent prior to the NOOP commands. Do not include the synchronization word or anything prior to it in this count, and do not use any number of NOOPs other than two or three to finish sending a JTAG read command sequence. See Configuration Register Read Procedure (JTAG), page 371 and Configuration Memory Read Procedure (1149.1 JTAG), page 374 for examples. Table 4-20: NOOP Commands at the End of the Virtex-II Pro Bitstream Explanation Type 1 write 1 words to CRC CRC = 0x00009A32 Type 1 write 1 words to CMD DESYNCH command Type 1 NOOP word 0 Type 1 NOOP word 1
Configuration Registers
All configuration operations are executed by reading or writing to the configuration registers. Table 4-21 summarizes these registers; a detailed explanation of each register follows. Table 4-21: Register Name CRC FAR FDRI FDRO CMD CTL MASK STAT LOUT COR MFWR FLR KEY CBC IDCODE Virtex-II Pro Configuration Registers Read Write Address Y Y N Y Y Y Y Y N Y N Y N N Y Y Y Y N Y Y Y N Y Y Y Y Y Y Y 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 CRC register Frame address register Frame data input register (write configuration data) Frame data output register (readback configuration data) Command register Control register Masking register for CTL Status register Legacy output register (DOUT for daisy chain) Configuration option register Multiple frame write register Frame length register Initial key address register Initial CBC value register Device ID register Description
344
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Explicit CRC checks are performed by writing a pre-calculated CRC value into the CRC register in a distinct configuration packet. Table 4-22 shows the command and data sequence for an explicit CRC check. Table 4-22: Example Packet forVirtex-II Pro CRC Check Explanation Type 1 write 1 words to CRC CRC = 0x00009A32
AutoCRC is an implicit CRC write that occurs at the end of a write to the Frame Data Input Register (FDRI). The last 32-bit word in a write packet to the FDRI register is automatically interpreted as a CRC value. The AutoCRC word is not included in the packet word count. Note that if the entire bitstream is written in a single Type 2 packet, only one AutoCRC check occurs. Table 4-23 shows an AutoCRC check. Table 4-23: Example Packets for Frame Write with AutoCRC Explanation Type 1 Packet Header: Write 1 word to CMD Packet Data: WCFG command Type 1 Packet Header: Write 1 word to FAR Packet Data: Frame Address = 0x020000000 Type 1 Packet Header: Write 26 words to FDRI Packet Data: word 1
Configuration Data 30008001 00000001 30002001 02000000 3000401A 00000000 ... 00000000 0000A53B Packet Data: word 26 AutoCRC word
CRC checking is disabled by setting the -g CRC:Disable option in Bitgen. This option sets the CRC_DISABLE bit in the Configuration Options Register (COR) to '1'. When CRC checking is disabled, AutoCRC and explicit CRC checks still appear, although they use the default CRC value of (0x0000DEFC), shown in Table 4-24.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
345
Chapter 4: Configuration
Table 4-24:
Example Packets for CRC/AutoCRC Checks with Checking Disabled Explanation Type 1 write 0 words to FDRI Type 2 write 10530 words to FDRI Packet data write FDRI word 0
Configuration Data 30004000 50002922 00100000 ... 00000000 0000DEFC ... 30000001 0000DEFC
Frame Data Input Register (FDRI) and Frame Data Output Register (FDRO)
Configuration data frames are written to memory by shifting frame data into the Frame Data Input Register. Data written to the FDRI is placed in the configuration memory address specified by the FAR. Prior to writing to the FDRI, the CMD register must be loaded with the WCFG command and the correct Device ID must have been written to the IDCODE register. The write operation is pipelined through the frame buffer such that the first frame of data is written to the configuration memory while the second frame is being shifted through the frame buffer. For this reason, the FDRI must be flushed with one frame of pad data at the end of a write to configuration memory so that the last data frame is loaded. Therefore, the smallest FDRI write operation requires two frames of data: the frame to be loaded into configuration memory, followed by a frame of pad data to flush the first out of the FDRI (see Figure 4-36). The configuration process is explained in detail in the Configuration section. After a number of bits equal to the value in the FLR have been shifted into the FDRI, frame data in the FDRI are loaded in parallel into the frame specified by the value in the FAR. After a write to the FDRI has completed, the Virtex-II Pro device automatically interprets the next 32-bit word as an AutoCRC value (see CRC). Configuration data frames are read from memory through the Frame Data Output Register. Prior to reading from the FDRO, the CMD register must be loaded with the RCFG command. The length of the read from the FDRO is specified by the FDRO read packet header.
346
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The read operation is pipelined through the frame buffer such that the first frame is driven to the configuration interface as the second frame is being read from memory (Figure 4-36). For this reason, the first frame read out of the device is not valid data; readback data begins with the second frame read from the device. Because of the frame buffer, the smallest FDRO read requires two frames of data: the first frame to clear the frame buffer, followed by the frame of configuration data. The readback process is explained in detail in the Readback section. Reads from the FDRO register do not generate a CRC value, nor is an AutoCRC performed after reading from the FDRO.
Configuration Interface Configuration Interface
ug002_c3_036_092404
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
BRAM
BRAM
CLBs
CLBs
CLBs
IOBs
IOBs
347
Chapter 4: Configuration
START
0101
RCAP RCRC
0110 0111
AGHIGH
1000
SWITCH
1001
GRESTORE
1010
SHUTDOWN
1011
GCAPTURE
1100
DESYNCH
1101
SBITS
348
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Control Register Description Bit Index Various Description Reserved CTL register bits for testing. Always leave these bits set to 0. Security Level: 0: Read/Write OK (default) 1: Readback disabled 2,3: Readback disabled, writing disabled except to the CRC register. The configuration interface defined by M2:M0 remains after configuration. Typically used only with the SelectMAP interface to allow reconfiguration and readback. 0: No (default) 1: Yes Active Low signal to place I/Os into a high-Z state.
SBITS
5:4
PERSIST
GTS_USER_B
GHIGH_B
MODE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x
DONE
GWE
INIT
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
349
Chapter 4: Configuration
Status Register Description Bit Index Description Encryption keys are stored with a tag indicating their position among the other keys. If the keys are sent in the wrong order, it will be indicated by this status bit. 0: No decryptor key sequence error 1: Devryptor keys were not used in the correct sequence Write FDRI issued before or after decrypt operation.
BAD_KEY_SEQ
15
DEC_ERROR
14
0: No decryptor error 1: Decryptor error. Assert PROG to recover Attempt to write to FDRI without successful IDCODE check. 0: No ID_ERROR 1: ID_ERROR. Assert PROG to recover The DONE bit in the STATUS register reflects the actual level on the DONE pin. If the DONE signal is released by the device but held Low externally, this bit remains Low. 0: DONE pin = logic 0 1: DONE pin = logic 1 The INIT bit in the STATUS register reflects the actual level on the INIT pin. 0: INIT pin = logic 0 1: INIT pin = logic 1 Status of the MODE pins (M2:M0). Status of the GHIGH_B signal.
ID_ERROR
13
DONE
12
INIT
11
MODE GHIGH_B
10:8 7
0: GHIGH_B is asserted 1: GHIGH_B is deasserted Status of the Global Write Enable signal. 0: All FFs and BRAMs are write disabled 1: FFs and BRAMs are write enabled Status of the GTS_CFG_B signal.
GWE
GTS_CFG_B
0: All I/Os in high-Z state 1: I/Os are not placed in High-Z by this signal Note that there are other ways of forcing I/Os into a high-Z state, including GTS_USR_B, as well as through various JTAG instructions. Indicates that input data is being clocked in too fast. This can happen if the CCLK frequency exceeds FCC_SELECTMAP in SelectMAP mode. 0: No legacy input error 1: Legacy input error
IN_ERROR
350
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Status Register Description (Continued) Bit Index Description This signal reflects the logical AND of all MATCH signals. There is one MATCH signal per I/O bank. If no DCI I/Os are instantiated in a given bank,the banks MATCH signal = 1. 0: DCI not matched 1: DCI is matched This is a logical AND function of all DCM LOCKED signals. Unused DCM LOCKED signals =1. 0: DCMs not locked 1: DCMs are locked Status of the Triple-DES decryptor. 0: Decryptor security not set 1: Decryptor security set Status of the CRC. 0: No CRC error 1: CRC error
DCI_MATCH
DCM_LOCK
PART_SECURED
CRC_ERROR
DONE_PIPE
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
RESEVRED
RESEVRED
SSCLKSRC
RESERVED
OSCFSEL
SINGLE
www.xilinx.com
351
Chapter 4: Configuration
Configuration Options Register Description Bit Index 29 0: CRC enabled 1: CRC disabled When this bit is set, all DCMs will be reset if the AGHIGH command is issued. Description
CRC_BYPASS
SHUT_RST_DCM
26
0: DCMs cannot be reset through the configuration logic 1: DCMs will reset during shutdown readback or reconfiguration Adds a pipeline stage for the DONEIN signal. The DONEIN signal reflects the logic level on the DONE pin, not whether the device has released the DONE pin. This pipeline stage can be useful if the rise time on the DONE pin is slow, which could otherwise cause configuration to fail. 0: No pipeline stage for DONEIN 1: Add pipeline stage for DONEIN By default the DONE pin is an open-drain output, meaning that the pin actively drives a logic '0' before configuration, then goes into a high-Z state when it is "released" during Startup. This setting requires an external pull-up resistor on the DONE pin, and is typically applied to Slave devices in a serial daisy-chain.
DONE_PIPE
25
DRIVE_DONE
24
Alternately, the DONE pin can be configured as an activelydriven output, meaning that the pin actively drives a logic '1' when it is released. 0: DONE pin is an open-drain output (released = high-Z) 1: DONE pin is an actively driven output (released = logic '1') The SINGLE bit determines whether the CAPTURE_VIRTEX2 primitive operates in one-shot mode or in continuous sample mode. This bit is set when the "one-shot" attribute is attached to the CAPTURE_VIRTEX2 primitive (see Readback Capture, page 382). 0: SINGLE mode disabled. In this mode, capture values are loaded on every clock cycle while CAP is asserted. 1: SINGLE mode enabled. In this mode, capture values are loaded only once, regardless of how many clock cycles the CAP signal is asserted for. Selects the CCLK frequency for Master configuration modes (see Table 4-29). Startup sequence clock source: 00: CCLK 01: UserClk (per connection on the CAPTURE_VIRTEX2 block) 1x: JTAGClk
SINGLE
23
OSCFSEL
22:17
SSCLKSRC
16:15
352
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Configuration Options Register Description (Continued) Bit Index Description Startup cycle to release the DONE pin: 000: 001: 010: 011: 100: 101: Startup cycle 1 Startup cycle 2 Startup cycle 3 Startup cycle 4 Startup cycle 5 Startup cycle 6 Startup cycle 0 Startup cycle 1 Startup cycle 2 Startup cycle 3 Startup cycle 4 Startup cycle 5 Startup cycle 6 No Wait Startup cycle 0 Startup cycle 1 Startup cycle 2 Startup cycle 3 Startup cycle 4 Startup cycle 5 Startup cycle 6 No Wait
DONE_CYCLE
14:12
Startup cycle to stall in until DCI matches: 000: 001: 010: 011: 100: 101: 110: 111:
MATCH_CYCLE
11:9
Startup cycle to stall in until DCMs lock: 000: 001: 010: 011: 100: 101: 110: 111:
LOCK_CYCLE
8:6
Startup cycle to deassert the Global Three-State (GTS) signal: GTS_CYCLE 5:3 000: 001: 010: 011: 100: 101: Startup cycle 1 Startup cycle 2 Startup cycle 3 Startup cycle 4 Startup cycle 5 Startup cycle 6
Startup phase to deassert the Global Write Enable (GWE) signal: GWE_CYCLE 2:0 000: 001: 010: 011: 100: 101: Startup cycle 1 Startup cycle 2 Startup cycle 3 Startup cycle 4 Startup cycle 5 Startup cycle 6
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
353
Chapter 4: Configuration
OSCFSEL-Specified Master CCLK Settings OSCFSEL (binary) 000010 010001 000100 000101 000110 000111 CCLK (MHz) 13 15 20 26 30 34 OSCFSEL (binary) 001010 001101 010111 011010 011101 110010 CCLK (MHz) 41 45 51 55 60 OSCFSEL (binary) 100111 110011 101010 110100 101101
354
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Example Packets for Bitstream Compression Using MFWR (Continued) Configuration Data (hex) 30002001 Explanation Type 1 write 1 words to FAR FAR Address = 0x00000200 Type 1 write 1 words to CMD MFWR command Type 1 write 2 words to MFWR packet data write MFWR word 0 packet data write MFWR word 1 Type 1 write 1 words to FAR FAR Address = 0x00000400 Type 1 write 2 words to MFWR packet data write MFWR word 0 packet data write MFWR word 1
4 00000200 30008001 5 00000002 30014002 6 00000000 00000000 30002001 7 00000400 30014002 8 00000000 00000000
Since configuration frames are arranged vertically, designs that span the fewest possible configuration frames achieve greater compression. Identical frames are usually found in Block RAM columns that are initialized with identical values or in unused CLB or Block RAM columns. To estimate the amount of compression achieved: Identify the number of identical CLB or BRAM columns. CLB columns are only identical if they are unused and have no routing passing through them. BRAM columns are identical if the same initialization values are used for multiple BRAM columns. Calculate the number of configuration frames for the column type of interest: # config frames = (# frames per column) x (# of columns) The number of saved configuration frames is given by: #Saved configuration frames = (#identical frames 1). A rough estimate of the number of saved configuration bits is therefore given by: #Saved configuration bits = (# of saved configuration frames) x (# of bits per frame)
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
355
Chapter 4: Configuration
Device ID (IDCODE)
The Device ID (IDCODE) Register contains the device-specific identification code. This register is separate from the JTAG IDCODE register although it uses the same 32-bit identification code. The purpose of this register is to ensure that the bitstream has been created for the correct device. After writing to the IDCODE register the value is automatically compared; if it does not match the expected IDCODE value the ID_ERROR signal is asserted, halting configuration. This prevents a Virtex-II or Virtex-II Pro bitstream that is targeted for one device from successfully programming a different Virtex-II or Virtex-II Pro devicefor example, an XC2VP2 bitstream is prevented from programming an XC2VP4 device by this mechanism. A successful write to the Device ID register is required prior to writing frame data. Table 4-31 lists Virtex-II Pro IDCODEs. Table 4-31: Device XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 Virtex-II Pro IDCODEs IDCODE 0x01226093 0x0123E093 0x0124A093 0x01266093 0x01866093 0x0127E093 Device XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 IDCODE 0x01292093 0x0129E093 0x012BA093 0x018BA093 0x012D6093
Configuration
Configuration can begin after the device is powered and initialization has finished, as indicated by the INIT pin being released. After initialization, the packet processor ignores all data presented on the configuration interface until it receives the synchronization word; after synchronization the packet processor waits for a valid packet header to begin the configuration process.
356
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
2. 3.
5. 6.
7.
8.
9.
10. Write configuration frame data to FDRI, including 1 frame of pad data. One frame of pad data must follow the frame data write to flush the frame buffer, as explained in Frame Data Input Register (FDRI) and Frame Data Output Register (FDRO), page 346. For full configuration, the length of the FDRI write is given by: #FDRI Words = (#frames + 1 pad frame) x (frame length in words) After the last frame of data is sent to the device, a frame of pad data is sent in the same FDRI write to push the last data frame from the Frame Buffer to the FDRI register. This pad frame is included in the packet header word count. The data content of the pad frame does not matter. After the FDRI write finishes, the next 32-bit word is interpreted by the device as an AutoCRC value. The AutoCRC value is not included in the packet word count. 11. Write the GRESTORE command to the CMD register. GRESTORE command updates all slice and IOB registers with their initial values. 12. Write the Last Frame (LFRM) command to the CMD register. The LFRM command deasserts the internal GHIGH signal, activating all interconnect. The GHIGH signal is first activated during initialization (i.e., after the PROG pin is pulsed), and remains activated until the LFRM command is issued.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
357
Chapter 4: Configuration
13. Send START command to bring device into startup sequence. The START command begins the startup sequence for SelectMAP and Serial configuration modes, using the CCLK or USRCLK signal to clock the sequence. For JTAG the JTAG JSTART instruction must be issued so that the JTAG TCK clocks the startup sequence. 14. Write to Control Register. See Control Register (CTL), page 348 for more information. 15. Perform final CRC check. A CRC value is always created, even if CRC checking is disabled in Bitgen. When CRC checking is disabled, the default CRC value of 0x0000DEFC is written to the CRC register. 16. Send DESYNCH command. The DESYNCH command "desynchronizes" the configuration logic. Further configuration data are ignored until a new synchronization word is received. 17. Write at least 64 bits of pad data (NOOP commands) to flush packet buffer. The packet buffer must be flushed with 64 bits of packet data. For this sequence of commands, the pad bits push the DESYNCH command into the packet processor. 18. Continue sending CCLK or TCK pulses until DONE goes High. Depending on the startup options and external conditions (for example, if the DONE pin is held Low externally), additional CCLK pulses might be needed to bring the device out of the startup sequence. Refer to Configuring Through Boundary-Scan, page 329 for further details on using this procedure with the JTAG configuration interface. Each of these steps is performed by a single configuration packet except for synchronization (step 1) and the large FDRI write (step 10), which is performed by a Type 1, Type 2 packet combination. Table 4-32 shows how the default configuration steps are written in an XC2VP7 bitstream. Table 4-32: Step 1 2 00000007 30016001 3 00000069 30012001 4 XXXXXXXX 3001C001 5 0124A093 3000C001 6 XXXXXXXX 30008001 7 00000009 Default XC2VP7 Bitstream for Initial Configuration Configuration Data (hex) AA995566 30008001 Sync word Type 1 write 1 words to CMD RCRC command Type 1 write 1 words to FLR Frame Length = 105 words (actual XC2VP7 frame length 1 = 105 words = 0x69) Type 1 write 1 words to COR COR settings (dependent on user options) Type 1 write 1 words to ID Device ID = 0x0124A093 (XC2VP7) Type 1 write 1 words to MASK CTL Register MASK (dependent on user options) Type 1 write 1 words to CMD SWITCH command Explanation
358
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Default XC2VP7 Bitstream for Initial Configuration (Continued) Configuration Data (hex) 30002001 Explanation Type 1 write 1 words to FAR FAR Address= 0x00000000 Type 1 write 1 words to CMD WCFG command Type 1 write 0 words to FDRI Type 2 write 140026 words to FDRI: (1320 frames + 1) x (106 words per frame) = 140026 words Packet data write FDRI word 0
8 00000000 30008001 9 00000001 30004000 500222FA 10 00100000 ... 00000000 XXXXXXXX 30008001 11 0000000A 30008001 12 00000003 30008001 13 00000005 3000A001 14 XXXXXXXX 30000001 15 XXXXXXXX 30008001 16 0000000D 20000000 17 20000000 18 XXXXXXXX
Packet data write FDRI word 140025 Auto CRC word (design dependent) Type 1 write 1 words to CMD GRESTORE command Type 1 write 1 words to CMD LFRM command Type 1 write 1 words to CMD START command Type 1 write 1 words to CTL CTL settings (dependent on user options) Type 1 write 1 words to CRC CRC (design dependent) Type 1 write 1 words to CMD DESYNCH command Type 1 NOOP word 0 Type 1 NOOP word 1 Continue sending CCLK or TCK pulses until DONE goes High.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
359
Chapter 4: Configuration
Since the user design continues to operate during active reconfiguration, this style of reconfiguration must be used with caution. Internal contention can occur if a device is overwritten with a new design through active reconfiguration, potentially damaging the device. Furthermore, all SRL16, Distributed RAM, and BlockRAM contents are reinitialized by a full bitstream, clearing any data written into these memory elements by the user design. To bring the device into the Shutdown state through the SelectMAP interface, the configuration logic is synchronized and the SHUTDOWN command is written to the CMD register (Table 4-33). To bring the device into the Shutdown state through the JTAG interface, the JTAG JSHUTDOWN command is issued and the TAP controller is brought to the RTI state for 12 TCK cycles. The Shutdown sequence runs the startup sequence in reverse: Deassert EOS Pull the DONE pin Low Assert GTS, placing all I/Os in a high-Z state (except for persistent conrfiguration pins) De-assert GWE, preventing RAMs and flip-flops from changing state
Neither the start-up sequence nor the shutdown sequence can finish if the CRC_ERROR signal is asserted. To ensure the shutdown sequence completes successfully, it should always be preceded by the RCRC (Reset CRC) command. To bring a device out of the shutdown state, the device must be brought through the startup sequence. Table 4-33: SelectMAP Shutdown Sequence Explanation Type 1 write 1 words to CMD SHUTDOWN command
JTAG Shutdown Sequence (XC2VP2, XC2VP4, or XC2VP7 Description Set and Hold TDI X X X X 111001101 1 X X TMS 1 0 1 0 0 1 1 0 # of Clocks TCK 5 1 2 2 9 1 1 12
Clock five 1s on TMS to bring the device to the TLR state Move into the RTI state Move into the Select-IR state Move into the Shift-IR State Shift the first 9 bits of the JSHUTDOWN instruction, LSB first Shift the MSB of the JSHUTDOWN instruction while exiting SHIFT-IR Move into the Update-IR State Move into the RTI state; remain there for 12 TCK cycles
360
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The procedure for shutdown reconfiguration is identical to the "default" configuration sequence described above, except that the SHUTDOWN command is issued to the device immediately after synchronization.
10. Write WCFG command to CMD register 11. Write configuration frame data to FDRI, including 1 frame of pad data 12. Write the GRESTORE command to the CMD register 13. Write Last Frame (LFRM) command 14. Write START command to CMD register to begin startup sequence 15. Perform final CRC check 16. Write DESYNCH command to CMD register 17. Write at least 64 bits of pad data (NOOP commands) to flush packet buffer 18. Continue sending CCLK pulses until DONE goes High
Partial Reconfiguration
Virtex-II Pro devices allow partial reconfigurationrewriting a subset of configuration frames, either while user design is suspended ("Shutdown" partial reconfiguration) or while the user design is operating ("Active" partial reconfiguration). There are two reasons to perform partial reconfiguration: To change design behavior without fully reconfiguring a device To correct memory upsets in high-radiation environments
This document addresses the needs of commercial customers wishing to change design behavior. Aerospace customers seeking more information on the use of partial reconfiguration for correcting configuration memory upsets in high-radiation environments should contact their Xilinx FAE or Sales Representative, or open a technical support Webcase at http://www.support.xilinx.com. Since Xilinx does not document the function of the configuration bits within every frame, users should combine the information in the Partial Reconfiguration Process section with one of the software flows described in the Partial Reconfiguration Applications and Software Flows section below.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
361
Chapter 4: Configuration
10. Write frame data to FDRI (packet size = # frames + 1 pad frame) 11. Write the default AutoCRC value of (0x0000DEFC) 12. Write the GRESTORE command to the CMD register. 13. Send Last Frame (LFRM) command 14. Send START command to bring device into startup sequence 15. Perform final CRC check 16. Send DESYNCH command 17. Send at least 64 bits of pad data to flush packet buffer 18. Continue sending CCLKs pulses until DONE goes High
10. Write default CRC value (0x0000DEFC) 11. Write DESYNCH command 12. Write two NOOP words (0x20000000) to flush packet buffer
362
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Consecutive frames of configuration frame data can be written to FDRI in a single packet (step 10 in the Shutdown Partial Reconfiguration process; step 7 in the Active Reconfiguration process), since the FAR automatically increments when each frame is written to configuration memory. In some cases, it is necessary to write to non-consecutive frames; in such instances, the new frame address must be explicitly written to the FAR and steps 8-11 repeated. As always, one frame of pad data must be included at the end of every FDRI packet, and the word following each FDRI packet is interpreted as an AutoCRC. The precautions that apply to full active reconfiguration (see Active and Shutdown Reconfiguration, page 359) also apply to partial active reconfiguration. Table 4-35 shows the configuration packets needed to actively reconfigure a single frame on an XC2VP7 device. Table 4-35: Step 1 2 Active Partial Reconfiguration for a Single XC2VP7 Frame Configuration Data AA995566 30008001 00000007 3001C001 0124A093 30016001 00000069 30008001 00000001 30002001 XXXXXXXX 300040D4 ... 8 9 10 0000DEFC 30008001 00000007 30000001 0000DEFC 30008001 0000000D 00000002 00000002 Default AUTOCRC value Write to CMD RCRC Type 1 write 1 words to CRC CRC = 0x0000DEFC (Default value) Write to CMD Desync command NOOP NOOP Sync Word Write to CMD RCRC Write to IDCODE register Device ID Write to FLR Frame Length Write to CMD WCFG Write to FAR Frame address Write 212 words to FDRI ( 2 x 106 words per frame) Explanation
3 4 5
11 12
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
363
Chapter 4: Configuration
Modular Design
The Modular Design flow for partial reconfiguration, also described in Xilinx Application Note XAPP290, is intended for partially reconfiguring larger design changes into a system. The flow provides for a static, non-reconfigurable design area and a dynamic, reconfigurable area that can be partially reconfigured with two or more partial reconfiguration modules.
PartialMask
The Bitgen "PartialMask" feature allows users to pick which configuration columns are included in an active reconfiguration bitstream. PartialMask bitstreams are intended only for active partial reconfiguration, and must be used with the -g activereconfig:yes Bitgen switch. Bitstreams that are created using this flow cannot be used for initial configuration, since they do not include the START command or allow for the startup sequence. Per the Development System Reference Guide, there are six PartialMask settings: PartialGCLK. Adds the center global clock column to the list of columns written to a partial bitstream. Equivalent to the PartialMask0:1 setting. PartialLeft. Adds all columns on the left side of the device, excluding the global clock column, to the list of columns written to a partial bitstream. PartialRight. Adds all columns on the right side of the device, excluding the global clock column, to the list of columns written to a partial bitstream. PartialMask0 <mask>. Adds columns in BA0 (Block Address 0: GCLK, IOB, IOI, and CLB columns) as indicated by the hexadecimal mask to the list of columns written to a partial bitstream. PartialMask1 <mask>. Adds columns in BA1 (BRAM columns) as indicated by the hexadecimal mask to the list of columns written to a partial bitstream. PartialMask2 <mask>. Adds columns in BA2 (BRAM Interconnect columns) as indicated by the hexadecimal mask to the list of columns written to a partial bitstream.
364
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
For the PartialMaskN settings, <mask> is a hexadecimal string that indicates which columns within a memory block are included in the partial bitstream. The bits in the hex string map to configuration columns; each '1' indicates a column that is included in the partial bitstream, while each '0' indicates a column that is excluded from the partial bitstream. Nibbles are rounded out by appending '0's to the bit positions that do not have corresponding configuration columns. Figure 4-40 illustrates the mapping between the <mask> bit positions and the configuration columns.
BRAM INT BRAM INT
BRAM
CLB
CLB
CLB
CLB
IOB
BA MJA
0 0 0 0 0 0
0 0 0
IOB
IOI
IOI
Column Type
BRAM
GCLK
0 1 2 3 4 5 n n n 0 m 0 m + + + 2 3 4
Par tialmask0
Par tialmask1
b[0]
b[m]
Par tialmask2
ug002_c3_037_030405
Figure 4-40:
Two examples follow for deriving masks for a XC2V40 Virtex-II device. (The procedure is identical for Virtex-II Pro devices.) The XC2V40 device has 8 CLB columns, 2 BlockRAM columns, and 2 BlockRAM Interconnect columns. PartialMask Example 1: All columns included in bitstream except BRAM columns. To include all columns in BA0 and BA1, the <mask> for PartialMask0 and PartialMask1is created using '1's for all BA0 and BA1 columns. To exclude all columns in BA2, the <mask> for PartialMask2 is all '0's. Figure 4-41 shows how the <mask> values are derived.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
b[0]
365
Chapter 4: Configuration
CLB 1
CLB 2
CLB 3
CLB 4
CLB 5
CLB 6
CLB 7
CLB 8
GCLK
IOB
Figure 4-41:
To generate a partial bitstream for Example 1, use the command line: bitgen -g ActiveReconfig:Yes -g PartialMask0:1FFF -g PartialMask1:0 -g PartialMask2:3 <design>.ncd PartialMask Example 2: Only BRAM columns included in bitstream. To exclude all columns in BA0 and BA1, the <mask> for PartialMask0 and PartialMask1is all '0's. To include all columns in BA2, the <mask> for PartialMask2 is all '1's. Figure 4-42 shows how the <mask> values are derived.
XC2V40 BA0 Column Map
NO COL NO COL CLB 1 CLB 2 CLB 3 CLB 4 CLB 5 CLB 6 CLB 7 CLB 8 GCLK
IOB
Figure 4-42:
To generate a partial bitstream for Example 2, use the command line: bitgen -g ActiveReconfig:Yes -g PartialMask0:0000 -g PartialMask1:3 -g PartialMask2:0 <design>.ncd
366
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
IOB
IOI
IOI
IOB
IOI
IOI
BlockRAM "Savedata"
Writes to Virtex-II Pro BlockRAMs during shutdown reconfiguration can be disabled by setting the BlockRAM "Savedata" option in the original configuration bitstream. The Savedata option is enabled using FPGA Editor, as described in Xilinx Application Note XAPP290. The Savedata option is not intended for use during active reconfiguration, as it can interfere with BlockRAM operation. The Savedata option is safe to use with Shutdown reconfiguration.
Readback
Virtex-II Pro devices allow users to read configuration memory through the SelectMAP or JTAG interface. There are two styles of readback: Readback Verify and Readback Capture. During Readback Verify, the user reads all configuration memory cells, including the current values on all user memory elements (LUT RAM, SRL16, and BlockRAM). Readback Capture is a superset of Readback Verify: in addition to reading all configuration memory cells, the current state of all internal CLB and IOB registers is read, which can be useful for design debugging. Readback is possible while the FPGA design is active or in a shutdown state, although users are advised to avoid active readback because it can corrupt BlockRAM, Distributed RAM, and SRL16 contents. During active readback, the user design continues to operate while configuration memory are being read. To read configuration memory, users must send a sequence of commands to the device, indicating the starting configuration memory readback address and the number of words to be read from memory. Once initiated, the device sends the specified memory contents to the SelectMAP or JTAG interface. The following sections describe the steps for reading configuration memory: Configuration Memory Read Procedure (SelectMAP), page 369 Configuration Memory Read Procedure (1149.1 JTAG), page 374 Configuration Memory Read Procedure (1532 JTAG), page 378
Users can send the readback command sequence from a microprocessor, CPLD, or FPGAbased system, or use iMPACT to perform JTAG-based readback verify. iMPACT, the device programming software provided with the Xilinx Integrated Software Environment (ISE), can perform all readback and comparison functions for Virtex-II devices and report to the user whether there were any configuration errors. iMPACT cannot, however, perform capture operations, although Readback Capture is seldom used for design debugging since Chipscope ILA, sold separately through the Xilinx website, provides superior design debugging functionality in a user-friendly interface. See Using ChipScope ILA, page 383 for more information. Once configuration memory has been read from the device, the next step is to determine if there are any errors by comparing the readback bitstream to the configuration bitstream. An explanation of how this is done can be found in Verifying Readback Data, page 379.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
367
Chapter 4: Configuration
precluding further configuration operations. Beyond these security and encryption requirements, no special considerations are necessary to enable readback through the Boundary-Scan port. If capture functionality is needed, the CAPTURE_VIRTEX2 primitive must be instantiated in the user design (Figure 4-48, page 382). To capture the state of user registers, the user design triggers the CAP input on this primitive, storing the current register values in configuration memory. The register values are later read out of the device along with all other configuration memory. See Readback Capture, page 382 for more information.
Explanation
The user must change the SelectMAP interface from write to read control between steps 3 and 4, and back to write control after step 4, as illustrated in Figure 4-43.
368
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
CS_B
RDWR_B
WRITE: D[0:7] ARE INPUTS READ: D[0:7] ARE OUTPUTS WRITE
HI-Z
D[0:7]
HI-Z
A A 9 9 5 5 6 6 2 8 0 0 E 0 0
HI-Z
X S S
S X
0 0
HI-Z
CCLK BUSY
HI-Z HI-Z HI-Z HI-Z
UG071_49_012805
Figure 4-43:
To read registers other than STAT, the address specified in the Type 1 packet header in Step 2 of Table 4-36 should be modified and the word count changed if necessary. Reading from the FDRO register is a special case that is described in the procedure below.
10. Write the START command. 11. Write the RCRC command. 12. Write the DESYNCH command. 13. Write at least 64 bits of NOOP commands to flush the packet buffer. Continue sending CCLK pulses until DONE goes High.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
369
Chapter 4: Configuration
Each of these steps is performed by a single configuration packet except for synchronization (step 1) and the large FDRO read (step 7), which is performed by a Type 1, Type 2 packet combination. For active readback, step 2, step 4, and step 10 are omitted. Remember that BRAM frames and CLB frames that contain SRL16s or Distributed RAM must not be read back actively. In practice, active readback of the CLB frames should stop at the second-to-last CLB frame, since reading back the last CLB frame will cause the FAR to increment into the first BRAM frame, corrupting the BRAM contents. Table 4-37 shows the readback command sequence. Table 4-37: Shutdown Readback Command Sequence (SelectMAP), XC2VP7 Device Step
1 2
Explanation
Type 1 write 1 words to CMD SHUTDOWN command Type 1 write 1 words to CMD RCRC command Type 1 NOOP word 0 Type 1 NOOP word 1 Type 1 NOOP word 2 Type 1 NOOP word 3 Type 1 write 1 words to FAR FAR address= 0x00000000 Type 1 write 1 words to CMD RCFG command Type 1 read 0 words from FDRO Type 2 read 140026 words from active register (FDRO) Type 1 NOOP word 0 Type 1 NOOP word 1 packet data read FDRO word 0
Read Read
Packet data read FDRO word 140025 Type 1 write 1 words to CMD START command Type 1 write 1 words to CMD RCRC command Type 1 write 1 words to CMD DESYNCH command Type 1 NOOP word 0 Type 1 NOOP word 1
10
11
12
13
370
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
TMS
1 0 1 0
# of Clocks (TCK)
5 1 2 2
Shift the first 9 bits of the CFG_IN or CFG_OUT instruction, LSB first
6 7 8 9 10 11 Notes:
Shift the MSB of the CFG_IN or CFG_OUT instruction while exiting SHIFT-IR Move into the SELECT-DR state Move into the SHIFT-DR state Shift data into the CFG_IN register or out of the CFG_OUT register while in SHIFT_DR, MSB first. Shift the LSB while exiting SHIFT-DR Reset the TAP by clocking five 1's on TMS
1. The JTAG instruction opcodes given in this table are for XC2VP2 through XC2VP7 devices. Other Virtex-II Pro devices have larger instruction registers, so the Instruction Opcodes for these devices must be modified. See Boundary-Scan Instruction Set, page 322 for more information, or refer to the appropriate device BSDL file.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
371
Chapter 4: Configuration
1. 2.
Reset the TAP controller. Shift the CFG_IN instruction into the JTAG Instruction Register through the SHIFT-IR state. The LSB of the CFG_IN instruction is shifted first; the MSB is shifted while moving the TAP controller out of the SHIFT-IR state. Shift packet write commands into the CFG_IN register through the SHIFT-DR state: a. b. c. Write the Synchronization word to the device. Write the "Read STAT register" packet header to the device. Write exactly three pad words to the device to flush the packet buffer.
3.
The MSB of all configuration packets sent through the CFG_IN register must be sent first; the LSB is shifted while moving the TAP controller out of the SHIFT-DR state. Note that this is the opposite of how JTAG instructions are shifted into the JTAG Instruction Register. Since an odd number of words (1) is sent to the device for this JTAG read operation, it must end with exactly three pad words. This is because all JTAG read command sequences must consist of an even number of words (see Packet Processor, page 343 for details). 4. Shift the CFG_OUT instruction into the JTAG Instruction Register through the Shift-IR state. The LSB of the CFG_OUT instruction is shifted first; the MSB is shifted while moving the TAP controller out of the SHIFT-IR state. Shift 32 bits out of the Status register through the SHIFT-DR state. Shift the CFG_IN instruction into the JTAG Instruction Register through the Shift-IR state. Shift packet write commands into the CFG_IN register through the Shift-DR state: a. b. c. 8. Write the Write to CMD register packet header to the device. Write the DESYNCH command to the device. Write two pad words to the device to flush the packet processor.
5. 6. 7.
Reset the TAP controller. The device is desynchronized when the TAP controller moves into the Test-Logic-Reset state.
Table 4-39: Status Register Readback Command Sequence (JTAG), XC2VP2 through XC2VP7 Devices Set and Hold Step Description
Clock five 1s on TMS to bring the device to the TLR state. 1 Move into the RTI state. Move into the SELECT-IR state. Move into the SHIFT-IR state. Shift the first 9 bits of the CFG_IN instruction, LSB first. 2 Shift the MSB of the CFG_IN instruction while exiting the SHIFT-IR state. Move into the SELECT-DR state. Move into the SHIFT-DR state.
TDI
X X X X 111000101 (CFG_IN) 1 X X
TMS
1 0 1 0 0 1 1 0
# of Clocks (TCK)
5 1 2 2 9 1 2 2
372
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 4-39: Status Register Readback Command Sequence (JTAG), XC2VP2 through XC2VP7 Devices (Continued) Set and Hold Step Description TDI
a: 0xAA995566 b: 0x2800E001 c: 0x20000000 0x20000000 0x20000000 0 X X 111000100 (CFG_OUT) 1 X X 0xSSSSSSSS
TMS
# of Clocks (TCK)
Shift configuration packets into the CFG_IN data register, MSB first. 3
159
Shift the LSB of the last configuration packet while exiting the SHIFT-DR state. Move into the SELECT-IR state. Move into the SHIFT-IR state. Shift the first 9 bits of the CFG_OUT instruction, LSB first.
1 1 0 0 1 1 0 0
1 3 2 9 1 2 2 31
Shift the MSB of the CFG_OUT instruction while exiting the SHIFT-IR state. Move into the SELECT-DR state. Move into the SHIFT-DR state. Shift the contents of the STAT register out of the CFG_OUT data register.
Shift the last bit of the STAT register out of the CFG_OUT data register while exiting the SHIFT-DR state. Move into the SELECT-IR state. Move into the SHIFT-IR State. Shift the first 5 bits of the CFG_IN instruction, LSB first
1 1 0 0 1 1 0
1 3 2 9 1 2 2
Shift the MSB of the CFG_IN instruction while exiting SHIFT-IR Move into the SELECT-DR state Move into the SHIFT-DR state Shift configuration packets into the CFG_IN data register, MSB first. Shift the LSB of the last configuration packet while exiting SHIFT-DR
127
8 Notes:
Reset the TAP Controller. The device is desynchronized when the TAP controller moves into the Test-Logic-Reset state.
1. The JTAG instruction opcodes given in this table are for XC2VP2 through XC2VP7 devices. Other Virtex-II Pro devices have larger instruction registers, so the instruction opcodes for these devices must be modified. See Boundary-Scan Instruction Set, page 322 for more information, or refer to the appropriate device BSDL file.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
373
Chapter 4: Configuration
The packets shifted in to the JTAG CFG_IN register are identical to the packets shifted in through the SelectMAP interface when reading the STAT register through SelectMAP.
5.
d. Write the "Write FAR register" Type 1 packet header to the device.
h. Write the "Read FDRO register" Type 1 packet header to the device. The FDRO read length is given by: FDRO Read Length = (words per frame) x (frames to read +1) One extra frame is read to account for the frame buffer, which produced one pad frame at the beginning of the read. i. j. Write a Type 2 packet header to indicate the number of words to read from the device. Write exactly two pad words to the device to flush the packet buffer.
The MSB of all configuration packets sent through the CFG_IN register must be sent first. The LSB is shifted while moving the TAP controller out of the SHIFT-DR state. Since an even number of words (2) are sent to the device for this JTAG read operation, it must end with exactly two pad words. If the read operation had consisted of only a Type 1 packet header, instead of the Type 1, Type 2 packet combination that is used here, the sequence would have ended with exactly three pad words. This is because all JTAG read command sequences must consist of an even number of words (see Packet Processor, page 343 for details). 6. Shift the CFG_OUT instruction into the JTAG Instruction Register through the SHIFT-IR state. The LSB of the CFG_OUT instruction is shifted first; the MSB is shifted while moving the TAP controller out of the SHIFT-IR state. Shift frame data from the FDRO register through the SHIFT-DR state.
7.
374
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
8. 9.
Shift the CFG_IN instruction into the JTAG Instruction Register through the SHIFT-IR state. Shift packet write commands into the CFG_IN register through the SHIFT-DR state: a. b. c. e. f. g. Write a NOOP command. Write the Write to CMD register packet header to the device. Write the START command. Write the RCRC command. Write the Write to CMD register packet header to the device. Write the DESYNCH command to the device.
h. Write two pad words to the device to flush the packet processor. 10. Shift the JSTART instruction into the JTAG Instruction Register. 11. Move to the RTI state and clock the STARTUP sequence by applying a minimum of 12 TCK cycles. 12. Reset the TAP controller. Table 4-40: Shutdown Readback Command Sequence (JTAG), XC2VP2 through XC2VP7 Devices Set and Hold Step Description TDI
Clock five 1s on TMS to bring the device to the TLR state. 1 Move into the RTI state. Move into the SELECT-IR state. Move into the SHIFT-IR State. Shift the first 9 bits of the JSHUTDOWN instruction, LSB first. 2 Shift the MSB of the JSHUTDOWN instruction while exiting the SHIFT-IR state. Move into the UPDATE-IR state. Move into the RTI state; remain there for 12 TCK cycles. 3 Move into the SELECT-IR state. Move into the SHIFT-IR State. Shift the first 9 bits of the CFG_IN instruction, LSB first 4 Shift the MSB of the CFG_IN instruction while exiting SHIFT-IR Move into the SELECT-DR state Move into the SHIFT-DR state X X X X 111001101 (JSHUTDOWN) 1 X X X X 111000101 (CFG_IN) 1 X X
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
375
Chapter 4: Configuration
Table 4-40: Shutdown Readback Command Sequence (JTAG), XC2VP2 through XC2VP7 Devices (Continued) Set and Hold Step Description TDI
a: b: c: d: e: f: g: h: 0xAA995566 0x30002001 0x00000000 0x30008001 0x00000007 0x28006000 0x480222FA 0x20000000 0x20000000 0 X X 111000100 (CFG_OUT) 1 X X X
TMS
# of Clocks (TCK)
Shift configuration packets into the CFG_IN data register, MSB first 5 Shift the LSB of the last configuration packet while exiting the SHIFT-DR state Move into the SELECT-IR state Move into the SHIFT-IR state Shift the first 9 bits of the CFG_OUT instruction, LSB first 6 Shift the MSB of the CFG_OUT instruction while exiting the SHIFT-IR state. Move into the SELECT-DR state. Move into the SHIFT-DR state. Shift the contents of the FDRO register out of the CFG_OUT data register. Shift the last bit of the FDRO register out of the CFG_OUT data register while exiting the SHIFT-DR state. Move into the SELECT-IR state. Move into the SHIFT-IR state. Shift the first 9 bits of the CFG_IN instruction, LSB first. 8 Shift the MSB of the CFG_IN instruction while exiting the SHIFT-IR state. Move into the SELECT-DR state. Move into the SHIFT-DR state.
287
1 1 0 0 1 1 0 0
X X X 111000101 (CFG_IN) 1 X X
1 1 0 0 1 1 0
376
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 4-40: Shutdown Readback Command Sequence (JTAG), XC2VP2 through XC2VP7 Devices (Continued) Set and Hold Step Description TDI
a: b: c: d: e: f: g: h: 0x20000000 0x30008001 0x00000005 0x30008001 0x00000007 0x30008001 0x0000000D 0x20000000 0x20000000 0 X 111001100 (JSTART) 1 X X X
TMS
# of Clocks (TCK)
Shift configuration packets into the CFG_IN data register, MSB first. 9
287
Shift the LSB of the last configuration packet while exiting the SHIFT-DR state. Move into the UPDATE-DR state. Shift the first 9 bits of the JSTART instruction, LSB first. 10 Shift the MSB of the JSTART instruction while exiting the SHIFT-IR state. Move into the UPDATE-IR state. 11 12 Notes: Move into the RTI state; remain there for 12 TCK cycles. End by placing the TAP controller in the TLR state.
1 1 0 1 1 0 1
1 1 9 1 1 12 5
1. The JTAG instruction opcodes given in this table are for XC2VP2 through XC2VP7 devices. Other Virtex-II Pro devices have larger instruction registers, so the Instruction Opcodes for these devices must be modified. See Boundary-Scan Instruction Set, page 322 for more information, or refer to the appropriate device BSDL file.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
377
Chapter 4: Configuration
START
Load ISC_ENABLE
Load ISC_READ
Load ISC_PROGRAM RTI 1 TCK cycles Load Reset CRC command No End of bitstream Yes A Load ISC_DISABLE
Go to Test-Logic-Reset
STOP
UG002_c4_39_102004
Figure 4-44:
378
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Readback Files
The Xilinx Bitstream Generator can produce several files to assist the user in reading and comparing configuration memory. These files are described in Table 4-41. Table 4-41: File Ext. Readback Files BitGen Setting
-b readback -g readback
File Type
Description
An ASCII file that contains readback commands, rather than configuration commands, and expected readback data where the configuration data would normally be. This file must be used with the .msk file Binary version of .rba file. This file must be used with the .msk file. An ASCII file that contains only expected readback data, including the initial pad frame. No commands are included. This file must be used with the .msd file. A binary file that contains the same configuration commands as a .bit file, but replaces the contents of the FDRI write packet with mask data that indicate whether the corresponding bits in the .bit file should be compared. If a mask bit is 0, the corresponding bits in the readback data stream should be compared. If a mask bit is 1, the corresponding bit in the readback data stream should be ignored. An ASCII file that contains only mask bits. The first bit in the .msd file corresponds to the first bit in the .rbd file. Pad data in the actual readback stream are accounted for in the .msd and .rbd files. If a mask bit is 0, that bit should be verified against the bit stream data. If a mask bit is 1, that bit should not be verified. An ASCII file that contains information on each of the nodes in the design that can be captured for readback. The file contains the absolute bit position in the readback stream, frame address, frame offset, logic resource used, and name of the component in the design.
.rba
ASCII
.rbb
Binary
-g readback
.rbd
ASCII
-g readback
.msk
Binary
-m
.msd
ASCII
-g readback
.ll
ASCII
-l
The design.rba and design.rbb files combine readback commands with expected readback data, whereas the .rbd file contains only expected readback data. Systems that use a .rbd file for readback must store readback commands elsewhere. The actual readback data must be masked against a .msk or .msd mask file, as certain bits within the expected readback stream in the .rba, .rbb, and .rbd files should be ignored. The readback command set files do not indicate when users must change the SelectMAP or JTAG interface from write to read control; the user must handle this based on the Readback Command Sequences described above.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
379
Chapter 4: Configuration
Frame Data
UG071_51_081404
Figure 4-45:
The readback data stream is verified by comparing it to the original configuration frame data that were programmed into the device. Certain bits within the readback data stream must not be compared, however, since these might correspond to user memory or null memory locations. The location of "don't care" bits in the readback data stream is given by the mask files, the .msk and .msd files. These files have different formats although both convey essentially the same information. Once readback data have been obtained from the device, either of the following comparison procedures can be used: 1. Compare readback data to the .rbd "golden" readback file, mask using the .msd file. The simplest way to verify the readback data stream is to compare it to the .rbd "golden" readback file, masking readback bits with the .msd file. This approach is simple because there is a 1:1 correspondence between the start of the readback data stream and the start of the .rbd and .msd files, making the task of aligning readback, mask, and expected data easier.
.msd File Readback Data Stream 1 frame Pad Frame File Header Pad Frame .rbd File File Header Pad Frame
Frame Data
Frame Data
UG071_52_081404
Figure 4-46:
380
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The .rbd and .msd files contain an ASCII representation of the readback and mask data along with a file header that lists the file name, etc. This header information should be ignored or deleted. The ASCII '1s' and '0s' in the .rbd and .msd files correspond to the binary readback data from the device. Take care to interpret these files as text, not binary sources. Users might wish to convert the .rbd and .msd files to a binary format using a script or text editor, as this can simplify the verify procedure for some systems and reduce the size of the files by a factor of eight. The drawback to this approach is that in addition to storing the initial configuration bitstream and the .msd file, the golden .rbd file must be stored somewhere, increasing the overall storage requirement. 2. Compare readback data to the configuration .bit file, mask using the .msk file. Another approach for verifying readback data is to compare the readback data stream to the frame data within the FDRI write in the original configuration bitstream, masking readback bits with the .msk file. After sending readback commands to the device, comparison begins by aligning the beginning of the readback frame data to the beginning of the FDRI write in the .bit and .msk files. The comparison ends when the end of the FDRI write is reached. This approach requires the least in-system storage space, since only the .bit, .msk, and readback commands must be stored.
Readback Data Stream 1 frame Pad Frame Commands Commands .msk File File Header .bit File File Header
Frame Data
Frame Data
Figure 4-47:
The .rba and .rbb files contain expected readback data along with readback command sets. They are intended for use with the .msk file, although they are better suited to readback for Virtex devices (see Xilinx Application Note XAPP138) than for Virtex-II devices.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
381
Chapter 4: Configuration
Readback Capture
The configuration memory readback command sequence is identical for both Readback Verify and Readback Capture. However, the Capture sequence requires an additional step to sample internal register values. Users can sample CLB and IOB registers by instantiating the CAPTURE_VIRTEX2 primitive in their design (Figure 4-48) and asserting the CAP input on that primitive while the design is operating. On the next rising clock edge on the CAPTURE_VIRTEX2 CLK input, the internal GRDBK signal is asserted, storing all CLB and IOB register values into configuration memory cells. These values can then be read out of the device along with the IOB and CLB configuration columns by reading configuration memory through the readback process described above. The capture sequence causes the current register value to be stored to the same memory cell that programs the register's initial state. If the GRESTORE command is sent after the capture sequence has changed the state of this cell, the registers return to an unintended state. The capture operation can also be performed by writing the GCAPTURE command to the CMD register.
Trigger with External or Internal Signal.
CAPTURE_VIRTEX2 CAP
CLK
Synchronize to External or Internal Clock.
ug002_c4_35_091900
Figure 4-48: Virtex-II and Virtex-II Pro Library Primitive Table 4-42: Signal GCAPTURE Capture Signals Description Captures the state of all slice and IOB registers. Complement of GRESTORE. Initializes all registers as configured. Access "CAP" input on capture block, user controlled. Also CMD register via GCAPTURE command. CMD register.
GRESTORE
If the CAP signal is left asserted over multiple clock cycles, the Capture cell is updated with the new register value on each rising clock edge. To limit the capture operation to the first rising clock edge, the user can add the ONESHOT attribute to the CAPTURE_VIRTEX2 primitive. More information on the ONESHOT attribute can be found in the Constraints Guide. Once the configuration memory frames have been read out of the device, the user can pick the captured register values out of the readback data stream. The capture bit locations are given in the logic allocation file (design.ll) as described below.
382
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
UG071_55_081404
Figure 4-49:
Figure 4-49 shows a snippet from a logic allocation file for the ISE "jc2_top" example design. The line from the header comments explaining the line format has been moved to the start of the bit offset data for clarity. The <offset> field gives the absolute bit offset from the beginning of configuration memory (frame address 0x00000000). The <frame address> field gives the frame address that the capture bit is located in, and the <frame offset> field gives the bit offset from the start of the frame. The <information> field gives the mapping between the bit and the user designfor example, the "DIR" register (Figure 4-49) that is located in Slice X8Y15 is located at bit offset 100790. Note that captured DFF values, along with LUTRAM and SRL16 values, are stored in their inverted sense.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
383
Chapter 4: Configuration
384
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Chapter 5
Pinout Information
Introduction
Virtex-II Pro devices are available in the following package styles: FG256, FG456, and FG676: Wire-bond fine-pitch BGA of 1.00 mm pitch FGG256, FGG456, and FGG676: Pb-free wire-bond fine-pitch BGA of 1.00 mm pitch FF672, FF896, FF1152, FF1148, FF1517, FF1704, and FF1696: Flip-chip fine-pitch BGA of 1.00 mm pitch
Virtex-II Pro X devices are available in the following package styles: FF896 and FF1704: Flip-chip fine-pitch BGA of 1.00 mm pitch
Refer to the Virtex-II Pro and Virtex-II Pro X Platform FPGA Data Sheet for complete device specifications and all available pinout tables. All devices available in a given package are pinout-compatible, and are listed in the same pinout table. Global pins, including JTAG, configuration, and power/ground pins, are listed at the end of each pinout table. Pins that are not available for the smaller devices are listed in the "No Connects" column. Each device is split into eight I/O banks to allow for flexibility in the choice of I/O standards.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
385
Table 5-2, the FG256/FGG256 pinout table, is included in this volume as an example of the pinout tables available in the Data Sheet and on the distribution CD-ROM. Always check the online Data Sheet at www.xilinx.com for the most current technical information on this and all other Xilinx devices.
Pin Definitions
Table 5-1 provides a description of each pin type listed in Virtex-II Pro pinout tables. Table 5-1: Virtex-II Pro Pin Definitions Direction Description
Input/Output
All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled IO_LXXY_#, where: IO indicates a user I/O pin. LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for the positive and negative sides of the differential pair. # indicates the bank number (0 through 7)
Dual-Function Pins:
IO_LXXY_#/ZZZ Dual-function pins are labelled IO_LXXY_#/ ZZZ, where "ZZZ" can be one of the following pins: Per Bank - VRP, VRN, or VREF Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, D0/DIN D7, RDWR_B, or CS_B These dual functions are defined in the following section:
In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration.
INIT_B
Bidirectional (open-drain)
When Low, this pin indicates that the configuration memory is being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. The pin becomes a user I/O after configuration.
386
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 5-1:
Pin Name
GCLKx (S/P)
Description
These are clock input pins that connect to Global Clock Buffers. These pins become regular user I/Os when not needed for clocks. These pins can be used to clock the RocketIO transceiver. See the RocketIO Transceiver User Guide for design guidelines and BREFCLK-specific pins, by device.
This pin is for the DCI voltage reference resistor of P transistor (per bank). This pin is for the DCI voltage reference resistor of N transistor (per bank). These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed (per bank).
M2, M1, M0
Input
TMS PWRDWN_B
Other Pins:
DXN, DXP VBATT RSVD VCCO VCCAUX VCCINT GND N/A Input N/A Input Input Input Input Temperature-sensing diode pins (Anode: DXP, Cathode: DXN). Decryptor key memory backup supply. Connect to VCCAUX or GND if battery is not used. Reserved pin - do not connect. Power-supply pins for the output drivers (per bank). Power-supply pins for auxiliary circuits. Power-supply pins for the internal core logic. Ground.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
387
Table 5-1:
Pin Name
AVCCAUXRX# AVCCAUXTX# BREFCLKN, BREFCLKP (2) VTRXPAD# VTTXPAD# GNDA# RXPPAD# RXNPAD# TXPPAD# TXNPAD#
Description
Analog power supply for receive circuitry of the RocketIO MGT (2.5V). Analog power supply for transmit circuitry of the RocketIO MGT (2.5V). Differential clock input that clocks the RocketIO X MGTs populating the same side of the chip (top or bottom). Can also drive DCMs for RocketIO X MGT use. Receive termination supply for the RocketIO MGT (1.8V - 2.8V). Transmit termination supply for the RocketIO MGT (1.8V-2.8V). Ground for the analog circuitry of the RocketIO MGT. Positive differential receive port of the RocketIO MGT. Negative differential receive port of the RocketIO MGT. Positive differential transmit port of the RocketIO MGT. Negative differential transmit port of the RocketIO MGT.
Notes: 1. All dedicated pins (JTAG and configuration) are powered by VCCAUX (independent of the bank VCCO voltage). 2. Virtex-II Pro X devices XC2VPX20 and XC2VPX70 only. Each BREFCLK(N/P) differential clock input pair takes the place of one regular Virtex-II Pro dual-function IO/GCLKx(S/P) pair on each side of the chip (top or bottom). For RocketIO BREFCLK, see section BREFCLK Pin Definitions (RocketIO Only) immediately following.
For detailed information about using BREFCLK/BREFCLK2, including routing considerations and pin numbers for all package types, refer to Chapter 2, "Digital Design Considerations," in the RocketIO Transceiver User Guide.
388
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 5-2:
FG25/FGG2566 XC2VP2 and XC2VP4 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Description IO_L01N_0/VRP_0 IO_L01P_0/VRN_0 IO_L02N_0 IO_L02P_0 IO_L03N_0 IO_L03P_0/VREF_0 IO_L06N_0 IO_L06P_0 IO_L07P_0 IO_L09N_0 IO_L09P_0/VREF_0 IO_L69N_0 IO_L69P_0/VREF_0 IO_L74N_0/GCLK7P IO_L74P_0/GCLK6S IO_L75N_0/GCLK5P IO_L75P_0/GCLK4S Pin Number C2 C3 B3 C4 A2 A3 D5 C5 D6 E6 E7 D7 C7 D8 C8 B8 A8
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IO_L75N_1/GCLK3P IO_L75P_1/GCLK2S IO_L74N_1/GCLK1P IO_L74P_1/GCLK0S IO_L69N_1/VREF_1 IO_L69P_1 IO_L09N_1/VREF_1 IO_L09P_1 IO_L07N_1 IO_L06N_1 IO_L06P_1 IO_L03N_1/VREF_1 IO_L03P_1 IO_L02N_1 IO_L02P_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1
A9 B9 C9 D9 C10 D10 E10 E11 D11 C12 D12 A14 A15 C13 B14 C14 C15
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
389
Table 5-2:
FG25/FGG2566 XC2VP2 and XC2VP4 (Continued) Bank Pin Description Pin Number
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO_L02N_2 IO_L02P_2 IO_L03N_2 IO_L03P_2 IO_L04N_2/VREF_2 IO_L04P_2 IO_L06N_2 IO_L06P_2 IO_L85N_2 IO_L85P_2 IO_L86N_2 IO_L86P_2 IO_L88N_2/VREF_2 IO_L88P_2 IO_L90N_2 IO_L90P_2 IO_L90N_3 IO_L90P_3 IO_L89N_3 IO_L89P_3 IO_L87N_3/VREF_3 IO_L87P_3 IO_L85N_3 IO_L85P_3 IO_L06N_3 IO_L06P_3 IO_L05N_3 IO_L05P_3 IO_L03N_3/VREF_3 IO_L03P_3 IO_L02N_3
E14 E15 E13 F12 F13 F14 F15 F16 G13 G14 G15 G16 G12 H13 H14 H15 H16 J16 J15 J14 J13 K12 K16 K15 K14 K13 L16 L15 L14 L13 L12 M13 M16
390
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 5-2:
FG25/FGG2566 XC2VP2 and XC2VP4 (Continued) Bank 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Pin Description IO_L02P_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 IO_L01N_4/DOUT IO_L01P_4/INIT_B IO_L02N_4/D0 IO_L02P_4/D1 IO_L03N_4/D2 IO_L03P_4/D3 IO_L06N_4/VRP_4 IO_L06P_4/VRN_4 IO_L07P_4/VREF_4 IO_L09N_4 IO_L09P_4/VREF_4 IO_L69N_4 IO_L69P_4/VREF_4 IO_L74N_4/GCLK3S IO_L74P_4/GCLK2P IO_L75N_4/GCLK1S IO_L75P_4/GCLK0P Pin Number N16 M15 M14 P15 P14 R14 P13 T15 T14 N12 P12 N11 M11 M10 N10 P10 N9 P9 R9 T9
5 5 5 5 5 5 5 5 5 5 5 5 5
IO_L75N_5/GCLK7S IO_L75P_5/GCLK6P IO_L74N_5/GCLK5S IO_L74P_5/GCLK4P IO_L69N_5/VREF_5 IO_L69P_5 IO_L09N_5/VREF_5 IO_L09P_5 IO_L07N_5/VREF_5 IO_L06N_5/VRP_5 IO_L06P_5/VRN_5 IO_L03N_5/D4 IO_L03P_5/D5
T8 R8 P8 N8 P7 N7 M7 M6 N6 P5 N5 T3 T2
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
391
Table 5-2:
FG25/FGG2566 XC2VP2 and XC2VP4 (Continued) Bank 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 Pin Description IO_L02N_5/D6 IO_L02P_5/D7 IO_L01N_5/RDWR_B IO_L01P_5/CS_B IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 IO_L02P_6 IO_L02N_6 IO_L03P_6 IO_L03N_6/VREF_6 IO_L05P_6 IO_L05N_6 IO_L06P_6 IO_L06N_6 IO_L85P_6 IO_L85N_6 IO_L87P_6 IO_L87N_6/VREF_6 IO_L89P_6 IO_L89N_6 IO_L90P_6 IO_L90N_6 IO_L90P_7 IO_L90N_7 IO_L88P_7 IO_L88N_7/VREF_7 IO_L86P_7 IO_L86N_7 IO_L85P_7 IO_L85N_7 IO_L06P_7 IO_L06N_7 IO_L04P_7 Pin Number P4 R3 P3 P2 M3 M2 N1 M1 M4 L5 L4 L3 L2 L1 K4 K3 K2 K1 K5 J4 J3 J2 J1 H1 H2 H3 H4 G5 G1 G2 G3 G4 F1
392
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 5-2:
FG25/FGG2566 XC2VP2 and XC2VP4 (Continued) Bank 7 7 7 7 7 7 7 0 0 0 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 N/A N/A Pin Description IO_L04N_7/VREF_7 IO_L03P_7 IO_L03N_7 IO_L02P_7 IO_L02N_7 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_7 VCCO_7 VCCO_7 CCLK PROG_B Pin Number F2 F3 F4 F5 E4 E2 E3 F8 F7 E8 F9 F10 E9 H12 H11 G11 K11 J12 J11 M9 L9 L10 M8 L8 L7 K6 J6 J5 H6 H5 G6 N15 D1
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
393
Table 5-2:
FG25/FGG2566 XC2VP2 and XC2VP4 (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description DONE M0 M1 M2 TCK TDI TDO TMS PWRDWN_B HSWAP_EN RSVD VBATT DXP DXN AVCCAUXTX6 VTTXPAD6 TXNPAD6 TXPPAD6 GNDA6 GNDA6 RXPPAD6 RXNPAD6 VTRXPAD6 AVCCAUXRX6 AVCCAUXTX7 VTTXPAD7 TXNPAD7 TXPPAD7 GNDA7 GNDA7 RXPPAD7 RXNPAD7 VTRXPAD7 AVCCAUXRX7 AVCCAUXRX18 Pin Number P16 N3 N2 P1 D16 E1 E16 C16 N14 C1 D14 D15 D2 D3 B5 B4 A4 A5 C6 C6 A6 A7 B6 B7 B11 B10 A10 A11 C11 C11 A12 A13 B12 B13 R13
394
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Table 5-2:
FG25/FGG2566 XC2VP2 and XC2VP4 (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description VTRXPAD18 RXNPAD18 RXPPAD18 GNDA18 GNDA18 TXPPAD18 TXNPAD18 VTTXPAD18 AVCCAUXTX18 AVCCAUXRX19 VTRXPAD19 RXNPAD19 RXPPAD19 GNDA19 GNDA19 TXPPAD19 TXNPAD19 VTTXPAD19 AVCCAUXTX19 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND Pin Number R12 T13 T12 P11 P11 T11 T10 R10 R11 R7 R6 T7 T6 P6 P6 T5 T4 R4 R5 N4 N13 M5 M12 E5 E12 D4 D13 R16 R1 B16 B1 T16 T1 R2
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
395
Table 5-2:
FG25/FGG2566 XC2VP2 and XC2VP4 (Continued) Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pin Description GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number R15 L6 L11 K9 K8 K7 K10 J9 J8 J7 J10 H9 H8 H7 H10 G9 G8 G7 G10 F6 F11 B2 B15 A16 A1
396
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Pinout Diagrams
This section contains pinout diagrams for all Virtex-II Pro package/device combinations: FG256/FGG256 Fine-Pitch BGA Pinout Diagrams
FG256/FGG256 Composite Pinout Diagram (XC2VP2, XC2VP4), page 399 FG256/FGG256 Banked Pins (XC2VP2, XC2VP4), page 400 FG256/FGG256 Dedicated/Other Pins (XC2VP2, XC2VP4), page 401 FG456/FGG456 Composite Pinout Diagram (XC2VP7), page 403 FG456/FGG456 Dedicated/Other Pins (XC2VP7), page 404 FG456/FGG456 Composite Pinout Diagram (XC2VP4), page 405 FG456/FGG456 Banked Pins (XC2VP4, XC2VP7), page 406 FG456/FGG456 Composite Pinout Diagram (XC2VP2), page 407 FG456/FGG456 Banked Pins (XC2VP2), page 408 FG456/FGG456 Dedicated/Other Pins (XC2VP2, XC2VP4, page 409 FG676/FGG676 Composite Pinout Diagram (XC2VP30, XC2VP40), page 411 FG676/FGG676 Banked Pins (XC2VP30, XC2VP40), page 412 FG676/FGG676 Composite Pinout Diagram (XC2VP20), page 413 FG676/FGG676 Banked Pins (XC2VP20), page 414 FG676/FGG676 Dedicated/Other Pins (XC2VP20, XC2VP30, XC2VP40), page 415 FF672 Composite Pinout Diagram (XC2VP7), page 417 FF672 Banked Pins (XC2VP7), page 418 FF672 Dedicated/Other Pins (XC2VP7), page 419 FF672 Composite Pinout Diagram (XC2VP4), page 420 FF672 Banked Pins (XC2VP4), page 421 FF672 Composite Pinout Diagram (XC2VP2), page 422 FF672 Banked Pins (XC2VP2), page 423 FF672 Dedicated/Other Pins (XC2VP2, XC2VP4), page 424 FF896 Composite Pinout Diagram (XC2VP20, XC2VP30), page 425 FF896 Banked Pins (XC2VP20, XC2VP30), page 426 FF896 Composite Pinout Diagram (XC2VP7), page 427 FF896 Banked Pins (XC2VP7), page 428 FF896 Dedicated/Other Pins (XC2VP7, XC2VP20, XC2VP30), page 429 FF896 Composite Pinout Diagram (XC2VPX20), page 430 FF896 Banked Pins (XC2VPX20), page 431 FF896 Dedicated/Other Pins (XC2VPX20), page 432
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
397
FF1152 Composite Pinout Diagram (XC2VP50), page 433 FF1152 Dedicated/Other Pins (XC2VP50), page 434 FF1152 Composite Pinout Diagram (XC2VP40), page 435 FF1152 Banked Pins (XC2VP40, XC2VP50), page 436 FF1152 Dedicated/Other Pins (XC2VP40), page 437 FF1152 Composite Pinout Diagram (XC2VP30), page 438 FF1152 Banked Pins (XC2VP30), page 439 FF1152 Dedicated/Other Pins (XC2VP30), page 440 FF1152 Composite Pinout Diagram (XC2VP20), page 441 FF1152 Banked Pins (XC2VP20), page 442 FF1152 Dedicated/Other Pins (XC2VP20), page 443 FF1148 Composite Pinout Diagram (XC2VP50), page 445 FF1148 Banked Pins (XC2VP50), page 446 FF1148 Composite Pinout Diagram (XC2VP40), page 447 FF1148 Banked Pins (XC2VP40), page 448 FF1148 Dedicated/Other Pins (XC2VP40, XC2VP50), page 449 FF1517 Composite Pinout Diagram (XC2VP70), page 451 FF1517 Banked Pins (XC2VP70), page 452 FF1517 Composite Pinout Diagram (XC2VP50), page 453 FF1517 Banked Pins (XC2VP50), page 454 FF1517 Dedicated/Other Pins (XC2VP50, XC2VP70), page 455 FF1704 Composite Pinout Diagram (XC2VP100), page 457 FF1704 Banked Pins (XC2VP100), page 458 FF1704 Composite Pinout Diagram (XC2VP70), page 459 FF1704 Banked Pins (XC2VP70), page 460 FF1704 Dedicated/Other Pins (XC2VP70, XC2VP100), page 461 FF1704 Composite Pinout Diagram (XC2VPX70), page 462 FF1704 Banked Pins (XC2VPX70), page 463 FF1704 Dedicated/Other Pins (XC2VPX70), page 464 FF1696 Composite Pinout Diagram (XC2VP100), page 465 FF1696 Banked Pins (XC2VP100), page 466 FF1696 Dedicated/Other Pins (XC2VP100), page 467
398
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
H P A N I
Y T X S Z
Y T X S Z R
M K O
1 0 2 Z Y T X S
2 3 4 5 6 7 8 9
WC Z Y T X S
10 11 12 13 14 15
16
* Callouts for max number of I/Os per bank include dual-purpose pins shown in table, right.
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R
Other Pins DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_109a_072704
Figure 5-1:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
399
11
* Callouts for max number of I/Os per bank include dual-purpose pins shown in table, right.
Dedicated Pins
Other Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_109b_072704
Figure 5-2:
400
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
1 A B C D E F G H J K L M N P R T
10
11
12
13
14
15
16 A B C D E F G H J K L M N P R T
H P A N I
Y T X S Z
Y T X S Z R
M K O
1 0 2 Z Y T X S
2 3 4 5 6 7 8 9
WC D Y T X S
10 11 12 13 14 15 16
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_109c_072704
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
401
402
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
M Y T X S Z Y T X S Y T X S Z Z R O
K B
C D E F G H J K L M N P R T U V W Y AA AB 21 22
Z Y T X S
7 8 9 10 11 12
C Z Z DW Y T X S Y T X S
13 14 15 16 17 18 19 20
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R
Other Pins DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_109a_072704
Figure 5-4:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
403
11
13
15
17
19
21
H M A Y T X S Y T X S Y T X S Y T X S K B P A N Z Z Z R Z C O I D E F G H J K L M N P R T U V 1 C W 0 2 Z Z Z Z DW Y Y T X S Y T X S Y T X S Y T X S AA AB 2 4 6 8 10 12 14 16 18 20 22 1 3 5 7 9 11 13 15 17 19 21
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_109c_072704
Figure 5-5:
404
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
n n n n M H n n n n A n n n n Y T X S Y T X S n n n n K B P n R A N n Z Z C O I D E F G H J K L M N P R T U V 1 C W n DW 0 2 n Z Z Y n n n n Y T X S Y T X S n n n n AA n n n n n n n n AB 2 4 6 8 10 12 14 16 18 20 22 1 3 5 7 9 11 13 15 17 19 21
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R
Other Pins DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_109d_072704
Figure 5-6:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
405
Dedicated Pins
Other Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_109e_072704
Figure 5-7:
406
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
H n n n n n n n n Y T X S A N n Z I n n n n n n n n n n n n n n n n n n n n n n n 1 0 2 n Z n n n n Y T X S n n n n n n n n n n n n n n n
n n n n M A Y T X S n n n n K B n R Z C O D n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
E F G H J K L M N P R T U V W Y AA AB
n n n n
n n n n
n n n n
n n n n
n n n n
C n DW Z Y T X S n n n n n n n n
11 12 13 14 15 16 17 18 19 20 21 22
10
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R
Other Pins DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_109g_072704
Figure 5-8:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
407
n n n n
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
n n n n n n n n n n n n
n n n n n n n n n n n n n n n n n n n n n n
n n n n
n n n n
n n n n
n n n n
n n n n
10
11
12
13
14
15
16
17
18
19
20
21
22
Dedicated Pins
Other Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_109h_072704
Figure 5-9:
408
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
11
13
15
17
19
21
n n n n M H n n n n A n n n n Y T X S Y T X S n n n n K B P n R A N n Z Z C O I D E F G H J K L M N P R T U V 1 C W n DW 0 2 n Z Z Y n n n n Y T X S Y T X S n n n n AA n n n n n n n n AB 2 4 6 8 10 12 14 16 18 20 22 1 3 5 7 9 11 13 15 17 19 21
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_109i_072704
Figure 5-10:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
409
410
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
A H Y T X S Z N I
Y T X S Z
Y T X S Z
Y T X SM Z R O
K B
C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 25 26
Z 2 1 Y T X S 0
3 4 5 6 7 8
Z Y T X S
9 10 11 12 13 14
Z Y T X S
15 16 17 18 19
Z D Y T X S C W
20 21 22 23 24
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_126a_072704
Figure 5-11:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
411
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_126b_072704
Figure 5-12:
412
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
A H Y T X S Z N I n n
Y T X S Z
Y T X S Z
Y T X SM Z R O n n
K B
C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 25 26
n n
n n
n n
n n
Z 2 1 Y T X S 0
3 4 5 6 7 8
Z Y T X S
9 10 11 12 13 14
Z Y T X S
15 16 17 18 19
Z D Y T X S C W
20 21 22 23 24
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_126d_072704
Figure 5-13:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
413
n n
n n
n n
n n
n n
n n
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_126e_072704
Figure 5-14:
414
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
A H Y T X S Z N I
Y T X S Z
Y T X S Z
Y T X SM Z R O
K B
C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 25 26
Z 2 1 Y T X S 0
3 4 5 6 7 8
Z Y T X S
9 10 11 12 13 14
Z Y T X S
15 16 17 18 19
Z D Y T X S C W
20 21 22 23 24
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_126c_072704
Figure 5-15:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
415
416
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
A B C D E n F M G N K O H I J K L M N P R T U V 1 W C Y n n n n n AA n n AB 2 D 0 AC W AD Z Z Z Z AE X T Y S X T Y S X T Y S X T Y AF 6 8 10 12 14 16 18 20 22 24 26 5 7 9 11 13 15 17 19 21 23 25
X T Y Z R
S X T Y Z
S X T Y Z
S X T Y Z P H n n n n A
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_110a_082502
Figure 5-16:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
417
A B C D E n n n n n n n n F G H J K L M N P R T U V W Y n n n n n n n n AA n n AB n n AC AD AE AF 2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11 13 15 17 19 21 23 25
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_110b_082502
418
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
S X T Y Z R M K O
S X T Y Z
S X T Y Z
S X T Y Z P H A N I
C D W Z S X T Y
2 3 4 5 6 7 8
1 2 Z S X T Y
9 10 11 12 13 14
Z S X T Y
15 16 17 18 19
0 Z S X T Y
20 21 22 23 24 25 26
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_110c_082502
Figure 5-18:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
419
A B C D E n F G H J K L M N P R T U V n n 1 W C n n n n n n Y n n n n n n n n n AA n n n n n n AB 2 D n n n n n n 0 AC W n n AD Z Z Z Z AE X T Y S X T Y S X T Y S X T Y AF 6 8 10 12 14 16 18 20 22 24 26 5 7 9 11 13 15 17 19 21 23 25
X T Y Z R
S X T Y n Z n n n n n n n M n n n K n O
S X Z n n n n n n
T Y S X T Y n Z n n P n H n n n n n A n N I
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_110d_012805
Figure 5-19:
420
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
A B n n C n n n n n n D n n n n E n n n n n n n n n n n n F n n n n n n G n n H J K L M N P R T U V n n W n n n n n n Y n n n n n n n n n n n n AA n n n n n n AB n n n n n n n n AC n n AD AE AF 2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11 13 15 17 19 21 23 25
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_110e_082502
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
421
n n n n n n n n n R n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
n n n n n n n
n n n n n n n n n n n
n n n n n n
n n n n n n
n n n n n
D W n n n n n n n
4 5 6
S X T Y n Z n n n n n n n M n n n K n O n n n n n n n n n n n n n n n C n n n n n n n n n n n Z n S X T Y n
7 8 9 10 11 12 13 14
S X Z n n n n n n
n n n n n n Z S X
15 16
n n n n n n n n T Y n n n n P n H n n n A n n n n N I n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n 1 n n n n n n n n n n n 2 n n 0 n n n n n n T Y n n n n
17 18 19 20 21 22 23
n n n n n n
n n n n n n n n n n
n n n n n n
n n n n n n n n n n n n
24
25
26
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_110g_082502
Figure 5-21:
422
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
n n n n n n
n n n n n n n n n n
n n n n n n
n n n n n n
n n n n n n n
n n n n n n n n n n n
n n n n n n
n n n n n n
n n n n n n n n n n n n n n n n n n n n n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n n n n n n n n n n n n n n n n n n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n n n n n n n
n n n n n n
n n n n n n
n n n n n n
n n n n n n n n n n n n
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_110h_082502
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
423
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
10
11
12
13
14
15
16
17
18
19
20
22
24
25
26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
n n n n n n n n n R M K O
S X T Y Z
S X T Y Z
n n n n n n n n n P H A N I
C D W n n n n n n n n n
2 3 4 5 6 7 8
1 2 Z S X T Y
9 10 11 12 13 14
Z S X T Y
15 16 17 18 19
0 n n n n n n n n n
20 21 22 23 24 25 26
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_110i_082502
Figure 5-23:
424
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
S X T Y Z R O K M
S X T Y Z
S X T Y Z
S X T Y Z N I P H A
C D W
2 1 0
Z S X T Y 4 5 6 7 8 9 10
Z S X T Y 11 12 13 14 15 16
Z S X T Y 17 18 19 20 21 22 23
Z S X T Y 24 25 26 27
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_111a_090302
Figure 5-24:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
425
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_111b_072804
426
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
n n n n
n n n n n n n n
n n n n n n n C n n n n W n n n n n n n n n n Z S X T Y 1 2 3 4 5 6 7
n n n D
A B C D n n n E n n n F n n n n G n n n n H n n J K L M N P R T U V W n n Y n n AA n n n n n n AB n n n n 2 1 n n AC n n n n n n AD 0 n n n n n n n n n AE n n n n n n n n n n n AF n n n n AG n n Z n n Z n n Z AH n S X T Y S X T Y n S X T Y AJ n n AK 10 12 14 16 18 20 22 24 26 28 30 9 11 13 15 17 19 21 23 25 27 29 X T Y Z S X
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_111d_072804
Figure 5-26:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
427
n n n n
n n n n n n n n n n n n n n n n n n n n
n n n n n n n n n n n n n n n n n n n n n n n n
A B C D n n E n n n F n n G n n H n J K L M N P R T U V W n n Y n n AA n n n n n n AB n n n n n n AC n n n n n n AD n n n n n n n n n AE n n n n n n n n n n n AF n n n n AG n n n n n n AH n n AJ n n AK 10 12 14 16 18 20 22 24 26 28 30 9 11 13 15 17 19 21 23 25 27 29
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_111e_072804
428
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
S X T Y Z R O K M
S X T Y Z
S X T Y Z
S X T Y Z N I P H A
C D W
2 1 0
Z S X T Y 2 3 4 5 6 7 8 9 10
Z S X T Y 11 12 13 14 15 16
Z S X T Y 17 18 19 20 21 22 23
Z S X T Y 24 25 26 27 28 29 30
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_111c _082502
Figure 5-28:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
429
S X T Y Z R O K M
S X T Y Z E B
S X T Y Z
S X T Y Z N I P H A
C D W
2 1 0
Z S X T Y 4 5 6 7 8 9 10
Z S X T Y 11 12 13 14 15
E Z B S X T Y 16 17 18 19 20 21 22 23
Z S X T Y 24 25 26 27
Dedicated Pins C P D 2 1 0 H K I O M W B E CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B BREFCLKN BREFCLKP
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_111f_072804
Figure 5-29:
430
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_111g_072804
Figure 5-30:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
431
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
S X T Y Z R O K M
S X T Y Z E B
S X T Y Z
S X T Y Z N I P H A
C D W
2 1 0
Z S X T Y 2 3 4 5 6 7 8 9 10
Z S X T Y 11 12 13 14 15
E Z B S X T Y 16 17 18 19 20 21 22 23
Z S X T Y 24 25 26 27 28 29 30
Dedicated Pins C P D 2 1 0 H K I O M W B E CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B BREFCLKN BREFCLKP N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_111f_072704
432
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y Z Z Z Z Z Z Z Z
R O K M P H A
N I
C D W
2 1 0
Z Z Z Z Z Z Z Z S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_112a_082802
Figure 5-32:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
433
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP
S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y Z Z Z Z Z Z Z Z
R O K M P H A
N I
C D W
2 1 0
Z Z Z Z Z Z Z Z S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_112c_082302
Figure 5-33:
434
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
n n n n n n n n S X T Y S X T Y n n n n S X T Y S X T Y n n n n S X T Y S X T Y n n Z Z Z Z Z Z
R O K M P H A
N I
C D W
2 1 0
n n Z Z Z Z Z Z S X T Y S X T Y n n n n S X T Y S X T Y n n n n S X T Y S X T Y n n n n n n n n
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_112d_082802
Figure 5-34:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
435
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_112b_082802
Figure 5-35:
436
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP
n n n n n n n n S X T Y S X T Y n n n n S X T Y S X T Y n n n n S X T Y S X T Y n n Z Z Z Z Z Z
R O K M P H A
N I
C D W
2 1 0
n n Z Z Z Z Z Z S X T Y S X T Y n n n n S X T Y S X T Y n n n n S X T Y S X T Y n n n n n n n n
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_112f_082302
Figure 5-36:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
437
n n n n n n n n n n n S X T Y n n n n n Z n n n n n n n n n R n O K M
n n n n n n S X T Y S X T Y n n n n S X n Z Z Z n n n n n n n N n n n P n n H A
n n n n T Y n n n n n n n
C D W
n n n n n n
n n n n n n
2 1 0 n n n n Z n S X T Y n n n n n n n n
26 27 28 29 30 31 32 33
n n n n n n n n n n Z n Z Z n n n n S X T Y n n n n S X T Y S X T Y n n n n n n n n n n n n n n n n
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_112g_082802
Figure 5-37:
438
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
n n n n
n n n n n n n n n n
n n n n n n
n n n n
n n n n n n n n n n n n
n n n n n n n n n n n n
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_112h_082802
Figure 5-38:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
439
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP
n n n n n n n n n n n n n n n n n n n n S X T Y n n n n S X T Y S X T Y n n n n S X T Y n n n n n n n n Z Z Z Z
R O K M P H A
N I
C D W
2 1 0
n n n n Z Z Z Z n n n n S X T Y n n n n S X T Y S X T Y n n n n S X T Y n n n n n n n n n n n n n n n n n n n n
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_112i_082302
Figure 5-39:
440
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
n n n n n n n n n S X T Y n n n Z n n n n n n n n n n n R n n n n O n n n n K n n M n n
n n n n n n n n n n S X T Y S X T Y n n n n S X n n Z Z Z n n n n n n n n n n n n N n n n n P n n HA n n n
n n n n T Y n n n n n n n n n n n n n n n I n n n n n n n n n
n n n n n n n n n n n n
1 2 3
n n n n C D n n n nW n n n n n n n n n n n n Z n n n S X T Y n n n n n n
4 5 6 7 8 9 10 11
n n n n
n n n n
n n Z Z n n S X T Y S X T Y n n n n n n
12 13 14 15 16 17 18 19 20 21 22 23
n n 2 1 n n 0 n n n n n n n n n n n n n n n n Z n n n S X T Y n n n n n n
24 25 26 27 28 29 30 31
n n n n n n n n n n n n
32 33 34
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_112j_011603
Figure 5-40:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
441
n n n n n n n n n n n n n n n n n n n n n n n n
n n n n n n n n n n
n n n n n n n n
n n n n n n n n n n n n n n n n n n n n n n
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_112k_011603
Figure 5-41:
442
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP
n n n n n n n n n n n n n n n n n n n n S X T Y n n n n S X T Y S X T Y n n n n S X T Y n n n n n n n n Z Z Z Z
R O K M P H A
N I
C D W
2 1 0
n n n n Z Z Z Z n n n n S X T Y n n n n S X T Y S X T Y n n n n S X T Y n n n n n n n n n n n n n n n n n n n n
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_112l_082302
Figure 5-42:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
443
444
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
O K RM
I P H N A
D CW
2 0 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_123a_082002
Figure 5-43:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
445
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_123b_082002
Figure 5-44:
446
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
O K RM
n n
n n
I P H N A
D CW n n n n
2 0 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_123d_082002
Figure 5-45:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
447
n n
n n
n n
n n
16
17
18
19
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_123e_082002
Figure 5-46:
448
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1
11
13
15
17
19
21
23
25
27
29
31
33
O K RM
I P H N A
D CW
2 0 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_123f_082002
Figure 5-47:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
449
450
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
S X T Y S X T Y S X T Y S X T Y Z Z Z Z R K M
S X T Y S X T Y S X T Y S X T Y Z Z Z Z P H N
A I
C D
2 1
W Z Z Z Z S X T Y S X T Y S X T Y S X T Y
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
0 Z Z Z Z S X T Y S X T Y S X T Y S X T Y
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B
N A R
Other Pins S X T Y Z
NO CONNECT
ug012_c4_107a_082202
Figure 5-48:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
451
Dedicated Pins
Other Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_107b_082202
Figure 5-49:
452
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
S X T Y S X T Y S X T Y S X T Y Z Z Z Z n n n n R n n n n K n n n n n n M n n n n n n n n n n n n n n O
n n n n n n n n n n n n n n n n S X
1 2 3 4 5
M N P R T U V W Y AA AB AC AD AE AF AG AH n n n n 2 1 C D AJ n n AK n n n n AL n n n AM n n n n n n n n AN n n n n n n n AP 0 W n n n n n AR n n n n n n AT Z Z Z Z Z Z Z Z n AU T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y AV AW 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B
N A R
Other Pins S X T Y Z
NO CONNECT
ug012_c4_107d_082202
Figure 5-50:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
453
n n n n n n n n n n n n n n n n
n n n n n n n n
n n n n n n n n n n n n n n n n
n n n n n n n n n n n n n n n n
n n n n n n n n n n n n n n n n
n n n n n n n n n n n n
n n n n n n n n n n n n
n n n n n n n n n
n n n n n n n
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Dedicated Pins
Other Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_107e_082202
Figure 5-51:
454
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 1
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW
S X T Y S X T Y S X T Y S X T Y Z Z Z Z R K M
S X T Y S X T Y S X T Y S X T Y Z Z Z Z P H N
A I
C D
2 1
W Z Z Z Z S X T Y S X T Y S X T Y S X T Y
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
0 Z Z Z Z S X T Y S X T Y S X T Y S X T Y
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B
N A R
Other Pins S X T Y Z
NO CONNECT
ug012_c4_107c_082202
Figure 5-52:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
455
456
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y O Z Z Z Z Z Z Z Z Z I Z R N A H M K P
W D Z Z Z Z Z Z Z C Z S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
0 2 Z 1 Z X T Y S X T Y
35 36 37 38 39 40 41
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_124a_091703
Figure 5-53:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_124b_091703
Figure 5-54:
458
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y O Z Z Z Z Z Z Z Z Z I Z n n R N n n A n n H M n n K P n n n n n n n n n n n n n n
W D Z Z Z Z Z Z Z C Z S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
n n n n n n n n n n n
n n n n n n n n n n n
0 2 Z 1 Z X T Y S X T Y
35 36 37 38 39 40 41
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_124d_091703
Figure 5-55:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
459
n n n n n n n n n n n
n n n n n n n n n n n
n n n n n n n n n n n
n n n n n n n n n n n
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_124e_091703
Figure 5-56:
460
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y O Z Z Z Z Z Z Z Z Z I Z R N A H M K P
J
K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 1
W D Z Z Z Z Z Z Z C Z S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
0 2 Z 1 Z X T Y S X T Y
35 36 37 38 39 40 41
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_124c_082302
Figure 5-57:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
461
J
K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 1
S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y O Z Z Z Z Z Z Z Z Z I Z n n R N n n A n n B H M n n E K P n n n n n n n n n n n n n n
W D Z Z Z Z Z Z Z C Z S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
n n n n n n n n n n n
B E
n n n n n n n n n n n
0 2 Z 1 Z X T Y S X T Y
35 36 37 38 39 40 41
Dedicated Pins C P D 2 1 0 H K I O M W B E CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B BREFCLKN BREFCLKP
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_124f_072704
Figure 5-58:
462
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
J
K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 1 2 3 4 5 6 7 8 9 10 11 12 13
n n n n n n n n n n n
n n n n n n n n n n n
n n n n n n n n n n n
n n n n n n n n n n n
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Dedicated Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_124g_072704
Figure 5-59:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
463
S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y O Z Z Z Z Z Z Z Z Z I Z R N A B H M E K P
J
K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 1
B E W D Z Z Z Z Z Z Z C Z S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
0 2 Z 1 Z X T Y S X T Y
35 36 37 38 39 40 41
Dedicated Pins C P D 2 1 0 H K I O M W B E CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B BREFCLKN BREFCLKP N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_124h_072704
Figure 5-60:
464
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Bank 1 - 111 Max User I/Os* Bank 0 - 111 Max User I/Os*
1 A B C D E F G H 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 38 40 42 37 39 41 A B C D E F G H J Bank 7 K 180 Max L User I/Os* M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM Bank 6 AN AP 180 Max AR User I/Os* AT AU AV AW AY BA BB 34 35 36 37 38 39 40 41 42
n n n n n n R K M O n n
n n n n n n P H N n n A I
J
K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 1 2 3 4 5 6 7 8 9
n n C D W n n n n n n n n
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
n n 2 1 0 n n n n n n n n
25 26 27 28 29 30 31 32 33
Bank 4 - 111 Max User I/Os* Bank 5 - 111 Max User I/Os*
* Callouts for max number of I/Os per bank include dual-purpose pins shown in table, right.
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R
Other Pins DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
ug012_c4_125d_082302
Figure 5-61:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
465
Bank 1 - 111 Max User I/Os* Bank 0 - 111 Max User I/Os*
1 A B C D E F G H 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 38 40 42 37 39 41 A B C D E F G H J Bank 7 K 180 Max L User I/Os* M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM Bank 6 AN AP 180 Max AR User I/Os* AT AU AV AW AY BA BB 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
n n n n n n
n n n n n n
J
K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
n n
n n
n n
n n
n n n n n n n n
16 17 18 19 20 21 22 23 24 25
n n n n n n n n
26 27
Bank 4 - 111 Max User I/Os* Bank 5 - 111 Max User I/Os*
* Callouts for max number of I/Os per bank include dual-purpose pins shown in table, right.
Dedicated Pins
Other Pins
DIN/D0-D7 CS_B RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair
VCCO
NO CONNECT
ug012_c4_125e_082302
Figure 5-62:
466
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
J
K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB 1 2 3 4 5 6 7 8 9
R K M O A I
P H N
C D W
2 1 0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Dedicated Pins C P D 2 1 0 H K I O M W CCLK PROG_B DONE M2, M1, M0 HSWAP_EN TCK TDI TDO TMS PWRDWN_B N A R DXN DXP VBATT RSVD
Other Pins S X T Y Z AVCCAUXRX VTRXPAD AVCCAUXTX VTTXPAD GNDA RXNPAD RXPPAD TXPPAD TXNPAD
ug012_c4_125c_082302
Figure 5-63:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
467
468
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Package Specifications
This section contains specifications for the following Virtex-II Pro packages: FG256/FGG256 Fine-Pitch BGA Package (1.00 mm Pitch), page 470 FG456/FGG456 Fine-Pitch BGA Package (1.00 mm Pitch), page 471 FG676/FGG676 Fine-Pitch BGA Package (1.00mm pitch), page 472 FF672 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 473 FF896 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 474 FF1152 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 475 FF1148 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 476 FF1517 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 477 FF1704 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 478 FF1696 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 479
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
469
Figure 5-64:
470
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Figure 5-65:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
471
Figure 5-66:
472
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Figure 5-67:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
473
Figure 5-68:
474
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Figure 5-69:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
475
Figure 5-70:
476
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Figure 5-71:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
477
Figure 5-72:
478
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Figure 5-73:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
479
Flip-Chip Packages
As silicon devices become more integrated with smaller feature sizes as well as increased functionality and performance, packaging technology is also evolving to take advantage of these silicon advancements. Flip-chip packaging is the latest packaging option introduced by Xilinx to meet the demand for high I/O count and high performance required by today's advanced applications. Flip-chip packaging interconnect technology replaces peripheral bond pads of traditional wire-bond interconnect technology with area array interconnect at the die/substrate interface. The area array pads contain wettable metallization for solders (either eutectic or highlead), where a controlled amount of solder is deposited either by plating or screenprinting. These parts are then reflowed to yield bumped dies with relatively uniform solder bumps spread over the surface of the device. Unlike traditional packaging in which the die is attached to the substrate face up and the connection is made by using wire, the bumped die in a flip-chip package is flipped over and placed face down, with the conductive bumps connecting directly to the matching metal pads on the ceramic or organic laminate substrate. The solder material at molten stage is self-aligning and produces good joints even if the chip is placed offset on the substrate. Flip-chip packages are assembled on high-density, multi-layer ceramic or organic laminate substrates. Since flip-chip bump pads are in area array configuration, very fine lines and geometry on the substrates are required to be able to successfully route the signals from the die to the periphery of the substrates. Multi-layer build-up structures offer this layout flexibility on flip-chip packages, and they provide improvements in power distribution and signal transmission characteristics.
Thermal Data
Thermal Considerations
The Virtex-II Pro device is a feature-rich FPGA product based on the high-performance Virtex-II architecture. The product incorporates numerous features such as multiple RocketIO Multi-Gigabit Transceivers (MGTs), one or more embedded IBM PowerPC processors, high-speed SelectI/O technology supporting a variety of I/O standards, onboard digitally controlled impedance (DCI) technology, and much more. In fully configured designs that engage all these features at high clock rates, power consumption can add up quickly.
480
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Unlike the features of ASICs or even of microprocessors, the combination of Virtex-II Pro features that will be utilized in an application are not known ahead of time. Therefore, as in previous FPGA devices, it remains challenging to predict the power requirements and resulting thermal management needs of a Virtex-II Pro device in a given package. These devices, therefore, do not come with a preset thermal solution. The end users conditions will determine what solutions will be most appropriate. In consideration of the high heatgenerating potential of the Virtex-II Pro devices, package offerings are tailored to include medium and high power capable options that allow external thermal management to meet the applications requirements. Table 5-3 shows thermal resistance parameters for Virtex-II Pro products. Table 5-3: Thermal Data for Virtex-II Pro Packages
JunctionLead to-Ambient Pitch Theta-JA (mm) Range, in Air (C/Watt) 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 24 - 28 18 - 22 16 - 18 14 -16 10 - 12 10 - 12 10 - 12 10 - 12 10 - 12 10 - 12 Junction-to-Case Theta-JC Range (C/Watt) 3.0 - 5.0 2.0 - 2.5 2.0 - 2.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Junction-to-Board Psi-JB ("Theta-JB") Typical (C/Watt) 14.0 10.0 7.6 6.5 3.7 3.7 3.7 3.7 3.7 3.7 Power With Heatsink Max Power, (Watts) Bare Pkg Theta-SA = 1.5 C/Watt (Watts) Theta-CS = 0.1 C/Watt TA = 50 C TJMAX = 100 C TA = 50 C, TJ = 100 C 1.7 2.5 3.0 3.3 4.5 4.5 4.5 4.5 4.5 4.5 N/A (1) N/A (1) N/A (1) 16 21 21 21 21 21 21
Package
FG256/FGG256 2-4L PCB, 17x17 FG456/FGG456 4L PCB, 23x23 FG676/FGG676 4L PCB, 27x27 FF672/FFG672 27x27 Flip-Chip FF896/FFG896 31x31 Flip-Chip FF1152/FFG1152 35x35 Flip-Chip FF1148/FFG1148 35x35 Flip-Chip FF1517/FFG1517 40x40 Flip-Chip FF1704/FFG1704 42.5x42.5 Flip-Chip FF1696/FFG1696 42.5x42.5 Flip-Chip
JA (Theta-JA): Thermal resistance, junction-to-ambient (Xilinx-supplied) JC (Theta-JC): Thermal resistance, junction-to-case (use with ratio of heat through the top) JB (Psi-JB, or "Theta-JB"): Thermal resistance in still air, junction-to-board SA (Theta-SA): Thermal resistance, heatsink (manufacturer-supplied) CS (Theta-CS): Thermal resistance, heatsink adhesive (manufacturer-supplied) Notes:
1. The heat sink used in this example is not mechanically compatible with the FG256/FGG256, FG456/FGG456, and FG676/FGG676 packages.
Virtex-II Pro packages can be grouped into three broad performance categorieslow, medium, and highbased on their power handling capabilities. All of the packages can use external thermal enhancements, which can range from simple airflow to schemes that can include passive as well as active heatsinks. This is particularly true for highperformance flip-chip packages where system designers have the option to further
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
481
enhance the packages to handle in excess of 20 watts, with arrangements that take system physical constraints into consideration. Table 5-4 shows simple but incremental power management schemes that can be brought to bear on flip-chip packages. Table 5-4: Power Low End (1 6 Watts) Mid Range (4 10 Watts) High End (8 25 Watts) Virtex-II Pro Flip-Chip Thermal Management Technique Bare package with moderate air 8C 12C/Watt Passive heatsink with air 5C 10C/Watt Active heatsink 2C 3C/Watt or better Description Bare package. Package can be used with moderate airflow within a system. Package is used with various forms of passive heatsinks and heat spreader techniques. Package is used with active heatsinks, TEC, and boardlevel heat spreader techniques
482
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
effectively. An otherwise cooler component might be heated by other heat contributing components on the board.
VCC Decoupling
Fast changing ICC transitions must be supplied by local decoupling capacitors, placed very closely to the VCC device pins or balls. These capacitors must have sufficient capacitance to supply ICC for a few nanoseconds, and must have low intrinsic resistance and inductance. X7R or NPO ceramic surface-mounted capacitors of 0.01 to 0.1 F, one per VCC device pin, are appropriate. 0.1 F can supply 1A for 2 ns with a 20 mV voltage droop. 1A 2 ns = 2 nanocoulomb = 100 nF 0.02V Low impedance at >100 MHz is important. Some capacitance variation with temperature is acceptable. A series of values of decoupling capacitors are needed in order to supply transient current to the device over all frequency ranges. The highest frequency capacitors should be in the range of 300 pF to 1 nF. The smallest capacitors are the first-line source for ICC, and they must be placed very close to the VCC pins. An inch of copper plane represents an inductance of several nanohenries, defeating the purpose of the decoupling capacitor. Therefore, the highest frequency (smallest value) capacitors should be mounted within 0.4 inches (1 cm) of the VCC and ground pin pair that it is decoupling. On large full-array BGA packages like the FF1152 and FF1517, following the decoupling guidelines presents implementation challenges. Note that the power and ground balls on these packages are grouped in banks. A subset of the initial line of high-frequency decoupling capacitors should be mounted directly opposite the component on the reverse side of the board and within the apparent boundary of the component. At least one and typically two 0.1 F chipcaps per bank should be used. The balance of the high-frequency bypass requirements can be implemented outside the periphery on these full-array packages. Backing up this local decoupling is one tantalum capacitor of 10 F to 100 F, able to supply multiple amperes for about 100 ns.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
483
Finally, each board needs a power-supply decoupling electrolytic capacitor of 1000 F to 10,000 F, able to supply even more current for a portion of the supply switching period. As described below, larger capacitors inevitably have higher series resistance and inductance, which is the reason for the above-mentioned hierarchy of supply decoupling. As a general rule, multiple capacitors in parallel always offer lower resistance and inductance than any single capacitor. Bypass capacitors must have vias (at least two per pad) abutting the pads, or vias in the pads, to provide the lowest inductance connection.
Decoupling Capacitors
The ideal decoupling capacitor would present a short circuit to ground for all AC signals. A real capacitor combines a given amount of capacitance with unavoidable parasitics, a small series resistance, and inductance. At low frequencies, the composite impedance is capacitive: that is, it decreases with increasing frequency. At high frequencies, it is inductive and increases with frequency, making the decoupling ineffective. In between, there is the LC resonant frequency, where the capacitor looks like a small resistor. This is the range where it is most effective. Different technologies provide different trade-offs between desirable features like small size and high capacitance, and undesirable features like series resistance and inductance. Electrolytic and tantalum capacitors offer the largest capacitance in a given physical size, but also have the highest inductance. This makes them useful for decoupling low frequencies and storing large amounts of charge, but useless for high frequency decoupling. Surface-mount ceramic capacitors, on the other hand, offer the lowest inductance and the best high-frequency performance, but offer only a small amount of capacitance, usually less than a microfarad. Figure 5-74 shows the frequency-dependent impedance and resistance of a typical electrolytic capacitor of 1500 F, while Figure 5-75 and Figure 5-76 show the equivalent data for ceramic bypass capacitors of 33,000 pF and 3,300 pF, respectively. Note that the resonant frequency for the small ceramic bypass capacitor at 100 MHz is 10,000 times higher than the resonance frequency of the large electrolytic capacitor at 10 KHz. For more technical information on decoupling capacitors, see the manufacturers websites.
10
0.1
0.01 0.01
0.1
10 1 Frequency kHz
100
1000
UG002_C4_014_111400
Figure 5-74:
484
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
10
Impedence (Ohms)
Figure 5-75:
10
Impedence (Ohms)
Figure 5-76:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
485
For an outer-layer trace (air on one side), the propagation delay is 140 ps/inch, or 55 ps/cm. For an inner-layer trace (FR4 with =4.5 on both sides), the propagation delay is 180 ps/inch, or 70 ps/cm. The voltage-to-current ratio at any point along the transmission line is called the characteristic impedance Z0. A field solver, which is available in most signal integrity simulation software, may be used to determine the impedance of a given trace geometry. As a first order approximation, it is determined by w/d, the ratio of trace width w to the distance d above the ground or VCC plane. For an outer layer trace (microstrip), Z0 = 50 when w = 2d (e.g., w = 12 mil, d = 6 mil), Z0 = 75 when w = d (e.g., both 6 mil = 0.15 mm). For an inner layer trace between two ground or VCC planes (stripline), Z0 = 50 when w = 0.6 d (e.g., w = 5 mil, d = 8 mil), Z0 = 75 when w = 0.25 d (impractical). Most signal traces fall into the range of 40 to 80. A slow transition treats a short narrow trace as a lumped capacitance of about 2 pF/inch (0.8 pF/cm). However, if the trace is so long or the signal transition so fast that the potential echo from the far end arrives after the end of the transition, then the trace must be analyzed as a transmission line. In this case, the driver sees the trace not as a lumped capacitance, but rather as a pure resistance of Z0. The signal transition then travels along the trace at the speed mentioned above. At any trace-impedance discontinuity all or part of the signal is reflected back to the origin. If the far end is resistively terminated with R=Z0, then there is no reflection. If, however, the end is open, or loaded with only a CMOS input, then the transition doubles in amplitude, and this new wave travels back to the driver, where it may be reflected again, resulting in ringing. Such ringing has a serious impact on signal integrity, reduces noise margins, and can lead to malfunction, especially if an asynchronous signal or a clock signal crosses the input threshold voltage unpredictably. Two alternate ways to avoid reflections and ensure signal integrity are parallel termination and series termination.
Parallel Termination
Reflections from the far end of the transmission line are avoided if the far end is loaded with a resistor equal to Z0. A popular variation uses two resistors, one to VCC, one to ground, as the Thevenin equivalent of Z0. This reduces the load current for one signal level, while increasing it for the other. Parallel termination inherently has some dc power consumption. DCI on-chip termination may be used to realize parallel termination schemes. See Figure 5-77.
486
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Vcc
R = Z0
Z0
Vcc
R= 2 x Z 0
Z0
R= 2 x Z 0
ug002_c4_043_111901
Figure 5-77:
Parallel Termination
Series Termination
While parallel termination eliminates reflections, series termination relies on the reflection from the far end to achieve a full-amplitude signal. For series termination, the driver impedance is adjusted to equal Z0, thus driving a half-amplitude signal onto the transmission line. At the unterminated far end, the reflection creates a full-amplitude signal, which then travels back to the driver where it is absorbed, since the output impedance equals Z0. See Figure 5-78.
R = Z0
Z0
ug002_c4_44_111400
Figure 5-78: Series Termination Series termination dissipates no dc power, but the half-amplitude round-trip delay signal means that there must be no additional loads along the line. Series termination is ideal (and only meaningful) for single-source-single-destination interconnects. DCI on-chip termination may be used to realize series termination schemes through the use of controlled impedance drivers.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
487
Crosstalk
Crosstalk can happen when two signals are routed closely together. Current through one of the traces creates a magnetic field that induces current on the neighboring trace, or the voltage on the trace couples capacitively to its neighbor. Crosstalk can be accurately modeled with signal integrity software. Two easy-to-remember rules of thumb are: Crosstalk falls off with the square of increasing distance between the traces. Crosstalk also falls off with the square of decreasing distance to a ground plane.
V Peak Crosstalk Voltage = ----------------------------1 + ( D H )2
where V is the voltage swing D is the distance between traces (center to center)
Example:
3.3V swing, and two stripline traces 5 mils apart and 5 mils above the ground plane. Peak Crosstalk Voltage = (3.3V)/(1 + (0.005/0.005)2 ) = 1.65V This can cause a false transition on the neighboring trace. Separating the trace by an additional 5 mils is significantly better: Peak Crosstalk Voltage = (3.3V)/(1 + (0.01/0.005)2 ) = 0.66V
488
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
If only one signal can be escaped between two pads, only two rows of pins can be escaped per layer. For FG packages (1.0mm pitch) one signal of width 5 mils (0.13mm) can be escaped between two pads, assuming a space constraint equal to the trace width. For a discussion of signal routing specific to Virtex-II Pro devices, see www.xilinx.com for currently available application notes. As packages are able to handle more I/Os with a minimum increase in size, the signal integrity of those signals must be considered, regardless of clock frequency. Especially with the largest packages, precise PCB layer stackup is required. Parameters such as board material, trace width, pad type, and stackup must be defined based on simulation, and the fabrication drawings must be marked Precise Layer Stackup, and the stackup must be specified. A number of board-level signal integrity simulators exist. Careful attention to PCB design rules creates a robust design with low EMI and high signal reliability.
Power Ground
Figure 5-79:
The number of layers required for effective routing of these packages is dictated by the layout of balls in each package. If several other technologies and components are already present on the board, the system cost is factored with every added board layer. The intent of a board designer is to optimize the number of layers required to route these packages, considering both cost and performance. This section provides guidelines for minimizing required board layers for routing BGA products using standard PCB technologies (5 mil wide lines and spaces or 6 mil wide lines and spaces). For high performance and other system needs, designers can use premium technologies with finer lines/spaces on the board. The pin assignment and pin grouping scheme in BGA packages enables efficient routing of the board with an optimum number of required board layers.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
489
VL VH W
D L M
Mask Opening Outside of Land
e
Non-Solder-Mask-Defined Land Patterns or Land-Defined Land Patterns are recommended for all packages.
x157_02_120500
Land Pad Characteristics Component Land Pad Diameter (SMD) (4) Solder Land (L) Diameter Opening in Solder Mask (M) Diameter Solder (Ball) Land Pitch (e) Line Width Between Via and Land (w) Distance Between Via and Land (D) Via Land (VL) Diameter Through Hole (VH), Diameter Pad Array Matrix or External Row Periphery Rows
Notes: 1. Dimensions in millimeters. 1. 3 x 3 matrix for illustration only, one land pad shown with via connection. 1. FG456 package has solder balls in the center in addition to the periphery rows of balls. 1. Component land pad diameter refers to the pad opening on the component side (solder-mask defined).
490
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
For Xilinx BGA packages, NSMD (Non Solder Mask Defined) pads on the board are suggested. This allows a clearance between the land metal (diameter L) and the solder mask opening (diameter M) as shown in Figure 5-80. The space between the NSMD pad and the solder mask, and the actual signal trace widths depends on the capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces are smaller. Selection of the pad types and pad sizes determines the available space between adjacent balls for signal escape. Based on PCB capability, the number of lines that can share the available space is described in Figure 5-81. Based on geometrical considerations, if one signal escapes between adjacent balls, then two signal rows can be routed on a single metal layer. This is illustrated in Figure 5-81, as routing with one line/channel, either at 6 mil lines and spaces or 5 mil lines and spaces. The blocked nature of multi-gigabit transceiver (MGT) at the top edge prevents a direct implementation of one line/channel arrangement in layer 1. Using this suggested routing scheme, a minimum of eight PCB layers are required to route up to 10 signal rows in a package. These Virtex-II Pro BGA packages may incorporate up to 16 MGT channels per package. The balls that make up these channels are grouped within the two outer rows of top and bottom edges. This outer row arrangement allows easy escape and pairing of signals. Accommodation of any filtering schemes off the chip can be accomplished in close proximity as well. A slightly lower trace width than that employed on the top and bottom external or exposed traces can be used by the inner signal rows routed in internal layers. Depending on the signal being handled, the practice of "necking down" a trace in the critical space between the BGA balls is allowable. Changes in width over very short distances can cause small impedance changes. Validate these issues with the board vendor and signal integrity engineers responsible for design. It is also suggested to implement the MGT signals in stripline arrangement. Figure 5-81 describes a board-level layout strategy for a Xilinx 1.0 mm pitch FF672 package, which incorporates four MGT channels at the top edge. Detail A in Figure 5-81 describes the opening geometry for the land pad and the solder mask. Routing with 5 mil lines/trace allows one signal per channel (between the balls). For successful routing, eightrow-deep signal traces require six to eight PCB layers. Figure 5-82 shows the suggested schematic of layers for the eight-layer routing scheme. By using a premium board technology such as Microvia Technologyallowing up to 4 mil lines and spacesefficient routing with a reduced number of board layers is made possible. A grouping scheme for power, ground, control, and I/O pins may also enable efficient routing. Figure 5-83 and Figure 5-84 show examples of suggested layer-by-layer board escape routing strategy used to implement MGT and LVDS pairs for two of the Virtex-II Pro packages, the wire-bond FG456 and the flip-chip FF672. These drawings assume a standard PCB technology of 5 mil wide lines and spaces. More details are contained in XAPP157, which is available on the web at www.xilinx.com/bvdocs/appnotes/xapp157.pdf, as is a full-color (PDF) version of this document.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
491
I/O Rows
8
PCB Layer 8
A B C D E F G H J K L M
Detail "A"
Signal (L1)
PWR Plane
GND Plane
Legend:
I/O GND PWR VCCINT V INT
Detail "A"
0.55 mm (0.022) 0.45 mm (0.018)
Signal (S1) Power/Gnd Signal (S2) Signal (S3 MGT) Power/Gnd Signal (S4) Power/Gnd Signal (S5)
Figure 5-82:
492
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Figure 5-83:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
UG012_C4_122_031405
493
Figure 5-84:
494
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
UG012_C4_121_031405
XPower
XPower is the first graphic power-analysis software available for programmable logic design. Earlier than ever in the design flow you can analyze total device power, power per net, routed, or partially routed or unrouted designs. You can also receive graphical or ASCII-based reports, all driven from a comprehensive graphic interface, or use a command-line driven batch-mode execution. XPower supports Virtex-II Pro and Virtex-II advanced FPGA devices and the XPLA3 family of CPLD devices, offering the broadest device support available in programmable power estimation. XPower also supports the importing of simulation data from ModelSim VCD files, greatly reducing the time spent setting up net activity, and increasing overall estimation accuracy. XPower uses device knowledge and design data to project device power and by-net power utilization. This is a significant advance from the static estimation pages most logic providers offer their customers, and it is a leap forward in providing logic designers with accurate power dissipation information. Features include: Support for Virtex-II Pro, Virtex-II, Virtex-E, Virtex, and Spartan-II FPGAs in ISE 4.1i XPLA3 device support through ISE WebPACK 4.1i VCD simulation file import for ModelSim Windows 98 and NT, Windows ME and Windows 2000, and Solaris support Graphic and/or ASCII report formats Menu-driven or batch-mode execution Device data read directly from Xilinx layout files Save and recall setup data Recognize small voltage variations on VCC
More details are available under the Xpower link on the www.xilinx.com website.
IBIS Models
The need for higher system performance leads to faster output transitions. Signals with fast transitions cannot be considered purely digital. It is therefore important to understand their analog behavior by signal integrity analysis. To simulate the signal integrity of printed circuit boards (PCB) accurately and solve design problems before the PCB is fabricated, models of the I/O characteristics are required. SPICE models were traditionally used for this purpose, however, a manufacturer's SPICE models contain proprietary circuit-level information. Therefore, there was a need for a model type which does not give details of the circuit topology, or process parameters. One such standard is the I/O Buffer Information Specification (IBIS) format originally suggested by Intel. In the early 1990's, the IBIS Open Forum was formed and the first IBIS specification was written to promote tool independent I/O models for system signal integrity analysis. IBIS is now the ANSI/EIA-656 and IEC 62014-1 standard. IBIS accurately describes the signal behavior of the interconnections without disclosing the actual technology and circuitry used to implement the I/O. The standard is basically a black-box approach to protect proprietary information.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
495
IBIS Generation
IBIS models are generated either from SPICE simulations or from actual device measurements. A SPICE netlist of the I/O buffer is required to produce V/I and dV/dt simulation curve data. The SPICE simulation data is then converted to an IBIS format/syntax file. IBIS models that are derived from measurement data do not have process corner information, unlike IBIS models that are derived from SPICE simulation data. It is only practical to measure a few parts, and it is therefore impossible to represent the extremes of production by such a method.
Advantages of IBIS
Using IBIS models has a great advantage to the user in that simulation speed is significantly increased over SPICE, while accuracy is only slightly decreased. Nonconvergence, which can be a problem with SPICE models and simulators, is eliminated in IBIS simulation. Virtually all EDA vendors presently support IBIS models and ease of use of these IBIS simulators is generally very good. IBIS models for most devices are freely available over the Internet, making it easy to simulate several different manufacturers devices on the same board.
496
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Model (i.e., 3-state) Temperature Range (typical, minimum, and maximum) Voltage Range (typical, minimum, and maximum) Pull-Up Reference Pull-Down Reference Power Clamp Reference Ground Clamp Reference I/V Tables for:
Rise and Fall dV/dt for minimum, typical, and maximum conditions (driving 50) Package Model (optional) <package_number>.pkg with RLC sections.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
497
dV/dt curves describe the transient characteristics of a buffer more accurately than ramps. A minimum of four dV/dt curves are required to describe a CMOS buffer: pull-down ON, pull-up OFF, pull-down OFF, and pull-up ON. dV/dt curves incorporate the clock-to-out delay, and the length of the dV/dt curve corresponds to the clock speed at which the buffer is used. Each dV/dt curve has t = 0, where the pulse crosses the input threshold.
IBIS Simulations
The circuit shown in Figure 5-85 models a Virtex-II Pro LVCMOS_18F driver and receiver, connected by a 6-inch 50 circuit board trace. The rise and fall simulation results show that there is a large amount of overshoot and undershoot, which is actually limited by the IOB clamp diodes.
UG012_c4_114_111301
Figure 5-85:
Unterminated Example
By adding a series termination resistor to the driver output, the overshoot and undershoot can be effectively controlled. The simulation results in Figure 5-86 show that by adding a 25 termination there is minimal overshoot and undershoot.
498
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
UG012_c4_115_111901
Figure 5-86:
An alternative is to use a DCI source impedance controlled driver. The results shown in Figure 5-87 show the waveforms from an LVDCI_18 driver, which has virtually no overshoot or undershoot.
UG012_c4_116_111901
Figure 5-87:
IBIS Simulators
Several different IBIS simulators are available today, and each simulator provides different results. An overshoot or undershoot of 10% of the measured result is tolerable. Differences between the model and measurements occur because not all parameters are modeled. Simulators for IBIS models are provided by Cadence, Avanti Corporation, Hyperlynx, Mentor, Microsim, Intusoft, Veribest, and Viewlogic.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
499
BSDL Files
Preliminary BSDL files are provided from the IC Design Process. Final BSDL files have been verified by an external third party test and verification vendor. Table 5-6 lists the Virtex-II Pro BSDL file names. Table 5-6: Virtex-II Pro BSDL File Names XC2VP20_FG696.BSD XC2VP20_FF896.BSD XC2VP20_FF1152.BSD XC2VP30_FG696.BSD XC2VP30_FF896.BSD XC2VP30_FF1152.BSD XC2VP40_FG696.BSD XC2VP40_FF1152.BSD XC2VP40_FF1148.BSD XC2VP50_FF1152.BSD XC2VP50_FF1148.BSD XC2VP50_FF1517.BSD XC2VP70_FF1517.BSD XC2VP70_FF1704.BSD XC2VP100_FF1704.BSD XC2VP100_FF1696.BSD
500
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Appendix A
BGN DRC
BIT
RBT
PROMGen
Hardware Debugger
X9227
Figure A-1:
BitGen
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
501
BitGen Syntax
The following syntax creates a bitstream from your NCD file.
bitgen [<options>] <infile[.ncd]> [<outfile>] [<pcf_file>]
options is one or more of the options listed in BitGen Options, page 503. <infile> is the name of the NCD design for which you want to create the bitstream. You can specify only one design file, and it must be the first file specified on the command line. You do not have to use an extension. If you do not, .ncd is assumed. If you do use an extension, it must be .ncd. <outfile> is the name of the output file. If you do not specify an output file name, BitGen creates one in the same directory as the input file. If you specify -l on the command line, the extension is .ll (see -l command line option). If you specify -m (see -m command line option), the extension is .msk. If you specify -b, the extension is .rbt. Otherwise, the extension is .bit. If you do not specify an extension, BitGen appends one according to the aforementioned rules. If you do include an extension, it must also conform to the rules. <pcf_file> is the name of a physical constraints (.pcf) file. BitGen uses this file to determine which nets in the design are critical for tiedown, which is not available for Virtex families. BitGen automatically reads the .pcf file by default. If the physical constraints file is the second file specified on the command line, it must have a .pcf extension. If it is the third file specified, the extension is optional; .pcf is assumed. If a .pcf file name is specified, it must exist, otherwise the input design name with a .pcf extension is read if that file exists. A report file containing all BitGens output is automatically created under the same directory as the output file. The report file has the same root name as the output file with a .bgn extension.
BitGen Files
This section describes input files that BitGen requires and output files that BitGen generates.
Input Files
Input to BitGen consists of the following files. NCD filea physical description of the design mapped, placed and routed in the target device. The NCD file must be fully routed. PCF filean optional user-modifiable ASCII Physical Constraints File. If you specify a PCF file on the BitGen command line, BitGen uses this file to determine which nets in the design are critical for tiedown (not used for Virtex families).
Output Files
Output from BitGen consists of the following files. BIT filea binary file with a .bit extension. The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file can then be downloaded into the FPGA memory cells, or it can be used to create a PROM file (see Using PROMGen, page 509).
502
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
RBT filean optional rawbits file with a .rbt extension. The rawbits file is ASCII ones and zeros representing the data in the bitstream file. If you enter a -b option on the BitGen command line, an RBT file is produced in addition to the binary BIT file (see -b (Create Rawbits File), page 503). LL filean optional ASCII logic allocation file with a .ll extension. The logic allocation file indicates the bitstream position of latches, flip-flops, and IOB inputs and outputs. A .ll file is produced if you enter a -l option on the BitGen command line (-l (Create a Logic Allocation File), page 509). MSK filean optional mask file with a .msk extension. This file is used to compare relevant bit locations for executing a readback of configuration data contained in an operating FPGA. A MSK file is produced if you enter a -m option on the BitGen command line (see -m (Generate a Mask File), page 509). BGN filea report file containing information about the BitGen run. DRC filea Design Rule Check (DRC) file for the design. A DRC runs and the DRC file is produced unless you enter a -d option on the BitGen command line (see -d (Do Not Run DRC), page 503).
BitGen Options
Following is a description of command line options and how they affect BitGen behavior.
-g (Set Configuration)
-g <option>:<setting>
The -g option specifies the startup timing and other bitstream options for Xilinx FPGAs. The settings for the -g option depend on the designs architecture. These options have the following syntax:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
503
Binary
Creates a binary file with programming data only. Use this option to extract and view programming data. Any changes to the header will not affect the extraction process. Settings: Default: No, Yes No
CclkPin
Adds an internal pull-up to the Cclk pin. The Pullnone setting disables the pullup. Settings: Default: Pullnone, Pullup Pullup
Compress
This option uses the multiple frame write feature in the bitstream to reduce the size of the bitstream, not just the .bit file. Using the Compress option does not guarantee that the size of the bitstream will shrink.
ConfigRate
Virtex-II Pro uses an internal oscillator to generate the configuration clock, CCLK, when configuring in a master mode. Use the configuration rate option to select the rate for this clock. Settings: Default: 4, 5, 7, 8, 9, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, 60 4
DCMShutdown
When DCMShutdown is enabled, the DCM (Digital Clock Manager) resets if the SHUTDOWN and AGHIGH commands are loaded into the configuration logic. Settings: Default: Disable, Enable Disable
DebugBitstream
If the device does not configure correctly, you can debug the bitstream using the DebugBitstream option. A debug bitstream is significantly larger than a standard bitstream. The values allowed for the DebugBitstream option are No and Yes. Note: You should use this option only if your device is configured to use slave or master serial mode. Values: No, Yes In addition to a standard bitstream, a debug bitstream offers the following features: Writes 32 0s to the LOUT register after the synchronization word Loads each frame individually Performs a cyclical redundancy check (CRC) after each frame Writes the frame address to the LOUT register after each frame
DisableBandgap
Disables bandgap generator for DCMs to save power. Settings: Default: No, Yes No
504
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
DONE_cycle
Selects the Startup phase that activates the FPGA Done signal. Done is delayed when DonePipe=Yes. Settings: Default: 1, 2, 3, 4, 5, 6 4
DonePin
Adds an internal pull-up to the DONE Pin pin. The Pullnone setting disables the pullup. Use this option only if you are planning to connect an external pull-up resistor to this pin. The internal pull-up resistor is automatically connected if you do not use this option. Settings: Default: Pullup, Pullnone Pullup
DonePipe
This option is intended for use with FPGAs being set up in a high-speed daisy chain configuration. When set to Yes, the FPGA waits on the CFG_DONE (DONE) pin to go High and then waits for the first clock edge before moving to the Done state. Settings: Default: No, Yes No
DriveDone
This option actively drives the DONE Pin high as opposed to using a pullup. Settings: Default: No, Yes No
Encrypt
Encrypts the bitstream. (For more information, see Bitstream Encryption in Chapter 3.) Settings: Default: No, Yes No
GTS_cycle
Selects the Startup phase that releases the internal 3-state control to the I/O buffers. The Done setting releases GTS when the DoneIn signal is High. DoneIn is either the value of the Done pin or a delayed version if DonePipe=Yes Settings: Default: Done, 1, 2, 3, 4, 5, 6, Keep 5
GWE_cycle
Selects the Startup phase that asserts the internal write enable to flip-flops, LUT RAMs, and shift registers. It also enables the BRAMs. Before the Startup phase both BRAM writing and reading are disabled.The Done setting asserts GWE when the DoneIn signal is High. DoneIn is either the value of the Done pin or a delayed version if DonePipe=Yes. The Keep setting is used to keep the current value of the GWE signal Settings: Default: Done, 1, 2, 3, 4, 5, 6, Keep 6
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
505
KeyFile
Specifies the name of the input encryption file. Settings: <string>
LCK_cycle
Selects the Startup phase to wait until DLLs/DCMs lock. If NoWait is selected, the Startup sequence does not wait for DLLs/DCMs. Settings: Default: 0, 1, 2, 3, 4, 5, 6, NoWait NoWait
M0Pin
The M0 pin is used to determine the configuration mode. Adds an internal pull-up, pulldown or neither to the M0 pin. The following settings are available. The default is PullUp. Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M0 pin. Settings: Default: Pullup, Pulldown, Pullnone Pullup
M1Pin
The M1 pin is used to determine the configuration mode. Adds an internal pull-up, pulldown or neither to the M1 pin. The following settings are available. The default is PullUp. Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M1 pin. Settings: Default: Pullup, Pulldown, Pullnone Pullup
M2Pin
The M2 pin is used to determine the configuration mode. Adds an internal pull-up, pulldown or neither to the M2 pin. The default is PullUp. Select Pullnone to disable both the pull-up resistor and pull-down resistor on the M2 pin. Settings: Default: Pullup, Pulldown, Pullnone Pullup
506
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Match_cycle
Specifies a stall in this Startup cycle until DCI (Digitally Controlled Impedance) match signals are asserted. Settings: Default: NoWait, 0, 1, 2, 3, 4, 5, 6 NoWait
Persist
This option is needed for Readback and Partial Reconfiguration using the SelectMAP configuration pins. If Persist is set to Yes, the pins used for SelectMAP mode are prohibited for use as user IO. Refer to the data sheet for a description of SelectMAP mode and the associated pins. Settings: Default: No, Yes No
ProgPin
Adds an internal pull-up to the ProgPin pin. The Pullnone setting disables the pull-up. The pull-up affects the pin after configuration. Settings: Default: Pullup, Pullnone Pullnone
ReadBack
This option allows you to perform Readback by the creating the necessary bitstream. When specifying the -g Readback option, the .rba, .rbb, .rbd, and .msd file are created.
Security
Selecting Level1 disables Readback. Selecting Level2 disables Readback and Partial Reconfiguration. Settings: Default: None, Level1, Level2 None
StartCBC
Sets the starting CBC (Cipher Block Chaining) value. The pick option causes BitGen to select a random number for the value. Settings: Default: Pick, <hex_string> Pick
StartKey
Sets the starting key number. Settings: Default: 0, 3 0
StartupClk
The startup sequence following the configuration of a device can be synchronized to either Cclk, a User Clock, or the JTAG Clock. The default is Cclk. Cclk Enter Cclk to synchronize to an internal clock provided in the FPGA device.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
507
JTAG Clock Enter JtagClk to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.
UserClk Enter UserClk to synchronize to a user-defined signal connected to the CLK pin of the STARTUP symbol. Settings: Default: Cclk (pinsee Note), UserClk (user-supplied), JtagCLK Cclk
Note: In modes where Cclk is an output, the pin is driven by an internal oscillator.
TckPin
Adds a pull-up, a pull-down or neither to the TCK pin, the JTAG test clock. Selecting one setting enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pull-down. Settings: Default: Pullup, Pulldown, Pullnone Pullup
TdiPin
Adds a pull-up, a pull-down, or neither to the TDI pin, the serial data input to all JTAG instructions and JTAG registers. Selecting one setting enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pulldown. Settings: Default: Pullup, Pulldown, Pullnone Pullup
TdoPin
Adds a pull-up, a pull-down, or neither to the TdoPin pin, the serial data output for all JTAG instruction and data registers. Selecting one setting enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pulldown. Settings: Default: Pullup, Pulldown, Pullnone Pullup
TmsPin
This option selects an internal pullup or pulldown on the TMS (JTAG Mode Select) pin. Settings: Default: Pullnone, Pullup, Pulldown Pullup
UnusedPin
Adds a pull-up, a pull-down, or neither to the UnusedPin, the serial data output for all JTAG instruction and data registers. Selecting one setting enables it and disables the others. The Pullnone setting indicates there is no connection to either the pull-up or the pulldown. The following settings are available. The default is PullDown. Settings: Default: Pullup, Pulldown, Pullnone Pulldown
508
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
UserID
You can enter up to an 8-digit hexadecimal code in the User ID register. You can use the register to identify implementation revisions.
Using PROMGen
The PROMGen program is compatible with the following families. Virtex/Virtex-E/Virtex-II/Virtex-II Pro
PROMGen formats a BitGen-generated configuration bitstream (BIT) file into a PROM format file (Figure A-2). The PROM file contains configuration data for the FPGA device. PROMGen converts a BIT file into one of three PROM formats: MCS-86 (Intel), EXORMAX (Motorola), or TEKHEX (Tektronix). It can also generate a Hex file format.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
509
BIT
PROMGen
HEX
Figure A-2:
PROMGen
There are two functionally equivalent versions of PROMGen. There is a stand-alone version you can access from an operating system prompt. You can also access an interactive version, called the PROM File Formatter, from inside the Design Manager for Alliance or the Project Manager in Foundation. This chapter describes the stand-alone version; the interactive version is described in the PROM File Formatter Guide. You can also use PROMGen to concatenate bitstream files to daisy-chain FPGAs. Note: If the destination PROM is one of the Xilinx Serial PROMs, you are using a Xilinx PROM
Programmer, and the FPGAs are not being daisy-chained, it is not necessary to make a PROM file. See the Hardware User Guide for more information about daisy-chained designs.
PROMGen Syntax
Use the following syntax to start PROMGen from the operating system prompt:
promgen [<options>] [<options>] can be any number of the options listed in PROMGen Options, page 511. Separate multiple options with spaces.
PROMGen Files
This section describes the PROMGen input and output files.
Input Files
The input to PROMGEN consists of BIT files one or more bitstream files. BIT files contain configuration data for an FPGA design.
Output Files
Output from PROMGEN consists of the following files.
510
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
PROM filesThe file or files containing the PROM configuration information. Depending on the PROM file format used by the PROM programmer, you can output a TEK, MCS, or EXO file. If you are using a microprocessor to configure your devices, you can output a HEX file, containing a hexadecimal representation of the bitstream. PRM fileThe PRM file is a PROM image file. It contains a memory map of the output PROM file. The file has a .prm extension.
Original Data
8 1000
A 1010
0101 5
0001 1
Figure A-3:
Bit Swapping
In a bitstream contained in a BIT file, the Least Significant Bit (LSB) is always on the left side of a byte. But when a PROM programmer or a microprocessor reads a data byte, it identifies the LSB on the right side of the byte. In order for the PROM programmer or microprocessor to read the bitstream correctly, the bits in each byte must first be swapped so they are read in the correct order. In this release of the Xilinx Development System, the bits are swapped for all of the PROM formats: MCS, EXO, and TEK. For a HEX file output, bit swapping is on by default, but it can be turned off by entering a -b PROMGen option that is available only for HEX file format.
PROMGen Options
This section describes the options that are available for the PROMGen command.
-c (Checksum)
promgen -c
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
511
The -c option generates a checksum value appearing in the .prm file. This value should match the checksum in the prom programmer. Use this option to verify that correct data was programmed into the prom.
-d (Load Downward)
promgen -d <hexaddress0> <filename> <filename> ...
This option loads one or more BIT files from the starting address in a downward direction. Specifying several files after this option causes the files to be concatenated in a daisy-chain. You can specify multiple -d options to load files at different addresses. You must specify this option immediately before the input bitstream file. The multiple file syntax is as follows:
promgen -d <hexaddress0> <filename> <filename> ...
The -f option executes the command line arguments in the specified <command_file>.
The -l option disables the length counter in the FPGA bitstream. It is valid only for 4000EX, 4000XL, 4000XLA, 4000XV, and SpartanXL Devices. Use this option when chaining together bitstreams exceeding the 24-bit limit imposed by the length counter.
This option loads one or more BIT files up or down from the next available address following the previous load. The first -n option must follow a -u or -d option because -n does not establish a direction. Files specified with this option are not daisy-chained to previous files. Files are loaded in the direction established by the nearest prior -u, -d, or -n option. The following syntax shows how to specify multiple files. When you specify multiple files, PROMGen daisy-chains the files.
promgen -d <hexaddress> <file0> -n <file1> <file2> ...
The following syntax when using multiple -n options prevents the files from being daisychained:
promgen -d <hexaddress> <file0> -n <file1> -n <file2> ...
512
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
This option specifies the output file name of a PROM if it is different from the default. If you do not specify an output file name, the PROM file has the same name as the first BIT file loaded. .ext is the extension for the applicable PROM format. Multiple file names may be specified to split the information into multiple files. If only one name is supplied for split PROM files (by you or by default), the output PROM files are named <file>_<#>.<ext>, where <file> is the base name, <#> is 0, 1, etc., and <ext> is the extension for the applicable PROM format.
promgen -d <hexaddress> <file0> -o <filename>
-p (PROM Format)
-p {mcs | exo | tek | hex}
This option sets the PROM format to one of the following: MCS (Intel MCS86), EXO (Motorola EXORMAX), TEK (Tektronix TEKHEX). The option may also produce a HEX file, which is a hexadecimal representation of the configuration bitstream used for microprocessor downloads. If specified, the -p option must precede any -u, -d, or -n options. The default format is MCS.
This option reads an existing PROM file as input instead of a BIT file. All of the PROMGen output options may be used, so the -r option can be used for splitting an existing PROM file into multiple PROM files or for converting an existing PROM file to another format.
-s (PROM Size)
-s <promsize1> <promsize2> ...
This option sets the PROM size in kilobytes. The PROM size must be a power of 2. The default value is 64 kilobytes. The -s option must precede any -u, -d, or -n options. Multiple <promsize> entries for the -s option indicates the PROM will be split into multiple PROM files. Note: PROMGen PROM sizes are specified in bytes. The Programmable Logic Data Book specifies PROM sizes in bits for Xilinx serial PROMs (see -x option).
-u (Load Upward)
-u <hexaddress0> <filename1> <filename2> ...
This option loads one or more BIT files from the starting address in an upward direction. When you specify several files after this option, PROMGen concatenates the files in a daisy-chain. You can load files at different addresses by specifying multiple -u options. This option must be specified immediately before the input bitstream file.
The -x option specifies one or more Xilinx serial PROMs for which the PROM files are targeted. Use this option instead of the -s option if you know the Xilinx PROMs to use.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
513
Multiple <xilinx_prom> entries for the -x option indicates the PROM will be split into multiple PROM files.
Examples
To load the file test.bit up from address 0x0000 in MCS format, enter the following information at the command line:
promgen -u 0 test
To daisy-chain the files test1.bit and test2.bit up from address 0x0000, and the files test3.bit and test4.bit from address 0x4000, while using a 32K PROM and the Motorola EXORmax format, enter the following information at the command line:
promgen -s 32 -p exo -u 00 test1 test2 -u 4000 test3 test4
To load the file test.bit into the PROM programmer in a downward direction starting at address 0x400, using a Xilinx XC1718D PROM, enter the following information at the command line:
promgen -x xc1718d -d 0x400 test
To specify a PROM file name that is different from the default file name, enter the following information at the command line:
promgen [<options>] <filename> -o <newfilename>
514
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Appendix B
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
515
ug002_appB_fs48
Figure B-1:
516
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
ug002_appB_vo48
Figure B-2:
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
517
ug002_appB_vo20
Figure B-3:
518
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Appendix C
Primary or Secondary
Primary batteries simplify the design as they cannot be recharged, and therefore require no extra circuitry. Secondary batteries require a method of charging, and can be damaged if charging currents are not controlled. Primary batteries can last up to 15 years (shelf life) which means that a battery could be placed in circuit, and forgotten about for the life of the product. Secondary batteries can provide significant current for a month or more, but then require recharging.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
519
If the design goal is to configure the keys at the factory, and then ship the product, lithium primary cells are the first choice, followed by silver oxide as a second choice. These two examples will be detailed below. If the design goal is to install keys in the field, through a system level secure key management system, then rechargeable batteries should be considered as they may outlast the product life as long as the product remains operational. A rechargeable example is also given.
All batteries may have a risk of explosion or fire if they are shorted. The use of a small surface mount resistor as a fuse is a necessary precaution.
Battery Summary
Table C-1: Primary Cell Types and Characteristics Lithium
Nominal Voltage: Temperature Range: Lifetime: Comments: 3.0V 40C to +150C > 15 years Best choice for long life Industrial grade Safely disposable
Silver Oxide
1.55V 10C to +60C > 10 years Used in medical systems Hazardous waste
Alkaline
1.5V 20C to +54C > 1 year Inexpensive Safely disposable (except Minnesota)
Table C-2:
520
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Design Examples
Case #1:
A 15-year operational life is desired, using a primary extended-temperature-range lithium button or coin cell. The current required is for ten Virtex-II or Virtex-II Pro FPGAs, or 10 x 100 nA = 1 uA, continuous. Leakage currents from the printed circuit board (PCB) are about 1 uA. Thus, total current = 2 A. The smallest coin cell from Panasonic is the BR1225A 48 mAh (milliampere hour), size 0.49" diameter by 0.1" height. The capacity in mAh divided by the current is the number of hours to end-of-life voltage. In this case, the number of hours available is : 48mAh / .002 mA = 24,000 hours (~2.7 years) To obtain 15 years, we need a larger-capacity battery. Notice in this case that the PCB leakage is limiting battery life. If the PCB is specified with lower leakage (which typically requires de-ionized water wash cycles), the smallest coin cell is adequate for about 5 years of life. If a 15-year life is required, a larger cell may be used. The cost of the larger-capacity battery might be offset by eliminating the de-ionized PCB water wash. End-of-life battery voltage is 2.0V DC. Start-of-life battery voltage is 3.0V DC, nominal. There are no restrictions on disposal of this type of battery, so there is no need for hazard labels. Adding a series diode is a good way to isolate the battery from the device. It allows for current testing by placing a current meter across the diode.
Case #2:
A Rayovac 675G is primary silver oxide cell, size 0.5" diameter by 0.2" thick. It provides 190 mAh starting at 1.55V and ending at 1.0V. In the previous case, where 1 uA operating current plus 1 uA PCB leakage yielded a total current of 2 A, a single cell would reach only about 11 years of life rather than the 15 years required. Limiting the PCB leakage to less current is one option to achieve longer battery life. Another option is to use two cells in parallel to achieve the 15-year life requirement. Because silver is considered a hazardous waste, there are restrictions on the disposal of a silver oxide battery. Customer instructions and labels regarding battery disposal will add to the cost of the system.
Case #3:
A system is designed to utilize a lithium polymer rechargeable battery. The batteries require a sophisticated charge controller IC to prevent damage and optimize performance. A National LM3621 charger IC is chosen to keep the cell charged, and requires only 1 A from the cell to function. The total requirement is now 3 A. There is a 5% charge loss per month, with no load utilizing a Battery Engineering 152-102-6.3 4000 mAh Polymer Rechargeable Lithium Battery, so the shelf life after first charge is ~20 months. The life with 3 A load is 21 years, much longer than the self discharge of 5% per month. If no other use of the current is required, a smaller battery may be used to balance out the self-discharge life. If a goal of one year is desired, the smallest cell from the catalog (86-54-3.5, 700 mAh) may be used.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
521
Start-of-cycle voltage may be as high as 4.6V, so it must be dropped to 3.6V for the Virtex-II and Virtex-II Pro BBRAM power pin. Use of 1N914 or 1N4148 diodes in series is suggested to drop the voltage. End-of-cycle voltage will not go below 3.0V. The voltage drop from the diodes reduces this to a lower number, but this is still well above the 1.0V required by the VBATT pin. In general, a 10 nA current is enough to drop the voltage 0.4 volts using two 1N914/1N4148 diodes. If the total current is less than the minimum forward current specified for the diode, this guideline can be used to estimate how many diodes are required in series to achieve a certain voltage drop. Double-check with the diode vendor and with lab measurements to confirm. There is no disposal restriction on the lithium polymer battery, but the charging restrictions require a special integrated circuit, and there are many rules to be followed in the proper use of a rechargeable lithium cell.
Case #4:
The cost and care required for the lithium battery in Case #3 were cause for rejection in the design review process. The alternative is nickel metal hydride, which has no disposal concerns, and can be charged with a simple series resistor. A Panasonic HHR55AAA/FT (requiring a AAA cell holder) will provide 560 mAh capacity, more than enough for our application. For charging, the self-discharge rate of the battery needs only to be offset. Nickel Metal Hydride batteries lose ~1% capacity per day, so charging at C/100 (where C= capacity in mAh) would just offset the self-discharge. Since it is safe to charge a nickel metal hydride battery at C/20 forever, a good compromise choice would be C/50, or 11 mA. If the local power supply is 3.3V and the terminal battery voltage when fully charged is 1.45V, a series diode is required to prevent the battery from discharging when the power is turned off. Using a 1N914 diode, the drop is 0.7V, and 3.3 1.45 0.7 = 1.15V. For 11 mA, / the required resistor is therefore about 105. A 110 1 8-watt 5% resistor is all that is needed. In order to replace the battery (if needed), a capacitor is added in parallel to the battery to hold the voltage for the time it takes to replace a battery. For 2 A, we solve for capacitance in I = C dV/dt, or C = I dt/dV. For a dV of 0.4 volts, a dT of 100 seconds, and a current of 1 A, the capacitance required is 250 F. The next safe standard value would be 470 F. A high-quality, low-leakage aluminum electrolytic or tantalum would be recommended.
522
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Glossary
Click on a letter, or scroll down to view the entire glossary.
ABCDEFGHIJKLMNOPQRSTUVWXZ
A
AC Coupling
Method of interfacing drivers and receivers through a series capacitor. Often used when the differential swing between drivers and receivers is compatible, but common mode voltages of driver and receiver are not. Requires that a minimum data frequency be established based on the RC time constant, necessitating a run length limit.
Addressing Modes
Techniques used by software or hardware in calculating an address.
Asynchronous
Logic that is not synchronized by a clock. Asynchronous designs can be faster than synchronous ones, but are more sensitive to parametric changes, and are thus less robust.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
523
Glossary
Attenuation
Reduction in amplitude of a signal.
B
Back Annotation
Automatically attaching timing values to the entered design format after the design has been placed and routed in a field-programmable gate array (FPGA).
Big Endian
A representation of a multi-byte value that has the most significant byte of any multi-byte data field stored at the lowest memory address. Also see Little Endian..
Bitstream
The bitstream is a binary representation of an implemented FPGA design. The bitstream is generated by Xilinx bit generation tools (BitGen and Makebits) and is denoted with the .bit extension. For information on creating BIT files, refer to the Hardware Debugger Reference/User Guide.
Block RAM
An 18 Kb block of random access memory (RAM) inside the Virtex-II Pro device. Dual-port and synchronous operation are desirable.
Block SelectRAM
Fully-synchronous, dual-port memories in the Virtex-II Pro FPGAs. Each of these memories contain 18 x 1024 (18,432) bits. The organization of each memory is configurable. Block SelectRAM
524
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Book E
A Motorola and IBM jointly written architectural definition and instruction set for embedded PowerPC implementations.
Boot ROMs
The program used to bring up a computer or system that is stored in Read Only Memory
Breakpoint
A location in a program at which execution is to be stopped and control of the processor switched to the debugger. Mechanisms for creating and removing breakpoints are provided by most debugging tools.
C
Cache
A small block of high-speed memory located between the processor and main memory. Cache stores frequently used data and instructions. Cache improves system performance by reducing the need to access the system's slower main memory.
Cache Block
See Cache Line
Cache Line
A portion of a cache array that contains a copy of contiguous systemmemory addresses. Cache lines in PPC405 are 32 bytes long and aligned on a 32 byte address.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
525
Glossary
Cache Set
See Congruence Class.
Capture Data
The flip-flop and pad data saved from the logic cells and I/O blocks into the bitstream for readback. Use the CAPTURE_VIRTEX primitive in your HDL code to specify the trigger and clock for the capture operation.
Channel Bonding
Feature of multi-channel high-speed transcievers. Allows multiple channels to be sued together, offering a greater aggregate bandwidth.
Chirp
Bit sequence which is transmitted by a high-speed transciever when it is not in use. The chirp is usually a repeating pattern of IDLE characters. The purpose of the chirp is to keep clock recovery circuits aligned and active while the link is not transmitting data.
526
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Coherency
Coherency describes the ordering of reads from and writes to a single memory location. A memory system is coherent when the value read from a memory address is always the last value written to the address. In a system where all devices read and write from a single, shared system memory, memory is always coherent.
Comma
A comma is a K character used by the transceiver to align the serial data on a byte/half-word boundary (depending on the protocol used), so that the serial data is correctly decoded into parallel data.
Common Mode
The DC component of a signal. In differential channels, it is the average voltage of the differential pair.
Compiler
Software that converts a higher-language description into a lowerlevel representation. For FPGAs, the complete partition, place, and process.
Configuration Bitstream
Configuration commands with configuration data.
Configuration Commands
Instructions for the Virtex-II Pro device. There are two classes of Configuration Command Major and Minor. The Major Commands read and write data to configuration registers in the Virtex-II Pro device. The Minor commands instruct the Virtex-II Pro configuration logic to perform specific functions.
Configuration Data
Bits that directly define the state of programmable logic. These are written to a Virtex-II Pro device in a configuration bitstream, and read as readback data from a Virtex-II Pro device.
Configuration File
The internally stored file that controls the FPGA sot hat it performs the desired logic function. Also, the act of loading an FPGA with that file. That is, the process of programming Xilinx SRAM-based FPGAs with a bitstream.
Configuration Frame
The configuration bits in a Virtex-II Pro device are organized in columns. A column of CLBs with the I/O blocks above and below the CLBs contain 48 frames of configuration bits. The smallest number of bits that can be read or written through the configuration interfaces is one frame.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
527
Glossary
Configuration Interface
A logical interface on the Virtex-II Pro device through which configuration commands and data can be read and written. A interface consists of one or more physical device pins.
Configuration Readback
The operation of reading configuration data (also known as readback data) from a Virtex-II Pro device.
Congruence Class
A collection of cache lines with the same index.
Constraints
Performance requirements imposed on the design, usually in the form of maximum allowable delay, or the required operating frequency.
Context Switch
The process of switching from one task to another in a multitasking operating system. A context switch involves saving the context of the running task and restoring the previously-saved context of the other.
Cross Compiler
A compiler that runs on a particular processor architecture and produces code for a different architecture.
Crosstalk
Undesirable signal coupling from noisy aggressor nets to victim nets. May be eliminated by increasing the spacing between the nets or reducing signal amplitude of the aggressor net.
CS Pin
The CS pin is the Chip Enable pin for Virtex-II Pro devices. It is used only in SelectMAP mode. When CS is asserted (Low) the device examines data on the Data bus. When CS is de-asserted (High), all CCLK transitions are ignored.
528
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
D
DataFrame
A DataFrame is a block of configuration data. A configuration bitstream contains many such frames, each with a start bit and stop bits. Also see Configuration Frame.
DC Balanced
A channel is said to be DC Balanced if it has an equal number of 1s and 0s transmitted across it. Encoding schemes like 8B10B are designed to ensure this.
DC Coupling
Method of interfacing drivers and receivers without the use of series capacitors. A direct connection (through PCB trace) from driver to receiver.
Debug Monitor
A piece of embedded software that has been designed specifically for use as a debugging tool. It usually resides in ROM and communicates with a debugger via a serial port or network connection. The debug monitor provides a set of primitive commands to view and modify memory locations and registers, create and remove breakpoints, and execute your program. The debugger combines these primitives to fulfill higher-level requests like program download and single-step.
Debugger
A software development tool used to test and debug embedded software. The debugger runs on a host computer and connects to the target through a serial port or network connection. Using a debugger you can download software to the target for immediate execution. You can also set breakpoints and examine the contents of specific memory locations and registers.
Deterministic Jitter
The component of jitter attributable to the data pattern in the channel. Different digital patterns have different spectral contents. These differing spectral contents give rise to varying amounts of signal jitter.
Dhrystone MIPS
Dhrystone is a benchmark program for testing a system's integer performance. The objective is to compare the performance of a machine against the performance of a reference machine. The industry
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
529
Glossary
has adopted the VAX 11/780 as the reference 1 MIPS (Million Instruction Per Second) machine.
Differential Signaling
A signaling scheme which uses two complementary signals to transmit data. Differential signaling offers faster data rates at reduced signal swing with higher signal-to-noise ratio.
DIN Pin
During serial configuration, the DIN pin is the serial configuration data input receiving data on the rising edge of CCLK. During parallel configuration, DIN is the D0 input. After configuration, DIN is a userprogrammable I/O pin.
Dirty Bit
A bit in a memory cache or virtual memory page that has been modified by the CPU but not yet written back to storage.
Dispersion
"Smearing" of a signal or waveform as a result of transmission through a non-ideal transmission line. Through a non-ideal medium, signals travel at different velocities according to their frequency. Dispersion of the signal is the result. All cables and PCB transmission lines are non-ideal.
DONE Pin
The DONE pin on a Xilinx FPGA is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a low level on DONE can be configured to delay the global logic initialization and the enabling of outputs.
Double Word
Eight bytes or 64 bits.
DOUT Pin
During configuration in any mode except Express and SelectMAP, the DOUT pin is the serial configuration data output that can drive the DIN pin of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it is received at the DIN pin (in Master Serial Mode only).
DOUT/BUSY Pin
For Virtex-II Pro devices, the DOUT/BUSY pin has a dual purpose, depending on device mode. When the device is in Serial mode, this pin functions as DOUT. When the device is in SelectMAP/Slave Parallel mode, this pin functions as a handshaking signal. If BUSY is asserted (High) on a rising edge of CCLK, the data is not seen on the data bus, and should be held until the data is accepted.
530
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
E
EDIF (Electronic Data Interchange Format)
Industry standard for specifying a logic design in text (ASCII) form.
Effective Address
The un-translated memory address as seen by a program.
Emulator
Short for ICE (In-Circuit Emulator).
Endianness
See Big Endian and Little Endian.
Equalization
Amplification or attenuation of certain frequency components of a signal. Used to counteract the effects of a non-ideal transmission medium.
Exception
An abnormal event or condition that requires the processors attention. They can be caused by instruction execution or an external
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
531
Glossary
device. The processor records the occurrence of an exception and they often cause an interrupt to occur.
Eye Diagram
An eye diagram of a signal overlays the signals waveform over many cycles. Each cycles waveform is aligned to a common timing reference, typically a clock. An eye diagram provides a visual indication of the voltage and timing uncertainty associated with the signal. It can be generated by synchronizing an oscilloscope to a timing reference. The vertical thickness of the line bunches in an eye diagram indicate the magnitude of AC voltage noise, whereas the horizontal thickness of the bunches where they cross over is an indication of the AC timing noise or jitter. Fixed DC voltage and timing offsets are indicated by the position of the eye on the screen.
Eye Mask
The size of the eye opening in the center of an eye diagram indicates the amount of voltage and timing margin available to sample this signal. Thus, for a particular electrical interface, a fixed reticule or window could be placed over the eye diagram showing how the actual signal compares to minimum criteria window, know as the eye mask. If a margin rectangle with width equal to the required timing margin and height equal to the required voltage margin fits into the opening, then the signal has adequate margins. Voltage margin can often be traded of for timing margin.
F
Fall Time
The time it takes for a waveform to transition from the high logic state to the low logic state. Fall time is usually measured from 90% of the total signal swing to 10% of the signal swing.
532
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Flash
Non-volatile programmable technology, and alternative to electrically-erasable programmable read-only memory (EEPROM) technology. The memory content can be erased by an electrical signal. This allows in-system programmability and eliminates the need for ultraviolet light and quartz windows in the package.
Flip-Flop
Single-bit storage cell that samples its data input at the active (rising or falling) clock edge, and then presents the new state on its Q output after that clock edge, holding it there until after the next active clock edge.
Flush
A cache or TLB operation that involves writing back a modified entry to memory, followed by an invalidation of the entry.
Frame
See Configuration Frame.
Function Generator
Also called a look-up table (LUT), with N inputs and one output. Can implement any logic function of its N inputs. N can be between 3 and 6; 4-input function generators are most popular.
G
Gate
Smallest logic element with several inputs and one output. The AND gate output is High when all inputs are High. The OR gate output is High when at least one input is High. The NAND gate output is Low
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
533
Glossary
when all inputs are High. A 2-input NAND gate is used as the measurement unit for gate array complexity.
Gate Array
An ASIC where transistors are predefined, and only the interconnect pattern is customized for the individual application.
GNU
A recursive acronym GNU Not Unix (pronounced guh-NEW). The Free Software Foundation's GNU project was launched in 1984 to develop a complete Unix-like operating system that is freely distributed.
H
Halfword
Two bytes, or 16 bits.
HardWire
Xilinx name for a low-cost derivative of an FPGA, where the configuration is fixed, but functionality and footprint are identical with the original FPGA-based design.
Harvard Architecture
Harvard architecture has separate data bus and an instruction bus. This allows instruction and data access in parallel making faster execution than a Von-Neuman architecture possible. PPC405 core is built on Harvard architecture.
Hierarchical Design
Design description in multiple layers, from the highest (overview) tot he lowest (circuit details). An alternative is flat design, where everything is described at the same level of detail.
534
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Hit
An indication that requested information exists in the accessed cache array, the associated fill buffer, or on the corresponding OCM interface.
HyperTransport
A high-performance bus solution developed by Advanced Micro Devices and several partners to break the I/O bottleneck in 32- and 64bit systems. HyperTransport provides a scalable architecture that provides better than an order of magnitude increase in bus transaction throughput over existing I/O bus architectures such as PCI, PCI-X and AGP. Formerly called Lightning Data Transport (LDT).
I
ICE (In-Circuit Emulator)
A debugging tool that takes the place of (emulates) the processor on the target board. Emulators frequently incorporate a special "bondout" version of the target processor that allows the user to observe and record its internal state as the program is executing.
Idle Pattern
A data sequence transmitted by a high-speed transciever as a placeholder or for link maintenance. The particular sequence of an IDLE pattern is determined by the communication protocol, and is usually a control character like K28.5.
Index Register
A special purpose register used by a processor when performing indexed addressing. The value in the index register is usually the reference location to which a displacement will be added.
INIT Pin
The INIT pin is a quadruple function signal. Before and during configuration, INIT is a bidirectional signal. A 1 - 10 k external pullup resistor is recommended. As an active-Low open-drain output, INIT is held Low during power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used to hold the FPGA in the internal WAIT state before the start of configuration. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O become active in the Startup sequence, INIT becomes a user-programmable I/O.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
535
Glossary
Instruction Set
Is referred to the set of instructions that the microprocessor can execute. The instruction set specifies the types of instructions (such as load/store, integer arithmetic, and branch instructions), the specific instructions, and the encoding used for the instructions. The instruction set definition also specifies the addressing modes used for accessing memory.
Interrupt Latency
The amount of time between the assertion of an interrupt and the start of the associated interrupt service routine.
Interrupt Vector
A special code that identifies the circuit requesting an interrupt.
IP (Intellectual Property)
In the legal sense, patents, copyrights, and trade secrets. In integrated circuits (ICs), predefined large functions, called cores, that help the user complete a large design faster.
J
Jitter
The jitter of a periodic signal is the delay between the expected transition of the signal and the actual transition. Jitter is a zero mean random variable. When worst case analysis is undertaken the maximum value of this random variable is used.
536
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Jitter Tolerance
Jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input that causes a predefined, acceptable loss at the output. For example jitter applied to the input of an OC-N equipment interface that causes an equivalent 1dB optical power penalty.
Jitter Transfer
Jitter transfer is defined as the ratio of jitter on the output of a device to the jitter applied on the input of the device, versus frequency. Jitter transfer is important in applications where the system is utilized in a loop-timed mode, where the recovered clock is used as the source of the transmit clock.
K
Kernel
An essential part of any multitasking operating system software which controls how the rest of the system can operate. The kernel is to software what the CPU is to hardware.
L
LAN (Local Area Network)
A computer network that spans a relatively small area. Most LANs are confined to a single building or group of buildings. However, one LAN can be connected to other LANs over any distance via telephone lines and radio waves. A system of LANs connected in this way is called a WAN (Wide Area Network).
Latency
The time between when something happens and when its response is generated. This is often critical in real-time applications
LC (Logic Cell)
Metric for FPGA density. The basic building block of the Virtex-II Pro CLB. An LC includes a 4-input function generator, carry logic, and a storage element.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
537
Glossary
Linker
A software development tool that accepts one or more object files as input and outputs a relocatable program. The linker is thus run after all of the source files have been compiled or assembled.
Little Endian
A representation of a multi-byte value that has the least significant byte of any multi-byte data field stored at the lowest memory address. Also see Big Endian.
LogiBLOX
Library of logic modules, often with user-definable parameters, like data width. Similar to LPM.
Logical Address
Synonym for effective address.
Loopback
Path in a high-speed transceiver which connects the output to the input, on either the PMA or PCS side, for testing purposes.
LUT SelectRAM
Shallow RAM structure implemented in CLB look-up tables (LUTs). Also see Block SelectRAM.
M
Machine Language
A computer language that is directly executable by a computer without the need for translation by a compiler or an assembler. Although the computer works on binary patterns, the program can usually be entered in octal or hexadecimal.
538
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Mapping
Process of assigning portions of the logic design to the physical chip resources (CLBs). With FPGAs, mapping is more demanding and more important a process than with gate arrays. Also see Synthesis.
Masking
A process in which an operation can be performed on a single bit.
Memory Map
Documentation that lists or shows the function of each location in memory.
Memory-Mapped I/O
A system of I/O in which each I/O location is treated as if it were memory.
MicroBlaze
A 32-bit soft processor developed by Xilinx
Miss
An indication that requested information does not exist in the accessed cache array, the associated fill buffer, or on the corresponding OCM interface.
Mnemonic
A easy to remember string representing a processor instruction. For example, EIEIO is the mnemonic of the PPC405 instruction Enforce In Order Execution of I/O.
Multilevel Signaling
System where multiple logic levels are utilized instead of just two (High and Low). This enables the tranmission of multiple bits in a single waveform. See http://www.signalintegrity.com/Pubs/misc/mls.htm.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
539
Glossary
MultiLINX Cable
The MultiLINX cable provides many complex functions and can be loaded with new firmware as it becomes available. It can be connected to the host computer in two ways: via a Serial port or a USB port. The MultiLINX cable is supported by the Hardware Debugger software for Slave Serial and SelectMAP/Slave Parallel programming (as appropriate), as well as readback/verify. It is also supported by the iMPACT software for JTAG programming of both CPLDs and FPGAs.
Multiprocessing
The use of more than one processor in a single computer system. Socalled "multiprocessor systems" usually have a common memory space through which the processors can communicate and share data. In addition, some multiprocessor systems support parallel processing.
N
Netlist
Textual description of logic and interconnects. Also see XNF File and EDIF (Electronic Data Interchange Format).
O
Object Code
The form of software after it has been translated (compiled) from the source code format a programmer writes into the machine format a microprocessor can understand. A set of processor-readable opcodes and data. The output of compilers, assemblers, linkers, and locators are files containing object code.
540
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
On-Chip Debugger
It can be considered as advanced on-chip debug monitor. It usually allows code download, memory/resource access, single stepping, reset, status, etc.
Optimization
Design change to improve performance. Also see Synthesis.
Overshoot
Phenomenon where a signal rises to a level greater than its steadystate voltage before settling to its steady-state voltage.
P
Pad
Pad bits are extra bits used to make the total number of bits in a frame an integral multiple of 32, the number of bits in a configuration word. A pad word is an extra word used at the end of a configuration frame for pipelining. A pad frame is an extra configuration frame used at the beginning of a configuration readback and at the end of a configuration write for pipelining.
Parallel Cable IV
Xilinx Parallel Cable IV (PC IV) is a high-speed download cable that configures or programs all Xilinx FPGA, CPLD, ISP PROM, and System ACE MPM devices. The cable takes advantage of the IEEE 1284 ECP protocol and Xilinx iMPACT software to increase download speeds over eight times faster than existing solutions.
Partitioning
In FPGAs, the process of dividing the logic into subfunctions that can later be placed into individual CLBs. Partitioning precedes placement.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
541
Glossary
PCMCIA
Personal Computer Memory Card Interface Association. Physical and electrical standard for small plug-in boards for portable computers.
Peak-to-Peak
In the case of peak-to-peak voltage, a measure of a signal's total amplitude. In the case of peak-to-peak jitter, a measure of the extremes of excursion of the bit transition times.
Physical Address
The actual address that is placed on the address bus when accessing a physically implemented memory location or register. This address can be translated from the effective address. When address translation is not used, this address is equal to the effective address.
Pin-Locking
Rigidly defining and maintaining the functionality and timing requirements of device pins while the internal logic is still being designed or modified. Pin-locking has become important, since circuit board fabrication times are longer than PLD design implementation times.
Placement
In FPGAs, the process of assigning specific parts of the design to specific locations (CLBs) on the chip. Usually done automatically. Also see Partitioning.
542
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
PowerPC
A RISC-based computer architecture developed jointly by IBM, Apple Computer, and Motorola corporation. The name PowerPC is derived from IBMs name for the POWER (Performance Optimization With Enhanced RISC) architecture.
Pre-emphasis
Pre-emphasis is magnitude boosting of high frequency spectral components before launching the signal (wave) onto the Transmission Line. Transmission Lines embedded in most standard PCB materials (FR4, Rogers 43xx, Nelco and Rogers) suffer varying degrees of dispersion and loss in the 1 gigahertz spectrum. This is mostly due to conductance losses (leakage from the copper trace to any other conducting structure) and Skin Effect. Dispersion is a phenomenon whereby spectral components travel at different velocities. The waveform looks smeared when it arrives at the receiver. Both of these "characteristics" play into a diminished and poorly received signal. By boosting the high freq. spectral components, the magnitude of these components can be diminished as the wave travels through the Transmission Line, but since it starts out larger than the lower frequency components, the composite signal arrives at the receiver looking the way it was intended. Pre-emphasis is done by simply increasing the maximum amplitude of the signal for one bit period. If the signal is 1 bit in duration, the amplitude is allowed to rise to a value which is some percentage
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
543
Glossary
greater in magnitude. At this point, if the signal is to stay at the same logic state, the driver sends a decreased magnitude signal, or nominal logic level. Every time a transition occurrs, the greater magnitude level is used. For all times after this that the same level is to be transmitted, the nominal magnitude is used.
Priority
the level of importance of an event. Most often, interrupts are assigned priorities.
Program Counter
A register that places addresses on the bus to retrieve information stored within a program.
PROGRAM Pin
The PROGRAM pin is an active-Low input that forces clearing of the FPGA configuration memory and is used to initiate a configuration cycle. While PROGRAM is held Low, the FPGA drives INIT Low and continues to clear the configuration memory. When PROGRAM goes High, the FPGA finishes the current clear cycle, executes another complete clear cycle, goes into a WAIT state, and releases INIT.
R
Random Jitter
Jitter caused by Power Supply noise, temperature variations and crosstalk.
Readback
Initiating a readback causes the configuration memory to become accessible to be serially clocked out and read from the device, or (bytewide in SelectMAP/Slave Parallel modes). The configuration memory contains the configuration data, facilitating a Read-Verification of the data. The configuration memory can also contain the CLB output logic states facilitating a Read-Capture of the internal logic states.ReadVerification and Read-Capture are used by the Hardware Debugger for hardware verification. For information on the readback specification and timing, refer to The Programmable Logic Data Book. For information on using the readback component in a design, refer to the Libraries Guide. For information on enabling the readback function in the Implementation Software, refer to the Development System Reference Guide. For information on using the Hardware Debugger refer to the Hardware Debugger Reference/User Guide. For information
544
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
on connecting the XChecker cable for readback, refer to the Hardware Users Guide.
Readback Data
Configuration data read from a Virtex-II Pro device. The data is organized as configuration frames.
Real Address
Synonym for physical address.
Real Mode
In real mode, programs address physical memory directly.
Register
A memory location that is part of a processor or an I/O device. In other words, it's not normal memory. Generally, each bit or set of bits within the register controls some behavior of the larger device.
Relative Addressing
An addressing mode that calculates a new address based on the position of an instruction within a program.
Ringing
Common name for the characterisitic waveform seen when a transmission line ends at a high impedance discontinuity. The signal first overshoots the target voltage, then sags below, then overshoots againand continues this oscillating pattern with decreasing swing amplitude until finally settling at the target voltage.
Rise Time
The time it takes for a signal to rise from 10% of its total logic swing to 90% of its total logic swing.
ROM Emulator
A debugging tool that takes the place of-or emulates-the ROM on the target board. A ROM emulator acts very much like a debug monitor, except that it includes its own serial or network connection to the host.
ROM Monitor
A piece of debugging code which usually communicates via a serial connection to a host computer or terminal. Also see Debug Monitor.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
545
Glossary
Routing
The interconnection or the process of creating the desired interconnection of logic cells to make them perform the desired function. Routing follows after partitioning and placement.
S
SAN (Storage Area Network)
A high-speed subnetwork of shared storage devices. A storage device is a machine that contains nothing but a disk or disks for storing data. A SAN's architecture works in a way that makes all storage devices available to all servers on a LAN (Local Area Network) or WAN (Wide Area Network).
Schematic
Graphic representation of a logic design in the form of interconnected gates, flip-flops, and larger blocks. Older and more visually intuitive alternative to the increasingly more popular equation-based or highlevel language textual description of a logic design.
SelectMAP Interface
One of the configuration interfaces on the Virtex-II Pro device. This is a byte-serial interface. The pins in the SelectMAP interface can be used as user I/O after configuration has been completed or remain configured as a configuration interface.
SelectRAM
Xilinx-specific name for RAM implemented in CLBs.
SERDES (Serializer/Deserializer)
A common name for a high-speed transciever that performs both parallel-to-serial and serial-to-parallel conversion.
Simulation
Computer modeling of logic and (sometimes) timing behavior of logic driven by simulation inputs (stimuli or vectors).
Single-Ended
Method of signaling which, unlike differential signaling, only transmits signals over one net.
546
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Slice
A subdivision of the Virtex-II Pro CLB. There are four vertical slices in each Virtex-II Pro CLB. Each slice contains two Logic Cells.
Soft IP
A synthesizable Intellectual Property which can be readily incorporated into an FPGA. Soft IP solves many of the time-to-market issues and also can simplify verification if a proper test bench is included.
Software Interrupt
An interruption of a program that is initiated by a software instruction. Software interrupts are commonly used to implement breakpoints and operating system entry points. Unlike true interrupts, they occur synchronously with respect to program execution.
SRAM
Static random access memory. Read-Write memory with data stored in latches. Faster than DRAM and with simpler timing requirements, but smaller in size and about four times more expensive than DRAM of the same capacity.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
547
Glossary
Stack
An area of memory used to implement a data structure that follows the last in, first out method of access. The stack is usually used by the processor to keep track of subroutine calls and returns.
Stack Pointer
A special purpose register that tracks the location of the last entry in the stack.
Static Timing
Detailed description of on-chip logic and interconnect delays.
Submicron
The smallest feature size is usually expressed in microns ( = one millionth of a meter, or a thousandth of a millimeter). The state of the art is moving from 0.35 to 0.25, and soon may reach 0.18. For comparison purposes, the wavelength of visible light is 0.4 to 0.8. One thousandth of an inch, or 1 mil, is 25.4.
Sync Word
A 32-bit word with a value that is used to synchronize the configuration logic.
Synchronous
Circuitry that changes state only in response to a common clock, as opposed to asynchronous circuitry that responds to a multitude of derived signals. Synchronous circuits are easier to design, debug, modify, and better tolerate parameter changes and speed upgrades than asynchronous circuits.
Synthesis
Optimization process of adapting a logic design to the logic resources available on the chip, like look-up tables, Longline, and dedicated carry. Synthesis precedes mapping.
T
TBUFs
Buffers with a 3-state option, where the output can be made inactive. Used for multiplexing different data sources onto a common bus.
Termination
Usually implemented with passive components, termination is used to interface drivers, receivers, and traces that have differing impedance values. Typically, device drivers and receivers do not match the impedance of the PCB trace that connects them.
548
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Termination resistors are employed to match the impedances of these components, maximizing signal transmission and reducing noise.
Timing
Relating to delays, performance, or speed.
Timing Driven
A design or layout method that takes performance requirements into consideration.
Trace
A PPC405 feature which supports tracing of the instruction stream being executed out of the instruction cache in real time.
Trap
1. A program interrupt, usually an interrupt caused by some exceptional situation in the user program. In most cases, the OS performs some action, then returns control to the program. 2. Internally generated exceptions that deal with such instances as arithmetic overflow, divide by zero, and bound check failure.
U
UART (Universal Asynchronous Receiver/Transmitter)
An 8-bit parallel-to-serial and serial-to-parallel converter, combined with parity and start-detect circuitry, and sometimes even FIFO buffers. Used widely in asynchronous serial communications interfaces, such as modems.
UI (Unit Interval)
Unit of time corresponding to one bit period. A unit interval is the time it takes to send one bit.
User Mode
User mode restricts access to some registers and instructions. Normally, application programs operate in this mode.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
549
Glossary
V
Virtual Address
An intermediate address used to translate an effective address into a physical address. It consists of a process ID and the effective address. It is only used when address translation is enabled.
Virtual Mode
In virtual mode, programs address virtual memory and virtualmemory addresses are translated by the processor into physicalmemory addresses. This allows programs to access much larger address spaces than might be implemented in the system.
VME
Older bus standard, popular with MC68000-based industrial computers.
Von-Neuman Architecture
Von-Neuman architecture has a shared bus for instruction and data access. Therefore simultaneous instruction and data transfer is not possible.
W
WAN (Wide Area Network)
A computer network that spans a relatively large geographical area. Typically, a WAN consists of two or more local-area networks (LANs).
Watchdog Timer
A hardware timer that is periodically reset by software. If the software crashes or hangs, the watchdog timer will expire, and the entire system will be reset automatically
Word
Four bytes, or 32 bits.
Write Back
A Cache write policy in which data written into the cache by the CPU is not written into main memory until that data line in the cache is to be replaced.
550
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
WRITE Pin
The WRITE pin is an input to Virtex-II Pro devices in the SelectMAP/Slave Parallel mode, indicating to the device which direction data is flowing on the Data bus. When WRITE is asserted (Low), data is entering the device (configuration). When WRITE is deasserted (High), data is leaving the device (readback). If WRITE changes state when the device isnt expecting it, an abort occurs. For more information on the WRITE pin, refer to The Programmable Logic Data Book, and in this User Guide, Design Considerations, page 67.
Write Through
A Cache write policy. A technique for writing data from the CPU simultaneously into the cache and into main memory to assure coherency
X
XNF File
Xilinx-proprietary description format for a logic design. Alternative is EDIF.
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
551
Glossary
552
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Index
Numerics
3-state output buffer 194 -l option 509 -m option 509 options 503 output files 502 PCF files 502 syntax 502 -w option 509 bitstream defined 524 encryption 269273 loading encrypted 272 block SelectRAM 123141 defined 524 timing model 36 timing parameters 37 board routability 489 board support package SeeBSP 525 boundary scan instruction set 322 mode 292 models 500 Boundary Scan Description Language (BSDL) 500 boundary scan interface defined 525 BSDL files 500 BSP 281 defined 525 buffers 3-state output 194 bidirectional LVDS 264 global clock 69 LDT 265 output 192 BUFGCE 82 defined 526 characteristic impedance See impedance characteristics land pads 490 checksum 512 ChipScope ILA 383 classification and export considerations 270 CLB defined 526 clearing configuration memory 294 CLK 108 CLK2X 100 CLKDV 100 CLKFB 96 CLKIN 95 clock de-skew 89 clock networks 6889 clocks 68 buffer input 71 distribution 68 forwarding 252 global buffers 69 global networks 68 multiplexer waveform 81 multiplexers 68 phase shifting 103 resources 69 coherency defined 527 comma defined 527 commands file, executing 512 compiler defined 527 memory 148 configuration 291 bitstream defined 527 Boundary Scan mode 292 clearing memory 294 -g option 503 JTAG 488 Master SelectMAP mode 292 Master Serial mode 292 mode pins 291 modes 291, 292 process 293 Slave SelectMAP mode 292 Slave Serial mode 292 conflict resolution 125 constraining placement 157
A
AC coupling defined 523 address mapping 132 addressing modes defined 523 addressing scheme 132 ALU defined 523 ASIC defined 523 Virtex-II Pro compared with 21 25, 481 asynchronous defined 523 ATM defined 523 IP core for 279, 282
B
BER 283 defined 524 BGN files 503 bidirectional LVDS 264 bidirectional signals 196 big endian defined 524 BIT files description 502 disabling 509 loading downward 512 loading up or down 512 loading upward 513 bit swapping description 511 disabling 511 BitGen -b option 503 -d option 503 description 501 disabling DRC 503 DRC file 503 encryption options 270 -g option 503 -h option 509 input files 502 -j option 509
C
cache defined 525 cache line defined 525 capacitors decoupling 484 cascadable shift registers 151 Cascading DCMs 95 CCLK 291 defined 526 and configuration mode 291 and master serial programming mode 304 CDR 23 defined 526 channel bonding
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
553
content-addressable memory (CAM) 151 control signals 89 CORE Generator system 274290 CoreConnect bus architecture defined 528 crosstalk 488 defined 528 CS pin defined 528
D
Data Encryption Standard (DES) 269 DC coupling defined 529 DCI 224243 I/O buffer library 231 software support 231 DCM 89, 89122 clock de-skew 90 control signals 89 frequency synthesis 89, 99 legacy support 98 miscellaneous timing parameters 63 operating frequency ranges 60 overview 89 phase shifting 89, 103 port signals 95 timing model 60 waveforms 119 DCMs cascading 95 clock de-skew 89 control signals 89 frequency synthesis 89 phase shifting 89, 103 port signals 95 waveforms 119 DCR defined 529 and processor block timing model 65 DDR I/O 243257 input 243 output 245 output with 3-state control 247 SDRAM 251 debugger defined 529 hardware 509 debugging using ChipScope ILA 383 decoupling capacitors 484 dedicated pins 291 DES 269 de-skew circuit 94
differential signaling 265 defined 530 Digital Clock Manager (DCM) 89 DIN pin defined 530 distributed SelectRAM 141151 DLLs characteristics 94 source clock input 95 DONE pin defined 530 DOUT pin defined 530 DOUT/BUSY pin defined 530 DRC disabling for BitGen 503 DRC file 503 DSOCM defined 531 See OCM: data side DSP 24, 279, 280, 286 defined 531 dynamic read operations 152
G
global clock buffers 69 global clock nets 68 global clocks input to output timing parameters 56 setup and hold timing parameters 58 GTL 208 GTL+ 209
H
Hardware Debugger 509 Harvard architecture defined 534 HSTL_I 210, 214 HSTL_II 211, 215 HSTL_III 212, 216 HSTL_IV 213, 217 HyperTransport defined 535 See LDT
E
EDIF 134, 146, 148, 156, 251, 276, 278 defined 531 effective address defined 531 embedded multipliers 178 timing model 40 timing parameters 40 encryption BitGen options 270 bitstream 269273 ESD defined 531 export considerations 270
I
I/O banks 385 I/O Buffer Information Specification See IBIS I/O standards single-ended 187 IBIS 495, 496 advantages 496 file structure 496 generation 496 I/V and dV/dt curves 497 ramp keyword 497 simulations 498 simulators 499 IEEE 1149.1 500 IEEE 1532 500 impedance defined 535 INIT pin defined 535 input DDR 243 input files BitGen 502 PROMGen 510 instruction set defined 536 boundary scan 322 IOBs
F
fall time defined 532 FDDRCPE 250 FDDRRSE 250 FIFO 279 defined 532 application notes 134 generating async 123 sync and async using CORE Generator 141 fine phase adjustment 103 flip-chip advantages 480 flip-chip packages 480 frequency synthesis 89
554
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
3-state timing parameters 51 input timing parameters 44 output timing parameters 48 timing model 43 IOBUF 196 IOSTANDARD attribute 233 ISOCM defined 536 See OCM: instruction side
J
jitter defined 536 random defined 544 JTAG 488 defined 537
low voltage positive emitter-coupled logic (LVPECL) 266 LUTs 151 defined 538 as shift registers 151161 LVCMOS15 222 LVCMOS18 222 LVCMOS25 223 LVCMOS33 223 LVDS 258265 defined 538 3-state buffer termination 264 bidirectional 264 primitives 258 transmitter termination 262 LVPECL 266268 primitives 266 receiver termination 267 transmitter termination 268 LVTTL 221
N
National Institute of Standards and Technology (NIST) 269 NO_CHANGE mode 125
O
OBUF 192 OBUFT 194 OCM defined 541 and processor block timing model 65 on-chip peripheral bus See OPB OPB defined 541 and MicroBlaze 288 IP cores for 281 IP for 289 operating frequency ranges 60 optimization defined 541 output buffer (OBUF) 192 output DDR 245 with 3-state control 247 output drive strength 199 output files BitGen 502 name, PROMGen 513 overwriting 509 PROMGen 510 output power/ground pairs 201 overshoot defined 541 overview of user guide 17
K
keys 272 creating 270
M
mask file 509 Master SelectMAP mode 292 Master Serial mode 292 memory clearing 294 memory compiler program 148 MicroBlaze 288, 289 defined 539 MMU defined 539 modes configuration 292 boundary scan 292 master SelectMAP 292 master serial 292, 304 slave SelectMAP 292 slave serial 292, 306 NO_CHANGE 125 programming See modes: configuration READ_FIRST 125 WRITE_FIRST 124 MSK files 503 MultiLINX cable defined 540 Multiplexers 162172 multiplexers 162 clocks 68 large 162 primary/secondary global 72 wide-input 166 multipliers embedded 178 Multipliers, embedded 178186
L
land pad characteristics 490 land pads 490 LDT 265 defined 537 buffers 265 implementation 265 software primitives 265 See also HyperTransport lead-free packages See Pb-free packages legacy support 98 library primitives and submodules 79 Lightning Data Transport See LDT little endian defined 538 LL files 503, 509 loading 272 locked output 96 logic allocation file 509 logical address See effective address loopback See RocketIO transceiver loopback low voltage differential signaling (LVDS) 258
P
Packages flip-chip 480 thermal considerations 480 FF1148 package diagram 476 banked pin diagram XC2VP40 448 XC2VP50 446 composite pin diagram XC2VP40 447 XC2VP50 445 dedicated pin diagram XC2VP40 449 XC2VP50 449 FF1152 package diagram 475 banked pin diagram
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
555
XC2VP20 442 XC2VP30 439 XC2VP40 436 XC2VP50 436 composite pin diagram XC2VP20 441 XC2VP30 438 XC2VP40 435 XC2VP50 433 dedicated pin diagram XC2VP20 443 XC2VP30 440 XC2VP40 437 XC2VP50 434 FF1517 package diagram 477 banked pin diagram XC2VP50 454 XC2VP70 452 composite pin diagram XC2VP50 453 XC2VP70 451 dedicated pin diagram XC2VP50 455 XC2VP70 455 FF1696 package diagram 479 banked pin diagram XC2VP100 466 composite pin diagram XC2VP100 465 dedicated pin diagram XC2VP100 467 FF1704 package diagram 478 banked pin diagram XC2VP100 458 XC2VP70 460 XC2VPX70 463 composite pin diagram XC2VP100 457 XC2VP70 459 XC2VPX70 462 dedicated pin diagram XC2VP100 461 XC2VP70 461 XC2VPX70 464 FF672 package diagram 473 banked pin diagram XC2VP2 423 XC2VP4 421 XC2VP7 418 composite pin diagram XC2VP2 422 XC2VP4 420 XC2VP7 417 dedicated pin diagram XC2VP2 424
XC2VP4 424 XC2VP7 419 FF896 package diagram 474 banked pin diagram XC2VP20 426 XC2VP30 426 XC2VP7 428 XC2VPX20 431 composite pin diagram XC2VP20 425 XC2VP30 425 XC2VP7 427 XC2VPX20 430 dedicated pin diagram XC2VP20 429 XC2VP30 429 XC2VP7 429 XC2VPX20 432 FG256/FGG256 package diagram 470 banked pin diagram XC2VP2 400 XC2VP4 400 composite pin diagram XC2VP2 399 XC2VP4 399 dedicated pin diagram XC2VP2 401 XC2VP4 401 example pinout table 388 FG456/FGG456 package diagram 471 banked pin diagram XC2VP2 408 XC2VP4 406 XC2VP7 406 composite pin diagram XC2VP2 407 XC2VP4 405 XC2VP7 403 dedicated pin diagram XC2VP2 409 XC2VP4 409 XC2VP7 404 FG676/FGG676 package diagram 472 banked pin diagram XC2VP20 414 XC2VP30 412 XC2VP40 412 composite pin diagram XC2VP20 413 XC2VP30 411 XC2VP40 411 dedicated pin diagram XC2VP20 415 XC2VP30 415 XC2VP40 415
pads 490 defined 541 Parallel Cable IV defined 541 parallel termination 486 Pb-free packages 385 PC20-84 specification 516 PCB layout considerations 483 PCF files BitGen 502 PCI defined 542 PCI33_3 221 PCI66_3 221 persist option 292 phase shifting 89, 103 physical address defined 542 pin-locking defined 542 pinout diagrams 397 pins 291 chip enable See CS Pin 528 CS defined 528 dedicated 291 DIN defined 530 DONE defined 530 DOUT defined 530 DOUT/BUSY defined 530 dual-function 292 INIT defined 535 power 294 PROGRAM defined 544 types 386 WRITE defined 551 pin-to-pin timing model 55 placement constraints 157 defined 542 PLB defined 543 port addressing scheme 132 port signals 95 power analysis software 495 power pins 294 PowerPC 405 processor block timing model 65 pre-emphasis defined 543 primitives
556
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
LVDS 258, 266 PRM files 511 PROGRAM pin defined 544 PROMGen -b option 511 -c option 512 -d option 512 description 509, 510 examples 514 flow diagram 509 -help option 512 input files 510 -l option 512 -n option 512 -o option 513 options 511 output file name 513 output files 510 -p option 513 -r option 513 -s option 513 supported families 509 -u option 513 -x option 513 PROMs bit swapping 511 files, description 511 formats 513 loading files 513 multiple files 513 package specifications 515 sizes 513
S
SelectIO-Ultra single-ended resources 186224 SelectMAP See configuration modes SERDES defined 546 series termination 487 shift registers cascadable 151 fully synchronous 158 operation 151 static length 159 signals bidirectional 196 simulation 24, 119, 129 defined 546 simultaneous-switching output (SSO) 201 single-ended defined 546 I/O standards 187 SelectIO-Ultra resources 186224 Slave SelectMAP mode 292 Slave Serial mode 292 slew rate 199 slices 172 defined 547 SO20 specification 517 solder balls 489 specifications PC20-84 516 PROM packages 515 SO20 517 VQ44 518 SRL16 151 SRLC16 151 SSTL2_I 218 SSTL2_II 219, 220 STARTUP_WAIT attribute 96 static length shift registers 159 static read operations 153 Sum of Products (SOP) 172178 synchronous defined 548 synchronous DRAM 251
defined 548 parallel 486 series 487 techniques 200 thermal considerations 480 thermal management 482 Timing Analyzer 27 timing models 27 block SelectRAM 36 DCM 60 embedded multiplier 40 IOB 43 pin-to-pin 55 PPC405 65 RocketIO MGT 65 timing parameters block SelectRAM 37 embedded multiplier 40 general slice 29 global clock input to output 56 global clock setup and hold 58 IOB 3-state 51 IOB input 44 IOB output 48 miscellaneous DCM 63 slice distributed RAM 32 slice SRL 35 TMULT 40 transmission line effects 200, 485 TRCE 27 Triple Data Encryption Algorithm (TDEA) 269 Triple DES 269
R
rawbits file 503 RBT files 503 read operations dynamic 152 static 153 READ_FIRST mode 125 readback defined 544 register defined 545 ringing defined 545 on PC board signals 486 rise time defined 545 RocketIO transceiver loopback defined 538 timing model 65 routability guidelines 489 routing defined 546
V
VBATT 272, 387, 519 VCC decoupling 483 VCCAUX 387 VCCINT 387 VCCO 199, 387 verification using ChipScope ILA 383 VHDL and Verilog templates 115, 135, 144, 149, 160, 168, 174, 185, 252 Virtex-II Pro compared with ASIC 2125, 481 DCI 224243 DES 269 LUTs 151 multiplexers 162 package specifications 469 pinout diagrams 397 slices 172 VQ44 specification 518 VREF 199
T
TBUFs defined 548 termination
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
www.xilinx.com
557
W
wide-input multiplexers 166 WRITE pin defined 551 WRITE_FIRST mode 124
558
www.xilinx.com
Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
Headquarters
2100 Logic Drive San Jose, CA 95124 Tel: (408) 559-7778 Fax: (408) 559-7114 TWX: (510) 600-8750
European Headquarters
Benchmark House, 203 Brooklands Rd. Weybridge Surrey KT13 0RH United Kingdom Tel: +44-1-870-7350-600 Fax: +44-1-870-7350-601 Benelux Tel : +32-53-848310 Fax: +32-53-848311 France and Spain Tel: +33-1-34-63-01-01 Fax: +33-1-34-63-01-09 Germany, Switzerland, and Austria Tel: +49-89-93088-0 Fax: +49-89-93088-188 Italy Tel: +39-02-487-12-101 Fax: +39-02-400-94-700 Sweden, Norway, Denmark, and Finland Tel: +46-8-594-61-660 Fax: +46-8-594-61-661 United Kingdom and Ireland Tel: +44-870-7350-603 Fax: +44-870-7350-604
North America
Madison, AL Tel: (256) 722-4050 Fax: (256) 722-9912 Phoenix, AZ Tel: (480) 753-4503 Fax: (480) 753-4504 Irvine, CA Tel: (949) 727-0780 Fax: (949) 727-3128 San Diego, CA Tel: (858) 558-5974 Fax: (858) 558-6418 Sunnyvale, CA Tel: (408) 245-9850 Fax: (408) 245-9865 Greenwood Village, CO Tel: (303) 220-7541 Fax: (303) 220-8641 Winter Park, FL Tel: (407) 673-8661 Fax: (407) 673-8663 Schaumburg, IL Tel: (847) 605-1972 Fax: (847) 605-1976 Deephaven, MN Tel: (612) 473-4816 Fax: (612) 473-5060 Marriottsville, MD Tel: (410) 442-9748 Fax: (410) 442-9749 Nashua, NH Tel: (603) 891-1098 Fax: (603) 891-0890
Japan
Tel: +81-3-5321-7711 Fax: +81-3-5321-7765
For information on Xilinx North American Sales Representative offices, see http://www.xilinx.com/company/sales/na_reps.htm For information on Xilinx International Sales Representative offices, see http://www.xilinx.com/company/sales/int_reps.htm