Module-4

Sequential Circuits
Ms. P Binduswetha
Assistant Professor- ECE dept
M.Tech., (Ph.D)
[email protected]
Contents : Sequential Logic design
• Sequential Circuits & types
• Latches
• Flip-flops
• Excitation tables
• Flip-flop conversions
• Registers
• Shift Registers & its types
• Counters :
• BCD Ripple counters
• Synchronous Counters
• Ring Counters
• Johnson Counter
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 Types of Logic Circuits

Combinational Logic circuits

• Combinational Logic Circuits-outputs depend only on current
inputs

Sequential Logic circuits

• Sequential Logic Circuits-outputs depends not only on current inputs but also on
the past sequence of inputs
Combinational Vs Sequential Circuits

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 Sequential Circuits
• A combinational circuit produces output solely depending on the current input.
• But a sequential circuit “remembers” its previous state.
• Its output depends on present inputs and previous state.
• Some examples:
• Latches
• Registers
• Memory
• parallel to serial
• serial to parallel converters
• Counters
 Sequential Logic circuits & The Flip-Flop

Inputs .
Combinational
. Outputs Output depends on
. .
Logic Gates present input and past
sequence of inputs.
Need to remember past
history.
Memory Elements
(Flip-Flops)
Clock

The stored data can be changed by applying varying inputs. Flipflops and latches are fundamentally building blocks
of digital electronic system. Both are used as data storage elements and it is the basic one in sequential logic.

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 Latch vs Flip-flop
• Latch: Level sensitive device
• Positive Latches and Negative latches
• Can be realized using multiplexers
• Flip-flop: edge triggered storage element
• Can be implemented using latches
• Cascade a negative latch with a positive latch to obtain a positive edge triggered register
• Flip flop: bi-stable component formed by the cross coupling of gates.
• The primary difference between a D flip-flop and D latch is the EN/CLOCK input.
• The flip-flop’s CLOCK input is edge sensitive, meaning the flip-flop’s output
changes on the edge (rising or falling) of the CLOCK input.
• The latch’s EN input is level sensitive, meaning the latch’s output changes on
the level (high or low) of the EN input.
Latches & Flipflops
• In digital electronics, a latch is one kind of a logic circuit, as a bistable
multivibrator.
• It has 2 stable states namely active high & active low.
• It works like a storage device by holding the data through a feedback lane
or path.
There are basically 4 main types of latches & flip-flops: SR, D, T & JK. Major
differences in these types are the number of inputs they have and how
they change state.
SR flipflop active Low= NAND gates
SR flipflop active HIGH = NOR gates
Master-slave edge triggered Flipflos
 S-R Latch
• Set-reset latch
• Use NOR gate to construct a stable
state network

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 S-R Latch (cont.)

• When S=R=1, the S-R latch will not

operate properly. (Is it a stable state, if
S=R=1?)
• Q an P are not complementary.
• If S=R=1 changed to S=R=0, then the
network will oscillate assuming both
gates have the same delay. (Critical race
occurs)

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Transparent D-Latch

EN D Q Q
D Q
0 X Q0 Q0

1 0 0 1
EN Q 1 1 1 0

EN: Enable

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D Flip-Flop: Excitation Table

D CLK Q Q
D Q 
0 0 1
1  1 0
CLK Q
 : Rising Edge of Clock

Flip-flop output will go to a state determined by the logic levels present at its synchronous control inputs just
prior to the active clock transition.

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J/K Flip-Flop: Excitation Table J Q

CLK

K Q

J K CLK Q

0 0  Q0 No Change

0 1  0 Clear

1 0  1 Set

1 1  Q0 Toggle

 : Rising Edge of Clock

Q : Complement of Q

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 D Flip Flop with
master- slave
The output of a flipflop will not
• Master latch with a slave latch change state immediately after the
• State changes only at clock edge. application of clk signal or async
inputs.
• Falling edge.
The time interval between
the time of application of
the triggering edge or
async IP and the time at
which the output actually
makes a transition is called
the propagation delay
time of the flipflop.

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 POS & NEG Edge Triggered D
Positive Edge Trigger
D CLK Q Q
D Q 0  0 1

1  1 0

CLK Q
 : Rising Edge of Clock

D CLK Q Q
D Q Negative Edge Trigger 0  0 1
1  1 0
CLK Q
 : Falling Edge of Clock

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 POS & NEG Edge Triggered J/K
Positive Edge Trigger
J K CLK Q
J Q 0 0  Q0
0 1  0
CLK
1 0  1
K Q
1 1  Q0
 : Rising Edge of Clock

Negative Edge Trigger J K CLK

J Q Q0 0 
CLK Q00 1  0
K Q 1 0  1
1 1 
Q0 : Rising Edge of Clock
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Flip-Flop Timing
1
Data Input
(D,J, or K)
0

tS tH
Setup Time Hold Time
Positive 1
Edge
Clock 0

Setup Time (tS): The time interval before the active transition of the clock
signal during which the data input (D, J, or K) must be maintained.

Hold Time (tH): The time interval after the active transition of the clock
signal during which the data input (D, J, or K) must be maintained.

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 Signals : PRESET/ Direct SET Sd/ DC
Asynchronous Inputs SET and
CLEAR / CLR or direct RESET Rd or
Asynchronous inputs (Preset & Clear) are DC CLEAR
used to override the clock/data inputs and
force the outputs to a predefined state. PR
The Preset (PR) input forces the output to: D Q

Q 1 & Q  0
The Clear (CLR) input forces the output to: CLK Q

Q  0 & Q 1
CLR

PR CLR CLK D
PRESET CLEAR CLOCK DATA Q Q
1 1  0 0 1 Async inputs are override inputs, used
to override all other inputs in order to
1 1  1 1 0
place flipflop in one state or other.
0 1 X X 1 0 Asynchronous Preset
1 0 X X 0 1 Asynchronous Clear
0 0 X X 1 1 ILLEGAL CONDITION
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Flip-Flops & Latches
74LS74
Dual Positive-Edge-Triggered D Flip-Flops with
Preset, Clear, and Complementary Outputs

74LS76
Dual Negative-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs

74LS75
Quad Latch

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74LS74: D Flip-Flop

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74LS76: J/K Flip-Flop

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74LS75: D Latch

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 Flip-flop tables & equations

• Truth table : It describes how the outputs are obtained for

given input combinations.
• Characteristic table: It shows the next state when input and
present states are known.
• Excitation table: It explains the input required to get given
combination of present and next state.

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 Asynchronous inputs
• Why makes it a synchronous input?
• Used to change state of a system
• If not synchronized, the signals may violate the setup time or hold
time of a receiving device.
• Metastable behavior
• State in the middle of 1 and 0.

Significance of Race around condition?

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FLIPFLOP EXCITATION TABLE
• Excitation tables of a flipflops can be obtained from the truth tables
of the same.
• It indicates that inputs required to be applied to the flipflop to take it
from the present state to next state.

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FLIPFLOP EXCITATION TABLES

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Characteristic equation: It specifies the next state
of a device as a function of its excitation (inputs)

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FLIP-FLOP CONVERSIONS
• So, there will be total of twelve flip-flop conversions.
• Follow these steps for converting one flip-flop to the other.
• Consider the characteristic table of desired flip-flop.
• Fill the excitation values inputs of given flip-flop for each combination
of present state and next state.
• For eg, The conversion of flip-flops to a JK flip-flop is to cross connect
the Q and Q outputs with the S and R inputs through additional 3-
input AND gates .
• If the J and K inputs are both HIGH, logic “1” then the Q output will
change state (Toggle) for as long as the clock input, (CLK) is HIGH.

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Flip-flop Conversion block diagram

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SR flip-flop to JK flip-flop

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SR flip-flop to T flip-flop

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SR flip-flop to D flip-flop

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 Registers & shift Registers
• In order to store multiple bits of information, we require multiple flip-flops.
The group of flip-flops, which are used to hold/ store/new data into register
serial to parallel OR shift the data with in register(left or right) OR retrieve
the binary data is known as Register.
• If the register is capable of shifting bits either towards right hand side or
towards left hand side is known as Shift register.
• Register's output depends on the past and present states of the inputs. The
device which follows these properties is termed as a sequential circuit.
• They are a group of flip-flops connected in a chain so that the output from
one flip-flop becomes the input of the next flip-flop.
• A register is a group of flip-flops used to store a binary word. One flip-flop is
needed for each bit in the data word.
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 Shift Registers
• A shift register is composed of a cascade of flip-flops in which the output (Q)
of each flip-flop is connected to the data (D) input of the next flip-flop in the
chain. A serial input (SI) is applied to the data (D) input of the first flip-flop.
• A Shift Register can shift the bits either to the left or to the right. A Shift
Register, which shifts the bit to the left, is known as "Shift left register", and it
shifts the bit to the right, known as "Right Shift register".
• Loading a register: Transferring new information into the register. Requires a
load control input.
• Parallel loading: all bits are loaded simultaneously.

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Types of Shift Registers are :

• Serial In Serial Out [SISO]

• Serial In Parallel Out [SIPO]
• Parallel In Serial Out [PISO]
• Parallel In Parallel Out [PIPO]
• Bi-directional Shift Register
• Universal Shift Register

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The SISO shift register is one of the simplest of the four configurations as it has
only three connections, the serial input (SI) which determines what enters the
left hand flip-flop, the serial output (SO) which is taken from the output of the
right hand flip-flop and the sequencing clock signal (Clk).

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Summary:

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SISO shift right mode

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PIPO Shift Register

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 Parallel Input Serial Output (PISO)

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 PISO
• In this operation the data are entered parallel.
• Output of previous FF is connected to the input of the next via a
combinational circuit.
• The binary input data B0,B1, B2 & B3 is applied through the same
combinational circuit.
• There are 2 modes: Shift mode OR Load mode

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 Bi-directional & PISO registers

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 Bi directional Shift register

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4-bit Universal Shift Register

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Universal Shift Registers
• This register is capable of performing :
• Left shifting
• Right shifting
• Parallel loading
• Universal shift registers are used as memory elements in computers.
Unidirectional shift register is capable of shifting in only one direction.
• A Reg is capable of shifting in one direction only = Unidirectional S.R.
• A Reg is capable of shifting in both direction= Bi-directional S.R
• If a Reg has both shifts and parallel load capabilities= Universal S.R.
• Whose IP& OP= either serial or parallel form
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Universal Shift register

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Shift Registers quick summary

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 Applications of Shift Registers

1.For Temporary data storage.

2.For multiplication and division
3.As a delay line
4.Ring counters
5.Parallel to serial converter
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 Counters
• A Counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal.
• Counters are used in digital electronics for counting purpose, they can count specific
event happening in the circuit.
• For example, in UP counter a counter increases count for every rising edge of clock.
Not only counting, a counter can follow the certain sequence based on our design like
any random sequence 0,1,3,2… .They can also be designed with the help of flip flops.
• They are used as frequency dividers where the frequency of given pulse waveform is
divided. Counters are sequential circuit that count the number of pulses can be either
in binary code or BCD form.
• The main properties of a counter are timing , sequencing , and counting.
Counter works in two modes
• Up counter
• Down counter

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Counters
• Counters are broadly divided into two categories
• Asynchronous counter: In asynchronous counter we don’t use
universal clock, only first flip flop is driven by main clock and the clock
input of rest of the following flip flop is driven by output of previous
flip flops.
• Synchronous counter: Unlike the asynchronous counter, synchronous
counter has one global clock which drives each flip flop so output
changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than
asynchronous counter as it does not have cumulative delay because
of same clock is given to each flip flop.

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 Asynchronous Counter

It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pulse is encountered, Q1 is
changing when rising edge of Q0 is encountered(because Q0 is like clock pulse for second flip flop) and so on. In
this way ripples are generated through Q0,Q1,Q2,Q3 hence it is also called RIPPLE counter. A ripple counter is a
cascaded arrangement of flip flops where the output of one flip flop drives the clock input of the following flip flop

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Async & Sync counter differences

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Sync Vs Async counters

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• Kindly Refer suggested Digital Electronics course Text Books and other online like NPTEL resources for more
design practice with full focus…
• Kumar, Anand. A., Fundamentals of Digital Circuits.
• Digital design by M. Morris mano
• Fundamentals of Logic Design by Charles H. Roth
• Digital design by John F. Wakerly
• Fletcher, W.L., An Engineering Approach to Digital design
• Taub, H and D. Schilling, Digital Integrated Electronics & many more
• Try to study Literatures to grab more stuff & knowledge…

• It’s the right time to strain your nerves and show your Potentials…
• Happy & Safe Learning…
• Pasulurri Sweta
• [email protected]

Thanking You

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