MODEL TEST PAPER FIRST TERM EXAMINATION SEVENTH SEMESTER [B. TECH] EMBEDDED SYSTEM [ETEC-401] ‘Time: 1% Hrs. MM: 30 Note: Q. no. 1. is compulsory. Attempt any two questions from remaining. Q.1. (a) Explain the 8051 architecture with block di 7 is different from microprocessor. Bagram sana Ans. 8051 Architecture: extemal interupts On-chip — Interrupt ROM for Timer — i control program on & Ps counter . = | IL a Oe Bus 4110 Serial Contr! Ports Port , | | vy ! XD RXD 8051 is an 8-bit microcontroller introduced in 1981. It has 128 bytes of RAM, 4K bytes of on-chip ROM, two timers, one serial pot, and four ports (each 8-bits wide) all on a single chip. The 8081 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data at a time, Data larger than 8-bits has to be broken into 8-bit pieces to be processed by the CPU. 8051 can have a maximum of 64K bytes of on-chip ROM, but many manufacturers have put only 4K bytes on the chip. 8051 can have external memory also. We can connect 64KB of external ROM & G4KB of externa! ROM with it, RAM of 8051 is divided in four register banks, bit addressable memory anda seratch pad (general purpose storage). It also has SFR's (Special function register) like TMOD, TCON, IB, DPTR ete. Different SFR's have different functionality 8051 has the capability to communicate serially with IBM PO at different baud rates, Also, there are six different interrupt sources Reset, Timor 0, Timer 1, Bxternal interrupt 0 (INTO), External interrupt 1 (INT'L) and serial communication interruptSeventh Semester, Embedded System — % 8051 microcontroller is different from microprocessor in the sense that itis ha CPU along with a fixed amount of RAM, ROM and I/O Ports, timers and counters a single chip. While in designing a micro—processor based system these peripher need to be connected externally, which makes the system bulkier and much mi expensive, But microprocessor based systems have the advantage of versatility such | and that the designer can decide on the amount of RAM, ROM and I/O ports needed to fit the task at hand, This is not the case with microcontrollers, Q.1. (6) Discuss PSW of 8051. ‘Ans, PSW (Program status word) is an 8-bit register. It is used to indicate some conditions that result after an instruction is executed. cy [Ac [Fo[ si] Rs0 [ov [-[P CY = Carry Flag + snows carry or borrow after addition or subtraction, AC Auxilliary carry flag — itis set if there is a carry from D, to D, druing an ADD or SUB oe operation. ee P— Parity Flag— it reflects the number of sin Accumulator, P=1,for oddno, of | IC Y's and P= 0 for even no. of 1's = -_ 0, > overflow flag—> this flag is set whenever the result of a signed no. operation | is too large, causing the high-order bit to overflow into the sign bits 4 Te RSI, RSO > Register bank select bits ae RSL RSO Reg. bank pe 0 0 0 x o Z 1 Lt : 0 2 aS 1 3 FO Available to the user for general purpose, wag }-1. (e) Diffe Hatin j ji Q ot za ra ai pes eles absolute jump and relative jump. 41 Ans. It is executed by LCALL or LJMP instruc is instruction in which the first byte is the opcode and second and ee ae 3 i 61 nust be within 2k bytes becau: = 2 Diese ze as ey address, This is the main differ coma ene eye sl instructions. In LCAL] , Jump can be anywhere withi ile it ACALL, jump can be within 2K bytes of range only, t® O4 KB memory when a Relative jump : All conditional jumps are relative 7 a v jumps, For ex, :J%, JNO, te all such instructions have target add, Which is calestated ey the oaienee ot PC wei ie, relative to PC (Program counter), iy QL. (d) Differentiate between general p microcontroller. posse mioroprooessor and ‘Ans.1(d) Refer Q.No.1(b) of first term 2016 Q.1.(e) Discuss the 8051 architecture and discuss ts feature ‘Ans, Refer Q.No.1(d) of first term 2016titishaving nters ete. on peripherals traction, 1D or SUB odd no. of operation ejump. a B-byte resents ) can be 2-bytes sof the ACALL, while in C, JNB, ts of PC or and LP. University-{B.Tech. Akash Books MTP-3 Q.2. (a) Explain the features of PIC microcontroller. Ans. The features of PIC microcontroller are given below: 1. PIC uses harvard architecture and they are high peformance RISC processor Harvard architecture has the program memory and data memory as separate memories and are accessed from separate buses. 2. The register files/data memory can be directly or indirectly addressed. All special fucntion registers, including the program counter, are mapped in the data memory. 3. The program memory bus is 14-bits wide in PIC. The entire instruction is fetched ina single machine cycle. All the required information is contained within a instruction and executed in a single cycle. 4. When PIC is operated at its maximum clock rate, almost each intruction can be executed within 0.2us or five instructions can be executed per microsecond. 5. The PIC can put itself to sleep to save power during intervals when it has nothing todo. Thus, PIC supports a power saving SLEEP mode. A software command allows the PIC to enter into this mode. The PIC remains in SLEEP mode till it is resét again. 6.Asingle instruction of PIC can select and drive a single output pin high or low in its instruction execution time (0.2 us). A load of up to 25 mA can be driven by this pin. 7. There is a built-in serial peripheral interface. 8. The PIC can control up to 12 independent interrupt sources, 9. Analog to digital conversion function is supported by most of the PICs. Q.2. (b) Explain the features of 16C6X microcontroller. Ans. The core features of PIC16C6X microcontroller are stated below. 1, It is RISC processor and uses Harvard architecture, 2. The instruction set of PIC16C6X consists of only 35 single word intructions. 3. All instructions are single cycle intructions exept for program branches which are two-cycle. 4. It has interrupt capability. 5. Its operating speed i DO- 20 MHz clock input, DC - 200 ns instruction cycle 6. Ithas eight level deep hardware stack 7. It supports direct, indirect and relative addressing modes. 8, It has inbuild power-on-reset (POR) 9 It includes power-up time (PWR'T) and oscillator start-up timer (OST) 10, It aslo contains watchdog time (WD) with its own on-chip RC oscillator for reliable operation. 11, Ithas programmable code protection, 12. It supports a power saving SLEEP mode, 13, Ithas sel ctable oscillator options, 14, It includes low power, high speed CMOS EPROM/ROM. 16, Its design is fully static0! sor are ais oP ARAIT procapeat are cr i ARM ALEA (31.0) ‘Address register Address Incrementer Incrementer bus |» nEXEC Register bank + DATA32 (31 * 32-bit registers) : [¢— BIGEND (status registers) }+— PROG32 }*— MCLK —— | + nWalr [> nw ; | + new Booth's Instruction [Fira multiplier decoder [f_ MRO and |g nRESET { centro! fe — ABORT Booth’s a [> nOPC. multiplier [> nTRANS —— + [> nMREQ [> nSEQ 32-bit ALU [—> LOCK —> ncPl }e— CPA \*—cPB }— nM[4:0) ! [ Instruction pipeline Instruction pipeline and read data register and read data register Bie de) DBE DOUTI31:0]nENOUT DATA(31.0] 1 Instruction Pipeline and Read Data Register; It gets the content of i . ° e memory locatic pointed to by the address bus lines A[31:0}, of Address Rogister. The external 82-bit data-in lines DATA[31;0) put the content into this register, % 2. Instruction Decoder and Control Logic: It has @ ¢ i I " Li number of conti 3 determining the operation policy of the processor, Also, it outputs a ea ae signals useful for interfacing tho processor with other porphorals be 3, Addrens Register: It holds the address of tho noxt iy io J r ‘i ol oxt instruction/dati Address bus A131:0) originates from it, Tho input signal ALB dotemrainea von cad . which the register’s contont romain ayaiuble on the AL31:0) li Seta ramaiinh lines, Content is availab 4, Address Incrementer; Winerements the Addross Register’ a amount to point to the next instruction/data, ister valuehy an. sreronrl aay: LP. University-{B.Tech.]-Akash Books MTP-5 5. Register Bank: It contains 31,32-bit register accessible in different modes of operation of the processor. it also contains 6 status registrs, each of size 32-bits. 6. Booth's Multiplier: It is used in the multiplication instructions, 7. Barrel Shifter: One of the operands of data processing instruction can be shifted by a few bit positions. The barrel shifter located at the input of ALU performs this function. 8, ALU; A 32-bit ALU performs the arithmetic and logic functions. 9. Write Data Register: It holds the value to be written into the memory. The 32-bit value is available in the DOUT [31:0] Q.3. (6) What are the control and status signals in ARM7 processor. Ans. Control and Status Signals inARM7 Fig. 2.2 Shows a functidnal diagram of ARM7 CPU. The signals can be grouped as per their functionality. based on this, the signals can be grouped as: + Processor mode: includes the signals nM[4:0]. * Memory interface: A[31:0], DATA[31:0], DOUT (31:0), nENOUT, nMREQ, SEQ, nREW, nBW, LOCK. + Memory management interface. nTRANS, ABORT. * CLock signals: MCLK and nWAIT. * Configuration signals: PROG32, DATA32, BIGEND: + Interrupts: nIRQ, nFIQ « Bus control signals: ALE, DBE. * Power lines: VDD and VSS. * Special signals: nEXEC and nRESET. Q.4. (a) What are the instruction set of ARM processor. Ans. Instruction Set: The instruction set and addressiong modes are strucutred to give minimum memory reference instruction. Three registers, the stack pointer (R15), the program counter (R14) and the link register (R13) make the program flow finely optimized. The instructions are described within the following major categories: + Data movement instruction + Aritimetic instructions * Logical instruction * Branch instructions * Load instructions * Store instructions * Swap instructions * Co-processor instructions The addressing modes appear simple but are quite extensive. The addressing modes vary with the processor instructions. The possible modes for (Version 4 ARM) are as follows: * Mode 1 ; Shifter operands for data processing, * Mode 2 ; Load and store unsigned byte * Mode 3 ; Load and store half word or signed hyte * Mode 4; Load and store multiple * Mode 5; Load and store co-processor For each of thes instruction groups there are specific addressing modes.ded System Seventh Semester, Em ae 7 tructions. i oer erie ee ARM processor fopPOTEs too ier cet nen od THUMB, While the ARM instruction set sone sored ae Pers ltcsarss tot intent, Pee atractond cha Cae " in Fane aaeeguseahows the THUMB instruction decompressor. processor. aa eo 1 THMBnucton srt cosa er rere Bas, ‘Var a AT [ash] [eeesnntae] [RES 1 pee Set to is ‘Thumb decompressor Select high or low half-word Instruction pipeline ¥ data in from memory Fig. THUMB instruction decompressor THUMB instruction set must always be entered by running a BX/BLX instruction, ‘These instructions are similar to their ARM counterparts, with a few exceptions, ¢ 1. THUMB instructions are executed unconditionally, excepting the branch instructions. 2. THUMB instructions have unlimited access to registers RO-R7 and R13-R15, A reduced number of instructions ean’ access the fullregiste cor Only a few instructions can access registers RB-R12, 3. The instructions look more |i example, instructions like PUSH and POP are present forstack aren the final implementation is via the ARM multibyte transfer instrueti¢ a descending stack with the stack pointor hardwired te Ria. 4. No MSR and MRS instructions, ke @ conventional processo:ction MODEL TEST PAPER Presa SECOND TERM EXAMINATION ated by, SEVENTH SEMESTER [B. TECH] EMBEDDED SYSTEM [ETEC-401]. ime: 144 Hrs. MM :30 Note: @. no. 1. is compulsory. Attempt any two questions from remaining. Q.1. (@) What is the use of watch dog timer? Ans. Watch Dog Timer: It is timing device that can be set for a preset time interval and an event must occur during that interval else the device will generate the timeout signal. For example we anticipate that a set of tasks must finish withing 100 ms. The WDT disables and stops in case the tasks finish within 100 ms. The WDT generates interrupts after 100 ms and executes a routine that runs because the tasks failed to finish in the anticipated interval. WDT has a no.of applications, One application in a mobile phone is that the display is turned off in case no GUI interaction takes place within a specified time. Another application in a mobile phone is that if'a given menu is not selected by a click within a present time interval another menu can be presented or beep can be generated to invite user's attention. Q.1. (6) Explain inter task communication. Ans. Inter task communication: Multitasking systems can handle data sharing and hardware resource among multiple tasks. Itis usually "Periloces” for two taks to access the similar specific data or hardware resources simultaneously. There are three general approaches to resolve this problem. * Temporarily masking or disabling interupts * Message passing * Binary semaphores. Q.1. (c) What is the meaning of task service function. Ans. Task: Task is the term used for the process in the RTOSes for the embedded systems. A task consists of a sequentially executable programs under a state-control by an OS. The state information of a task is reprsented by the task state 9running, blocked or finished), task structure-its data, objects and resources and task control block. So, task is defined as embedded rpgram computational unit that runs on a CPU under the state control of kernal of an OS ion, Q2. (a) Differentiate real time operating system and typical operating systems. Fah Ans. RTOS: An RTOS is a multitasking OS for the applications needing meeting of time deadlines and functioning in real time constraints, Real time constraint mea constraint on time interval between occurence of an event and system expected response ba to the event. ons RTOS provides some additional services along with basic OS services. And these are: Be * Process priority allocation gh + Pre-emption ents: * Process predictability * Memory Management * Asynchronous 1/0 subsystem,yo si . : = ‘MTP Seventh Semester, Embedded System = Q.2. (b) What is the importance of device management in an embedded system. a re, ‘Ans.2. (6) Device Management: An embedded system is designed to multiple functions and has to control multiple physical and virtual devices, devices are like timers, keyboards, display, flash memory ete. "i Virtual devices are like a file, a pipe, a socket etc. A device driver is software of opening, connecting or binding reading writin Inte closing or controlling actions of the device. It accesses a parallel or serial port when an ex mice, disk, pipe and socket at specific address. "itl devices sue A device manager software provide code for detecting the presence of devig Q4. (a initialising these and for testing the devices that are present. the manager ingly Ans. I software for allocating and registering port addresses for the various devices at disting operating different address, including codes for detecting any collision between these, if amy 4} Possible to ensures that any device accesses to one taks only ata any given instant, time-sensi Q.3. (a) What are the kernels of RTOS. a Ans. A Real Time Operating System can provide many resources to applica) product a writers - including TCP/IP stacks, files systems, etc. The Kernel is the part of f od operating system that is responsible for task management, and interta mati communication and synchronisation. Free RTOS is a real time kernel. Saute ‘The heart of a real-time OS (and the heart of every OS, for that matter) is the ker controller Akernel is the central core of an operating system, and it takes care of all the OS Instead o 1. Booting and nom-1 2, Task Scheduling ts 3. Standard Funetion Libraries > Now, we will talk about booting and boot-loaders later, so we should mentional] gy least one thing about standard function libraries: In an embedded system, thereis ieee enough memory (if any) to maintain a large function library. If ‘are goingtobe] time included, they must be small, and important, eee =e In an embedded system, frequently the i anit «a ; ly the kernel will boot t i ports and the global data items. Then, it will start the cehed nee eatialize = hardware timers that need to be started. Afte ihe een a = out of memory (except for the library fancecrg atthe Kemel basically gets dum ‘ane running the child tasks, 7 Mactions, ifany), and the scheduler will bare Q8. (b) Explain multitasking in RTOS, aan Ans. Multitasking, in an operatin j ita operating system is able to keep track of where you erage ge ora at a tes persia to the other without losing information, You are in these tasks and go from can ocet In the case of a computer with a operatio the cas sin any point in time, meaning that the CPU eatin cag atk it aid tobe aa “a Multitasking solves the problem by scheduling wine es instructions for that new vale any given time, and when anotho, ne which task may be the one runnint on thalt v waitit get CPU from one task o another ones ealednan ees vi is achieved when context switches occur fy adopt one of many different scheduling at ein multiprogramming ‘systems, the an operation that requires waiting for 4 rategios, running task ke ops runnit it Mn external event (og eee a at t (¢.g. reading from a tape)”for a w eee LP. University-[B.Tech.-Akash Books ieee until the computer's scheduler forcibly swaps the runn Multiprogramming systems are Seen to masilte CPU weaset okt Gish * In time-sharing systems, the running task is required to rel é voluntarily or by an extornal event sich asa Hardware interupk Ide rtepor sia are designed to allow several programs to execute apparently simultaneously, * In real-time systems, some waiting tasks are guaranteed to be given the CPU when an external event occurs. Real time systems are designed to control mechanical devices such as industrial robots, which require timely processing, 4, (@) Explain real time linux, Ans, RTLinux is a hard realtime RTOS microkernel that runs the entire Linux ‘operating system as a fully preemptive process. The hard real-time property makes it Possible to control robots, data acquisition systems, manufacturing plants, and other time-sensitive instruments and machines from RTLinux applications. RTLinux was developed by Victor Yodaiken, Michael Barabanov, CortDougan and others at the New Mexico Institute of Mining and ‘Technology and then as a commercial product at FSMLabs The key RTLinux design objective was to add hard real-time capabilities to a commodity operating system to facilitate the development of complex control programs with both capabilities. For example, one might want to develop a real-time motor controller that used a commodity database and exported a web operator interface. Instead of attempting to build a single operating system that could support real-time and non-real-time capabilities, RTLinux was designed to share a computing device between a real-time and non-real-time operating system so that (1) The real-time operating system could never be blocked from execution by the non-real-time operating system and (2) Components running in the two different environments could easily share data. As the name implies RTLinux was originally designed to use Linux as the non-real- time system but it eventually evolved so that the RTCore real-time kernel could run with either Linux or BSD UNIX. Q-4. (b) Discuss the problem of sharing data by multiple tasks and routines. What is the solution for shared data problem, Ans, Shared data problem: Assume that several function share a variable, Suppose the variable is of 128 bits & the processor is of 92 bits, The operations of the variable will be using four 32-bit ALU operations, Assuming that the 128-bit operation on the variable is non-atomic (Atomic operation is one, which can't be subdivided into suboperations or none of the suboperations can be left incomplete and no other operation can stort before all suboperations are complete), But in non-atomie operation, the operation can be interrupted before all the Four operations are completed, An interrupt can oceur at the end of each 32-bit ALU Operation, not necessarily at the end of 128-—bit operation, Therefore, the called 181k or another function can use the incompletely operated variable or can change that variable whon it shares with another function, on return, new values of that variable will be found and the incomplete operations will be performed on that new 128-bit variable in place of the old one,: aa sa T TERM EXAMINATION [SEPT. 2016] _ , ; SEVENTH SEMESTER [B.TECH] EMBEDDED SYSTEM [ETEC-401] ime: 14 brs. MLM.:30 | Note: Attempt any two more question from the rest. Question No.1 is compulsory. Q. 1.All Question are compulsory 5 i Q. 1. (a) What is Embedded System? Explain with the help of suitable | a examples. What are the characteristics of Embedded System? @) ‘Ans. An embedded system is a system that has embedded software and computer- hardware, which makes it a system dedicated for an applications or specific part- of an application or product or a part of a larger system. ‘Applications: Embedded systems have very diversified applications. A few selected application areas of embedded systems are telecommunications, smart cards, missiles and satellites, computer networking, digital consumer electronic and automotives. Q.1. (b) What is the difference between Microcontroller and Microprocessor? _ Write any three differences. @) ‘Ans. Difference between microprocessor and microcontroller: (i) A microprocessor is a single chip CPU whereas a microcontroller has CPU and much of the remaining circuitry to make a microcomputer. (ii) Microprocessor has many opcodes for moving data from external memory to the CPU but microcontroller has one or two (iii) Microprocessor may have one er two types of bit handling instructions, microcontroller have many bit handling instructions (iv) Microprocessor is concerned with rapid movement of code and data from external address to the chip but the microcontroller is concerned with rapid movement of bits wi thin the chip. Qu. (c) Discuss the difference between General Purpose and Embedded System. Give suitable examples. (2) ‘Ans. General Computer System is a computer that is built to be customizable in software, like desktop PCs and laptops, we can make it do many thing, sometimes together, with low or no constraints on power, performance or cost, also a general computing system is contained in itself, it's not a part of a larger system butt is the system itself. Embedded System, as it appears from its name, is a part of a bigger system, a computer restricted to one function (or a finite set of functions) that controls, monitors ’ or integrate with larger systems like automotive, robotics, home appliances and military applications. , Q.1. (d) Draw the 8051 architecture and discuss its features. @) 1 has 128 bytes of RAM, 4K bytes of on-chip ROM, two timers, one serial port, and four ‘Ans. 8051 Architecture: 8051 is an 8-bit microcontroller introduced in 1981. It input/output ports (each 8-bits wide) all on a single chip. The 8051 is an 8-bit processor meaning that the CPU can work on only 8 bits of data at a time. Data larger than 8-bits has to be broken into 8-bit pieces to be processed by the CPU, 8051 can have a maximumSeventh Semester, Embedded System 2-2016 3 K bytes of on-chip ROM, but many manufacturers have put only 4K byte of 64K bytes of on- : “chip. External interrupts On-chip i Interrupt ROM fer program “ control cca Qs Bus a Control o LP a XD RXD 20 tH} 8051 can have external memory also. We can connect 64KB of external. ROM = S4KB of external ROM with it. RAM of 8051 is divided in four register banks, Addressable memory and a sératch pad (general purpose storage). It also has SI {Special function register) like TMOD, TCON, IE, DPTR ete. Different SFRts different functionality. 8051 has the capability to communicate serially with IBM PC at different todo. Thx Jrlesrcnag there are six different interrupt sources Reset, Timer 0, Timer 1, Ext ¥ interrupt 0 (INTO), Exte: interrupt 1 (INT1) ang 8051 microcontroller is different from microproce CPU along with a fixed amount of RAM, ROM and /O. 4 single chip. While in designing si to be connected externally, which makes the sy m bulkier and much ‘ redo miewprocean rated systems have the advantage of verantititf eactide on the amount of RAM, ROM and 1/0 ports needed to fit serial communication inten essor in the sense that it is hal Ports, timers and counters et ‘nicro—Processor based system these per task at hand. This is not, the ® case with microcontrollers teghatoe 1 (Describe the RAM architecture of 8051. “ea Ans, RAM @Etage a ane! RAM 016061 1s Ofsli6 128 Byton, 80 ite addyons go is 00-7FH. RAMs conta logte unite +4 Memory banks (Bunk 0,1, 9, 4) O00-(RH RANGE programe » 16-byten of bitaddonsuble migmory Ss + Scratch Pad RAM of 80 bytoyLP. University-(B.Tech)-Akash Books 2016-3 Bank 0 (Address Range : 00-07H) Bank 1 (Address Range : 08-0F H) Bank 2 (Address Range: 10-17 H) Bank 3 (Address Range : 18-01F H) Address TF Scratch-Pad 30H a 2FH Bitaddressable ae RAM om Bank3 18H | a7 Bank 2 | 10H OFH Bank 1 oot ore mit Banko Q.2. (a) What is PIC? What are the features of PIC processor? ) ‘Ans. The features of PIC microcontroller are given below: 1. PIC uses harvard architecture and they are high peformance RISC processors. Harvard architecture has the program memory and data memory as separate memories and are accessed from separate buses. 2. The register files/data memory can be directly or indirectly addressed. All special fuention registers, including the program counter, are mapped in the data memory. 3. The program memory bus is 14-bits wide in PIC. The entire instruction is fetched ina single machine cycle. All the required information is contained within a instruction and executed in a single cycle. 4, When PIC is operated at its maximum clock rate, almost each intruction ean be executed within 0.2u8s or five instructions can be executed per microsecond, 5. The PIC can put itself to sleep to save power during intervals when it has nothing todo, Thus, PIC supports a power saving SLEEP mode. A software command allows the PIC to enter into this mode. ‘The PIC remains in SLEEP. mode till itis reset again. 6. Asingle instruction of PIC can select and drive a single output pin high or low in its instruction execution time (0.2 is). A load of up to 25 mA can be driven by this pin. 7. There is a built-in serial peripheral interface 8. The PIC can control up to 12 independent interrupt sources 49, Analog to digital conversion function is supported by most of the PICs. Q. 2, (b) Explain Von-Neumann and Harvard architecture. What aro the technical reasons that Harvard architecture is better than Von Neumann architecture? 6) ‘Ans, The Von Neumann architecture describes a design architecture for an electronic digital computer with parts consisting of a processing unit containing an arithmetic logic unit and processor registers; a control unit containing an instruction register ancl program count Hoth data and instructions; external mass storage and input and output mechanisms,Seventh Semester, Embedded System 4-2016 Central Processing Unit Control unit | Output input Arithmetical logic unit _——# Device F I ‘Memory unit ‘The Harvard architecture is computer architecture with physically penarel@ and signal pathways for instructions and data. These early machines had data ston entirely contained within the central processing unit, and provided no access tal instruction storage as data, Programs needed to be loaded by an operator; the pr could not initialize itself. ALU Instruction Controt Data memory unit memory HD ‘The design ofa von Neumann architect 'ure machine is simpler than that ofa Ha: architecture machine, which is also a stor ‘ed-program system but has one dedicated of address and data buses for reading data from and writing data to memory, a another set of address and data buses for instruction fetching, Q. 3.(a) What are SFRs of PIC? Explain in details, Ans. SFR of PIC MICROCONTROLLER Fano) RAO) RW(O) RA) _R(1)_ AMX) RAVE). RAW) rat B76 BS Bd BIS Bk2. BRI BRO Ans. RIS! The STATUS register contains: the arithmetic status of the W register, the RESBIet Computin status and the bank select bits for data memory. One ehoald be careful when yriti 4 value to this register because if you do it wrong, the results may be different thi Expected. For example, you try to clear all bits using the CLAY” STATUS instructi@ aiff the result in the register will be QOOxxtxx instoad of the expected ovoda»G0. sua) The diff errors occur because some ofthe bits af this rogistor are not ortieaed soe corp tod OSH hardware as well as because tho bits 8 und 4 aro readable only, Foe theee reaeal oie it is required to change its content (for example, to change active bank),LP. University-(B.Tech)-Akash Books 2016-5 recommended to use only instructions which do not affect any Status bits (C, DC and Z). + IRP — Bit selects register bank. It is used for indirect addressing. *1— Banks 0 and 1 are active (memory location 00h-FFh) + 0—Banks 2 and 3 are active (memory location 100h-1FFh) + RP1,RPO — Bits select register bank. They are used for direct addressing. RPI RPO ACTIVE BANK 0 0 Banko” 0 1 Bank1 1 0 Bank2 ja 1 Bank3 e storage T0- Time-out ae 1 — After power-on or after executing CLRWDT instruction which resets watch- dog timer or SLEEP instruction which sets the microcontroller into low- process] consumption mode 0 After watch-dog timer time-out has occurred. PD - Power-down bit. 1—After power-on or after executing CLRWDT instruction which resets watch- dog timer. 0—After executing SLEEP instruction which sets the microcontroller into low- consumption mode. +Z-Lerobit 1 — The result of an arithmetic or logic operation is zero. 0—The result of an arithmietie or logic operation is different from zero. + DC - Digit carry/borrow bit is changed during addition and subtraction if an “overflow” or a “borrow” of the result occurs es 1—Acarry-out from the 4th low-order bit of the result has occurred. Ricated get 0—No carryout from the 4th low-order bit of the result has occurred. mory, and _* C-Carry/Borrow bit is changed during addition and subtraction ifan “overflow” or a “borrow” of the result occurs, ic. ifthe result is greater than 255 or less a than 0. 4 1—Acarry-out from the most significant bit of the result has occurred. 0—No carry-out from the most significant bit of the result has occurred. ces Q. 3, (b) What is the difference between CISC and RISC? Explain with name __ Suitable examples. List the controllers and processor with their classification interms of CISC and RISC. 6) Ans, RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction e RESET | Set Computing) are two computer architectures that are predominantly used nowadays, nwriting The main difference between RISC and CISC is in the number of computing cycles each ent thao of their instructions take, With CISC, each instruction may utilize a much greater truction, | "Umber of cycles before completion than in RISC, 00. Such ‘The differences are: ng tothe * CISC instructions utilize more cycles than RISC asons, if * CISC has way more complex instructions than RISC ), it 116 * geventh Semester, Embedded System a i RISC : : has fewer instructions than F 23 ee oan was tond to be slower than RISC implementa acute typically use CISC while tablets, smart phones other a Senta shown below represents the controller and processor with RI and SICS Control unit Leena Micro program Cache contol memory I Main memory CISC ARCHITECTURE Instruction cache Data Cache (Instruction) Main memory RISC ARCHITECTURE Q.4,(a) Explain the features of ARM. Ans, An ARM processor is one of a family of CPUs based on the RISCE instruction set computer) architecture developed by Advanced RISC Machi Feature of ARM processor are: * ARM makes 32-bit and 64-bit RISC multi-core processors. * RISC processors are designed to port } . 1 ied to perform a smaller number of types: instructions 60 that they can operate at r forming more instructions per second MIPS), Ni#her speeds worforming m * By stripping out unneeded instruct R E ctions and optimizing pathwayss Provide outstanding performance at-a fraction of the pare ae instruction set computing) devices, * ARM processors are extensive): ly used in consumer electronic ‘ayers and other mobile devices, 8 smart phones, tablets, multimedia plLP, University-(B.Tech)-Akash Books 2016-7 + Because of their reduced instruction set, they require fewer transistors, which | enable a smaller die size for the integrated circuitry (IC), Use + The ARM processor's smaller size, reduced complexity and lower power consumption makes them suitable for increasingly miniaturized devices, Ise * Load/store architecture + An orthogonal instruction set. * Mostly single-cycle execution, + Enhanced power-saving design. * Hardware virtualization support, Q. 4. (b) Explain the architecture of ARM processor. Ans. Refer Q. 3. (a) of End Term Examination 2016,EMBEDDED SYSTEM [ETEC—401] ime: 1.80 brs. MM. :30 Note:Note :@:No. 1s Compulsory. Attempt any two more question from the Q.1All Question are compulsory. Q.1 (a) What is Embedddea System? Exy ii ? plain with the examples. What are the characteristics of Embedde Synteny one ea Ans. An embedded system is a system that has embedded software and computer hardware which makes ita system dedicated for an applications or specific part of aa application or product or a part of a larger system: rest, Applications: Embedded systems have very diversified applications. A few selected application areas of embedded systems are telecommunications, smart cards, missiles and satellites, computer networking, digital consumer electronic and automotives. Q1 (b) What is the difference between Microcontroller and Microprocessor? Write any three differences? (2) Ans, Difference between microprocessor and microcontroller: (iA microprocessor is a single chip CPU whereas a microcontroller has CPU and much of the remaining cireuitry to make a microcomputer. (ii) Microprocessor has many opcodes for moving data from external memory to the CPU but microcontroller has one or two. (iii) Microprocessor may have one or two types of bit handling instructions, Ricrocontroller have many bit handling instructions. (iv) Microprocessor is concerned with rapid movement of code and data from external Address to the chip but the microcontroller is concerned with rapid movement of bits Within the chip. Q.1 (c) Discuss the difference between General Purpose and aioe stem. Give suitable example. Ans. Refer Q.1(c) of First Term 2016, Q.1 (d) Draw the 8051 architecture and discuss its features, ‘Ans. 8051 Architecture: 8051 is an 8-bit microcontroller introduced in 1981. It 1n-chip ROM, two timers, one serial port, and four jai 26 bytes of RAM, 4K bytes of on hip ingle chip. ‘The 8051 is an 8-bit processor, Mpuvoutput ports (each 8-bits wide) all on a sit oe piccene SIE CU nce ones ch len nanan “ : @) 151 can have external memory al¥0, four rogister banks, bit addressable fete ROM mihi, RAM of 0518 JE i ory and a scratch pad (general purpose NAVNHE save diffrent functionality, "ister like TMOD, TTCON, I, DPR ete, Differ2017 Seventh Semester, Embedded System 24 { Q.2(a) Pipeline ai diagram. Ans. T 1, PIC u Tiger Harvard are Counter and area 2, Ther fucntion regi 3. The pr ina single m and executed fe i 4. When ¥ executed wit 5. The Pl to do. Thus, P PIC to enter gsc Bus 40 Sol j its instacdaa cone cee j 7. There is HOH ! 8. The PIC / 9. Analogt ar J XD RxD | ‘The archits eS / 5 = C at different} 8051 has te capability to communicate serially with IBM PC at = rates. Also, there are six different interrupt sources Reset, Timer 0, Timer 1, Elf Ze soa Pt OCINTO), External interrupt 1 (INT) and serial communication int ren 8051 microcontroller is different from microprocessor in the sense that it is havin along with a fixed amount of RAM, ROM and I/O Ports, timers and counters él] Proasany ingle chip, While in designing a micro—processor based system these peripheral ta Dag Sonnected externally, which makes the system bulkier and much more expel But microprocessor based systems have the advantage of versatility such thil designer can decide on the amount of RAM, ROM and 1/O ports needed to fit thelil — hand. This is not the case with microcontrollers / Q.1 (©) Describe the RAM architecture of 80 register bank? ‘Ans. RAM of 8051 is of size 128 Bytes, So its address range is 00-7FH. RAM ay containing: > 4Memory banks (Bank 0,1, 2, 3) 7” Wrbytes of bit-addressable memor y > Seratch Pad RAM of 80 bytoy Bank 0 (Addross Range 00-071) Note: Higher order Harverd architect Bank 1 (Address Range ; 0g. ‘OF H) “ore | 2 Bank 2 (Address Ran, FH piers er Separate memories t Bank 3 (Address Range ; 18. O1P H) aures of PIC processor? Explain the ler with its operation and prone (5) ps, The features of PIC microcontroller are given below: | 4, When PIC is operated at its max; | executed within 0.2ns or five instructio 5. The PIC can put itself to sleep to todo. Thus, PIC supports ap PiCtoenter into this mode ‘imum clock rate, almost each intruction can be ns can be executed per microsecond. Save power during intervals when it has nothing ower saving SLEEP mode. A software command allows the ‘The PIC remains in SLEEP mode till it is reset again. §.Asitigle instruction of PIC can select and drive a single output pin high or low in its instruction execution time (0.2 us), Aload of up to 25 mA can be driven by this pin, 7. There is a built-in serial peripheral interface. 8. The PIC can control up to 12 independent interrupt sources. 9. Analog to digital conversion function is supported by most of the PICs. The architecture is given below. ie Data bus Pon -{ Program courier it bas EPROM 2 Tah ? tera. rogram Ee ae L, Ra errf memory (PERSE | | ‘eons “a teens (so roe le-rea RadTock: te. of Programa ram aca” E9 Pots 1s 0 ass 7 im RBONT 194 TSI) ta oe es [LJ oes ona rats 503 Re7.RB asl < ae od it andi Se de ae é Seoei| | [al Tae | || ster, x p fens racer |] We oa By 09 ol | aac | Wes poo Bey SS ‘1 P8eaciKour a £ aa a MACTR Vo0Ves 2 TATUS register. Note: Higher order bits are from the STATUS reglt “ere ch program and data are accossed form sehivgcturo in which program PIC16C61 uses a harverd archit ; arate memories using separate buses2017 Seventh Semester, Embedded Systen : 4 Address and data bus 5 i 14 of i ie bus in PIC16C61 is 14 ot wide, $0 CSC ape a sore is internal. . memory. All program memory is int q : ; 4 k ae PIC16C61 contains 8-bit ALU. 0 as oe perioral ‘hist i al 0} f ~ operations such as add, subtract, shift and logic: fe trontioned, arithmetic opertions are two's complement in nature. onic es Q.2.(b) Explain Interrupt in PIC architecture. What is INTCON? Explain; = the associated register with interrupts. and ar ‘Ans, Interrupts of PIC with ROM location is given as spa Interrupt rs ROM Location (Hex) inten Power - on Reset 0000 finish i High Priority Interrupt 0008 (Default upon power - on reset) WI | Low Priority Interrupt 0018 B Er Step in executing an interrupt present ‘Upon activation of an interrupt the microcontroller goes through the following st 1, It finishes the instruction it is executing and saves the address of the instruction (program counter) on the stack. 2. It jumps to a fixed location in memory called the interrupt vector table, interrupt vector table directs the microcontroller to the address of the interrupt routine (ISR). 3. The microcontroller gets the address of the ISR from the interrupt vector and jumps tot. It starts to execute the interrupt service subroutine unit it reaches last instruction of the subroutine which is RETFIE (return from interrupt exit). instruetio instructio) INTCON register is given below, * Bys el Provide ou ss instruction GIE TMROIE} INTOIE. Res GIE (Global Interrupt Enable) — : GIE = 0 Disables all inter z i leas the ae enabled individually" * 9,20 interrupt is acknowledged Re IfGIE = 1, interru, 0 J interruputs are allowed t ‘ setting the corresponding j enable eget: Bach intern ved Ms r interrupt source is enal ‘TMRoLe ig interrupt, enable bit, ‘Timer 0 interrupt enable =0 Disables Timor TOSBIT D6 ‘Timer 0 8 - bit/16 selector bit 1 = Timer0 is configured as an 8 - bit timer/countel Timer0 is configured as a 16-bit timer/counté TOCs Ds Timer clock source select bit 1 = External clock from RA4/TOCK I pin 0 = Internal clock (F,,./4 from XTAL oscillator) Timer0 source edge select bit 1 Increment on H- to- L transition on TOCKIBI 0 = Incerement on L- to-H transition on TOCKIB PSA D3 ‘Timer0 prescaler assignment bit : 1 = Timer0 clock in 0 =Timer0 clock inj TOSE D4 put bypasses prescaler, Put comes from prescaler® ‘TOPS2:TOPS0 D2D1D0 Timed preted selector if 900=1:2 Prescate value (Rose/ 4/2) 0001 = 1:4 Preseate value (fosd/ 44) 0108 Proscale value (Rose Proseale value (fos Procale value (Fos Prescale Value ( 1:128 Proscale value (FosTERM EXAMINATION SEVENTH SEMESTER [Rowe EMBEDDED SYsTE: 11% brs. 018) ER [B.TECH] =e M [ETEC~401] yanguno.Ziscompulsory. Attempt any two more Questions from heres. Qu-All Questions are compulsory. ; (a)Differentiate between Microcontroller and Microprocessor with t respect the ] jptheir architecture and instructions. (2) - Ans. Difference between microprocessor and microcontroller: and (i)A microprocessor is a single chip CPU whereas a microcontroller has CPU and uch of the remaining circuitry to make a microcomputer. rs, i ‘ uy (ii) Microprocessor has many opcodes for moving data from external memory to the CPU but microcontroller has one or two. (iii) Microprocessor may have one or two types of bit handling instructions, microcontroller have many bit handling instructions. (iv) Microprocessor is concerned with rapid movement of code and data from external address to the chip but the microcontroller is concerned with rapid movement of bits within the chip Q. 1. (b) What are the characteristics of Embedded System. (2) Ans. Characteristics of an Embedded System : * Single-functioned — An embedded system usually performs’a specialized operation and does the same repeatedly. For example: A pager always functions as a pager. ‘ * Tightly constrained — All computing systems have constraints on design metrics, but those on an embedded system can be especially tight. Design metrics is a measure of an implementation’ features such as its cost, size, power, and performance. Itmust be of a size to fit on a single chip, must perform fast enough to process data in real time and consume minimum power to extend battery life. * Reactive and Real time — Many embedded systems must continually react to o changes in the system’s environment and must compute certain results in real time is without any delay. Consider an example of a car eruise controller; it continually monitors Bg andreacts to speed and brake sensors. It must compute acceleration or de-accelerations a repeatedly within a limited time; a delayed computation can result in failure to control of ze | theear, 3 * Microprocessors based ~ It must be microprocessor or microcontroller based, a as its software usually embeds in ROM, It * Memory - It must haye a memory, ves not need any secondary memories in the computer. * Connected — It must have connected peripherals to connect input and output devices. and flexibility. Hardware . * HW-SW systems — Software is used for more featur isu “Used for performance and security.tn Semester, Embedded System ‘Seventl : rts in 8051 and PIC microcontroller, any Oe nave 4 VO ports each comprising 8 hy, cordingly in total of 32 inputoutpat pn sanected to peripheral devices are available for ugg ae is input/output ports. ‘They are used for the jn, ly has ieee Most of these port pins are mui athe ripheral features on the devices, Al] i be peripheral action is enabled in a pin, if r ions, The PIC 16F877 chip basically hag 5, 2-2018 Q.1.(c) How ‘the microco! PIC eeries normal interfacing with other cy ing alternate functi . directional. W! ‘chip are bi-direction: a as its general input/output functic peer ~ 1 Pui Q 1. (a) Discuss the difference between General Purpose and kj ‘System. Give: suitable examples. 2 ‘Ans. General Computer System is a computer that is built to be cus software, like desktop PCs and laptops, we can make it do many thing, together, with low or no constraints on power, performance or cost, also a computing eystem is contained in itself, i's not a part of a large system butit system itself. Embedded System, as it appears from its name, is a part of a bigger computer restricted to one function (or a finite set of functions) that controls, m or integrate with larger systems linke automotive, robotics, izome appliances and) applications. Explain with the help of 8051 example. peeecematn of time delay is most important concept in embedded 1e ey we need to generate precise time delay between two actions imi 0Ohe a stapplications, We-can generate the time + LOOPS or by using i ; delay using the techniquel in built, delay functions, a piss for generating precise Delay using 8051 Timers Fre Produce time delay accurately, ivide the time delay with timer clock Period, NNNNetime delay/} 085s 2Subtract the resulta, nt Value fi 36, MMMM =65536.NINNIY a 4.Convert the ditterey MLE Value to, pe: he hoxa decimal form, 4.Loud this value to the timer roy) TH = xx vee TL e¥VH @ 2% (a) Ex ai , architocturg, iM!” the PIC eh Itootury Now is this difteront fol Note: Higher o Harverd archi and data are aczesse Address aad d 1 Kx 14 of program: is Sit wide. ALU: The PICL operations such 38 mentioned, anithme Q.2 ©) Bxpla Ans, Memory| + Program M after we have Dart the program mem + Data Mem SPR (Special Fact We store in the Ds These two my She of them very * Data REP! Amemory that al ‘Tho PICLGF ord x 14 bit pro WNP it to the mi burnLP University{B.Tech}-Akash Books 5 The architecture is given below, oe 4; Program counter (Bata bus_§ ‘s ort 0 eas [uae fi (13:bi) reaisters am 3648 a Program 4 - Raarrock! Tsteton, raw nage Pots ; TTT Te Diectaae 7 CARaeMOR | oft Maieet ReonT i Re7RBt a 3. re ae Be) te 5 scveuxy LE Cer) Cc2CtKOUT Timer 0 Note: Higher order bits are from the STATUS register. Harverd architectures: PIC16C61 uses a harverd architecture in which program and data are accessed form separate memories using separate buses. Address and data bus: Address bus in PIC16C61 is 14-bit wide. So it can access 1 K x 14 of program memory. All program memory is internal. Data bus in PIC16C61 is 8-bit wide. ALU: The PIC16C61 contains 8-bit ALU. It is capable of performing arithmetic sperations such as add, subtract, shift and logical operations. Unless otherwise mentioned, arithmetic opertions are two's complement in nature. Q. 2. (b) Explain Memory interfacing in PIC architecture. Ans. Memory of the PIC16F877 divided into 3 types of memories: * Program Memory ~A memory that contains the program(which we had written), ‘er we have burned it. As a reminder, Program Counter executes commands stored in the program memory, one after the other * Data Memory — This is RAM memory type, which contains a special registers like SPR Special Faction Register) and GPR (General Purpose Register). The variables that "tore in the Data Memory during the program are deleted after we turn of the micro, which makes the access to each ated data bui These two memories have sepé ofthem very easy. “Aga Data a srasable Programmable Read-Only Memory) ~ vA EEPROM (Electrically Erasable Prog) Ren Only MeO ry that allows storing the variables as a result of burning the written prog PICIGF87XA devices have a 13-bit proj init bit program memory space, This memory is used to bore Maho the microcontroller: The PIC16F876A/877A devieos have : ram memory that can be electrically erased and reprogrammed Peram into the micro, we erase an old program and write anew one: n counter capable of addressing an 8K the program after we 8K words x 14 bitsof Bach cime we ramall, Return Retfie RE Stack Level 1 ‘Stack Level 2 ee a | Stack Level 8 Reset Vector t vector 0004h Interrupt 0005h ° Page O7FFh ‘o800h Page 1 On-Chip_ ore Program 1000h pean: Page 2 47FFH 1800h Page 3 1FFFh PIC16F876A/877A program memory map and stack Program Counter ofthe current ‘instruction. It is autor (PC) keeps track of the program execution by holding’ oe matically incremented to the next instructi the current ‘instruction execution. The PICIGF87XA family has an 8-level deep x 13-bit wide hardware st, stack space is not part of either Program or data space and the stack point readable or writable, In the PIC microcontrollers, this is a special block of] ‘used only for this purpose 1 rhe CALL instruction is us, address is copied to the Po, is pushed onto the stack when a CALL HEPUnte4, oF an interrupt causes’, branch. ‘The stack is popped in the RETURN, RETLW or a Rutty instruction execution The stack operates ay ' the “intern starts at address 0000 ~ Reset Pt service routine” (ISR).LP. University-{B.Tech]-Akash Books 2018-5 what is watchdog timer? Explain in context of ARM ‘ tosupport yours answer. and PIC. cs Watch Dog Timer: Its timing device that can be set for a preset time interval -must occur during that interval else the device will generate the timeout orexample we anticipate that a set of tasks must finish withing 100 ms, The jes and stops in case the tasks finish within 100 ms. The WDT yonralag after 100 ms and executes a routine that runs because the tasks failed to ‘nthe anticipated interval. 7 oThas a no.of applications. One application in a mobile phone is that the display Jared off in case no GUI interaction takes place within a specified time. Another Gpisstion in a mobile phone is that if a given menu is not selected by a click within a ‘psattime interval another menu can be presented or beep can be generated to invite ‘seattention. Q3. (b) Explain the following: () AMBA ‘Ans. It defines a multilevel busing system, with a system bus and a lower-level geipheral bus. These include two system buses: the AMBA High-Speed Bus (AHB) or the Advanced System Bus (ASB), and the Advanced Peripheral Bus (APB). Designed for ‘astom silicon, these provide standard bus protocols for connecting on-chip IP, custom logic, and specialized functions. These bus protocols are independent of the ARM processor and generalized for SoC application. ‘The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-standard, ‘on-chip interconnect specification for the connection and management of functional blocks Sn system-on-a-chip (SoC) designs. It facilitates development of multi-processor designs ‘with large numbers of controllers and peripherals. Since its inception, the scope of AMBA, \d micro controller devices. (5) has, despite its name, gone far beyon« ‘The objective of the AMBA specification is to: « Facilitate right-first-time development of embedded microco one or more CPUs, GPUs or signal processors, yntroller products with idress juring « Be technology independent, to allow reuse of IP cores, peripheral and system mscrocells across diverse IC processes . To > Encourage modular system design to improve processor independence, and the is BOY development of reusable peripheral and system IP libraries om + Minimize silicon infrastructure while supporting high performance and low power nated on-chip commun n the i) DMA atio? ‘Ans. Direct Memory Access (DMA): During any xiven bus eysle, one of the ayatom. tio? components connected to the system bus is given control of the bus "Phi component is, p of seid to be tho master during that eyele and the component its camaunieating with is aid to be the slave, ‘Tho CPU with its bus control loyle is norwnally the waster, but other beet specially designed compononts can gain control ofthe bus by sonding a bus request to a SePL After the current bus oye is completed the CPU will return a bus grant signal and the component sending the request will become the master1th Semester, Embedded System Sevent 6-2018 . ides di Use sear rovides direct 1 “hemor on se oie gg ‘ ‘ essor is temporari i le ae = borrows the address bus, data bus, and cong ae ean ee nd transfers the data bytes directly between an Ug rat from the microprocess¢ cea 1 : series of memory locations. : oa i Option = = high-speed memory-to- memory ty ’ at si transfer is also used to do eS te pe signals are used to request and acknowledge a DMA transfering 1BM PC ser cessor-based system. ares as ene e ibsieitat signal which asks the microprocessortonigy | This in done ret crater nit register | control of the buses after the current bus eycl fa aes isa bus grant signal which indicates that the microprog capability of has indeed released control of its buses by placing the buses at their high-impedan, | (serial mode’ zero. We can: states * The HOLD input has a higher priority than the INTR or NMI interrupt inguy a Q.4.(a) Explain the following: naa (i) Interrupt Vs. Polling. @ a 2 Ans. 5 software a Basis For Interrupt Polling of | Gonpaties 3 must be used Basic Device notify CPU that it needs | CPU constantly checks devia i ee zs CPU attention status whether it needs OPUs || Ams. Refer attention. | Mechanism | An interrupt is a hardware Polling is a Protocol. _|_ mechanism, Servicing Interrupt handler services the Device Taleation | Interrupt requea lina indie Comand-ready bit indicates the) Papp Lihstdevice needs servicing. | devine scene servicing CPU CPU is disturbed only when a | CPU has to wait and check whet) device zee pele ine Which | a device needs servicing whieh 8 CPU eyeles rt —t epee eee. Wastes lots of CPU cycles. Occurrence n interrupt can om — a ape serrupt ean occur at any | PU Polls the devices at regu Bitcoagy interval. Polling becomes inefficient om CPU rarely finds a device read! Example Let the bell ring the the door to check who has rae Constantly keep on opening oor to check whether anybody oe (i) Baud Rate programming, Ans, There aro two ways to i “ome the baud rate of data transfor in the 8058us nd ase sor nee LP. University-{B:Tech}-Akash Books ae “ahigher-frequency crystal abit in the PCON register, shown below 0, Dy (swoon. = [= T= JT cet [ero [Po Ton jon 1 is not feasible in many situations since the system crystal is fixed More ly, it is not feasible because the new crystal may not be compatible with the serial COM port's baud rate Therefore, we will explore option 2. There is a way to double the baud rate of the 8051 while the crystal frequency is fixed fGsisdone with the register called PCON (power control). The PCON register is an 8- fingister of the 8 bits, some are unused and some are used for the power control taibility of the 8051 The bit that is used for the serial communication is 0, the SMOD Jeisl mode) bit. When the 8051 is powered up, 0, (SMOD bit) of the PCON register is fp We can set it to high by MOV A, PCON place a copy of PCON in ACC SBTB ACC.7 ;make D,-1 MOV PCON,A ;now SMOD-1 without ; changing any other bits software and thereby double the baud rate The following sequence of instructions PCON, since it is not a bit-addressable register: ‘ust be used to set high D7 of Q.4. (b) Explain the Timers Registers details in context of ARM and PIC. (5) ‘Ana. Refer Q. 4.(b) of First Term Examination 2017.