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Kunjal Bhalja: Contact

This document contains contact information and a summary of experience for Kunjal Bhalja. It lists their email, LinkedIn profile, and location in Ahmedabad, India. It then summarizes their experience in functional and formal verification, development of verification IP using SystemVerilog and UVM, and knowledge of protocols like PCIe, DisplayPort, and Ethernet.

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0% found this document useful (0 votes)
79 views2 pages

Kunjal Bhalja: Contact

This document contains contact information and a summary of experience for Kunjal Bhalja. It lists their email, LinkedIn profile, and location in Ahmedabad, India. It then summarizes their experience in functional and formal verification, development of verification IP using SystemVerilog and UVM, and knowledge of protocols like PCIe, DisplayPort, and Ethernet.

Uploaded by

noushadh tk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Contact
[email protected]
Kunjal Bhalja
ASIC Engineer
www.linkedin.com/in/kbhalja Ahmedabad, Gujarat, India
(LinkedIn)

Summary
Top Skills
PCIe Experience in Functional and Formal Verification domains.
Display Port Hands-on Experience with RTL Verification and VIP Development.
UVM Experience with development of Verification IP from scratch using
System Verilog and UVM,
Experience with defining and executing directed/random testcases..
Knowledge of protocols PCIe, Gigabit Ethernet, ACE, APB, AHB,
I2C, DisplayPort.

Experience
Fungible, Inc., Acquired by Microsoft
Member Of Technical Staff
June 2021 - Present (1 year 11 months)

PerfectVIPs
Senior ASIC Verification Engineer
October 2015 - August 2021 (5 years 11 months)
Ahmedabad Area, India

Pronesis Technologies
Member of Technical Staff
July 2014 - September 2015 (1 year 3 months)
* RTL Verification.

* Verification IP development.

* Functional & Code Coverage implementation and analysis.

TechnoCinch Solutions
ASIC Verification Engineer
June 2013 - June 2014 (1 year 1 month)
* Development of Display Port Verification IP.

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* Responsible for writing test plan and performing direct/random testing for
functional verification.

Education
Gujarat Tehcnological University
Bachelor of Engineering (BE), Electrical and Electronics
Engineering · (2009 - 2013)

Divine Buds School,Maninagar,Ahmedabad,Gujarat.


 · (2009)

Bright School,Karelibaug,Baroda,Gujarat
 · (2004)

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