QP CODE : 58022

LINEAR INTEGRATED CIRCUITS SOLUTION

(CBCGS SEM – 4 MAY 2019)
BRANCH – ELECTRONICS AND TELECOMMUNICATION
Q.1 Attempt any 4 questions:
a) Give Ideal Characteristics of op-amp and give their practical values. (05)

SOLUTION:
Various characteristics of an Ideal and practical op-amp are as follows

Sr.No. Characteristics Practical op-amp Ideal op-amp

value value
1 Input Resistance (Ri) 2 MΩ Infinite
2 Output Resistance (Ro) 75 Ω 0
3 Voltage gain (AV) 2 × 105 Infinite
4 Bandwidth B.W. 1 MHz Infinite
5 CMRR 90 dB Infinite
6 Slew rate (S) 0.5 V/µs Infinite
7 Input offset voltage (Vios) 2 mV 0
8 PSRR 150 µV/V 0
9 Input bias current (IB) 50 nA 0
10 Input offset current (Iios) 6 nA 0

b) Compare linear and switching voltage regulator. (05)

SOLUTION:

Sr.No. Parameter Linear Regulator Switching Regulator

1 Circuit Diagram

2 Region of operation Active region Saturated or Cut-off

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3 Switching No switching Transistor acts as a switch
4 Complexity Less High
5 Efficiency Low (40%) High (90%)
6 Switching frequency Very low Very high (25kHz)
7 Switching losses Zero Very high
8 RFI/EMI Absent Very high
9 Component stress High Very high
10 Regulation Excellent Good
11 Cost Lowest Moderate
12 Size/Weight Large/Bulky Small/Light weight
13 Power handling Low High
capacity

c) Design a circuit for Vo = V1 + V2 using single op-amp and few resistors. (05)

SOLUTION:
The above circuit can be designed by using non-inverting summing amplifier.

If V1 and V2 are the input voltages the output of non-inverting summing amplifier
is given as

VO = AVF ×

So, to get desired output AVF should be equal to 2.

But, AVF=1 +

Hence, for RF=R1=R, AVF=2

Hence the circuit can be designed as follow

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d) What are the advantages of switch capacitor filters? (05)

SOLUTION:

1. The primary advantage of switched capacitor filters is that they can be easily
implemented on an integrated circuit.

2. Performance similar to an analog RC op-amp based filter can be obtained using

a switched capacitor topology, while avoiding the need for an ADC, DSP, and DAC
on a chip.

3. Switched capacitor circuits use capacitors and switches to emulate the behavior
of resistors. Additionally, the frequency response is determined by the ratio of the
capacitors, so even low frequency filters can be easily realized on-chip.

4. The real benefit of switched capacitor filters is for IC implementations such that
while the absolute value of capacitances and resistances have a poor tolerance,
the matching between similar devices is very good. This makes it possible to
implement relatively high precision analog filters on a chip.

In an integrated circuit, you would choose a switched capacitor filter for the
following reasons:

 Minimizing chip area is a priority

 You will not be doing significant digital processing on the chip
 The output of the DSP would be an analog signal

e) Explain op-amp as Window detector. (05)

SOLUTION:
1. Op-amp can be used as a window detector so as to detect whether the input
voltage Vin lies within a specified range (between VH and VL). This range is referred
as Window.

2. A window detector circuit can be obtained as follows using 2 op-amps and 2

transistors that operates as switch.

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3. The outputs of 2 comparators are connected to the transistors and output
voltage is collected from common collector terminal of the transistors.

4. If Vin is between the two reference voltages i.e. VL < Vin < VH then the outputs of
both the comparators will be low. So both the transistor will be in off state and
hence output will be high else low.

5. Hence, the three output conditions are as follows

i. Vo=+VCC for VL < Vin < VH

ii. Vo= VCE (sat) for Vin < VL
iii. Vo= VCE (sat) for Vin > VH

Hence, when the output is high (i.e. applied VCC is obtained at output) if the input
voltage is in the range else low.

Q.2.

a) With the help of a neat diagram and voltage transfer characteristics explain
the working of an inverting Schmitt trigger. Derive the expression for its
threshold levels. (10)

SOLUTION:
1. The inverting Schmitt trigger is as shown below

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2. The resistance divider formed by R1 and R2, connected between the output and
non-inverting terminal of the op-amp introduces the positive feedback.
3. The Schmitt trigger is basically an inverting comparator with positive or
regenerative feedback introduced. Hence also known as regenerative
comparator.
4. External input Vin is applied to the inverting input of the op-amp. The resistor
ROM is called offset minimizing resistor and is equal to parallel combination of R 1
and R2.
5. The reference voltage is V1 developed across R2. This reference voltage is not
fixed but its sign and amplitude depends upon output voltage because,

V1= ×𝑉

6. The 2 different triggering/threshold voltages are defined for the Schmitt trigger
as follows:
 Upper threshold voltage VUT
 Lower threshold voltage VLT
7. The output voltage will change its state every time input voltage cross
threshold levels.
8. The upper threshold level is defined as value of Vin which forces a transition
from +Vsat to –Vsat in output voltage.
Similarly the lower threshold value is defined as value of V in which forces output
voltage to change from -Vsat to +Vsat in output voltage.
9. Thus upper and lower threshold/trigger voltages can be given as

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VUT = × Vsat

VLT = × –Vsat

Thus the magnitude of upper and lower threshold voltage is same but has
opposite sign hence also known as symmetrical Schmitt trigger.
10. Transfer characteristics of inverting Schmitt trigger is a shown

Such that when, Vin < VUT then Vo = +Vsat

Vin > VLT then Vo = -Vsat.
b) Draw a neat circuit diagram of Wien bridge oscillator using op-amp. Derive its
frequency of oscillation. What are the values of R and C for frequency of
oscillation to be 965 Hz? (10)
SOLUTION:
Working of Wien bridge oscillator

1. A Wien bridge oscillator with a non-inverting op-amp amplifier is as shown below

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2. The Wein bridge has 4 arms. The arm AD which contains a series of combination
of R and C, whereas arm CD contains a parallel combination of R and C.

This value of R and C is used to decide the value of oscillator frequency such that

f=

3. The resistors RF and R1 are used to generate a reference voltage which remains
constant independent of the frequency f.

4. The AC input voltage is applied between the points A and C of the bridge. When
Wien bridge is used in oscillator circuit, the feedback voltage is applied between
these points.

5. The AC output of the bridge is obtained between the points B and D which is
connected as inputs of the non-inverting amplifier.

6. The value of feedback factor β depends upon the frequency. At oscillator

frequency fo the phase shift introduced is zero and thus value of feedback factor β
is 1/3.

7. According to Barkhausen criteria the phase shift around the loop should be zero
and loop gain should be greater than 1.

i.e. |Aβ|≥1

substituting β=1/3, we get A≥3.

Therefore the gain of the amplifier should be greater than or equal to 3.

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8. Data: fo= 965 Hz

Let C=0.01 µF

Since fo =

R= = = 16.49 kΩ
× × × . ×

C=0.01 µF, R=16.49 kΩ

Q. 3.
a) Draw the circuit diagram of a square and triangular waveform generator using
op-amp and explain its working with the help of waveforms. (10)

SOLUTION:

A. Square wave generator:

A square wave generator using op-amp can be designed as follow

1. Let the voltage on the capacitor C is zero when power is applied to the circuit.
Therefore initially the voltage at the inverting terminal is zero i.e. V 2=VC=0.

2. Due to some output offset voltage present at output of op-amp, the voltage V 1
at non-inverting terminal is non zero and will have a value that depends on the

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output offset voltage and values of resistance R1 and R2. Hence differential voltage
Vd is equal to V1.

Operation:

The operation of square wave generator can be divided in 2 parts:

1. Operation from 0 to t1:

 The voltage V1 will start driving the op-amp output towards saturation. For
example if V1 is positive initially then it will drive the comparator output to
+Vsat if Vd is positive.
 With op-amp output equal to +Vsat the capacitor C starts charging through R
and VC starts increasing exponentially in the positive direction.
 The voltage V1 across R1 is given by
V1 = × Vsat

Hence V1 = β.Vsat where, β =

2. Operation from t1 to t2

 At t=t1 the capacitor voltage VC is equal to β.Vsat. As soon as the voltage on C

i.e. V2 becomes slightly more than V1, the differential voltage Vd changes its
polarity and op-amp output will suddenly switch to a negative saturation i.e.
–Vsat.
 Due to this sudden changeover voltage V1 also becomes negative as
V1 = × -Vsat
Hence, V1 = -β.Vsat
 The capacitor C starts discharging through R and the output stage of the op-
amp.
 As soon as VC becomes slightly more negative than V1, the differential voltage
polarity will be at t=t2 reversed and the op-amp output will suddenly switch
to a positive saturation i.e. +Vsat.

This process will repeat itself to generate a square waveform at the output of op-
amp.

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B. Triangular wave generator:

A triangular wave generator using op-amp can be obtained by a combination of

comparator and integrator as shown

 At t=t0 let the output of comparator be equal to +Vsat. Hence the

voltage at point A will be clamped to +VZ.
VA = +VZ
 Let us assume the integrator output at t=to is positive equal to
Vo(to) = × Vz
That means the capacitor is charged to this voltage with its right plate
positive.
 Due to positive voltage +VZ at point A the capacitor starts charging
linearly through the resistors R3 and R4. This will charge the left plate
of the capacitor towards appositive voltage. Therefore the net voltage

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 on the capacitor starts decreasing linearly.
 The charging current in the interval time to to t1 is given by
I+ =
 The voltage at non-inverting terminal of the comparator is given by
superposition theorem
( ). ( )
V3(t) = +
( ) ( )
 At instant t=t1 the instantaneous voltage at non-inverting terminal of
comparator i.e. V3(t) is given by above equation.
Due to this the voltage at point A will be clamped to –VZ and the
capacitor will discharge through R3 and R4.
 The capacitor voltage now starts becoming positive. The discharging
current is given by
I- =
As this current is constant, the voltage on the capacitor i.e. output
voltage increases linearly.

b) The circuit given in following figure is similar to that of internal diagram of

IC555 with slight modifications in the internal resistance to value 2R. Analyze this
circuit and draw the waveforms at output terminal Vout and across the capacitor
C. Comment on the duty cycle of output waveform when i) R A is less than RB ii) RA
is equal to RB, and iii) RA is greater than RB. (10)

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SOLUTION:
The above diagram represents IC 555 connected to R A, RB and C so as to form an
astable multivibrator.

The internal resistance of IC 555 is generally 5kΩ, but in the above case it is 2R.

Since all the resistors have same value i.e. 2R the voltage drop across both the
comparators would still be the same i.e. 1/3VCC and 2/3VCC.

Hence, there would be no change in output waveform of the above given astable
multvibrator irrespective of change in internal resistance.

The output waveform VOUT and waveform across capacitor C is given as

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Duty cycle of above circuit can be obtained as follows:

Duty cycle of astable multivibrator is given as follows

. ( )
D% = ( )
× 100 ….(1)
.

( )
Hence, D% = ( )
× 100

i) RA < RB

On substituting some random values for RA and RB such that RA < RB in equation 1

For example a) let, RA=2Ω, RB=2.1Ω

( ) ( . )
Then D% = ( )
× 100 = ( × 100 = 66.12%
× . )

b) let, RA=2Ω, RB=1000Ω

( ) ( )
Then D% = ( )
× 100 = ( )
× 100 = 50.04%
×

Hence value of D will lie between 50% and 66.66%.

ii) RA = RB
( )
If value of RA is equal to RB, D% = ( )
× 100 = × 100 = 66.66%

Hence when RA=RB duty cycle is 66%.

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iii) RA > RB

On substituting some random values for RA and RB such that RB < RA in equation 1

For example a) let, RA=2.1Ω, RB=2Ω

( ) ( . )
Then D% = ( )
× 100 = ( × 100 = 67.21%
. × )

b) let, RA=1000Ω, RB=2Ω

( ) ( )
Then D% = ( )
× 100 = ( × 100 = 99.80%
× )

Hence value of D will lie between 66.66% and 100%.

Q.4.

a) Design a second order Butterworth high pass filter for cut-off frequency of 1
kHz and pass-band gain of AF = 2. (10)

SOLUTION:

Data: fo = 1kHz = 103 Hz

Pass-band gain AF=2

Let us assume that R2=R3=R and C2=C3=C=0.01 µF

Step 1: Calculate value of R

R= =
× × × . ×

R = 15.91 kΩ

Step 2: Calculate RF and R1

AF = 1 +

2=1+

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𝑅
=1
𝑅

Let R1=10kΩ

Hence RF=10kΩ

Therefore, the components value are as follows

R1=10kΩ, RF=10kΩ

R2=R3=R=15.91 kΩ

C2=C3=C=0.01 µF

Step 3: Circuit diagram

b) With a neat circuit derive an expression for the output of an instrumentation

amplifier. (10)
SOLUTION:
An instrumentation amplifier can be implemented using 3 op-amps as shown in
the figure below.

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Consider 3 op-amps A1, A2 and A3 where A1 and A2 act as non-inverting amplifier
such that their inverting terminal (-) is connected to resistor R2 instead of ground.

The input impedance of all the op-amps (A1, A2 and A3) is assumed to be infinite,
the currents flowing would be zero. Hence the current flowing through the

resistors R1, R2 and R3 is same i.e. ‘I’.

Using the concept of virtual short we can obtain the voltages at nodes A and B as
follows

VA = V2 and VB = V1

Hence the expression for current I is,

I= =

The output voltage of op-amp 2 (A2) is given by

Vo2 = VA + IR1 = V2 + IR1

= V2 + R1

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 =

( )
=

The output voltage of OP-AMP1 is given by

V01 = VB – IR1

= V1 – IR1

= V1 - x R1

Hence the output of the first stage is given by

V02 - V01 = -

V02 - V01 = [1 +

Therefore, the gain of the first state is given by

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 AV1 = =1+

The second stage is a difference amplifier with a gain of

AV2 =

Therefore, the overall gain AV of the three OP-AMP instrumentation amplifier is

given by,

AV = AV1 x AV2

∴ AV = [1 + X

Hence by using a variable resistor R2 the overall gain can be easily and linearly
varied.

The output voltage is then given by,

V0 = AV x (V1 – V2)

The triple OP-AMP instrumentation amplifier is available in IC form. For example,

ICAD522 or INA 101. These devices will contain all the components except the
variable resistance R2 shown in the figure above.

Q.5.
a) With neat circuit explain R/2R ladder digital to analog converter. (10)
SOLUTION:
1. The circuit diagram for R-2R ladder DAC is as shown in figure below

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2. Unlike others wide range of resistors are not necessary to design a R-2R ladder
DAC. Only two resistors R and 2R are needed hence the name.
3. This method is suitable for the realization of IC where the value of R can be
anywhere between 2.5kΩ and 10kΩ but should not be less than 2.5kΩ.

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Operation of R-2R ladder:
1. The number of digits per binary is assumed to be 3(i.e. n=3). The switch
positions indicate that the binary word d1d2d3=100.
2. The original circuit can now be simplified as shown in Fig.1 and Fig.2. Fig.1 gets
further simplified into equivalent circuit as shown in fig.2.
3. The equivalent resistance to the left of node “B” in fig.1 is only 2R and node “A”
is virtual ground potential.
4. The simplified final equivalent circuit is as shown in figure 3. In figure 3 as 2
resistors 2R and R are connected parallel to produce 2R/3.
5. Voltage at node “B” is given as
( )
VB= × (−𝑉 )= -VR/4
( )

6. Hence the output voltage is given by

Vo=− ×𝑉 = × = =

Thus for binary input 100 the analog output produced is VR/2.
7. Similarly analog output for other values of input digital value can be obtained.
d1 d2 d3 Analog
Output
Voltage
0 0 0 0
0 0 1 VR/8
0 1 0 2VR/8
0 1 1 3VR/8
1 0 0 4VR/8
1 0 1 5VR/8
1 1 0 6VR/8
1 1 1 7VR/8

Advantages of R-2R ladder DAC:

 Because we need resistors of only two values i.e. R and 2R, it os
easier to build this circuit accurately.
 We can increase the number of input bits by just adding more

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 sections of same R/2R values.
 The equivalent resistance to the right of each labelled node
(A,B,C,….) will be equal to 2R. Hence current flowing downwards,
away from each node is equal to the current flowing towards right.
 Due to small resistance range required, the R-2R ladder can be
fabricated monolithically, with a high accuracy and stability.
b) With the help of a functional block diagram explain the working of voltage
regulator LM317 to give an output voltage variable from 6V to 12V to handle
maximum load current of 500mA. (10)
SOLUTION:

1. Functional block diagram of positive adjustable voltage regulator LM 317 is as

shown below

2. The functional block diagram above shows that LM 317 is a series regulator and
a Darlington pair acts as a series pass element.

3. The output voltage is compared with the internally generated voltage reference
to produce an error voltage which drives the Darlington transistor to regulate the
output voltage.

4. RLIMIT is an internal sensing resistance. The voltage across it is proportional to load

current. This voltage is applied to the internal protection circuitry.

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5. If the load current exceeds beyond its maximum value, the Darlington pair will
be automatically turned off to protect the IC.

6. LM 317 is monolithic IC voltage regulator with an adjustable output voltage

which can supply more than 1.5A current to the load. Its output voltage is
adjustable over a range of 1.2V to 37V.

7. It employs the internal current limiting and thermal shutdown and safe area
compensation.

Data: Vo = 6V to 12V

IL(max) = 500mA

Let us assume maximum value of IADJ = 100µA and let R1 = 240Ω.

1. Calculate minimum and maximum values of R 2

Vo = 1.25 1 + +𝐼 𝑅

Vo = 1.25 1 + + 100 × 10 ×𝑅

For Vo = 6V i.e. minimum the corresponding value of R2 will be R2min

∴ 6 = 1.25 1 + + 10 ×𝑅

R2min = 894.48 Ω

For Vo = 12V , value of R2max will be

∴ 12 = 1.25 1 + + 10 ×𝑅

R2max = 2025.24 Ω

Thus we want R2 to vary from 894.48 Ω to 2025.24 Ω. Hence we choose R2 to be a

series combination of a fixed resistor of 680 Ω and a potentiometer of 1k Ω value.

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2. To obtain 500mA, we should use TO-3 package with 20W power consumption
rating.

3. Filter capacitors:

We assume that the regulator is close to the unregulated input supply. Hence the
input capacitor Ci is not to be used. But for better ripple rejection use capacitor
C2 = 10µF between adjustment terminal and ground. The output capacitor Co=1 µF
is also being used.

4. Protective diodes:

As the output voltage is less than 25V and capacitors are smaller than 25µF, it is not
necessary to use the protective diodes.

The minimum voltage drop across LM 317 is 3V. Hence the input voltage V in ≥ 13V.

Hence the complete designed Voltage regulator is as shown below:

Q.6. Short notes on: (Attempt any four)

a) Effect of swamping resistor. (05)

SOLUTION:
Swamping resistor are the resistors used to increase the input resistance of a
differential amplifier connected in series to transistor and denoted by R E’.

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Effects of Swamping resistor are as follows:
1. The Q point gets shifted and needs to be readjusted.
2. The differential gain reduces substantially.
3. There is a considerable increase in the input resistance.
4. They minimize the effect of change in transistor parameters (e.g. h-parameters)

due to temperature, on the differential gain.

5. They also increase the linearity range of the differential amplifiers.
b) Current fold-back protection circuit in voltage regulator. (05)

SOLUTION:

The circuit above shows a simplified circuit schematic of a discrete voltage

regulator with foldback current limiting technique, which actually decreases the
output current while operating in overload conditions.

The advantage of foldback current limiting is that it reduces the power dissipation
taking place in the series pass transistor Q1 under the short circuit condition as
compared to power dissipation taking place in short circuit current protection.

As seen in the schematic above R3 and R4 are added to the short circuit protection.

Transfer characteristics of foldback current limiting circuit is as shown below

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c) Voltage to current converter (05)
SOLUTION:
1. A voltage to current converter accepts the input in voltage form i.e. V in and

produces output in the form of current i.e. Io. The output current is proportional

to input voltage.

2. The voltage to current converter can be classified into two categories

depending upon the position of the load.

 V to I converter with floating load.

 V to I converter with grounded load.

3. V to I converter with floating load:

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Applying KVL to input loop Vin = Vd + Vf

But since the open loop gain of op-amp is very large, Vd=0

Hence, Vin=VF

But, Vin=R1×Io …. (As IB~0)

Therefore, Io=

4. V to I converter with grounded load

Applying KCL at V1 we get IL=I1+I2

Where, I1= and I2=

Putting this in above equation

V1 =

AVF=2 hence, V0=2Vin

Therefore IL =

d) Peak detector circuit (05)

SOLUTION:
1. Peak detector is used to detect and hold the peak value of the input signal.
Output of this circuit will follow the peak value of the input signal and store the
maximum value infinitely.

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2. The two types of Peak detectors are as follows:

Positive peak detector

Negative peak detector

3. Positive peak detector:

 Following circuit shows a positive peak detector using op-amp

 The op-amp is used as voltage follower. Hence the gain of the circuit is 1.
 The diode D1 will be forward biased only in positive half cycle of the input,
hence this circuit is sensitive only to positive input voltages.
 D2 will not allow any negative voltage to go ahead. It will clamp negative
output voltage to -0.7 volts (practical diode) or 0V (ideal diode).
 The diodes D1 and D2 are assumed to be ideal and the output voltage V o is
nothing but the output voltage across the capacitor i.e. Vo=VC.
 This circuit can work in two modes: track mode and hold mde.
4. Negative peak detector:

 Following circuit shows a negative peak detector using op-amp

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  By reversing the direction of the diodes the same circuit will operate as a
negative peak voltage detector.
e) Working of PLL IC 565 (05)
SOLUTION:
1. PLL IC 565 is a 14 pin DIP and 10 pin metal can package. Pin configuration of
565 is as shown below

2. Functional block diagram of IC 565 is as shown below

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3. The free running frequency of VCO (i.e. when inputs 2 and 3 are grounded) is
given by
.
𝑓 = 𝐻𝑧

Where RT and CT are externally connected components to pin 8 or pin 9

respectively as shown in functional block diagram.

This externally connected RT can have a value between 2kΩ and 20kΩ whereas C T
can have any value.

4. To compare fi and fo pin 4 and pin 5 is connected externally.

5. The 3.6kΩ external resistor along with capacitor C connected between pin 7
and pin 10, such that value of this capacitor C should be sufficiently large to
minimize variation in output at pin 7.

6. The 565 PLL is capable of locking to and tracking an input signal over ±60%
bandwidth with respect to fo (center frequency).

7. The lock range fL of the PLL is given by

Lock range: ΔfL = ± 𝐻𝑧

Where f0= free running frequency of VCO in Hz

V=(+V) - (-V) volts.

8. The expression for the capture range is given by:

∆
Capture range : ∆𝑓 = ±
( )( . )× ×

Where C is expressed in farads.

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