ANALOG AND DIGITAL ELECTRONICS

LABORATORY
LAB MANUAL

II B.TECH -II/I SEMESTER (R18)

ACADEMIC YEAR : 2021-2022

UGC AUTONOMOUS

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

CMR ENGINEERING COLLEGE

KANDLAKOYA (V), MEDCHAL ROAD, HYDERABAD-501401

1
 DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
Vision of the Institute:
To be recognized as a premier institution in offering value based and futuristic
quality technical education to meet the technological needs of the society.
Mission of the Institute:
 To impart excellent technical education with state of art facilities
inculcating values and lifelong learning attitude
 To develop core competence in our students imbibing professional ethics
and team spirit
 To encourage research benefiting society through higher learning
Vision of the Department:
To promote excellence in technical education and scientific research in
electronics and communication engineering for the benefit of society.

Mission of the Department:

 To impart excellent technical education with state of art facilities inculcating
values and lifelong learning attitude
 To develop core competence in our students imbibing professional ethics and
team spirit
 To encourage research benefiting society through higher learning

PEOs:

PEO1: Establish themselves as successful professionals in their carrier & higher

education in Electronics & Communication engineering and allied fields through
rigorous quality education.
PEO2:Develop professionalism, ethics, excellent leadership quality, communication
skills, team work and multidisciplinary knowledge in their profession & adapt to
current trends by engaging lifelong learning
PEO3:Apply the acquired knowledge & skills in solving real life problems, to develop
novel technology and design products which are economically feasible and socially
relevant, for the benefits of the society

PSO:

PSO1:Ability to apply concepts of Electronics & Communication Engineering to

associated research areas of electronics, communication, signal processing, VLSI,
Embedded systems, IoT and allied technologies.
PSO2:Ability to design, analyze and simulate a variety of Electronics &
Communication functional elements using hardware and software tools along with
analytic skills

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Program Outcomes (POs) :

 PO1:Engineering knowledge: Apply the knowledge of mathematics,

science, engineering fundamentals, and an engineering specialization to the
solution of complex engineering problems.
 PO2:Problem analysis: Identify, formulate, review research literature, and
analyze complex engineering problems reaching substantiated conclusions
using first principles of mathematics, natural sciences, and engineering
sciences.
 PO3:Design/development of solutions: Design solutions for complex
engineering problems and design system components or processes that
meet the specified needs with appropriate consideration for the public
health and safety, and the cultural, societal, and environmental
considerations.
 PO4:Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis
and interpretation of data, and synthesis of the information to provide valid
conclusions.
 PO5:Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
modelling to complex engineering activities with an understanding of the
limitations.
 PO6:The engineer and society: Apply reasoning informed by the
contextual knowledge to assess societal, health, safety, legal and cultural
issues and the consequent responsibilities relevant to the professional
engineering practice.
 PO7:Environment and sustainability: Understand the impact of the
professional engineering solutions in societal and environmental contexts,
and demonstrate the knowledge of, and need for sustainable development.
 PO8:Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
 PO9:Individual and team work: Function effectively as an individual, and
as a member or leader in diverse teams, and in multi disciplinary settings.
 PO10:Communication: Communicate effectively on complex engineering
activities with the engineering community and with society at large, such
as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear
instructions.
 PO11:Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply
these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
 PO12:Life-long learning: Recognize the need for, and have the preparation
and ability to engage in independent and life-long learning in the broadest
context of technological change.

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 DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING

EVALUATION PATTERN
FOR BASIC ELECTRICAL ENGINEERING LABORATORY

The Basic Electrical Engineering lab evaluation can be broadly classified as per the
contents

Internal Assessment: 30 Marks

1. Two internals will be conducted for laboratory assessment.

2. Day-to-day work in the laboratory shall be evaluated for 20 marks.

3. Internal examination for practical shall be evaluated for 10 marks conducted by the
concerned laboratory teacher.

End Examination Assessment: 70 Marks

1. The end examination conducted for 70 marks with duration of 3 hours.

2. The end examination shall be conducted with external examiner and laboratory teacher.

3. The external examiner shall be appointed from the cluster of colleges as decided by the
University examination branch.

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 DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING

SAFETY PRECAUTIONS

1. Ensure appropriate attires: no slippers, sandals or open-toe footwear allowed.

2. Long hair should be properly tied.
3. Make sure hands are dry when conducting experiment. KEEP WATER BOTTLES
AWAY FROM EXPERIMENT AREA.
4. Make sure all power supplies are switched off before commencing with
connections.
5. Make circuit connections with test leads. Use only ONE hand when making
connections to avoid closing circuit with your body.
6. Signal tutor or technician to check and verify your wire connections are correct.
7. Switch on power supply and proceed with data collection for experiment.
8. After each set of readings, switch off power supply before making any changes to
wire connections.

When disconnecting test leads, remove the main power supply connections first, i.e.
DC positive voltage output or AC voltage live output

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 DEPARTMENT OF ELECTRONICS &COMMUNICATION
ENGINEERING

INSTRUCTIONS

INSTRUCTION FOR STUDENTS:-

1. Do not handle any equipment without reading the instructions /Instruction manuals.
2. Observe type of sockets of equipment power to avoid mechanical damage.
3. Do not insert connectors forcefully in the sockets.
4. Strictly observe the instructions given by the Teacher/ Lab Instructor.
5. After the experiment is over, the students must hand over the Bread board, Trainer
kits, wires, CRO probes and other components to the lab assistant/teacher.
6. It is mandatory to come to lab in a formal dress (Shirts, Trousers, ID card, and
Shoes for boys).
Strictly no Jeans for both Girls and Boys.
7. It is mandatory to come with observation book and lab record in which previous
experiment should be written in Record and the present lab’s experiment in
Observation book.
8. Observation book of the present lab experiment should be get corrected on the same
day and Record should be corrected on the next scheduled lab session.
9. Mobile Phones should be Switched OFF in the lab session.
10. Students have to come to lab in-time. Late comers are not allowed to enter the lab.
11. Prepare for the viva questions. At the end of the experiment, the lab faculty will
ask the viva questions and marks are allotted accordingly.
12. Bring all the required stationery like graph sheets, pencil & eraser, different color
pens etc. for the lab class.
13. While shorting 2 or more wires for common connections like grounding, do not
twist wires. Use shorting link on the bread board.

INSTRUCTIONS TO LABORATORY TEACHERS:-

1. Observation book and lab records submitted for the lab work are to be checked and
signed before the next lab session.
2. Students should be instructed to switch ON the power supply after the connections
are checked by the lab assistant / teacher.
3. The promptness of submission of records/ observation books should be strictly
insisted by awarding the marks accordingly.
4. Ask viva questions at the end of the experiment.
5. Do not allow students who come late to the lab class.
6. Encourage the students to do the experiments innovatively.

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 ANALOG AND DIGITAL ELECTRONICS LAB

COURSE OBJECTIVES:

This laboratory course enables students to get practical experience in design, assembly
and evaluation/testing of
 Analog components and circuits including Operational Amplifier, Timer, etc.
 Combinational logic circuits.
 Flip – Flops and their operations
 Counters and Registers using Flip-flops.
 Synchronous and Asynchronous Sequential Circuits.
 A/D and D/A Converters

COURSE OUTCOMES:

On the completion of this laboratory course, the students will be able to:
 Use various Electronic Devices like Cathode ray Oscilloscope, Signal
generators, Digital Trainer Kit, Multimeters and components like
Resistors, Capacitors, Op amp and Integrated Circuit.

 Design and demonstrate various combinational logic circuits.

 Design and demonstrate various types of counters and Registers using

Flip-flops

 Use simulation package to design circuits.

 Understand the working and implementation of ALU.

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 INDEX

EXPT. PAGE NO.

NO. EXPERIMENT NAME
HARDWARE LABORATORY

1 FULL WAVE RECTIFIER WITH AND 8

WITHOUT FILTERS
2 COMMON EMITTER AMPLIFIER 12

3 COMMON BASE AMPLIFIER 15

4 COMMON SOURCE AMPLIFIER 17

5 MEASUREMENT OF H-PARAMETERS OF A 21
TRANSISTOR IN CB,CE,CC
CONFIGURATIONS
6 INPUT AND OUTPUT CHARACTERISTICS 28
OF FET IN CS CONFIGURATION
7 REALIZATION OF BOOLEAN 32
EXPRESSIONS USING GATES
8 DESIGN AND REALIZATION LOGIC 37
GATES USING UNIVERSAL GATES

9 GENERATION OF CLOCK USING 41

NAND/NOR GATES
10 DESIGN A 4-BIT ADDER/SUBTRACTOR 43

11 DESIGN AND REALIZATION A 47

SYNCHRONOUS AND ASYNCHRONOUS
COUNTER

12 REALIZATION OF LOGIC GATES USING 50

DTL,TTL, ECL ETC.

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 1. FULL WAVE RECTIFIER WITH & WITHOUT FILTERS

AIM: To Rectify the AC signal and then to find out Ripple factor and percentage of
Regulation in Full-wave rectifier center tapped circuit with and without Capacitor
filter.

APPARATUS:

S.No Name Range / Value Quantity

1 Transformer 230V / 9-0-9V 1
2 Diode 1N4001 2
3 Capacitors 1000F/16V, 470f/25V 1
4 Decade Resistance Box - 1
5 Multimeter - 1
6 Bread Board and connecting wires - 1
7 Dual Trace CRO 20MHz 1

CIRCUIT DIAGRAMS:

WITHOUT FILTER AND WITH FILTER:

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THEORY:

A Rectifier is an electrical device that converts alternating current (AC),

which periodically reverses direction, to direct current (DC), which flows in only one
direction. The process is known as rectification. Physically, rectifiers take a number
of forms, including vacuum tube diodes, mercury-arc valves, copper and selenium
oxide rectifiers, semiconductor diodes, silicon-controlled rectifiers and other silicon-
based semiconductor switches. Historically, even synchronous electromechanical
switches and motors have been used. Early radio receivers, called crystal radios, used
a "cat's whisker" of fine wire pressing on a crystal of galena (lead sulfide) to serve as a
point-contact rectifier or "crystal detector".

Because of the alternating nature of the input AC sine wave, the process of
rectification alone produces a DC current that, though unidirectional, consists of
pulses of current. Many applications of rectifiers, such as power supplies for radio,
television and computer equipment, require a steady constant DC current (as would be
produced by a battery).

The circuit of a center-tapped full wave rectifier uses two diodes D1&D2.
During positive half cycle of secondary voltage (input voltage), the diode D1 is
forward biased and D2is reverse biased. The diode D1 conducts and current flows
through load resistor RL. During negative half cycle, diode D2 becomes forward
biased and D1 reverse biased. Now, D2 conducts and current flows through the load
resistor RL in the same direction. There is a continuous current flow through the load
resistor RL, during both the half cycles and will get unidirectional current as show in
the model graph. The difference between full wave and half wave rectification is that a
full wave rectifier allows unidirectional (one way) current to the load during the entire
360 degrees of the input signal and half-wave rectifier allows this only during one half
cycle (180 degree).

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PROCEDURE:

WITHOUT FILTER:

1. Connecting the circuit on bread board as per the circuit diagram.

2. Connect the primary of the transformer to main supply i.e. 230V, 50Hz
3. Connect the decade resistance box and set the RL value to 100Ω

4. Connect the Multimeter at output terminals and vary the load resistance
(DRB) from 100Ω to 1KΩ and note down the Vac and Vdc as per given
tabular form
5. Disconnect load resistance ( DRB) and note down no load voltage Vdc (V no
load)

6. Connect load resistance at 1KΩ and connect Channel – II of CRO at output

terminals and CH – I of CRO at Secondary Input terminals observe and
note down the Input and Output Wave form on Graph Sheet.

7. Calculate ripple factor   Vac

V
dc
8. Calculate Percentage of Regulation, %  Vno load Vfull load 100%
V
no load

WITH CAPACITOR FILTER:

1. Connecting the circuit as per the circuit Diagram and repeat the above
procedure from steps 2 to 8.

FWR WITH OUT CAPACITOR

S.No R(KΩ VdcFL Vac Γ=Vac/

1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10

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FWR WITH CAPACITOR

S.No R(KΩ VdcFL Vac Γ=Vac/

1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
WAVE SHAPES:

MODEL GRAPHS:

RESULT:

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WITHOUT FILTER:
Ripple Factor :
Regulation :

WITH CAPACITOR FILTER:

Ripple Factor :
Regulation :

PRECAUTIONS:

1. Check the wires for continuity before use.

2. Keep the power supply at Zero volts before Start.
3. All the contacts must be intact.

VIVA QUESTIONS:

1. What is a full wave rectifier?

2. How Diode acts as a rectifier?
3. What is the significance of PIV requirement of Diode in full-wave rectifier?
4. Compare capacitor filter with an inductor filter?
5. Draw the o/p wave form without filter? Draw the O/P? What is wave form
with filter?
6. What is meant by ripple factor? For a good filter whether ripple factor
should be high or low? What happens to the ripple factor if we insert the
filter?
7. What is meant by regulation? Why regulation is poor in the case
of inductor filter?
8. What is meant by time constant?
9. What happens to the o/p wave form if we increase the capacitor value?
What happens if we increase the capacitor value?
10. What is the theoretical maximum value of ripple factor for a full wave
rectifier?

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 2. COMMON EMITTER AMPLIFIER CHARACTERISTICS

AIM: To Find the frequency response of a Common Emitter Transistor Amplifier and to
find the Bandwidth from the Response, Voltage gain, Input Resistance, output
resistance.

APPARATUS:

S.No Name Range / Value Quantity

1 Regulated D.C Power supply 0–30 Volts 1
2 Transistor BC107 1
3 Resistors 1K 2
4 Resistors 100k,10K, 4.7K. Each 1
5 Capacitors 10f 3
6 Potentio Meter -- 1
7 Signal Generator ( 0 – 1MHz) 1
8 Dual Trace CRO 20MHz 1
9 Bread Board and connecting wires -- 1 Set

CIRCUIT DIAGRAM:-

THEORY:
The CE amplifier provides high gain &wide frequency response. The emitter
lead is common to both input & output circuits and is grounded. The emitter-base
circuit is forward biased. The collector current is controlled by the base current rather
than emitter current. The input signal is applied to base terminal of the transistor and
amplifier output is taken across collector terminal. A very small change in base current
produces a much larger change in collector current. When +VE half-cycle is fed to the
input circuit, it opposes the forward bias of the circuit which causes the collector
current to decrease, it decreases the voltage more –VE. Thus when input cycle varies
through a -VE half-cycle, increases the forward bias of the circuit, which causes the
collector current  to increases thus the output signal is common emitter amplifier is in
out of phase with the input signal.

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PROCEDURE:

1. Connect the circuit as per the Fig.1.,Apply Vcc of 12 Volts DC.

2. Apply I/P Voltage of 20mV at 1KHz from the Signal Generator and
observe the O/P on CRO.
3. Vary the frequency from 50 Hz to 1MHz in appropriate steps and note
down the corresponding O/P Voltage Vo in a tabular form .
4. Calculate the Voltage Gain Av = Vo/Vs and note down in the tabular form.
5. Plot the frequency (f) Vs Gain (Av) on a Semi-log Graph sheet
6. Draw a horizontal line at 0.707 times Av and note down the cut off points
and the Bandwidth is given by B.W = f2 – f1.

INPUT RESISTANCE RI:

1. Apply I/P Voltage of 20mV at 1KHz from the Signal Generator and
observe voltage Vi across R2 on CRO.
2. Without Disturbing the setup note Vi.
3. find Ii = (Vs – Vi) / Rs and Ri= Vi / Ii Ohms.

OUTPUT RESISTANCE (RO):

1. Apply I/P Voltage of 50mV at 1KHz from the Signal Generator and
observe the o/p on CRO

2. Connect a Potentio meter across the O/P terminals and without disturbing
Vs adjust the potentiometer such that o/p falls to V0/2

3. The Resistance of the potentiometer is equal to Ro.

TABULAR FORMS:

O/P
Frequency Voltage, Voltage Gain Av in dB= 20 log
S.No (Hz) Vo (V) Av =Vo/Vi (Av)
1 10
2 100
3 700
4 1K
5 10K
6 100K
7 500K
8 1M

15
MODEL GRAPH:

RESULT:
BandWidth B.W = f 2 – f1 = Hz
Voltage Gain Av =
Input Resistance Ri = ohms
Output Resistance Ro = ohms

PRECAUTIONS:

1. Check the wires for continuity before use.

2. Keep the power supply at Zero volts before Start
3. All the contacts must be intact

VIVA QUESTIONS:

1. What is an Amplifier?
2. How many types of an Amplifiers?
3. What is meant Band width, Lower cut-off and Upper cut-off frequency?
4. How much phase shift for CE Amplifier?
5. What are the applications?
6. Draw the Equivalent circuit for low frequencies?

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 3.COMMON BASE AMPLIFIER CHARACTERISTICS
AIM: -

1. Plot the frequency response of a BJT amplifier in common base configuration.

2. Calculate gain.
3. Calculate bandwidth.

COMPONENTS & EQUIPMENTS REQUIRED: -

S.No Device Range/Rating Qty

(a) DC supply
1. voltage 12V 1
(b) BJT BC10710 1
(c) Capacitors 10µF 3
(d) Resistors 50Ω,10kΩ, 20kΩ 1
2. Signal generator 0.1Hz-1MHz 1
3. CRO 0Hz-20MHz 1
4. Connecting wires

CIRCUIT DIAGRAM:

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PROCEDURE: -
1. Connect the circuit diagram as shown in figure for common base amplifier.
2. Adjust input signal amplitude in the function generator and observe an amplified
voltage at the output without distortion.
3. By keeping input signal voltage, say at 50mV, vary the input signal frequency
from 0 to 1MHz in steps as shown in tabular column and note the corresponding
output voltages.
4. Find Voltage Gain.
5. Draw a semi log graph for Gain in dB Vs Frequency.

PRECAUTIONS:

1. Avoid loose connections give proper input voltage

TABULAR
COLUMN: Input = 50mV
Frequency (in Output Voltage Gain Av=Vo/Vi Gain(in dB) =20log10(Vo/Vi)
Hz) (Vo)

20

50

100

1k

10k

100k

200,500K

1M

18
RESULT: -

3. Frequency response of BJT in CB mode amplifier is plotted.

4. Gain = _______dB (maximum).

3. Bandwidth= fH--fL = _________Hz.

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 4. COMMON SOURCE AMPLIFIER CHARACTERISTICS

AIM:
To conduct an experiment on a given JFET and obtain
1) Drain characteristics
2) Transfer Characteristics.
3) To find rd, gm, and μ from the characteristics.

APPARATUS:

S.No Name Range / Value Quantity

1 Dual Regulated D.C Power supply (0–30 Volts) 1

2 JFET BFW 10 or 11 1
3 D.C Ammeter (0 – 20mA) 1
4 D.C Voltmeters (0 – 2V), (0 – 20V) Each 1
5 Bread Board and connecting wires -- 1 Set

CIRCUIT DIAGRAM:-

2
THEORY:
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a voltage
amplifier. (See classification of amplifiers). As a transconductance amplifier, the input voltage is seen as
modulating the current going to the load. As a voltage amplifier, input voltage modulates the amount of
current flowing through the FET, changing the voltage across the output resistance according to Ohm's law.
However, the FET device's output resistance typically is not high enough for a reasonable transconductance
amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major
drawback is the amplifier's limited high-frequency response. Therefore, in practice the output often is routed
through either a voltage follower (common-drain or CD stage), or a current follower (common-gate or CG
stage), to obtain more favorable output and frequency characteristics.

PROCEDURE:

1. Connect the circuit as per the Fig.1,Apply Vdd of 12 Volts DC.

2. Apply I/P Voltage of 20mV at 1KHz from the Signal Generator and observe the O/P on CRO.
3. Vary the frequency from 50 Hz to 1MHz in appropriate steps and note down the corresponding
O/P Voltage Vo in a tabular form .
4. Calculate the Voltage Gain Av = Vo/Vs and note down in the tabular form.
5. Plot the frequency (f) Vs Gain (Av) on a Semi-log Graph sheet
6. Draw a horizontal line at 0.707 times Av and note down the cut off points and the Bandwidth is
given by B.W = f2 – f1.

RESULT:

PRECAUTIONS:

1. Check the wires for continuity before use.

2. Keep the power supply at zero volts before starting the experiment.
3. All the contacts must be intact.
4. For a good JFET ID will be ≥ 11.0 mA at VGS = 0.0 volts if not change the JFET.

VIVA QUESTIONS:

1. What are the advantages of JFET over BJT?

2. Why input resistance in FET amplifier is more than the BJT amplifier?
3. What is a uni-polar device?
4. What is pinch off voltage?
5. What are various FETs?
6. What is Enhancement mode and Depletion mode?
7. Draw the Equivalent circuit of JFET for low frequencies?
8. Write the mathematical equation for gm in terms of gmo?
9. Write equation of FET ID in terms of VGS and Vp?

5. MEASUREMENT OF H-PARAMETERS OF TRANSISTOR IN CB,CE,CC CONFIGURATIONS

2
AIM: To plot the Input and Output characteristics of a transistor connected in Common Emitter
Configuration and to find the h – parameters from the characteristics.

APPARATUS:

S.No Name Range / Value Quantity

1 Dual Regulated D.C Power supply 0–30 Volts 1

2 Transistor BC107 1
3 Resistors 120K 1
4 DC Ammeters (0-200A), (0-200mA) Each 1 No
5 DC Voltmeters (0-2V), (0-20V) Each 1 No
6 Bread Board and connecting wires - 1 Set

CIRCUIT DIAGRAM:-

THEORY:

A transistor is a three terminal device. The terminals are emitter, base, collector. In common emitter
configuration, input voltage is applied between base and emitter terminals and out put is taken across the
collector and emitter terminals. Therefore the emitter terminal is common to both input and output. The
input characteristics resemble that of a forward biased diode curve. This is expected since the Base-Emitter
junction of the transistor is forward biased. As compared to CB arrangement IB increases less rapidly with
VBE . Therefore input resistance of CE circuit is higher than that of CB circuit. The output characteristics
are drawn between Ic and VCE at constant IB. the collector current varies with VCE unto few volts only. After
this the collector current becomes almost constant, and independent of V CE. The value of VCE up to which the
collector current changes with VCE is known as Knee voltage. The transistor always operated in the region
above Knee voltage, IC is always constant and is approximately equal to IB.
The current amplification factor of CE configuration is given by

2
 Β = ∆IC/∆IB.

The transistor always operates in the active region. I.e. the collector current IC increases with V CE very
slowly. For low values of the VCE the IC increases rapidly with a small increase in V CE .The transistor is said
to be working in saturation region.
Output resistance is the ratio of change of collector emitter voltage ∆VCE , to change in collector current ∆IC
with constant IB. Output resistance or Output Impedance
hoe = ∆VCE / ∆IC at IB constant.

Input Impedance hie = ∆VBE / ∆IB at VCE constant.

Output impedance hoe = ∆VCE / ∆IC at IB constant.

Reverse Transfer Voltage Gain hre = ∆VBE / ∆VCE at IB constant.

Forward Transfer Current Gain hfe = ∆IC / ∆IB at constant VCE.

PROCEDURE:

TO FIND THE H – PARAMETERS:

Calculation of hie:

Mark two points on the Input characteristics for constant VCE. Let the coordinates of these two points
be (VBE1, IB1) and (VBE2, IB2).

VBE2 - VBE1
hie =
-------------- ;
IB2 - IB1
Calculation of hre:
Draw a horizontal line at some constant IB value on the Input characteristics. Find
VCE2, VCE1, VBE2, VBE1
VBE2 - VBE1
hrb = ---------------;
VCB2 - VCB1

Calculation of hfe:

Draw a vertical line on the out put characteristics at some constant VCE value. Find

Ic2, Ic1 and IB2, IB1 .

2
 IC
2 - IC1
hfe = ---------- ;
IB
2 - IB1

Calculation of hoe:

On the Output characteristics for a constant value of I B mark two points with coordinates (VCE2 , IC2)
and (VCE1 , IC1) .

I C2 -
IC1
------------
hob = --- ;
V CE2 -
VCE1

RESULTS:

h parameters are calculated in CE amplifier.

hie= --------- ohms. hre= -----------

hoe= -------- mhos. hfe = -----------

VIVA QUESTIONS:
1. What is the range of β for the transistor?
2. What are the input and output impedances of CE configuration?
3. Identify various regions in the output characteristics?
4. What is the relation between α and β
5. Define current gain in CE configuration?
6. Why CE configuration is preferred for amplification?
7. What is the phase relation between input and output?
8. Draw diagram of CE configuration for PNP transistor?
9. What is the power gain of CE configuration

2
CIRCUIT DIAGRAMS:

THEORY:

A transistor is a three terminal active device. T he terminals are emitter, base, collector. In CB
configuration, the base is common to both input (emitter) and output (collector). For normal operation, the E-
B junction is forward biased and C-B junction is reverse biased.

In CB configuration, IE is +ve, IC is –ve and IB is –ve. So,

VEB=f1 (VCB,IE) and

IC=f2 (VCB,IB)

With an increasing the reverse collector voltage, the space-charge width at the output junction increases
and the effective base width ‘W’ decreases. This phenomenon is known as “Early effect”. Then, there will be
less chance for recombination within the base region. With increase of charge gradient with in the base
region, the current of minority carriers injected across the emitter junction increases.The current
amplification factor of CB configuration is given by,

Α= ∆IC/ ∆IE

Output resistance is the ratio of change of collector emitter voltage ∆V CE , to change in collector current ∆I C
with constant IB.

Output resistance or Output impedance hoe = ∆VCE / ∆IC at IB constant.

Input Impedance hie = ∆VBE / ∆IE at VCB constant.
Output impedance hoe = ∆VCB / ∆IC at IE constant.
Reverse Transfer Voltage Gain hre = ∆VBE / ∆VCB at IB constant.
2
Forward Transfer Current Gain hfe = ∆IC / ∆IE at constant V
PROCEDURE:

TO FIND THE H – PARAMETERS:

Calculation of hib:

Mark two points on the Input characteristics for constant VCB. Let the coordinates of

these two points be (VEB1, IE1) and (VEB2, IE2).

VEB2 - VEB1
hib =
-------------
--- ;
IE2 -
IE1
Calculation of hrb:
Draw a horizontal line at some constant IE value on the input characteristics. Find
VCB2, VCB1, VEB2, VEB1
VEB2 - VEB1
hrb = -----------------;
VCB2 - VCB1

Calculation of hfb:
Draw a vertical line on the Output characteristics at some constant VCB value. Find
Ic2, Ic1 and IE2, IE1 .
I C2 -
IC1
-----------
hfb = -;
I E2 -
IE1

Calculation of hob:

On the Output characteristics for a constant value of I E mark two points with coordinates (VCB2 , IC2)
and (VCB1 , IC1) .

I C2 -
IC1
------------
hob = --- ;
V CB2 -

2
 VCB1

RESULTS:

h parameters are calculated in CB amplifier.

hib= --------- ohms. hrb= -----------

hob= -------- mhos. hfb = -----------

VIVA QUESTIONS:
1. What is the range of α for the transistor?
2. Draw the input and output characteristics of the transistor in CB configuration?
3. Identify various regions in output characteristics?
4. What is the relation between α and β?
5. What are the applications of CB configuration?
6.What are the input and output impedances of CB configuration?
7. Define α(alpha)?
8. What is EARLY effect?
9. Draw diagram of CB configuration for PNP transistor?
10. What is the power gain of CB configuration?

CIRCUIT DIAGRAM:-

2
THEORY:
   In common-collector amplifier the input is given at the  base and the output is taken at the emitter. In
this amplifier, there is no phase inversion between input and output. The input impedance of the CC
amplifier is very high and output impedance is low. The voltage gain is less than unity. Here the collector is
at ac ground and the capacitors used must have a negligible reactance at the frequency of operation.
                  This amplifier is used for impedance matching and as a buffer amplifier. This circuit is also
known as emitter follower.
PROCEDURE:
TO FIND THE H – PARAMETERS:

Calculation of hic:
hic=(Vbc/ib)
Calculation of hre:
hre=(Vbc/Vec)

Calculation of hfe:
Ie
-----------
hfe = -;
Ib

Calculation of hoe:

Ie
------------
hob = --- ;
V ec
RESULTS:

h parameters are calculated in CC amplifier.

hic= --------- ohms. hre= -----------

hob= -------- mhos. Hfe = -----------

2
 6.INPUT AND OUTPUT CHARACTERISTICS OF FET IN CS CONFIGURATION

AIM:

To conduct an experiment on a given JFET and obtain

1. Drain characteristics
2. Transfer Characteristics.
3. To find rd, gm, and μ from the characteristics.

APPARATUS:

S.No Name Range / Value Quantity

1 Dual Regulated D.C Power supply (0–30 Volts) 1

2 JFET BFW 10 or 11 1
3 D.C Ammeter (0 – 20mA) 1
4 D.C Voltmeters (0 – 2V), (0 – 20V) Each 1
5 Bread Board and connecting wires -- 1 Set

CIRCUIT DIAGRAM:-

THEORY:
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a voltage
amplifier. (See classification of amplifiers). As a transconductance amplifier, the input voltage is seen as
modulating the current going to the load. As a voltage amplifier, input voltage modulates the amount of
current flowing through the FET, changing the voltage across the output resistance according to Ohm's law.
However, the FET device's output resistance typically is not high enough for a reasonable transconductance
amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major
drawback is the amplifier's limited high-frequency response. Therefore, in practice the output often is routed
through either a voltage follower (common-drain or CD stage), or a current follower (common-gate or CG
stage), to obtain more favorable output and frequency characteristics.

2
PROCEDURE:

DRAIN CHARACTERISTICS:

1. Connect the circuit as per the Fig. 1 and start with VGG and VDD keeping at zero volts.
2. Keep VGG such that VGS = 0 volts, Now vary VDD such that VDS Varies in steps of 1 volt up to 10 volts.
And Note down the corresponding Drain current ID
3. Repeat the above experiment with VGS = -1V and -2V and tabulate the readings.
4. Draw a graph VDS Vs ID against VGS as parameter on graph.
5. From the above graph calculate rd and note down the corresponding diode current against the voltage
in the tabular form.
6.Draw the graph between voltages across the Diode Vs Current through the diode in the first quadrant as
shown in fig.

TRANSFER CHARACTERISTICS:

1. Set VGG and VDD at zero volts .keep VDS = 1Volt.

2. Vary VGG such that VGS varies in steps of 0.5 volts. Note down the corresponding Drain current I D,
until ID = 0mA and Tabulate the readings.

3. Repeat the above experiment for VDS = 3.0 Volts and 5.0 Volts and tabulate the readings.
4.Draw graph between VGS Vs ID with VDS as parameter.

5. From the graph find gm.

6. Now μ = gm x rd.

TABULAR FORM:

DRAIN CHARACTERISTICS:

VGS = 0 volts VGS = -1V VGS = -2V

S.No
VDS (V) ID (mA) ID (mA) ID (mA)
1 0.0
2 0.5
3 1.0
4 1.5
5 2.0
6 2.5
7 3.0
8 3.5

3
TRANSFER CHARACTERISTICS:

VDS = 1.0V VDS = 3.0V VDS = 5.0V

S.No
VGS (V) ID (mA) ID (mA) ID (mA)
1 0.0
2 0.5
3 1.0
4 1.5
5 2.0

MODEL GRAPH:

CALCULATIONS:
CALCULATION OF rd :

Construct a Triangle on one of the output characteristic for a particular V GS in the active region and
find ΔVDS and ΔI D
Now rd = ΔVDS/ ΔID (VGS = constant)

CALCULATION OF gm :

Construct a Triangle on one of the Transfer characteristics for a particular VDS find ΔVGS and ΔID.
Now gm = ΔID/Δ VGS (VDS = constant).

CALCULATION OF μ :
μ = gm*rd.
3
RESULT:
PRECAUTIONS:

1. Check the wires for continuity before use.

2. Keep the power supply at zero volts before starting the experiment.
3. All the contacts must be intact.
4. For a good JFET ID will be ≥ 11.0 mA at VGS = 0.0 volts if not change the JFET.

VIVA QUESTIONS:

1. What are the advantages of JFET over BJT?

2. Why input resistance in FET amplifier is more than the BJT amplifier?
3. What is a uni-polar device?
4. What is pinch off voltage?
5. What are various FETs?
6. What is Enhancement mode and Depletion mode?
7. Draw the Equivalent circuit of JFET for low frequencies?
8. Write the mathematical equation for gm in terms of gmo?
9. Write equation of FET ID in terms of VGS and Vp?

3
 7.REALIZATION OF BOOLEAN EXPRESSIONS USING GATES

AIM: Realization of Boolean expressions by using logic gates.

Apparatus Required: IC 7420, Trainer kit, Connecting wires, patch cards.

Not/complement Gate:

F=x’

Truth table:

AND Gate:

F=xy

Truth table:

3
OR Gate:

F=x+y

Truth table:

NAND Gate:

F=(xy)’

Truth table:

3
NOR Gate:

F=(x+y)’

Truth table:

EX-OR Gate:

F=xy’+x’y

Truth table:

3
EX-NOR Gate:

F= (xy’+x’y)’

Truth table:

PROCEDURE:

PART (A):
1. Supply connections are given at the corresponding pins of ICs.
2. Each IC is taken separately and the individual gates in each IC are tested by
giving inputs and the truth tables are verified.
3. Same procedure is repeated for all ICs.

PART (B):
1. Connect the circuit as per the given expression
I. F=(x+Y)’+y
II. F=(xy)’+x
III. F=(xy’+x’y)
IV. F=(xy’+x’y)

PRECAUTIONS:
1. The power supply pins must be checked whether power is available at
those pins using test probes.
2. No loose connections should be there and care must be taken to avoid
3
 shorting of pins

RESULT:

SAMPLE QUESTIONS:
4. Which logic gate gives the ouput logic high when if any one of input is high.
5. Which logic gate gives the ouput logic 0 when if any one of input is high.
6. Which logic gate gives the ouput logic high when both the inputs given as same.

3
 8.DESIGN AND REALIZATION OF LOGIC GATES USING UNIVERSAL GATES

AIM: To verify NAND and NOR as universal gates

Apparatus Required: IC 7420, Trainer kit, Connecting wires, patch cards.

REALIZATION OF BASIC GATE OPERATIONS USING NAND GATES:

1. AND Operation: 00
1 00
31
2 3
2

2. NOT Operation: 03
1
3
2

3. OR Operation: 03
1
3
2
03
1
3
2

03
1
3
2

4. XOR & XNOR Operation:

3
REALIZATION OF BASIC GATE OPERATIONS USING NOR GATE:

1. AND Operation: 02
2
1
3

02
2
1
3

02
2
1
3

2. NOT Operation: 02
2
1
3

3. OR Operation:
02
2 02
1 2
3 1
3

4. XNOR & XOR Operation:

3
PROCEDURE:

PART (A):
4. Supply connections are given at the corresponding pins of ICs.
5. Each IC is taken separately and the individual gates in each IC are tested by giving inputs and
the truth tables are verified.
6. Same procedure is repeated for all ICs.
PART (B):
2. Supply connections are given at the corresponding pins of ICs.
3. For realization of individual gates using NAND gates alone, the connections are made as per
the logic diagrams.
4. Inputs are given and the truth tables of individual gates are verified.
5. The same procedure is repeated for realization of individual gates using NOR gates.

PRECAUTIONS:

1. The power supply pins must be checked whether power is available at

those pins using test probes.
2. No loose connections should be there and care must be taken to avoid
shorting of pins.

RESULT:

SAMPLE QUESTIONS:
1. If one of the inputs of an EX-OR gate is high, its output will be--------
(same as other input/inverse of other input).
2. To INHIBIT( or DISABLE) an AND gate one of its input is connected to logic level------(0/1).
3. To DISABLE a NOR gate one of its inputs needs to be connected
to logic level-------------(0/1)
4. The number of rows in a truth table of 4 variables are------------------.
5. A 3 input NOR gate is required to detect the simultaneous occurrence of all the inputs in the LOW
state. Its output is-----------------------------(active low /active-high).
6. The minimum number of bits required to distinguish 108 distinct objects is--------.
7. What is the difference between a positive logic system and negative logic system?
8. What are universal gates? Why that name?
9. Minimum number of NAND gates necessary to realize EX-OR gate using NAND gates only is
--------.
10. Minimum number of NOR gates necessary to realize EX-OR gate using NOR gates only is
4
 9.GENERATION OF CLOCK USING NAND / NOR GATES

AIM: To Study and implement the generation of clock using NAND/NOR gates

APPARATUS:-
1) Trainer kit
2) Patch chords
3) CRO
4) Power supply

CIRCUIT DIAGRAM:-

PROCEDURE:-
1) Connect the power chord to the mains power supply
2) Turn on the trainer kit you can observe the led indication on the kit.
3) Now connect the CRO probe in channel ‘1’ to the NAND gate and connect the positive to the output of
the circuit and negative to the ground.
4) Observe the waveform on the CRO and note down the waveform time period and amplitude of the signal.
5) Plot the graph for the above readings.
 The above steps repeated for the NOR gate also.

OUTPUT WAVEFORMS:-

RESULT:

4
 10. DESIGN A 4 – BIT ADDER / SUBTRACTOR

AIM: To study and implement the 4 bit Adder/Subractor

APPARATUS:
1. Trainer kits
2. Patch cards
3. Power supply
CIRCUIT DIAGRAM:

4
RESULT: hence the 4bit adder/subtractor is implemented.
4
 11. DESIGN AND REALIZATION A SYNCHRONOUS AND
ASYNCHRONOUS COUNTER USING FLIP-FLOPS

AIM: Design and realization a synchronous and asynchronous counter using flip flops.
APPARATUS:
1. Trainer kits
2. Patch cards
3. Power supply

PROCEDURE:

1. Power supply connections are made for the two separate 7476 ICs.
2. The preset and clear pins of all flip-flops are disabled by connecting to HIGH for normal operation of
flip- flops and all JK inputs to 1( Vcc or HIGH)

3. All connections are made as per the circuit diagram. For UP counter operation (0000 to 1111), the Q
output of LSB flip-flop (to which clock of 1 Hz is applied) is connected as clock input for next higher
significant bit flip- flop and so on. For DOWN counter operation(1111 to 0000), the Q’ outputs are
connected as clock input for next significant flip-flops.

4. The Q outputs of all four flip- flops are connected to 4 output indicators for showing the count.

5. Apply clock input from pulser (press push button in the pulser and release it to produce a single
pulse) and verify the count and also counter operation. You can also give clock input of low
frequency from clock generator( about 1 Hz).

4
BINARY 4-BIT SYNCHRONOUS UP COUNTER:

BINARY 4-BIT SYNCHRONOUS DOWN COUNTER:

4
BINARY 4-BIT ASYNCHRONOUS UP COUNTER:

BINARY 4-BIT SYNCHRONOUS DOWN COUNTER:

PRECAUTIONS:

1. No pins must be left open. If we are not using particular pins in that
application, disable those pins.
2. Care has to be taken in identifying the LSB and MSBs.
2. Avoid loose connections and shorting of pins.

RESULT:

4
 EXPERMENT 12
REALIZATION OF LOGIC GATES USING DTL,TTL,ECL,ETC.

AIM: Realization of logic gates using DTL,TTL,ECL,etc.

EQUIPMENTS:
Resistors – TR(2N2222)- D(1N4007) – Voltmeter – Power
supply – Orcad software program.

CIRCUIT DIAGRAM:

 The basic DTL inverter

Figure 1. The DTL inverter

 The NAND gate

 The AND gate

4
 Figure 3. Two-input AND Gate

 The NOR gate

Figure 4. Two-input NOR Gate

 The OR gate

4
 The DTL OR gate combines the DTL NOR gate with DTL inverter. Figure 5
shows a two-input OR gate.

Figure 5. Two-input OR Gate

PROCEDURE:

Part 1:

1. Construct the circuit shown in Figure 2, V = 5V, RC= 1K, RB =10K

2. Find the truth table filling the following

VA VB VOUT
0 0
0 5
5 0
5 5

3. Filling the following table by making VA = VB = VIN and Draw the

VTC of this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5
Vout

4. Determine VOH,VOL,VIH,VIL
5. Draw the VTC of this gate by using the Orcad.

4
Part 2:
Draw the VTC of the circuit shown in Figure 3 by using the
Orcad and show the results.

V = 5V, RC= 1K, RB =10K

Part 3:

1. Construct the circuit shown in Figure 4, V = 5V, RC= 1K, RB =10K

2. Find the truth table filling the following

VA VB VOUT
0 0
0 5
5 0
5 5

3. Filling the following table by making VA = VB = VIN and Draw the

VTC of this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5
Vout

4. Determine VOH,VOL,VIH,VIL
5. Draw the VTC of this gate by using the Orcad.

Part 4:
Draw the VTC of the circuit shown in Figure 5 by using the Orcad and
show the results.

V = 5V, RC= 1K, RB =10K

 The Basic TTL Inverter

Figure1 shows the proposed change to convert a DTL inverter to a Transistor- Transistor
logic TTL equivalent. We have merely used one transistor to replace two diodes.

5
 Figure 1. The TTL inverter
 The NAND Gate
Figure 2 shows a two input TTL NAND gate. A multiple emitter BJT is used to
provide the inputs to the gate. A separate BJT could be used for each input with
coupled collectors. An advantage of the multiple emitters BJT is that it requires

much less chip area than using individual resistors.

Figure 2. Two-input NAND Gate

 The AND Gate

The TTL AND gate combines the TTL NAND Gate with TTL
Inverter.
Figure 3 shows a two-input AND Gate.

Figure 3. Two-input AND Gate

 The NOR Gate

5
 Figure 4 shows the schematic diagram of a TTL NOR Gate. As
you recall from earlier experiments, it is substantially the same as the
RTL and DTL NOR Gates we have already explored. The only

difference is that this time we are using the TTL input circuit.
Figure 4. Two-input NOR Gate

 The OR Gate

Figure 5. Two-input OR Gate

5
 If all inputs are less than VIL = VBE, 2(FA) – VCE, 1(sat) then both
BJT's (Q2, Q4) is cutoff, and Q6 is saturated. As a result the output
voltage is
VOL = VCE (sat).
Procedure:

Part 1:

1. Construct the circuit shown in Figure 2, V = 5V, RC= 1K, RB =10K

2. Find the truth table filling the following

VA VB VOU
T
0 0
0 5
5 0
5 5

3. Filling the following table by making VA = VB = VIN and Draw the

VTC of this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5
Vout

4. Determine VOH,VOL,VIH,VIL
5. Draw the VTC of this gate by using the Orcad.

Part 2:

Draw the VTC of the circuit shown in Figure 3 by using the

Orcad and show the results.

V = 5V, RC= 1K, RB =10K

Part 3:

1. Construct the circuit shown in Figure 4, V = 5V, RC= 1K, RB =10K

5
 2. Find the truth table filling the following

VA VB VOU
T
0 0
0 5
5 0
5 5
3. Filling the following table by making VA = VB = VIN and Draw the
VTC of this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5
Vout

4. Determine VOH,VOL,VIH,VIL
5. Draw the VTC of this gate by using the Orcad.

Part 4:

Draw the VTC of the circuit shown in Figure 5 by using the

Orcad and show the results.

V = 5V, RC= 1K, RB =10K

Theoretical Background
a) BJT Current Switch
Figure (1) shows the ideal BJT current switch. The input is at the base
of Qi, with the base of Qr held at a constant reference voltage VBB.
The coupled emitters are ideally connected to a constatnr current
sourc IEE. Where a resistor RE is connected between the coupled
emitters and VBB. The current IRE is that given by:

IRE = (VE – (-VEE)) / RE.

5
Outputs are taken at the collector of Qi and Qr, giving both
inverting and non- inverting outputs:
Vinv = Vci = Vcc –
Ici*Rci And
Vninv = Vcr = Vcc – Icr*Rcr

b) ECL current-switch voltage transfer characteristic

Figure (2) shows the basic ECL inverter and it's VTC.

5
5
 c) Basic ECL NOR/OR Gate
By adding additional input transistors with coupled collectors
and coupled emitters to the ECL current switch, the inverting
output becomes a NOR outputs and the non-inverting output
becomes an OR output.

First Configuration

2)Second configuration:

Procedures
Part 1: 5
 a) Connect the circuit in Figure 2 with VCC = 5V, -VEE =
0V, and VBB = 2.5V.
b) Fill in the following table to find VTC

Vin 0 0.5 1 1.5 2 2 2.4 2.5 2.6 2.7

Vout

Vin 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4 5

Vout

c) Determine VOH,VOL,VIH,VIL
d) Draw the VTC of this gate by using the Orcad.

Part 2:

Draw the VTC of the circuit shown in Figure 4 by using the

Orcad and show the results.