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Product Sample & Technical Tools & Support &

Folder Buy Documents Software Community

Not Recommended for New Designs


bq78350
SLUSB48 – JULY 2014

bq78350 CEDV Li-Ion Gas Gauge and Battery Management Controller Companion to the
bq769x0 Battery Monitoring AFE
1

1 Features
• Compensated End-of-Discharge Voltage (CEDV) 2 Applications
Gauging Algorithm • Light Electric Vehicles (LEVs): eBikes, eScooters,
• Supports SMBus Host Communication Pedelec, and Pedal-Assist Bicycles
• Flexible Configuration for 3- to 5-Series • Power and Gardening Tools
(bq76920), 6- to 10-Series (bq76930), and 9- to • Battery Backup and Uninterruptible Power Supply
15-Series (bq76940) Li-Ion and LiFePO4 Batteries (UPS) Systems
• Supports Battery Configurations up to 320 Ahr • Wireless Base Station Backup Systems
• Supports Charge and Discharge Current • Telecom Power Systems
Reporting up to 320 A
• External NTC Thermistor Support from 3 Description
Companion AFE The Texas Instruments bq78350 Li-Ion and LiFePO4
• Full Array of Programmable Protection Features Battery Management Controller and companion to the
– Voltage bq769x0 family of Analog Front End (AFE) protection
devices provides a comprehensive set of Battery
– Current Management System (BMS) subsystems, helping to
– Temperature accelerate product development for faster time-to-
– System Components market.
• Lifetime Data Logging Device Information(1)
• Supports CC-CV Charging, Including Precharge, PART NUMBER PACKAGE BODY SIZE (NOM)
Charge Inhibit, and Charge Suspend
bq78350 TSSOP (30) 7.80 mm x 6.40 mm
• Offers an Optional Resistor Programmable
(1) For all available packages, see the orderable addendum at
SMBus Slave Address for up to Eight Different the end of the datasheet.
Bus Addresses
• Drives up to a 5-Segment LED or LCD Display for
State-Of-Charge Indication
• Provides SHA-1 Authentication

4 Simplified Schematic

PACK+
bq76920

BAT
VC5 REGSRC
VC4 REGOUT
VCC LED1
VC3 CAP 1
MRST LED2
VC2 TS 1
BAT
VC1 SCL VAUX LED3
VC0 SDA KEYIN LED4
SRP VSS PRES
LED5
SRN CHG RBI
PUSH-BUTTON SAFE PWRM
ALERT DSG
FOR BOOT VSS DISP

SCL COM

SDA VEN
SMBC
ALERT SMBC
PRECHG SMBD
SMBA SMBD
GPIOA
GPIOB ADREN PACK–

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq78350 Not Recommended for New Designs
SLUSB48 – JULY 2014 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.13 Typical Characteristics ......................................... 11
2 Applications ........................................................... 1 9 Detailed Description ............................................ 12
3 Description ............................................................. 1 9.1 Overview ................................................................. 12
4 Simplified Schematic............................................. 1 9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
5 Revision History..................................................... 2
9.4 Device Functional Modes........................................ 14
6 Description (continued)......................................... 3
9.5 Programming........................................................... 15
7 Pin Configuration and Functions ......................... 4
10 Application and Implementation........................ 16
8 Specifications......................................................... 6
10.1 Application Information.......................................... 16
8.1 Absolute Maximum Ratings ...................................... 6
10.2 Typical Applications .............................................. 16
8.2 Handling Ratings....................................................... 6
11 Power Supply Recommendations ..................... 25
8.3 Recommended Operating Conditions....................... 6
8.4 Thermal Information .................................................. 7 12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
8.5 Electrical Characteristics: Supply Current................. 7
12.2 Layout Example .................................................... 27
8.6 Electrical Characteristics: I/O .................................... 7
8.7 Electrical Characteristics: ADC ................................. 8 13 Device and Documentation Support ................. 28
8.8 Electrical Characteristics: Power-On Reset .............. 8 13.1 Related Documentation......................................... 28
8.9 Electrical Characteristics: Oscillator......................... 8 13.2 Trademarks ........................................................... 28
8.10 Electrical Characteristics: Data Flash Memory ....... 8 13.3 Electrostatic Discharge Caution ............................ 28
8.11 Electrical Characteristics: Register Backup ............ 9 13.4 Glossary ................................................................ 28
8.12 SMBus Timing Specifications ............................... 10 14 Mechanical, Packaging, and Orderable
Information ........................................................... 28

5 Revision History
DATE REVISION NOTES
July 2014 * Initial Release

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6 Description (continued)
The bq78350 controller and the bq769x0 AFE support from 3-series to 15-series cell applications. The bq78350
provides an accurate fuel gauge and state-of-health (SoH) monitor, as well as cell balancing and a full range of
voltage-, current-, and temperature-based protection features.
The bq78350 offers optional LED or LCD display configurations for the capacity reporting. It also makes data
available over its SMBus 1.1 interface. Battery history and diagnostic data is also kept within the device in non-
volatile memory and is available over the same interface.

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7 Pin Configuration and Functions

30-Pin DBT Package

COM 1 30 SMBA

ALERT 2 29 ADREN
SDA 3 28 GPIO B

SCL 4 27 RBI
PRECHG 5 26 VCC

VAUX 6 25 VSS
BAT 7 24 MRST
PRES 8 23 VSS

KEYIN 9 22 VSS
SAFE 10 21 GPIO A
SMBD 11 20 LED5

VEN 12 19 LED4
SMBC 13 18 LED3

DISP 14 17 LED2
PWRM 15 16 LED1

Pin Functions
PIN
I/O (1) DESCRIPTION
NO. NAME
1 COM O Open Drain Output LCD common connection
2 ALERT I/O Input/Output to the bq769x0 AFE
3 SDA I/O Data transfer to and from the bq769x0 AFE. Requires a 10-k pullup to VCC.
4 SCL I/O Communication clock to the bq769x0 AFE. Requires a 10-k pullup to VCC.
Programmable polarity (default is active low) output to enable an optional precharge FET. This pin
5 PRECHG O has an internal pullup to 2.5 V when configured as active high, and is open drain when configured
as active low.
6 VAUX AI Auxiliary voltage input
7 BAT AI Translated battery voltage input
Active low input to sense system insertion. This typically requires additional ESD protection. If this
8 PRES I
pin is not used, then it should be tied to VSS.
A low level indicates application key-switch is inactive on position. A high level causes the DSG
9 KEYIN I
protection FET to open.
10 SAFE O Active high output to enforce an additional level of safety protection (for example, fuse blow)
SMBus data open-drain bidirectional pin used to transfer an address and data to and from the
11 SMBD I/OD
bq78350
Active high voltage translation enable. This open drain signal is used to switch the input voltage
12 VEN O
divider on/off to reduce the power consumption of the BAT translation divider network.
13 SMBC I/OD SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the bq78350
Display control for the LEDs. This pin is typically connected to bq78350 REGOUT via a 100-KΩ
14 DISP I resistor and a push-button switch connect to VSS. Not used with LCD display enabled and can be
tied to VSS.

(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
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Pin Functions (continued)


PIN
I/O (1) DESCRIPTION
NO. NAME
15 PWRM O Power mode state indicator open drain output
LED1/LCD1 display segment that drives an external LED/LCD, depending on the firmware
16 LED1 O
configuration
LED2/LCD2 display segment that drives an external LED/LCD, depending on the firmware
17 LED2 O
configuration
LED3/LCD3 display segment that drives an external LED/LCD, depending on the firmware
18 LED3 O
configuration
LED4/LCD4 display segment that drives an external LED/LCD, depending on the firmware
19 LED4 O
configuration
LED5/LCD5 display segment that drives an external LED/LCD, depending on the firmware
20 LED5 O
configuration
21 GPIO A I/O Configurable Input or Output. If not used, tie to VSS.
22 VSS — Negative supply voltage
23 VSS — Negative supply voltage
Master reset input that forces the device into reset when held low. This pin must be held high for
24 MRST I
normal operation.
25 VSS — Negative supply voltage
26 VCC P Positive supply voltage
RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of
27 RBI P
short circuit condition.
28 GPIO B I/O Configurable Input or Output. If not used, tie to VSS.
29 ADREN O Optional digital signal enables address detection measurement to reduce power consumption.
30 SMBA IA Optional SMBus address detection input

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8 Specifications
8.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC relative to VSS Supply voltage range –0.3 2.75 V
V(IOD) relative to VSS Open-drain I/O pins –0.3 6 V
VI relative to VSS Input voltage range to all other pins –0.3 VCC + 0.3 V
TA Operating free-air temperature range –40 85 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

8.2 Handling Ratings


MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
(1) (2)
VESD Human Body Model (HBM) ESD stress voltage –2 2 kV
Charged Device Model (CDM) ESD stress voltage (3) –500 500 V

(1) Electrostatic discharge (ESD) that measures device sensitivity and immunity to damage caused by assembly line electrostatic
discharges into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM enables safe
manufacturing with a standard ESD control process. Pins listed as 1000 V may actually have a higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM enables safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have a higher performance.

8.3 Recommended Operating Conditions


VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC Supply voltage 2.4 2.5 2.6 V
SAFE VCC
SMBC, SMBD, VEN 5.5 V
VO Output voltage range
ADREN, GPIO A, GPIO B, SDATA, SCLK,
VCC
PWRM, LED1...5 (when used as GPO)
BAT, VAUX, SMBA 1
SMBD, SMBC, ALERT, DISP, PRES, KEYIN 5.5
VIN Input voltage range V
SDATA, GPIO A, GPIO B, LED1...5 (when
VCC
used as GPI)
TOPR Operating Temperature –40 85 °C

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8.4 Thermal Information


bq78350
THERMAL METRIC (1) TSSOP (DBT) QFN (RSM) UNIT
30 PINS 32 PINS
RJA, High K Junction-to-ambient thermal resistance (2) 81.4 37.4
(3)
RJC(top) Junction-to-case(top) thermal resistance 16.2 30.6
RJB Junction-to-board thermal resistance (4) 34.1 7.7
°C/W
ψJT Junction-to-top characterization parameter (5) 0.4 0.4
ψJB Junction-to-board characterization parameter (6) 33.6 7.5
RθJC(bottom) Junction-to-case(bottom) thermal resistance (7) n/a 2.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer

8.5 Electrical Characteristics: Supply Current


VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Operating mode current No flash programming 650 (1) μA
(2)
I(SLEEP) Low-power storage mode current SLEEP mode 300 μA
I(SHUTDOWN) Low-power SHUTDOWN mode current SHUTDOWN mode 0.1 1 μA

(1) The actual current consumption of this mode fluctuates during operation over a 1-s period. The value shown is an average using the
default data flash configuration.
(2) The actual current consumption of this mode fluctuates during operation over a user-configurable period. The value shown is an average
using the default data flash configuration.

8.6 Electrical Characteristics: I/O


VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output voltage low SMBC, SMBD,
SDATA, SCLK, SAFE, ADREN, VEN, IOL = 0.5 mA 0.4 V
VOL GPIO A, GPIO B, PWRM
Output voltage low LED1, LED2, LED3,
IOL = 3 mA 0.4
LED4, LED5
Output voltage high SMBC, SMBD,
VOH SDATA, SCLK, SAFE, ADREN, VEN, IOH = –1 mA VCC – 0.5 V
GPIO A, GPIO B, PWRM
Input voltage low SMBC, SMBD, SDATA,
VIL SCLK, ALERT, DISP, SMBA, GPIO A, –0.3 0.8 V
GPIO B, PRES, KEYIN
Input voltage high SMBC, SMBD,
SDATA, SCLK, ALERT, SMBA, GPIO A, 2 6 V
VIH GPIO B
Input voltage high DISP, PRES, KEYIN 2 VCC + 0.3 V
CIN Input capacitance 5 pF
ILKG Input leakage current 1 µA

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8.7 Electrical Characteristics: ADC


VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range BAT, VAUX –0.2 1 V
Conversion time 31.5 ms
Resolution (no missing codes) 16 bits
Effective resolution 14 15 bits
Integral nonlinearity ±0.03% FSR (1)
(2)
Offset error 140 250 µV
Offset error drift (2) TA = 25°C to 85°C 2.5 18 V/°C
Full-scale error (3) ±0.1% ±0.7%
Full-scale error drift 50 PPM/°C
Effective input resistance (4) 8 MΩ

(1) Full-scale reference


(2) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference
(3) Uncalibrated performance. This gain error can be eliminated with external calibration.
(4) The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.

8.8 Electrical Characteristics: Power-On Reset


VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT– Negative-going voltage input 1.7 1.8 1.9 V
VHYS Power-on reset hysteresis 50 125 200 mV

8.9 Electrical Characteristics: Oscillator


VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(OSC) Operating frequency 4.194 MHz
–3% 0.25% 3%
f(EIO) Frequency error (1) (2)
TA = 20°C to 70°C –2 0.25 2
t(SXO) Start-up time (3) 2.5 5 ms
LOW FREQUENCY OSCILLATOR
f(LOSC) Operating frequency 32.768 kHz
–2.5% 0.25% 2.5%
f(LEIO) Frequency error (2) (4)
TA = 20°C to 70°C –1.5 0.25 1.5
t(LSXO) Start-up time (5) 500 ms

(1) The frequency error is measured from 4.194 MHz.


(2) The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25°C.
(3) The start-up time is defined as the time it takes for the oscillator output frequency to be within 1% of the specified frequency.
(4) The frequency error is measured from 32.768 kHz.
(5) The start-up time is defined as the time it takes for the oscillator output frequency to be ±3%.

8.10 Electrical Characteristics: Data Flash Memory


VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data retention See note (1) 10 Years
tDR
Flash programming write-cycles See note (1) 20,000 Cycles
(1)
t(WORDPROG) Word programming time See note 2 ms
I(DDdPROG) Flash-write supply current See note (1) 5 10 mA

(1) Specified by design. Not production tested.

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8.11 Electrical Characteristics: Register Backup


VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(RB) > V(RBMIN), VCC < VIT– 1500 nA
RB data-retention input
I(RB) V(RB) > V(RBMIN), VCC < VIT–, TA = 0°C
current 40 160
to 50°C
RB data-retention
V(RB) 1.7 V
voltage (1)

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8.12 SMBus Timing Specifications


VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SMBus operating
fSMB SLAVE mode, SMBC 50% duty cycle 10 100 kHz
frequency
SMBus master clock MASTER mode, no clock low slave
fMAS 51.2
frequency extend
Bus free time between
tBUF 4.7 ms
start and stop
Hold time after
tHD:STA 4
(repeated) start
Repeated start setup
tSU:STA 4.7
time
tSU:STO Stop setup time 4
RECEIVE mode 0
tHD:DAT Data hold time
TRANSMIT mode 300 ns
tSU:DAT Data setup time 250
tTIMEOUT Error signal/detect See note (1) 25 35 ms
tLOW Clock low period 4.7 µs
tHIGH Clock high period See note (2) 4 50
Cumulative clock low
tLOW:SEXT See note (3) 25 ms
slave extend time
Cumulative clock low
tLOW:MEXT See note (4) 10
master extend time
tF Clock/data fall time (VILMAX – 0.15 V) to (VIHMIN + 0.15 V) 300 ns
tR Clock/data rise time 0.9 VCC to (VILMAX – 0.15 V) 1000

(1) The bq78350 times out when any clock low exceeds tTIMEOUT.
(2) tHIGH:MAX is minimum bus idle time. SMBC = 1 for t > 50 μs causes a reset of any transaction in progress involving the bq78350.
(3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to stop.
(4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to stop.

Figure 1. SMBus Timing Diagram

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8.13 Typical Characteristics

1.2280 174.5
1.2275
Internal Voltage Reference (V)

174.0
1.2270

ADC Offset Error (V)


1.2265 173.5
1.2260
173.0
1.2255
1.2250 172.5

1.2245 172.0
1.2240
171.5
1.2235
1.2230 171.0
±40 ±20 0 20 40 60 80 ±40 ±20 0 20 40 60 80
Temperature (ƒC) C001 Temperature (ƒC) C002

Figure 2. Internal Voltage Reference Figure 3. ADC Offset Error


3.05 32.85
3.00
32.80
2.95
LED Sink Current (mA)

2.90 LFO Frequency (kHz)


32.75
2.85
2.80 32.70
2.75
32.65
2.70
2.65
32.60
2.60
2.55 32.55
±40 ±20 0 20 40 60 80 ±40 ±20 0 20 40 60 80
Temperature (ƒC) C003 Temperature (ƒC) C004

Figure 4. LED Sink Current Figure 5. LFO Frequency


4.190

4.185
HFO Frequency (MHz)

4.180

4.175

4.170

4.165

4.160
±40 ±20 0 20 40 60 80
Temperature (ƒC) C005

Figure 6. HFO Frequency

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9 Detailed Description

9.1 Overview
The bq78350 Li-Ion and LiFePO4 Battery Management Controller is the companion to the bq769x0 family of
Analog Front End (AFE) protection devices. This chipset supports from 3-series to 15-series cell applications with
capacities up to 320 Ahr, and is suitable for a wide range of portable or stationary battery applications. The
bq78350 provides an accurate fuel gauge and state-of-health (SoH) monitor, as well as the cell balancing
algorithm and a full range of voltage-, current-, and temperature-based protection features.
The battery data that the bq78350 gathers can be accessed via an SMBus 1.1 interface and state-of-charge
(SoC) data can be displayed through optional LED or LCD display configurations. Battery history and diagnostic
data is also kept within the device in non-volatile memory and is available over the same SMBus interface.

9.2 Functional Block Diagram


COM, ALERT, SMBA, ADREN,
KEYIN, SAFE, SDA, SCL,
GPIOA
SMBD, SMBC, PRECHG,VAUX,
GPIOB
VEN, DISP BAT, PRES
LED1...5
PWRM

8 8
8

Power VCC
Oscillator 32 kHz Interrupt * 2 Interrupt V SS
Regulation
System Clock Input/Output Controller
Event* 1 AND MRST
Management
RBI
System Clocks
Reset*
Wake Comparator
Event*

Data (8-bit) Analog Front End


Delta-Sigma ADC SRP
CoolRISC AND
CPU DMAddr (16-bit) Integrating SRN
Coulomb Counter

System I /O (13-bit)

PMAddr PMInst
(15-bit) (22-bit)

Peripherals
Communications
Program Memory Data Memory and
SMBus
Timers

Figure 7. Functional Block Diagram

9.3 Feature Description


The following section provides an overview of the device features. For full details on the bq78350 features, refer
to the bq78350 Technical Reference Manual (SLUUAN7).

9.3.1 Primary (1st Level) Safety Features


The bq78350 supports a wide range of battery and system protection features that can be configured. The
primary safety features include:
• Cell over/undervoltage protection
• Charge and discharge overcurrent

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Feature Description (continued)


• Short circuit protection
• Charge and discharge overtemperature with independent alarms and thresholds for each thermistor

9.3.2 Secondary (2nd Level) Safety Features


The secondary safety features of the bq78350 can be used to indicate more serious faults via the SAFE pin. This
pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. The
secondary safety protection features include:
• Safety overvoltage
• Safety undervoltage
• Safety overcurrent in charge and discharge
• Safety overtemperature in charge and discharge
• Charge FET and Precharge FET fault
• Discharge FET fault
• Cell imbalance detection
• Open thermistor detection
• AFE communication fault

9.3.3 Charge Control Features


The bq78350 charge control features include:
• Provides a range of options to configure the charging algorithm and its actions based on the application
requirements
• Reports the appropriate charging current needed for constant current charging, and the appropriate charging
voltage needed for constant voltage charging
• Supports pre-charging/0-volt charging
• Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range

9.3.4 Fuel Gauging


The bq78350 uses Compensated End-of-Discharge Voltage (CEDV) technology to measure and calculate the
available charge in battery cells. The bq78350 accumulates a measure of charge and discharge currents and
compensates the charge current measurement for the temperature and state-of-charge of the battery. The
bq78350 estimates self-discharge of the battery and also adjusts the self-discharge estimation based on
temperature.

9.3.5 Lifetime Data Logging


The bq78350 offers lifetime data logging, where important measurements are stored for warranty and analysis
purposes. The data monitored includes:
• Lifetime maximum temperature
• Lifetime minimum temperature
• Lifetime maximum battery cell voltage per cell
• Lifetime minimum battery cell voltage per cell
• Cycle count
• Maximum charge current
• Maximum discharge current
• Safety events that trigger SafetyStatus() updates. (The 12 most common are tracked.)

9.3.6 Authentication
The bq78350 supports authentication by the host using SHA-1.

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Feature Description (continued)


9.3.7 Battery Parameter Measurements
The bq78350 digitally reads bq769x0 registers containing recent values from the integrating analog-to-digital
converter (CC) for current measurement and a second delta-sigma ADC for individual cell and temperature
measurements.

9.3.7.1 Current and Coulomb Counting


The integrating delta-sigma ADC (CC) in the companion bq769x0 AFE measures the charge/discharge flow of
the battery by measuring the voltage drop across a small-value sense resistor between the SRP and SRN pins.
The 15-bit integrating ADC measures bipolar signals from –0.20 V to 0.20 V with 15-µV resolution. The AFE
reports charge activity when VSR = V(SRP) – V(SRN) is positive, and discharge activity when VSR = V(SRP) – V(SRN)
is negative. The bq78350 continuously monitors the measured current and integrates the digital signal from the
AFE over time, using an internal counter.
To support large battery configurations, the current data can be scaled to ensure accurate reporting through the
SMBus. The data reported is scaled based on the setting of the SpecificationInfo() command.

9.3.7.2 Voltage
The bq78350 updates the individual series cell voltages through the bq769x0 at 1-s intervals. The bq78350
configures the bq769x0 to connect to the selected cells in sequence and uses this information for cell balancing
and individual cell fault functions. The internal 14-bit ADC of the bq769x0 measures each cell voltage value,
which is then communicated digitally to the bq78350 where they are scaled and translated into unit mV. The
maximum supported input range of the ADC is 6.075 V.
The bq78350 also separately measures the average cell voltage through an external translation circuit at the
BAT pin. This value is specifically used for the fuel gauge algorithm. The external translation circuit is controlled
via the VEN pin so that the translation circuit is only enabled when required to reduce overall power
consumption. For correct operation, VEN requires an external pull-up to VCC, typically 100 k.
In addition to the voltage measurements used by the bq78350 algorithms, there is an optional auxiliary voltage
measurement capability via the VAUX pin. This feature measures the input on a 1-s update rate and provides the
programmable scaled value through an SMBus command.
To support large battery configurations, the voltage data can be scaled to ensure accurate reporting through the
SMBus. The data reported is scaled based on the setting of the SpecificationInfo() command.

9.3.7.3 Temperature
The bq78350 receives temperature information from external or internal temperature sensors in the bq769x0
AFE. Depending on the number of series cells supported, the AFE will provide one, two, or three external
thermistor measurements.

9.4 Device Functional Modes


The bq78350 supports three power modes to optimize the power consumption:
• In NORMAL mode, the bq78350 performs measurements, calculations, protection decisions, and data
updates in 1-s intervals. Between these intervals, the bq78350 is in a reduced power mode.
• In SLEEP mode, the bq78350 performs measurements, calculations, protection decisions, and data updates
in adjustable time intervals. Between these intervals, the bq78350 is in a reduced power mode.
• In SHUTDOWN mode, the bq78350 is completely powered down.
The bq78350 indicates through the PWRM pin which power mode it is in. This enables other circuits to change
based on the power mode detection criteria of the bq78350.

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9.5 Programming
9.5.1 Physical Interface
The bq78350 uses SMBus 1.1 with packet error checking (PEC) as an option and is used as a slave only.

9.5.2 SMBus Address


The bq78350 determines its SMBus 1.1 slave address through a voltage on SMBA, Pin 30. The voltage is set
with a pair of high value resistors if an alternate address is required and is measured either upon exit of POR or
when system present is detected. ADREN, Pin 29, may be used to disable the voltage divider after use to reduce
power consumption.

9.5.3 SMBus On and Off State


The bq78350 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing this
state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.

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10 Application and Implementation


10.1 Application Information
The bq78350 Battery Management Controller companion to the bq769x0 family of battery monitoring AFEs
enables many standard and enhanced battery management features in a 3-series to 15-series Li-Ion/Li Polymer
battery pack.
To design and implement a complete solution, users need the Battery Management Studio (bqSTUDIO) tool to
configure a "golden image" set of parameters for a specific battery pack and application. The bqSTUDIO tool is a
graphical user-interface tool installed on a PC during development. The firmware installed in the product has
default values, which are summarized in the bq78350 Technical Reference Manual (SLUUAN7). With the
bqSTUDIO tool, users can change these default values to cater to specific application requirements. Once the
system parameters are known (for example, fault trigger thresholds for protection, enable/disable of certain
features for operation, configuration of cells, among others), the data can be saved. This data is referred to as
the "golden image.”

10.2 Typical Applications


The bq78350 can be used with the bq76920, bq76930, or bq76940 device, but as default it is setup for a 5-series
cell, 4400-mA battery application using the bq76920 AFE.

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10.2.1 Schematic

BATT+

R49
100k
Q8
BSS84-7-F

Copyright © 2014, Texas Instruments Incorporated


Typical Applications (continued)

R47
300k
25 ppm/C
REGOUT

R50 R51 R55 R57


100k 1.00Meg 100k 221k
U2
26 16
VCC LED1
17
LED2
6 18
VAUX LED3
7 19
BAT LED4
20
LED5
2
ALERT ALERT
3 14
SDA SDA DISP
4
SCL SCL
12
VEN
8
PRES
9 29
SMB KEYIN ADREN
1 11 10
SMB is required for R77 R72 SMBD SAFE
2 13
gauge setup. SMBC
3 100 5
Signals would require isolation 100 R80 R70 PRECHG PRE
4 24 15
circuit for use in system MRST PWRM
100 100
J4 30 27
SMBA RBI

Product Folder Links: bq78350


21
GND
D30 D32 R73 R76 VSS C25
22
1.00Meg 1.00Meg VSS 0.1µF
1 23
5.6V 5.6V C24 NC VSS
28 25
E2 E4 0.1µF NC VSS
Not Recommended for New Designs

BQ78350DBT GND
GND
Q9 GND GND GND

R48
13.7k C23 CSD17381F4
3300pF
BATT-

GND GND

Figure 8. 5-Series Cell Typical Schematic, Gas Gauge (bq78350)


The schematic is split into two sections: the gas gauge section (Figure 8) and the AFE section (Figure 9).

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bq78350

17
18
bq78350
SLUSB48 – JULY 2014

BATT+ D11
R12
100
U1
10
R11 BAT
12
VC5
10.0k 13 9
VC4 REGSRC
14
R19 VC3
C5 15 8
VC2 REGOUT REGOUT
100 16
VC1
17 7
VC0 CAP1

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C7
1µF 6
R18 TS1
C4
100 18 5
SRP SCL
4
C6 SDA
Typical Applications (continued)

19
1µF SRN
2
R17 CHG C16 C18 RT1 C21 R41 R42


C3 20 1
ALERT DSG 1µF 4700pF 10.0k ohm 4.7µF 10.0k 10.0k
100
11 3
C5 NC VSS
1µF BQ7692000PW C15
C2 R16 2.2µF
100 GND

C4 ALERT SCL
GND GND
1µF SDA
J1
1 C5 C1 R15 R35
2 C4 100 499k C13
3 C3 470pF CHG
4 C2 C3
5 C1 1µF
R13 D26
6 C0 C0 C28 S1
GND C1 R36 3 1
100 18V
395021006 C1 C27 C29 3.01k 4 2 Q16
1µF 0.1µF 4-1437565-1
0.1µF 0.1µF
R59 R61 R65 Q14 GND
PRE
GND GND GND 100 100 GND 10.0k MMBTA92
R69
1.00k

R63 D24 D27


0 R68
1.00Meg

Product Folder Links: bq78350


BATT- R62 R66 R71 D28
4
4
Not Recommended for New Designs

1.00Meg 10.0k 1.00Meg


5,6, 5,6, 16V J3
BATT- R60 1,2,3 7,8 7,8 1,2,3 PACK- 1
NT1 0.001
Q12 Q15
1

Net-Tie CSD17501Q5A D25 CSD17501Q5A


R67 C33
D23 GND 1.00Meg 0.1µF
SMCJ28A 10V E1
28V R64 3 2 D29
1.0k C32
0.1µF
Q13
C30 C31 CSD17381F4

Figure 9. 5-Series Cell Typical Schematic, AFE (bq76920)


0.1µF 0.1µF J2
BATT+ PACK+ 1
www.ti.com

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Typical Applications (continued)


10.2.2 Design Requirements
Table 1 lists the device's default settings and feature configurations when shipped from Texas Instruments.

Table 1. TI Default Settings


Design Parameter Value or State
Cell Configuration 5s2p (5-series with 1 Parallel)
Design Capacity 4400 mAh
Device Chemistry Chem ID 1210 (LiCoO2/graphitized carbon)
Cell Overvoltage (per cell) 4250 mV
Cell Undervoltage (per cell) 2500 mV
Overcurrent in CHARGE Mode 6000 mA
Overcurrent in DISCHARGE Mode –6000 mA
Over Load Current 0.017 V/Rsense across SRP, SRN
Short Circuit in DISCHARGE Mode 0.44 V/Rsense across SRP, SRN
Over Temperature in CHARGE Mode 55°C
Over Temperature in DISCHARGE Mode 55°C
SAFE Pin Activation Enabled No
Safety Over Voltage (per cell) 4400 mV
Safety Under Voltage (per cell) 2500 mV
Shutdown Voltage 2300 mV
Cell Balancing Enabled Yes
Internal or External Temperature Sensor External Enabled
SMB BROADCAST Mode Disabled
Display Mode (# of Bars and LED or LCD) 5-bar LED
Dynamic SMB Address Enabled No (SMB Address = 0x16)
KEYIN Feature Enabled No
PRES Feature Enabled No

10.2.3 Detailed Design Procedure


By default, the bq78350 is initially setup to keep the CHG, DSG, and PCHG FETs OFF and many other features
disabled until the appropriate ManufacturingStatus() bit that enables ManufacturerAccess() commands are
received, or when the default Manufacturing Status is changed.
In the first steps to evaluating the bq78350 and bq769x0 AFE, use the ManufacturerAccess() commands to
ensure correct operation of features, and if they are needed in the application. Then enable features' reading for
more in-depth application evaluation.
Prior to using the bq78350, the default settings should be evaluated as the device has many configuration
settings and options. These can be separated into five main areas:
• Measurement System
• Gas Gauging
• Charging
• Protection
• Peripheral Features
The key areas of focus are covered in the following sections.

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10.2.3.1 Measurement System

10.2.3.1.1 Cell Voltages


The bq78350 is required to be configured in the AFE Cell Map register to determine which cells to measure
based on the physical connections to the bq76920 AFE. The cell voltage data is available through
CellVoltage1()…CellVoltage5(). The cell voltages are reported as they are physically stacked. For example, if the
device is configured for 3-series cells connected to VC1, VC2, and VC5 per the AFE Cell Map, then the cell
voltages are still reported via CellVoltage1(), CellVoltage2(), and CellVoltage3(), respectively.
For improved accuracy, offset calibration is available for each of these values and can be managed through the
bqSTUDIO tool. The procedure for calibration is described in the bq78350 Technical Reference Manual
(SLUUAN7) in the "Calibration" chapter.

10.2.3.1.2 External Average Cell Voltage


This is enabled by default (DA Configuration [ExtAveEN] = 1) and uses the external resistor divider connected
to the VEN and BAT pins to determine the average cell voltage of the battery pack. The average cell voltage is
available through ExtAveCellVoltage().

CAUTION
Care should be taken in the selection of the resistor and FETs used in this divider
circuit as the tolerance and temperature drift of these components can cause
increased measurement error and a gas gauging error if CEDV Gauging Config
[ExtAveCell] = 1 (default = 1).

For improved accuracy, offset and Gain calibration is available for this value and can be managed through the
bqSTUDIO tool. The procedure for calibration is described in the bq78350 Technical Reference Manual
(SLUUAN7) in the "Calibration" chapter.

10.2.3.1.3 Current
Current data is taken from the bq76920 and made available through Current(). The selection of the current sense
resistor connected to SRP and SRN of the bq76920 is very important and there are several factors involved.
The aim of the sense resistor selection is to use the widest ADC input voltage range possible.
To maximize accuracy, the sense resistor value should be calculated based on the following formula:
RSNS(min) = V(SRP) – V(SRN) / I(max) (1)
Where: |V(SRP) – V(SRN)| = 200 mV
I(max) = Maximum magnitude of charge of discharge current (transient or DC)

NOTE
RSNS(min) should include tolerance, temperature drift over the application temperature,
and PCB layout tolerances when selecting the actual nominal resistor value.
When selecting the RSNS value, be aware that when selecting a small value, for example,
1 mΩ, then the resolution of the current measurement will be > 1 mA. In the example of
RSNS = 1 mΩ, the current LSB will be 8.44 mA.

For improved accuracy, offset and gain calibration are available for this value and can be managed through the
bqSTUDIO tool. The procedure for calibration is described in the bq78350 Technical Reference Manual
(SLUUAN7) in the "Calibration" chapter.

10.2.3.1.4 Temperature
By default, the 78350 uses an external negative temperature coefficient (NTC) thermistor connected to the
bq76920 as the source for the Temperature() data. The measurement uses a polynomial expression to transform
the bq76920 ADC measurement into 0.1°C resolution temperature measurement. The default polynomial
coefficients are calculated using the Semitec 103AT, although other resistances and manufacturers can be used.

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To calculate the External Temp Model coefficients, use the bq78350 Family Thermistor Coefficient Calculator
shown in the application note, Using the bq78350 (SLUA726).
For improved accuracy, offset calibration is available for this value and can be managed through the bqSTUDIO
tool. The procedure for calibration is described in the bq78350 Technical Reference Manual (SLUUAN7) in the
"Calibration" chapter.

10.2.3.2 Gas Gauging


The default battery chemistry (Chem ID) is 1210, which is a Li-CoO2 type chemistry. Other secondary Li-Ion
based Chem IDs can be obtained from MathCAD Chemistry Selection Tool (SLUC138).
The default maximum capacity of the battery is 4400 mAh and this should be changed based on the cell and
battery configuration chosen.
QMAX = Design Capacity of the Cell × # of parallel cells
Where: Design Capacity of the Cell can be taken from the manufacturer data sheet.
The CEDV gas gauging algorithm requires seven coefficients to enable accurate gas gauging. The default values
are generic for Li-CoO2 chemistry, but for accurate gas gauging these coefficients should be re-calculated. The
procedure to gather the required data and generate the coefficients can be found at
http://www.ti.com/tool/GAUGEPARCAL.

10.2.3.3 Charging
The charging algorithm in the bq78350 is configured to support Constant Voltage/Constant Current (CC/CV)
charging of a nominal 18-V, 4400-mAh battery.

10.2.3.3.1 Fast Charging Voltage


The charging voltage is configured (Fast Charging: Voltage) based on an individual cell basis (for example, 4200
mV), but the ChargingVoltage() is reported as the required battery voltage (for example, 4200 mV × 5 =
21000 mV).

10.2.3.3.2 Fast Charging Current


The fast charging current is configured to 2000 mA (Fast Charging: Current) by default, which is conservative for
the majority of 4400-mAh battery applications. This should be configured based on the battery configuration, cell
manufacturer's data sheet, and system power design requirements.

10.2.3.3.3 Other Charging Modes


The bq78350 is configured to limit, through external components, and report either low or 0 ChargingVoltage()
and ChargingCurrent(), based on temperature, voltage, and fault status information.
The "Charge Algorithm" section of the bq78350 Technical Reference Manual (SLUUAN7) details these features
and settings.

10.2.3.4 Protection
The safety features and settings of the bq78350 are configured conservatively and are suitable for bench
evaluation. However, in many cases, users will need to change these values to meet system requirements.
These values should not be changed to exceed the safe operating limits provided by the cell manufacturer and
any industry standard.
For details on the safety features and settings, see the "Protections" and "Permanent Fail" sections of the
bq78350 Technical Reference Manual (SLUUAN7).

10.2.3.5 Peripheral Features

10.2.3.5.1 LED Display


The bq78350 is configured by default to display up to five LEDs in a bar graph configuration based on the value
of RemainingStateOfCharge() (RSOC). Each LED represents 20% of RSOC and is illuminated when the
bq78350 DISP pin transitions low, and remains on for a programmable period of time.

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In addition to many other options, the number of LEDs used and the percentage at which they can be illuminated
are configurable.

10.2.3.5.2 SMBus Address


Although the SMBus slave address is a configurable value in the bq78350, this feature is disabled by default and
the slave address is 0x16. The SMBus Address feature can allow up to nine different addresses based on
external resistor value variation per address.
The default setup of the bq78350 is generic, but there are many additional features that can be enabled and
configured to support a variety of system requirements. These are detailed in the bq78350 Technical Reference
Manual (SLUUAN7).

10.2.4 Application Performance Plots


When the bq78350 is powered up, there are several signals that are enabled at the same time. Figure 10 shows
the rise time of each of the applicable signals.

Figure 10. VCC, MRST, VEN, and PWRM Upon Power Up

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The bq78350 takes a short period of time to boot up before the device can begin updating battery parameter
data that can be then reported via the SMBus or the optional display. Normal operation after boot-up is indicated
by the VEN pin pulsing to enable voltage data measurements for the ExtAveCell( ) function. Figure 11 shows the
timing of these signals.

Figure 11. Valid VCC to Full FW Operation

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Figure 12, Figure 13, Figure 14, and Figure 15 show Measurement System Performance Data of the
bq78350 + the bq76920 EVM. This data was taken using a standard bq76920 EVM with power supplies
providing the voltage and current reference inputs.

10 10
At 4200mV At 2000mA
8 8
6 6
Voltage Error (mV)

Current Error (mA)


4
2 2
0 0
±2 ±2
±4 ±4
±6 ±6
±8 ±8
±10 ±10
±40 ±20 0 20 40 60 80 100 ±20 0 20 40 60 80
Forced Temperature (ƒC) C006 Forced Temperature (ƒC) C008

Figure 12. Cell Voltage Error Reported Through Figure 13. Battery Charge Current Error Reported Through
CellVoltage1…5() Current()

10 6
At ±2000mA
8 4
6 2
Temperature Error (ƒC)
Current Error (mA)

4 0
2 ±2
0 ±4
±2 ±6
±4 ±8
±6 ±10
±8 ±12
±10 ±14
±20 0 20 40 60 80 ±20 0 20 40 60 80
Forced Temperature (ƒC) C009 Forced Temperature (ƒC) C007

Figure 14. Battery Discharge Current Error Reported Figure 15. Battery Temperature (External) Error Reported
Through Current() Through Temperature()

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11 Power Supply Recommendations


The bq78350 is powered directly from the 2.5-V REGOUT pin of the bq769x0 companion AFE. An input
capacitor of 0.1 µF is required between VCC and VSS and should be placed as close to the bq78350 as
possible.
To ensure correct power up of the bq78350, a 100-k resistor between MRST and VCC is also required. See the
schematic for further details.

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12 Layout

12.1 Layout Guidelines


12.1.1 Power Supply Decoupling Capacitor
Power supply decoupling from VCC to ground is important for optimal operation of the bq78350. To keep the
loop area small, place this capacitor next to the IC and use the shortest possible traces. A large-loop area
renders the capacitor useless and forms a small-loop antenna for noise pickup.
Ideally, the traces on each side of the capacitor must be the same length and run in the same direction to avoid
differential noise during ESD. If possible, place a via near the VSS pin to a ground plane layer.
Placement of the RBI capacitor is not as critical. It can be placed further away from the IC.

12.1.2 MRST Connection


The MRST pin controls the gas gauge reset state. The connections to this pin must be as short as possible in
order to avoid any incoming noise. Direct connection to VCC is possible if the reset functionality is not desired or
necessary.
If unwanted resets are found, one or more of the following solutions may be effective:
• Add a 0.1-μF capacitor between MRST and ground.
• Provide a 1-kΩ pull up resistor to VCC at MRST.
• Surround the entire circuit with a ground pattern.
If a test point is added at MRST, it must be provided with a 10-kΩ series resistor.

12.1.3 Communication Line Protection Components


The 5.6-V Zener diodes, which protect the bq78350 communication pins from ESD, must be located as close as
possible to the pack connector. The grounded end of these Zener diodes must be returned to the PACK(–) node,
rather than to the low-current digital ground system. This way, ESD is diverted away from the sensitive
electronics as much as possible.

12.1.4 ESD Spark Gap


Protect the SMBus clock, data, and other communication lines from ESD with a spark gap at the connector. The
following pattern is recommended, with 0.2-mm spacing between the points.

Figure 16. Recommended Spark-Gap Pattern Helps Protect Communication Lines From ESD
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12.2 Layout Example

C21 C22

bq78350
VCC
RBI

Figure 17. bq78350 Layout

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13 Device and Documentation Support

13.1 Related Documentation


For related documentation, see the following:
• bq78350 Technical Reference Manual (SLUUAN7)
• Using the bq78350 Application Note (SLUA726)
• bq769x0 3-Series to 15-Series Cell Battery Monitor Family for Li-Ion and Phosphate Applications Data
Manual (SLUSBK2)

13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM
Not Recommended for New Designs

www.ti.com 4-Nov-2015

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

BQ78350DBT NRND TSSOP DBT 30 60 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ78350
& no Sb/Br)
BQ78350DBTR NRND TSSOP DBT 30 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ78350
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
PACKAGE OPTION ADDENDUM
Not Recommended for New Designs

www.ti.com 4-Nov-2015

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE MATERIALS INFORMATION
Not Recommended for New Designs

www.ti.com 11-Sep-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ78350DBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
Not Recommended for New Designs

www.ti.com 11-Sep-2014

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ78350DBTR TSSOP DBT 30 2000 367.0 367.0 38.0

Pack Materials-Page 2
Not Recommended for New Designs
PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BQ78350DBT NRND TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ78350
BQ78350DBTR NRND TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ78350

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ78350DBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ78350DBTR TSSOP DBT 30 2000 367.0 367.0 38.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
BQ78350DBT DBT TSSOP 30 60 530 10.2 3600 3.5

Pack Materials-Page 3
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