Learning Objectives

1. Learning to simulate digital logic circuits using LTSpice simulation tool

2. Familiarization with working of basic logic gates.
3. Simulation of Boolean function using LTSpice and implementation of the same using
Digital IC Trainer Kit.
Components required for implementation
7400 – Quad 2-input NAND 7402 – Quad 2-input NOR
7404 – Hex Inverter 7408 – Quad 2-input AND
7432 – Quad 2-input OR 7486 – Quad 2-input XOR

I. Installation of LTSPice and Simulation of basic logic gates using LTSpice

Installation details for installing in your laptop or PC:

1. Download file “LT_SPICE_Installation_Files.zip” from

https://drive.google.com/drive/u/0/folders/1DKxUX-n-
oXwcKMHzrdc0XaBCEvDy0pF0
2. Unzip the file. It contains the following files/folder
(a) ltspiceiv.exe
(b) 74hct.lib
(c) Sym (Folder)
(d) Example1.asc
3. Run the ltspiceiv.exe file to install LTSPICE on to your PC/laptop.

Installing 74XX SPICE Model in LT SPICE:

1. Open LTSpice from desktop and open a New Schematic from File tab.
2. Click on the Component tab (looks like a AND gate) on the new schematic
window
3. Note the path of the LT SPICE lib file
4. Copy paste 74ct.lib file in the folder C:\Program Files\LTC\LTspiceIV\lib\sub
5. Copy paste all the files contained in the downloaded folder
“Sym” into C:\Program Files\LTC\LTspiceIV\lib\sym
6. Click on the SPICE Directive tab as shown below:-

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 7. Select spice directive and type .include 74hct.lib
8. Place the SPICE directive on the schematic

Simulation of basic logic gates

9. Select the component tab and you will be able to see the 74XX series gates.
10. Ex. IC number: 74HCT08 for AND gate, 74HCT32 for OR gate ,….
11. Label i/p and o/p terminals of the gate.
12. Applying inputs to the input terminals:
From components tab select voltage and then by right-clicking and selecting
‘Advanced’ in which select PULSE. Set the 2-input voltages

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 For first input
T on =1µ, T period= 2µ → ok

For second input

T on =2µ, T period= 4µ → ok

And connect them to the input terminals of the logic gate

Note: Different combinations of inputs can be applied to the gate

13. To simulate:
14. right click → edit simulation → transient→ Stop time: 4µs → Run
15. Verify the truth table of the gate from the output
16. Try Similar runs for NOT, NAND, NOR and XOR Gates on LTSpice and verify
corresponding Truth Tables.

II. LTSpice Simulation of Boolean function and verification using Digital IC trainer kit

Boolean function of the 3-input majority circuit

Run #01: Simulation and implementation of 3-input majority circuit using AND – OR gates

The first circuit we will be investigating is a majority circuit. A majority circuit is a circuit whose
output is a 1 when a majority of input variables are 1’s and 0 otherwise. An incomplete truth table
of a 3-input majority circuit is given below. Complete the truth table.

Table 2.1: Truth table of majority circuit

A B C F
0 0 0 0
0 0 1
0 1 0
0 1 1 1
1 0 0
1 0 1 1
1 1 0
1 1 1

From the truth table write the output F in canonical SOP form & POS form
F (SOP form) =
F (POS form) =

Q1: How many AND gates and OR gates would be required to implement the canonical
SOP form of F? How many inputs should each of these gates have?

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From the above we can infer that implementing the canonical form of F as it is would require more
hardware resources, A better alternative would be to implement a simpler form of F. Using
Boolean algebra obtain a simplified expression for F and write it down.

Simplified expression for F:

Draw the circuit diagram of the simplified SOP form of F using 2 input AND gates and 2 input
OR gates. (Use the minimum number of gates)

CIRCUIT - 1

For the above circuit diagram fill in the following details :

No. of AND gates used : No. of OR gates used :

No. of 7408 (IC) used : No. of 7432 (IC) used :
Total number of ICs used :

Draw the circuit diagram to realize F using minimum number of 2 input AND and 2 input OR
gates.
CIRCUIT – 2

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Simulation of the simplified expression using LTSpice:

1. Select the component tab and you will be able to see the 74XX series gates.
2. Simulate the logic circuit of the simplified Boolean expression.
3. Connect appropriate inputs to the logic circuit and label the output.
4. Run the simulation and verify the truth table of the majority circuit

Table 2.2 Simulation results of 3-input majority circuit

A B C F

Now wire up the above circuit using the required number of ICs in the Digital IC trainer kit. (the
pin out of the ICs is given in Appendix A). Feed inputs using toggle switches and observe the
output on LEDs. Tabulate your observations for any four input combinations below.

Remember : Test the ICs on the IC tester before use.

Table 2.3: Experimental results of 3-input majority circuit

A B C F

Run #02: Simulation and implementation using NAND -NAND gates

The same function can be implemented using NAND gates alone. Draw the circuit diagram using
NAND gates below and fill in the following details.

CIRCUIT- 2 (Only NAND gates)

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No. of NAND gates used :
Total number of ICs used :

What are the advantages and disadvantages of the two implementations? Record your
comments below.
1)
2)
3)

Verify the circuit using LTSpice and Digital IC trainer kit

Table 2.4: Simulation and experimental results 3-input majority circuit using only NAND
gates

A B C F (Simulation) F (Digital IC
trainer kit)

Try Yourself: Verilog assignments

Exercise #01: Write the Verilog code of the NAND – NAND implementation of the majority
circuit. Simulate the circuit with the same inputs as in the experiment and verify that the circuits
are equivalent.

Exercise #02: Write the Verilog description of a 3 input XOR gate without using the XOR
primitive

III. Test yourself

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 1. Can a NOT gate be implemented using a) NAND gates only b) NOR gates only c)
XOR gates only? If so, how?
2. Name the universal gates. Why are they called ‘universal’?
3. How many 7400 ICs will be required to implement a) 2-input XOR gate b) input
XNOR gate? Draw diagrams to justify.
4. Why multiple variable XOR operation is called odd function? Write the canonical
SOP form of four variable odd function. Which operation would give rise to even
function?
5. Prove that any function can be implemented using only XOR and AND gates.
6. Write one advantage and one disadvantage of gray code over binary code.
7. Where is parity generation and checking useful?
8. The Verilog description of a circuit is given below. Draw the equivalent circuit and
identify its functionality.
module circuit(f,a,b,c);
input a,b,c;
output f;
wire ab,bc,ca;
or or1(ab,a,b),
or2(ac,a,c),
or3(bc,b,c);
and(f,ab,bc,ca);
endmodule

STEPS FOR IMPLEMENTING THE VERILOG CODE

1. Click on ISE Design 14.1 in desktop

2. Select the Simulation option when you are implementing the Verilog code and Testing
3. Go to File and click on New Project
4. Give a name to your project → Next
5. Select the Family: Spartan3, Device: XC3550 and Package: PQ208, speed : -4 → next → Finish
6. Right Click on the project you have created and then click on New Source → Select VERILOG
MODULE → Give a file name → Next
7. Specify INPUTS and OUPUTS for your design → Next
8. Summary of the given inputs and outputs is shown → FINISH.
9. A module will appear with the given inputs and outputs.

Write Verilog code for gate-level design of Majority Function using logic gates. In this design you require
three 2-input AND gates and two 2-input OR gates.

Partial Verilog Code for Majority Function: major_func.v

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 module major_func (
Input A,
Input B,
Input C,
Output F
);
Wire w1, w2, w3, w4;
and g1(w1, A, B); // AND gate instance for g1
// with A & B are as inputs and w1 as output.
// similarly write the AND gate instances
// for g2 & g4
//w1 & w2 are now inputs to OR gate g3.
or g3(w3, w1, w2);
// similarly write the OR gate instance for g5.
endmodule

STEPS FOR TESTING THE VERILOG CODE

1. For testing make sure the view is selected as Simulation.

2. Check the syntax of the Verilog code by double clicking on Behavioral Check syntax in the
Process window (Under ISim Simulator).
3. After the syntax is checked simulate your Verilog code by double clicking on Simulate
Behavioral Model. (Under ISim Simulator)
4. A simulation window will open.
5. Here you have to give different patterns to inputs by right-clicking on the input select “Force
Constant”.
6. Specify the value of the input. Then Click on Ok.

7. Repeat this for all inputs and then click to run the simulation for specified amount of time.
8. You can test your design by 8 input combinations below. Also follow these steps

9.

STEPS FOR IMPLEMENTING THE VERILOG CODE ONTO FPGA

1. For FPGA implementation, make sure the view is selected as Implementation

2. Write the code
3. Click on Synthesize-XST and wait for some time for the process to be completed.
4. Right-click on FLOORPLAN/AREA → RUN

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5. When the ‘Welcome to PlanAhead’ dialog pops up, click on “Close” to continue…
6. Click on plus sign to view all of the “Scalar Ports” i.e. input and output ports.

Here, pins P29, P35, P37 and P26

correspond to the inputs a, b, c
7.
For each port double-click on it. and the output f respectively.

Go to the end of the document to

refer to the table which shows pin
numbers corresponding to their
respective switches and output
LEDS on the kit.
8.
Then fill in the details for the “I/O Port properties” box as shown.

9. Fill in the site field and check the “Fixed” Checkbox.

10. Save and Close plan ahead.
11. Then Click on “Configure Target Device” → OK
12. After clicking “OK” on the dialog box, this window gets open.
13. Double Click on “Boundary Scan” as shown below.
14. Right Click near the hyperlink text.
15. Under the menu Left click on “Initialize chain”.
16. When the dialog box opens, locate your Project Directory
17. Click on bypass.
18. After bypassing, \
19.
20. in your project directory there will be a file with.bit extension will be generated. Select it and
then on click on Open to continue.
21.

22. Click on “Device2 ( FPGA xc3s50)”And then select “FPGA Device Specific Programming
Properties” → Click on OK to continue.
23. Click on “Program” and wait till it runs→ After running, “Program Succeeded” will appear.
24. Now the program is dumped into the FPGA kit successfully. Apply inputs and check the outputs
on FPGA Kit.