MATLAB

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 Familiarisation of MATLAB
AIM:-
To study about MATLAB and SIMULINK
OBJECTIVES:-
Upon completion of this experiment the students will be able to
1. To know various windows in MATLAB
2. To understand creation of vector and matrix
3. To use various utility matrices
THEORY:-
MATLAB is a software package for high-performance numerical computation and
visualization. It provides an interactive environment with hundreds of built-in functions for
technical computation, graphics, and animation. Best of all, it also provides easy extensibility
with its own high-level programming language. The name MATLAB stands for MATrix
LABoratory.
MATLAB's built-in functions provide excellent tools for linear algebra computations,
data analysis, signal processing, optimization, numerical solution of ordinary differential
equations (ODEs), quadrature, and many other types of scientific computations. Most of
these functions use state-of-the-art algorithms. There are numerous functions for 2 – D and
3– D graphics, as well as for animation.
The basic building block o f MATLAB is the matrix. The fundamental data type is the
array. Vectors, scalars, real matrices, and complex matrices are all automatically handled as
special cases of the basic data type.
MATLAB windows
Command window:
This is the main window. It is characterized by the MATLAB command prompt (>>).
When you launch the application program, MATLAB puts you in this window. All
commands, including those for running user-written programs, are typed m this window at
the MATLAB prompt.
Current Directory pane:
This pane is located on the left o f the Command Window in the default MATLAB
desktop layout. This is where all the files from the current directory are listed.
Workspace pane:
This sub-window lists all variables that programmers have generated so far and shows
their type and size.
Command History pane:
All commands typed on the MATLAB prompt in the command window get recorded,
even across multiple sessions in this window.
Figure window:
The output of all graphics commands typed in the command window are flushed to the
graphics or figure window, a separate gray window with (default) white background color.
The user can create as many figure windows as the system memory will allow.

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Editor window:
This is where programmers write, edit, create, and save programs in files called M-
files. The Programmers can use any text editor to carry out these tasks. On most systems,
MATLAB provides its own built-in editor.

Some basic functions

Function Description Syntax
Whos lists variables currently in the workspace with their size whos
Help lists topics on which help is available help topic
Clear clears the workspace, all variables are removed clear all
clear x,y,z
Clc clears command window Clc
Demo runs the demo program demo
lookfor lists help topics containing the word typed after that lookfor word
Working with Matrices
Arrays are the backbone of MATLAB computation. A matrix is entered row-wise, with
consecutive elements of a row separated by a space or a comma, and the rows separated by
semicolons or carriage returns. The entire matrix must be enclosed within square brackets.
Elements of the matrix may be real numbers , complex numbers or characters.

A= [ 1 2 3; 4 5 6] 
A vector is a special case of a matrix, with just one row or one column. It is entered the same
way as a matrix.
Examples:
u = [1 3 9] produces a row vector, and
v = [1 ; 3 ; 9] produces a column vector.

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• A scalar does not need brackets.
Example:
g = 9.81 ;
• Square brackets with no elements between them create a null matrix.
Example:
X=[]
Indexing (or subscripting)
Once a matrix exists, its elements are accessed by specifying their row and column
indices. Thus, A ( i , j ) in MATLAB refers to the element aij of matrix A, i.e. , the element in
the ith row and jth column.
The statement A (m : n , k : l ) specifies rows m to n and columns k to l of matrix A.
When the rows (or columns) to be specified range over all rows (or columns) of the matrix, a
colon can be used as the row (or column) index.
Thus, A ( : , 5 : 20 ) refers to the elements in columns 5 through 20 of all the rows of
matrix A. This feature makes matrix manipulation much easier and provides a way to take
advantage of the "vectorized" nature of calculations in MATLAB .
The dimensions of an existing matrix A may be obtained with the command size (A)
or more explicitly with [m , n] = size ( A ) , which assigns the number of rows and columns
of A to the variables m and n, respectively.
Transpose
The transpose of matrix A is obtained by typing A' , i . e . , the name of the matrix
followed by the single right quote. For a real matrix A, the command B = A' produces B = AT,
that is, bij = aji, and for a complex matrix A, B = A ' produces the conjugate Transpose;
that is, bij = conjugate of(aji).
Appending a row or column
A row can be easily appended to an existing matrix, provided the row has the same
length as the length of the rows of the existing matrix. The same thing goes for columns. The
command A= [A ; u] appends a row vector u to the rows of A,
While A= [A v] appends a column vector v to the columns of A.
A row or column of any size may b e appended to a null matrix.
Utility matrices
eye (m , n) returns an m by n matrix with ones on the main diagonal,
zeros (m , n) returns an m by n matrix of zeros,
one s (m , n) returns an m by n matrix of ones,
rand (m , n) returns an m by n matrix of random numbers,
randn (m , n ) returns an m by n matrix of normally distributed numbers ,
diag ( v ) generates a diagonal matrix with vector v on the diagonal,
diag (A) extracts the diagonal of matrix A as a vector, and
The first four commands with a single argument , e.g. , ones (m) , produce square
matrices of dimension m. For example, eye (3) produces a 3 x 3 identity matrix. See the
illustration shown

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Creating vectors
Very often we need to create a vector of numbers over a given range with a specified
increment. The general command to do this in MATLAB is
v = Initial Value : Increment : Final Value
If no increment is specified, MATLAB uses the default increment of 1
a = 0 : 10 : 100 produces a = [ 0 10 20 30 ……….. 100 ] ,
b = 0 : pi/50 : 2 *pi produces b =[ 0 , i .e. , a linearly spaced vector
from 0 to 2 spaced at
u = 2 : 10 produces u = [ 2 3 ... 10 ].
linspace (a , b , n) generates a linearly spaced vector of length n from a to b.
Example:
u = linspace ( 0 , 20 , 3) generates u= [0 10 20] .
Thus , u=linspace ( a , b , n) is the same as u=a : ( b-a) / (n-1 ) : b .
logspace (a, b , n) generates a logarithmically spaced vector of length n from 10 ^a to
10^b .
Example:
v=logspace ( 0 , 3 , 4 ) generates v = [ 1 10 100 1000] .
Elementary math functions
sin, sind sine,
asin , asind inverse sine,
cos , cosd cosine,
acos , acosd inverse cosine ,
tan , tand tangent ,
Sinh hyperbolic sine,
Asinh inverse hyperbolic sine,
Cosh hyperbolic cosine,
Acosh inverse hyperbolic cosine ,
Tanh hyperbolic tangent ,.
Exp exponential,
Example: exp (A) produces a matrix with elements eAij ) .
Log natural logarithm,
Example: log (A) produces a matrix with elements ln( Aij).
log10 base 10 logarithm,
Example: log 1 0 (A) produces a matrix with elements log10
(Aij )
Sqrt square root ,
Example: sqrt ( A ) produces a matrix with elements
Nthroot Example: nthroot ( A , 3 ) produces a matrix with elements

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SIMULINK
Simulink is a software package that enables you to model , simulate and analyze
systems whose outputs change over time. Such systems are often referred to as dynamic
systems. Simulink can be used to explore the behavior of a wide range of real world dynamic
systems including electrical circuits, shock absorbers, banking systems and many other
electrical, mechanical thermodynamic systems.

Simulating a dynamic system is a two step process with simulink. First a user create a
block diagram, using the simulink model editor that graphically depicts time dependent
mathematical relationships among the system inputs, states and output. The user then
commands simulink to simulate the system represented by the model from a specified start
time to a specified stop time.

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HDL

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 FAMILIARISATION OF XILINX ISE
AIM :-
To familiarize the Xilinx ISE software and Spartan 3 development board.
OBJECTIVES:-
Upon completion of this experiment the students will be able to
1. To create a new project and develop a verilog HDL program
2. To create a test bench waveform for simulation
3. To do behavioral simulation
4. To do synthesis on Spartan 3 Evaluation/ Development kit
TOOLS/ EQUIPMENT REQUIRED:-

Sl. No. Name / Specification Quantity

Windows based Desktop computer with USB/ COM 1
port loaded with Xilinx ISE
Spartan 3 Evaluation board with USB / Serial 1
communication cable

THEORY
VLSI design (very large scale integration ) means more than hundred gates in a single IC
chip.VLSI design concept can be classified into two.
1 VHDL (very high speed Hardware Description Language)
2 Verilog HDL
In general, HDL means hardware description Language. HDL concept is used to design
digital circuits easily and efficiently. In HDL design, program codes have to develop for a
particular digital design. Then it is verified using simulation software. ISE-Xilinx ( version
9.1 onwards) is one of the most popular and free simulation software. The behavioral
simulation will give us input/output waveforms, RTL model, truth table and K map. It can be
installed in windows based systems. After successful verification of the program , the codes
are temporarily ported to a generalized IC structure placed in a development kit. It can be
done with computer loaded with simulation software and development kit connected through
USB or serial COM port or LPT port. ( Depending upon different kits). Then the
performance of the digital circuit can be verified from the kit.

There are mainly two types of Development boards for digital VLSI Design . FPGA
based kit and CPLD based kit. FPGA means field programmable gate array. CPLD means
Complex Programmable Logic Devices. In FPGA , the basic building blocks are MOSFETs.
In CPLD, the basic building blocks are CCD ( Charge coupled devices). It is recommended
to use FPGA kits for our purpose.
In Verilog HDL, there are four levels of abstraction

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 1. Switch level
2. Gate level
3. Data flow modeling
4. Procedural level (Behavioral modeling)
Switch level
 Lowest level of abstraction
 Modules are implemented in terms of switches, storage nodes, and interconnection
between them
 Now it is obsolete
Gate level
 It is the beginners’ level
 Modules are implemented in terms of gates and inter connection between them
Data flow
 Modules are implemented by specifying the dataflow between hardware registers
Behavioral level
 This is the highest level of abstraction
 It is similar to C programming
 Modules are implemented in terms of desired design algorithms
 Concept of hardware implementation details are not required
Xilinx ISE Overview
The Integrated Software Environment (ISE™) is the Xilinx design software suite that allows
you to take your design from design entry through Xilinx device programming. The ISE Project
Navigator manages and processes your design through the following steps in the ISE design flow.
Design Entry
Design entry is the first step in the ISE design flow. During design entry, you create your
source files based on your design objectives. You can create your top-level design file using a
Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or using a schematic.
You can use multiple formats for the lower-level source files in your design.
Synthesis
After design entry and optional simulation, you run synthesis. During this step, VHDL,
Verilog, or mixed language designs become netlist files that are accepted as input to the
implementation step.
Implementation
After synthesis, you run design implementation, which converts the logical design into a
physical file format that can be downloaded to the selected target device. From Project Navigator, you
can run the implementation process in one step, or you can run each of the implementation processes
separately. Implementation processes vary depending on whether you are targeting a Field
Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).
Verification
You can verify the functionality of your design at several points in the design flow. You can
use simulator software to verify the functionality and timing of your design or a portion of your
design. The simulator interprets VHDL or Verilog code into circuit functionality and displays logical
results of the described HDL to determine correct circuit operation. Simulation allows you to create
and verify complex functions in a relatively small amount of time. You can also run in-circuit
verification after programming your device.

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Device Configuration
After generating a programming file, you configure your device. During configuration, you
generate configuration files and download the programming files from a host computer to a Xilinx
device.
PROCEDURE
I. Create a New Project
Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit
demo board.
To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type Prject name(eg:-tutorial) in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial
subdirectory is created automatically. It is a good practice to create a folder for all
our projects
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. Fill in the properties in the table as shown below:
♦ Product Category: All
♦ Family: Spartan3
♦ Device: XC3S200
♦ Package: FT256
♦ Speed Grade: -4
♦ Top-Level Source Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Preferred Language: Verilog (or VHDL)
♦ Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
7. Click Next to proceed to the Create New Source window in the New Project Wizard. At
the end of the next section, your new project will be complete.

II. Create an HDL Source

Creating a Verilog Source
Create the top-level Verilog source file for the project as follows:
1. Click New Source in the New Project dialog box.
2. Select Verilog Module as the source type in the New Source dialog box.
3. Type in the file name counter.
4. Verify that the Add to Project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown
below:

7. Click Next, then Finish in the New Source Information dialog box to complete the new
source file template.
8. Click Next, then Next, then Finish.

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