Digital Logic Design (EEEg4302)

Chapter 6 : Sequential Logics

AASTU
Department of Electrical and
Electronics Engineering By Milkias H.

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Outline
Chapter 6 : Sequential Logics
• Introduction
• Latches
• Flip-flops
• Edge Triggered Flip-flops
• Master Slave Flip-flops
• Applications

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 Introduction

• A sequential circuit consists of a combinational circuit to which storage elements

are connected to form a feedback path.
• Most digital systems like digital watches, digital phones, digital computers, digital
traffic light controllers and so on require memory elements.
• The storage elements are devices capable of storing binary information.
• The binary information stored in these elements at any given time defines the
state of the sequential circuit at that time.
• The most important memory elements are latch and Flip-Flop, which are made up
of an assembly of logic gates.

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 Introduction
• A sequential circuit receives binary information from external inputs that, together
with the present state of the storage elements, determine the binary value of the
outputs.
• These external inputs also determine the condition for changing the state in the
storage elements.
• The block diagram demonstrates that the outputs in a sequential circuit are a
function not only of the inputs but also of the present state of the storage
elements.

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 Introduction

• There are two types of sequential circuits:

• Synchronous sequential circuit: circuit output changes only at some discrete
instants of time. This type of circuits achieves synchronization by using a timing
signal called the clock.
• Asynchronous sequential circuit: circuit output can change at any time (clockless).
• The storage elements (memory) used in clocked sequential circuits are called
flip-flops.
• A flip-flop is a binary storage device capable of storing one bit of information. In a
stable state the output of a flip-flop is either 0 or 1.
• A sequential circuit may use many flip-flops to store as many bits as necessary.

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 Introduction
• The block diagram of a synchronous clocked sequential circuit is shown in figure
below.

• The outputs are formed by a combinational logic function of the inputs to the circuit
or the values stored in the flip-flops (or both).
• The value that is stored in a flip-flop when the clock pulse occurs is also determined
by the inputs to the circuit or the values presently stored in the flip-flop (or both).

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 Latches

• Is a type of temporary storage device that has two stable state.

• Latches are similar to flip-flops because they are Bistable devices that can reside in
either of two states using a feedback arrangement.
• Although latches are useful for storing binary information and for the design of
asynchronous sequential circuits, they are not practical for use as storage elements
in synchronous sequential circuits.
• The basic difference between latches and flip-slops is the way in which they are
changed from one state to the other.
• However, Latches are the building blocks of flip-flops.

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 SR - Latches

• The SR latch is a circuit with two cross-coupled NOR gates(Active HIGH) or two cross-
coupled NAND gates(Active LOW) and two inputs labeled S for set and R for reset.
• The latch has two useful states, When output Q = 1 and Q’ = 0, the latch is said to be
in the set state. When Q = 0 and Q’ = 1, it is in the reset state.
• Outputs Q and Q’ are normally the complement of each other. However, when both
inputs are equal to 1 at the same time, a condition in which both outputs are equal
to 0 (rather than be mutually complementary) occurs.
• If both inputs are then switched to 0 simultaneously, the device will enter an
unpredictable or undefined state or a metastable state. Consequently, in practical
applications, setting both inputs to 1 is forbidden.

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SR - Latches

SR latch with NOR gates(Active HIGH)

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SR latch with NAND gates(Active LOW)
 SR - Latches

Example
• If the S’ and R’ waveforms in the following figure(a) are applied to the inputs of the
latch in active-LOW input S’-R’ latch, determine the waveform that will be observed
on the Q output. Assume that Q is initially LOW.

• Solution : (b)
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 The Gated S-R Latch

• A gated latch requires an enable input, EN (G is also used to designate enable input)
• The operation of the basic SR latch can be modified by providing an additional input
signal that determines (controls) when the state of the latch can be changed by
determining whether S and R (or S‘ and R’) can affect the circuit.
• It consists of the basic SR latch and two additional NAND gates. The control input
(En) acts as an enable signal for the other two inputs.
• The outputs of the NAND gates stay at the logic-1 level as long as the enable signal
remains at 0.
• When the enable input goes to 1, information from the S or R input is allowed to
affect the latch. The set state is reached with S = 1, R = 0 and En = 1.

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 SR - Latches

Example
• Determine the Q output waveform if the inputs shown in following diagram (a) are
applied to a gated S-R latch that is initially RESET (Assume Q=0 initially).

• Solution : (b)

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 The Gated D – Latch (Transparent Latch)

• One way to eliminate the undesirable condition of the indeterminate state in the SR
latch is to ensure that inputs S and R are never equal to 1 at the same time. This is
done in the D latch.
• This latch has only two inputs: D (data) and En (enable). The D input goes directly to
the S input and its complement is applied to the R input.
• As long as the enable input is at 0, the cross-coupled SR latch has both inputs at the
1 level and the circuit cannot change state regardless of the value of D .
• The D input is sampled when En = 1. If D = 1, the Q output goes to 1 placing the
circuit in the set state. If D = 0, output Q goes to 0 placing the circuit in the reset
state.
• The D latch receives that designation from its ability to hold data in its internal
storage. It is suited for use as a temporary storage for binary information between a
unit and its environment.

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The Gated D – Latch (Transparent Latch)

D latch

Graphic symbols for latches

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 Flip-flops

• The flip-flop is a basic building block for counters, registers and other sequential
control logic and is used in certain types of memories.
• The main difference between latches and flip-flops is in the method used for
changing their state.
Latches – level triggered.
Flip-Flops – edge triggered.
• Triggering means making a circuit active. In level triggering the circuit will become
active when the gating or clock pulse is on a particular level. In edge triggering the
circuit becomes active at negative or positive edge of the clock signal.

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 Flip-flops

• Latches are “transparent” (any change on the inputs is seen at the outputs
immediately when C=1). This causes synchronization problems.(states change
randomly)
• Solution: use latches to create flip-flops that can respond (update) only on specific
times (instead of any time).
• There are two ways that a latch can be modified to form a flip-flop.
• One way is to employ two latches in a special configuration that isolates the output
of the flip-flop and prevents it from being affected while the input to the flip-flop is
changing. (Master-Slave Flip-flop)
• Another way is to produce a flip-flop that triggers only during a signal transition
(from 0 to 1 or from 1 to 0) of the synchronizing signal (clock) and is disabled during
the rest of the clock pulse.(Edge Triggered Flip-flops )

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 Edge Triggered Flip-flops

• An edge-triggered flip-flop changes state either at the Positive edge (rising edge)
or Negative edge (falling edge).

Positive edge-triggered flip-flops

Negative edge-triggered flip-flops

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Edge Triggered SR Flip-flops

• S-R flip-flop: on the triggering edge of the clock pulse,

S=HIGH (and R=LOW) a SET state(Q=1,Q’=0)
R=HIGH (and S=LOW) a RESET state(Q=0,Q’=1)
both inputs LOW a no change
both inputs HIGH a invalid
• Characteristic table of positive edge-triggered S-R flip-flop:
S R CLK Q(t+1) Comments
0 0 X Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  ? Invalid

X = irrelevant (“don’t care”)

 = clock transition LOW to HIGH
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 Edge Triggered SR Flip-flops

• It includes of 3 parts:
• A (1) basic NAND latch, (2) a pulse-steering circuit and (3) a pulse transition
detector (edge detector) circuit
• The pulse transition detector detects a rising (or falling) edge and produces a very
short-duration spike.

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 Edge Triggered D Flip-flops

• D flip-flop: single input D (data)

D=HIGH a SET state
D=LOW a RESET state
Q follows D at the clock edge.
• Convert S-R flip-flop into a D flip-flop: add an inverter.

A positive edge-triggered D flip-flop  = clock transition LOW to HIGH

formed with an S-R flip-flop.

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 Edge Triggered D Flip-flops

• Application: Parallel data transfer.

• To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and Q3 for storage.

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 Edge Triggered J-K Flip-flops

• J-K flip-flop:

J
Pulse Q
CLK transition
detector
Q'
K

• Characteristics table.
Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Q(t+1) = J.Q' + K'.Q
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 Edge Triggered T Flip-flops

• T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs
together.

• Characteristics table.

T CLK Q(t+1) Comments

0  Q(t) No change
1  Q(t)' Toggle

Q(t+1) = T.Q' + T'.Q

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 Edge Triggered T Flip-flops

• Application: Frequency division

• Application: Counter( to be covered)

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 Asynchronous Inputs

• S-R, D and J-K inputs are synchronous inputs, as data on these inputs are transferred
to the flip-flop’s output only on the triggered edge of the clock pulse.
• Asynchronous inputs affect the state of the flip-flop independent of the clock;
example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)]
When PRE=HIGH, Q is immediately set to HIGH.
When CLR=HIGH, Q is immediately cleared to LOW.
• Flip-flop in normal operation mode when both PRE and CLR are LOW(Active HIGH) .

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 Asynchronous Inputs

• A J-K flip-flop with active-LOW preset and clear inputs.

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 Master-Slave JK Flip-Flop

• Race Around Condition: In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a
long period of time, then Q output will toggle as long as CLK is high, which makes the
output of the flip-flop unstable or uncertain.
• Generally, the propagation delay of the gates is of the order of nanoseconds. So if
the clock pulse is of the order of microseconds, then the output will change
thousands of times within the clock pulse.
• This race-around condition can be avoided if Tc/4 < Tp. Due to the small propagation
delay of the ICs it may be difficult to satisfy the above condition

Tp = propagation delay of flip flop

Tc = time period of clock

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 Master-Slave JK Flip-Flop

• This problem is called race around condition in J-K flip-flop.

• This problem (Race Around Condition) can be avoided by ensuring that the clock
input is at logic “1” only for a very short time. This introduced the concept of Master
Slave JK flip flop.
• Master Slave JK flip flop – The Master-Slave Flip-Flop is basically a combination of
two JK flip-flops connected together in a series configuration. Out of these, one acts
as the “master” and the other as a “slave”.

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 Master-Slave JK Flip-Flop

• The output from the master flip flop is connected to the two inputs of the slave flip
flop whose output is fed back to inputs of the master flip flop.
• In addition to these two flip-flops, the circuit also includes an inverter.
• The inverter is connected to clock pulse in such a way that the inverted clock pulse is
given to the slave flip-flop. In other words if CP=0 for a master flip-flop, then CP=1 for
a slave flip-flop and if CP=1 for master flip flop then it becomes 0 for slave flip flop.

Timing Diagram of a Master flip flop

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 Master-Slave JK Flip-Flop

Working of a JK master slave flip flop

• When the clock pulse goes to 1 the slave is isolated; J and K inputs may affect the
state of the system. The slave flip-flop is isolated until the CP goes to 0. When the CP
goes back to 0 information is passed from the master flip-flop to the slave and
output is obtained.
• Firstly the master flip flop is positive level triggered and the slave flip flop is negative
level triggered, so the master responds before the slave.
• If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and
the clock forces the slave to reset, thus the slave copies the master.
• If J=1 and K=0, the high Q output of the master goes to the J input of the slave and
the Negative transition of the clock sets the slave, copying the master.
• If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave
toggles on the negative transition of the clock.
• If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

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Last slide

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