COMPUTER ORGANIZATION AND DESIGN 5th

Edition
The Hardware/Software Interface

Chapter 4
The Processor

Dr. Randa Mohamed

Agenda
◼ Introduction
◼ Logic design basics
◼ MIPS Datapath: R-Type & I-Type

Chapter 4 — The Processor — 2

 §4.1 Introduction
Introduction
◼ Processor design is composed of 2 modules:
Datapath and Control
◼ We will examine

1. Two MIPS implementations

◼ A simplified version (Single cycle MIPS)

◼ A more realistic pipelined version (Pipelined MIPS)

2. Implementation that supports

◼ R-type instructions, like ADD, SUB
◼ I-type instructions LW, SW
◼ Conditional branch instruction BEQ
◼ J-type branch instruction J
Chapter 4 — The Processor — 3
 §4.2 Logic Design Conventions
Logic Design Basics
◼ Information encoded in binary
◼ Low voltage = 0, High voltage = 1
◼ One wire per bit
◼ Multi-bit data encoded on multi-wire buses
◼ Combinational element
◼ Operate on data
◼ Output is a function of input
◼ State (sequential) elements
◼ Store information

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Combinational Elements

◼ AND-gate ◼ Adder A
Y
+
◼ Y=A&B ◼ Y=A+B B

A
Y
B

◼ Arithmetic/Logic Unit
◼ Multiplexer ◼ Y = F(A, B)
◼ Y = S ? I1 : I0
A
I0 M
u Y ALU Y
I1 x
B
S F

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Sequential Elements
◼ Stores data in a circuit
◼ Uses a clock signal to determine when to update
the stored value
◼ Edge-triggered: update when Clk changes from 0
to 1

Clk
D Q
D

Clk
Q

Chapter 4 — The Processor — 6

 Sequential Elements
◼ Storing with write control
◼ Only updates on clock edge when write control
input is 1
◼ Used when stored value is required later

Clk

D Q Write

Write D
Clk
Q

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 §4.3 Building a Datapath
Building a Datapath
◼ Datapath
◼ Elements that process data and addresses
in the CPU
◼ Registers, ALUs, mux’s, memories, …
◼ We will build a MIPS datapath incrementally
◼ Refining the overview design

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Datapath

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Multiplexers
◼ Can’t just join
wires together
◼ Use multiplexers

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Datapath

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Instruction Fetch

Increment by
4 for next
32-bit instruction
register

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Instruction Fetch

Increment by
4 for next
32-bit instruction
register

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Instruction Fetch

Field bit
31-26 25-21 20-16 15-11 10-6 5-0
positions
No. of bits 6 5 5 5 5 6
R-type op rs rt rd shamt funct
I-type 16- bit
op rs rt
immediate/address

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R-Format Instructions

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R-Format Instructions
◼ Read two source register operands (defined by rs,rt)
◼ Perform arithmetic/logical operation
◼ Write result in destination register (defined by rd)

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Register File

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ALU

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Load/Store Instructions

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Load/Store Instructions
◼ To read from the data memory, set Memory read =1
◼ To write into the data memory, set Memory write =1

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Load Instruction
◼ Read register operands & calculate address using 16-
bit offset What parts of R-type are altered?

Data[rs]

Offset (32)

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R-Type/Load Instruction
◼ Read register operands & calculate address using 16-
bit offset

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Store Instruction
◼ Read register operands & calculate address using 16-
bit offset
Data[rs]

Offset (32)

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R-Type/Load/Store Datapath

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Branch Instructions
◼ Read register operands
◼ Compare operands
◼ Use ALU, subtract and check Zero output
◼ Calculate target address (PC +4 +Add×4)
◼ Sign-extend displacement
◼ Shift left 2 places (word displacement)
◼ Add to PC + 4
◼ Already calculated by instruction fetch

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Branch Instructions
Just
re-routes
wires PC+4+ Add×4

Data[rs]

Data[rt]
Zero=1 Branch

Offset (32)

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Full Datapath

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Full Datapath: R-Type

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Full Datapath: I-Type (Load)

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Full Datapath: I-Type (Store)

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Full Datapath: I-Type (Beq:T)

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Full Datapath: I-Type (Beq:F)

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Instruction Execution Summary
Data path does an instruction in one clock cycle
1. Fetch: PC → instruction memory → instruction
2. Decode: Register numbers → register file → read
registers
3. Execute: Depending on instruction class
◼ Use ALU to calculate
◼ Arithmetic result

◼ Memory address for load/store

◼ Branch target address

◼ Access data memory for load/store

◼ PC  target address or PC + 4
Chapter 4 — The Processor — 34
Problems to Solve
4.1, 4.7

Chapter 4 — The Processor — 35