i An update to this article is included at the end

Int. J. Electron. Commun. (AEÜ) 66 (2012) 920–927

Contents lists available at SciVerse ScienceDirect

International Journal of Electronics and

Communications (AEÜ)
journal homepage: www.elsevier.de/aeue

0.5 V bulk-driven analog building blocks

G. Raikos ∗ , S. Vlassis, C. Psychalinos
Electronics Laboratory, Physics Department, University of Patras, GR-26504 Patras, Greece

a r t i c l e i n f o a b s t r a c t

Article history: Basic analog building blocks, such as voltage follower (VF), second generation Current Conveyor (CCII),
Received 27 September 2011 and Current Feedback Operational Amplifier (CFOA), capable for operating under 0.5 V supply voltage, are
Accepted 20 March 2012 introduced in this paper. The input stage of the proposed blocks is based on bulk-driven pMOS devices,
and simultaneously offers the advantages of almost rail-to-rail input/output voltage swing and capability
Keywords: for operation under the extremely low supply voltage. Their performances have been evaluated and
Low-voltage circuits
compared through simulation results using a standard 0.18 ␮m n-well process. The bandwidth of the
Analog filters
voltage and current followers for both CCII and CFOA is 11 MHz and 10 MHz, respectively. The power
Current conveyors
Current feedback operational amplifiers
consumption of CCII and CFOA is 30 ␮W and 50 ␮W, respectively.
Voltage followers © 2012 Elsevier GmbH. All rights reserved.
Input stages
Bulk-driven transistors

1. Introduction MOS devices operate in the conductance region only for input
common-mode level toward positive or negative supply rail. A tra-
During the last years, the increased density of integrated circuits ditional approach to increase the input common-mode range is
and the rapid growth of portable applications require reliable mod- implemented using parallel combination of pMOS and nMOS dif-
ern CMOS processes with scaled-down supply voltage and power ferential pairs [3–5]. Another gate-driven technique that improves
consumption [1]. Among the most important factors of CMOS VLSI the input common-mode range is based on dynamic level shifters
processes is the threshold voltage of the MOS devices. The lowest [6,7]. An alternative gate-driven technique employs floating gate
value of threshold voltage is mostly determined by the digital VLSI MOS devices [8,9], where a small charge stored into the floating
specifications such as operating frequency, implementation area, gate of the composite device reduces the effective threshold volt-
noise margin, and/or leakage currents. In modern nanoscale CMOS age. However, this approach faces reliability problems since the
processes, in spite of supply voltages will continuous scale down, floating gate voltage might be beyond the supply rails, featuring
the threshold voltage is not expected to decrease what is available also additional stress on the devices.
today. On the other hand, as the supply decreases the analog circuit Last years, the bulk-driven MOS approach has been involved in
designers face difficulties due to the fact that the threshold voltage the analog circuits design extending the common-mode dynamic
is not scaled down by the same amount as the supply voltage [2]. range under extremely low-voltage supplies. Many analog building
Therefore, in analog VLSI, the relatively low supply voltage limits blocks have been proposed such as operational transconductance
the effectiveness of traditional analog design techniques. amplifiers [10–16], voltage followers [17,18], voltage to current
Although the supply voltages are decreased, the input voltage converter [19] and current conveyors [20,21]. The input signal
swing, input common-mode dynamic range, and minimum allow- drives the bulk terminal of the input MOS devices while a sufficient
able supply voltage have to be as large as possible, in order to gate voltage keeps the input devices in the conductance region even
keep the signal-to-noise ratio sufficiently large. Therefore, under for rail-to-rail input common-mode range. Unfortunately, in stan-
these strict conditions, the design of basic analog building blocks, dard CMOS technologies, the bulk-transconductance is 4 or 5 times
such as operational amplifiers, requires a high efficient input stage smaller than the gate-transconductance and, therefore, the bulk-
regarding a low supply voltage. Traditional CMOS analog cells are driven circuits are expected to suffer from bad noise performance
mainly based on gate-driven differential transistor pairs, where the compared with gate-driven circuits.
input signal modulates the gate voltage of the MOS input devices. A novel low-voltage bulk-driven input stage is proposed in this
This approach is unsuitable for low supply voltages since the input work. The input stage is constructed from a traditional bulk-driven
pMOS differential pair, biased by a flipped voltage follower. The
advantage of the proposed input stage against the conventional
∗ Corresponding author. bulk-driven input stage is that it is capable for operating under
E-mail addresses: [email protected], [email protected] (G. Raikos). an extremely low supply voltage of 0.5 V, where the conventional

1434-8411/$ – see front matter © 2012 Elsevier GmbH. All rights reserved.
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 G. Raikos et al. / Int. J. Electron. Commun. (AEÜ) 66 (2012) 920–927 921

Fig. 1. Conventional topologies of (a) gate-driven and (b) bulk-driven input stages.

bulk-driven input stage is failed. Employing the proposed input gate-oxide capacitor. It should be also mentioned at this point that
stage the design of basic analog blocks, such as voltage follower, all voltages are referred to the bulk voltage.
CCII, and CFOA, has been performed. Based on Eq. (1) the input small-signal transconductance of the
The paper is organized as follows. The operation principle of the gate driven differential pair of Fig. 1(a) around the bias point, is
proposed input stage is described in Section 2, where a comparison given by the expression
with the traditional gate and bulk driven input stages has been also 
∂io  I
performed. The cells of voltage follower, CCII and CFOA which are gm.in.GDr = gm = = tail (2)
based on the proposed input stage are presented in Section 3. Ana- ∂vid  VG = VCM.in nUt
VB = const.
log filter design examples employing CCIIs and CFOAs are provided
VS = const.
in Section 4, where their performances have been evaluated and
compared using the Analog Design Environment of the Cadence where io is the small signal differential output current of the tran-
software with a standard CMOS n-well 0.18 ␮m process. sistors pair, and Itail is the tail current. Eq. (2) shows that the gate
transconductance is proportional to the tail current and indepen-
2. Proposed bulk-driven input stage dent from the input common-mode voltage, as long as the MOS
device operates in saturation region. For simplicity reasons, the
The most commonly used input stage, based on the gate- derivation of Eq. (2) is based on the fact that the differential pair is
driven differential transistor pair, is that shown in Fig. 1a. It fully symmetrical and, therefore, the common-source voltage VS
employs the differential input transistors pair Min.p , Min.n , a tail cur- of the Mp.in and Mn.in is constant (or ac ground) for differential
rent source Mtail , and the current mirror Mld.p − Mld.n which acts signals.
as active load. Transistor Mtail is biased at the voltage Vbp and, As it is shown in Eq. (1), the drain current depends on the source-
consequently, the differential pair is biased by the constant tail bulk voltage, since it modulates the drain current through the term
current Itail . The differential input signals Vp = VCM.in + (vid /2) and e−VT (VSB )/nUt . The threshold voltage is given by the expression
 
Vn = VCM.in − (vid /2) are applied between the gates of input transis-   
tors Min.p , Min.n , where vid is the differential input signal and VCM.in VT = VT 0 +  2˚F + VS − VB  − 2˚F (3)
the input common-mode voltage. A suitable VCM.in is necessary to
ensure the operation in the conductance region of the MOS input where ˚F is the body Fermi potential, and  is the body effect coeffi-
devices. cient [15,22] and [23]. According to Eqs. (1) and (3), the small-signal
Fig. 1b shows the conventional bulk-driven pMOS differential bulk-transconductance gmb around the bias point of the bulk-driven
pair. The topology is biased under the constant tail current Itail as differential pair of Fig. 1b, is given by
the gate-driven differential pair counterpart. The gate voltages are 
connected to ground and therefore the produced gate-to-source ∂io  I 
gm.in.BDr = gmb = = tail   
∂vid  VG = const nUt
2 2˚F + VS − VCM.in 
voltage keeps the input devices into the conductance region. The
differential input signal is applied between the bulk terminals of VB = VCM.in
the input transistors Min.p and Min.n . VS = const.
A simple model for the drain current IDS of a nMOS transistor in (4)
weak inversion region and in saturation is given by the following
equation [22] √
The factor ␥/2 (2F + |VS − VCM.in |) in Eq. (4) depends on the fab-
W rication process and it falls in the range 0.2–0.4. Thus, the bulk
IDS = IDo e(VGS −VT (VSB ))/nUt (1) transconductance is expected to be smaller than the gate-driven
L
transconductance. Also, gmb is function of the source-bulk voltage
where IDo = 2 COX (nUt )2 is the zero-bias current, Ut = kT/q is the VS − VCM.in and thus it depends on the input common mode voltage.
thermal voltage, VT is the threshold voltage which it depends on Fig. 2a illustrates the input-transconductance of the gate-
the source-bulk voltage VSB , and W/L is the transistor aspect ratio. driven input stage of Fig. 1a against the input common-mode
The factor n denoted as the subthreshold slope factor and is equal voltage. In the same Figure, the common-source voltage VS.GDr
to 1 + CD /Cox where CD is the depletion capacitance and Cox the of the input transistors is also plotted. According to Fig. 2a, the
922 G. Raikos et al. / Int. J. Electron. Commun. (AEÜ) 66 (2012) 920–927

Fig. 2. (a) Input-transconductance gm.in.GDr , common-source voltage VS.GDr and gate voltages VG.Min.p,n of the gate-driven diff. pair of Fig. 1(a) and (b). Input-transconductance
gm.in.BDr , common-source voltage VS.BDr and bulk voltages VB.Min.p,n of the bulk-driven diff. pair. Both transconductances are plotted against the input common-mode voltage
VCM.in .

gate-transconductance remains constant and equal to its maximum where VDD is the positive supply voltage of the circuit. Thus, the
value gm.o as VCM.in is toward ground (or negative supply); this is bulk-driven input stage is more efficient regarding the common-
originated from the fact that the tail current is constant. In this case, mode dynamic range, whistle gmb is smaller than gm . It should
the input devices Min.p.n and the tail transistors Mtail are biased deep be mentioned that the above considerations are valid only in the
in saturation region and, thus, the tail current is constant producing case that the parasitic bipolar transistors npn and pnp, which are
also a constant gm . As VCM.in increases, then gm decreases and near inherent in pMOS devices, are not triggered.
to positive supply voltage it collapses to zero. For common-mode Let us compare the gate- and bulk-driven input stage regarding
signals, the input transistors Min.p.n and Mtail acts as a voltage the minimum supply voltage VDD.min . As it is shown in Fig. 1a and
follower making the common-source voltage VS.GDr of Min.p(n) to b, VDD.min depends on the gate-to-source voltage VGS.ld of the load
follow the variation of VCM.in . Therefore, the variation VCM.in of transistor Mld.p . Therefore, the minimum allowable supply voltages
the input common-mode level is conveyed almost unchanged to VDD.min.GDr and VDD.min.BDr of the gate- and bulk-driven input stages,
the common-source voltage and, thus, VCM.in ≈ VS.GDr . As VCM.in respectively, are equal and given by
increases toward positive supply then the source voltage VS.GDr    
VDD. min .GDr = VDD. min .BDr = VGS.ld + VDS.sat.in  + VDS.sat.tail  (8)
increases as well, pushing the tail transistor Mtail toward linear
region. In this case, Itail decreases and gm starts to be reduced as where VDS.sat.in is the saturation drain-to-source voltage of the input
well. For VCM.in close to positive supply VDD the input devices are in transistors. Concluding, a bulk-driven input stage is more efficient
the cut-off region and, consequently, gm collapses to zero. Conclud- regarding the common-mode dynamic range compared with the
ing, the input common-mode range depends on the variation of the gate-driven counterpart but unfortunately they feature the same
common-source voltage. For constant gm , the input common-mode minimum supply voltage.
dynamic range VCM.DR.GDr of a gate driven input stage is given by Fig. 3 presents the proposed extremely low-voltage input stage.
   
VCM.DR.GDr = VDD − VGS.in (VCM.in ) − VDS.sat.tail 
The differential input signals Vp , Vn are applied again to the bulk
(5)
terminals of the input transistors Min.p and Min.n , respectively, as
where VSG.in is the gate-to-source voltage of input transistors in the conventional bulk-driven input stage. The gates of the input
which is function of VCM.in and VDS.sat.tail is the drain-to-source sat- transistors are connected to ground. The current mirror Mld.p − Mld.n
uration voltage of the tail transistor Mtail . It should be mentioned acts as active load and, simultaneously, imposes the drain current of
that |VGS.in | might be higher than the threshold voltage in order the input transistors equal to Itail /2. The tail transistor Mtail with the
transistor Min.p(n) to operate in the saturation region.
The input-transconductance and the common-source voltage
VS.BDr of a bulk-driven input stage of Fig. 1b against VCM.in are plot-
ted in Fig. 2b. The bulk-transconductance never collapses to zero
although VCM.in could be varied rail-to-rail. Since, the voltage at the
gate of the input devices is zero, the common-source voltage VS.BDr
is about one |VGS | higher than ground. Due to the fact that gmb is
smaller than gm , transistors Min.p.n and Mtail could be considered as
voltage attenuators for common-mode signals. According to Fig. 1b,
the variation VS.BDr regarding VCM.in is given by
gmb
VS.BDr = VCM.in (6)
gmb + gm
where the factor gmb /(gmb + gm ) is considered equal to the attenu-
ation of common-mode signals. Since, the factor gmb /(gmb + gm ) is
smaller than unity, VS.BDr is expected to be small, although VCM.in
can be varied between the two rails. Concluding, using bulk driven
differential pair, gmb never collapses to zero mainly due to the fact
that the voltage VS.BDr never pushes the tail transistor into the linear
region and therefore the common-mode dynamic range is given by
VCM.DR.BDr = VDD (7) Fig. 3. Proposed bulk-driven input stage with improved supply efficiency.
 G. Raikos et al. / Int. J. Electron. Commun. (AEÜ) 66 (2012) 920–927 923

Table 1
Comparison between conventional gate-driven, bulk-driven and proposed input stage.

Input stages

Gate-driven, Fig. 1a Bulk-driven, Fig. 1b Proposed Bulk-driven Fig. 3

   
VCM.DR CM Dynamic Range VDD − VGS.in (VCM.in ) − VDS.sat.tail VDD VDD
VDD.min Minimum supply V + V
  + V
   
VGS.ld + VDS.sat.in + VDS.sat.tail
V +V
GS.ld DS.sat.in DS.sat.tail GS.tail DS.sat.ld

VDD : supply voltage.

Fig. 4. (a) Voltage follower using the proposed input stage, (b) its symbol and (c) testing setup scheme. The transistors aspect ratios W/L in ␮m/␮m are Mtail :M2 :500/0.5,
Min.n.p :100/0.3, Mld.n.p :100/1 and M2 :200/1.

input transistor Min.n and the active load Mld.n construct a flipped where VGS.tail is the gate-to-source voltage of Mtail . Comparing Eqs.
voltage follower [24] and it is used to enforce the tail current to (6) and (7), we can conclude that the proposed input stage is more
be equal to Itail as in the conventional bulk-driven input stage of efficient regarding the minimum supply requirement although
Fig. 2b. The flipped voltage follower modifies the gate of Mtail to both proposed and conventional input stages achieve the same
ensure equal drain currents for both input devices. common-mode dynamic range. Table 1 presents a summary of the
Comparing the proposed bulk-driven input stage with the above considerations indicating the superiority of the proposed
conventional bulk-driven one it can be easily shown that the input stage.
common-mode dynamic range is rail-to-rail. The advantage of the
proposed input stage is the capability for operation under lower
supply voltage compared with the conventional bulk-driven input 3. 0.5 V bulk-driven building blocks
stage. The most critical path, regarding the minimum supply volt-
age, is formed by the stacked transistors Mtail and Mld.n . Therefore, Fig. 4a presents the circuit configuration of a voltage follower
minimum supply voltage VDD.min.BDr.pr of the proposed input stage using the proposed input stage. The circuit is actually a two stage
will be given by Miller amplifier since the common-source stage formed by M1
and M2 has been inserted. A negative feedback loop implemented
  between the drain of M2 and the bulk node of Min.p . Due to the
VDD. min .BDr.pr = VGS.tail  + VDS.sat.ld (9)
established feedback loop, the output voltage will be equal to the

Fig. 5. (a) CCII using the proposed input stage, (b) its associated symbol and (c) testing setup scheme. The transistors aspect ratios W/L in ␮m/␮m are Mtail :M2 :M4 :500/0.5,
Min.n.p :100/0.3, Mld.n.p :100/1 and M1 :M3 :200/1.
924 G. Raikos et al. / Int. J. Electron. Commun. (AEÜ) 66 (2012) 920–927

Table 2
Performance comparison with Sub-1 V bulk-driven CCII.

Parameters Units [21] Proposed

Process 0.18 ␮m TSMC 0.18 ␮m TSMC

VDD V ±0.4 0.5 Supply voltage
PDD ␮W 64 30 Power consumption
RY  ∞ ∞
RX  27 260
RZ k 890 113
X / Y 1 0.998 Voltage gain
iZ /iX 1 0.996 Current gain
Voff.X mV 0.4–0.5 0.35 Port X volatge offset
Ioff.Z nA – 5 Port Z current offset
DC VY range V −0.38:0.38 0.06:0.460 For X = Y ± 1 mV
DC IX range ␮A −7:7 −15:15 For iZ = iX
BW ( X / Y ) MHz 14 11
BW (iZ /iX ) MHz 13 10
Input voltage @THD = 1% – 200 mV Y.p

input voltage and, consequently, a voltage follower function is real- Having available the topologies of voltage follower in Fig. 4a and
ized. The RC network is used for the frequency stabilization of the CCII in Fig. 5a, the derivation of the corresponding CFOA structure
feedback loop. is just a one-step procedure. This is originated from the Functional
The performance of the topology in Fig. 4a has been evaluated by Block Diagram (FBD) in Fig. 8a where it is obvious that the cascade
employing MOS transistor models provided by the TSMC 0.18 ␮m connection of a CCII and a voltage follower leads to the realization
CMOS n-well process, with threshold voltages of nMOS and pMOS of a CFOA.
devices were about 0.45 V and −0.5 V, respectively. A single supply Table 3 presents the performances of the proposed CCII and
voltage VDD equal to 0.5 V was used. The follower’s performance CFOA. Both circuits feature small resistance at the node X and rela-
was optimized for an input common-mode voltage equal to 0.25 V tively high resistance at the node Z. The voltage and current tracking
(mid supply). The tail current was Itail = 20 ␮A leading to a current errors are small since they are about 0.998 and 0.5996, respectively.
consumption equal to IDD = 40 ␮A for the input stage. Although the The systematic voltage offset between ports Y and Z for the CCII
minimum channel length was 0.18 ␮m the used MOS devices was and ports Z and O of the CFOA is 0.35 mV while the current offset
designed with 0.3 ␮m channel length in order to achieve better between ports X and Z is about 5 nA. The voltage range of the port Y
drain-source conductance. The values of the passive components of of the CCII with tracking error between VY and VX less than ±1 mV
the RC frequency compensation network were R = 1 k and C = 2 pF. is about 0.4 V ranging from 0.06 V to 0.46 V. Also, the corresponding
The topology of the proposed CCII is depicted in Fig. 5a. It is current range of the port X with tracking error between IX and IX
constructed from the voltage follower of Fig. 4a in order to realize less than 40 nA is about 30uA ranging from −15 ␮A to 15 ␮A. The
the required voltage following between terminals X and Y. Also, the frequency bandwidth for the voltage gains X / Y , O / Z of CCII,
pairs of transistors M2 and M4 , and M1 and M3 have been employed CFOA, respectively is 11 MHz and the corresponding bandwidth of
in order to realize the current following between terminals X and
Z.
Fig. 6a shows the DC transfer characteristic VX /VY of the pro-
posed CCII where VX and VY are the voltages at terminal X and Y.
The voltage VX is plotted as function of VY where VY is varied rail-
to-rail. It is obvious that the voltage at the node X follows that of
the node Y, while the voltage tracking error is very small whistle
VY has near rail-to-rail variation. In spite of the rail-to-rail capabil-
ities of the input stage, the output swing are mostly depends on
the output stage of the CCII which is actually the common source
stage M1 –M2 . As VY is near to VDD or ground then transistors M2
or M1 are pushed to the triode region. In these cases, the voltage
gain of the output stage collapses and the voltage follower is not
able to operate properly any longer. Fig. 6b presents the ac response
of the voltage follower where the input frequency ranges between
1 Hz and 100 MHz. It should be mentioned here that all simulations
are performed using the analog design environment of Cadence
IC design framework with the associated TSMC 0.18 ␮m process
design kit (PDK).
In Fig. 7a the DC transfer characteristic IZ /IX is plotted where IZ
is the current flows from port Z and IX is the current flows from port
X. It should be mentioned that the output stage of CCII is actually
a class A output stage which is biased by the constant current of
20 ␮A. Therefore, the maximum allowable output current that CCII
is able to pull is 20 ␮A. Fig. 7b presents the frequency response of the
CCII where the input frequency ranges between 1 Hz and 100 MHz.
According to the authors literature survey there is only the CCII
implementation of Ref. [21] which is workable with supply voltage
less than 1-V. Table 2 presents a comparison between the above Fig. 6. (a) DC transfer characteristic VX /VY of the voltage follower and (b) the asso-
mentioned CCII and our implementation. ciated ac response.
 G. Raikos et al. / Int. J. Electron. Commun. (AEÜ) 66 (2012) 920–927 925

Table 3
Performance of the proposed CCII and CFOA.

Parameters UNITS CCII CFOA

VDD V 0.5 0.5 Single supply voltage

PDD ␮W 30 50
VCM V 0.25 0.25 Common mode voltage
RX  260 260
RY  ∞ ∞
RZ k 113 113
RO  – 250
X / Y 0.998 0.998 Voltage gain
O / Z – 0.998 Voltage gain
iZ /iX 0.996 0.996 Current gain
Voff.X mV 0.35 0.35 Port X volatge offset
Ioff.Z nA 5 5 Port Z current offset
Voff.O mV – 0.35 Port O voltage offset
Y.max V 0.06:0.460 0.06:0.460 For X = Y
iX.max ␮A −15:15 −15:15 For iZ = iX
Z.max V 0.06:0.450 0.06:0.460 For O = Z
BW ( X / Y ) MHz 11 11
BW ( O / Z ) MHz – 11
BW (iZ /iX ) MHz 10 10
THD of X 1% 1% Y.p = 200 mV, f = 10 kHz
THD of O – 1% Y.p = 200 mV, f = 10 kHz
THD of iZ 1% 1% Y.p = 200 mV, f = 10 kHz
Input referred noise (rms) ␮V 148 160
Dynamic Range dB 59.5 58.8

the current gain iZ /iX is about 10 MHz. Finally the total harmonic Employing a bias scheme VDD = 0.5 V and VCM = 0.25 the dc power
distortion is 1% for both CCI and CFOA for input amplitude equal to dissipation of the filter in Fig. 9 was 202.7 ␮W and for the filter in
0.2 V. The performances of the proposed CCII and CFOA topologies Fig. 10 was 156.6 ␮W.
will be evaluated in the next Section, through the realization of a Considering a lowpass filter function with 200 kHz cutoff fre-
lowpass filter function. quency and resistors with a value 10 kHz, the calculated values of
capacitors were C1 = C3 = 79.6 pF and C2 = 159.2 pF. The simulated
4. Bulk-driven analog filter design examples
frequency responses are given in Fig. 11, where the cutoff frequen-
cies for the filters in Figs. 9 and 10 were 199.6 kHz and 183 kHz,
Following the well-known leapfrog design technique, the
respectively.
topologies of a 3rd-order filter realized using CCIIs or CFOAs as
The linear performance of the filters has been evaluated by
active elements are depicted in Figs. 9 and 10, respectively.
applying am input signal with 10 kHz frequency and variable ampli-
tude. Employing the Periodic Steady State (PSS) offered by the
Analog Design Environment of the Cadence software, the derived
plots of Total Harmonic distortion (THD) as a function of the input

Fig. 7. (a) DC transfer characteristic IZ /IX of CCII and (b) the associated frequency Fig. 8. (a) Functional Block Diagram of a CFOA, (b) its symbol, (c) testing setup
response. scheme and (d) frequency response.
926 G. Raikos et al. / Int. J. Electron. Commun. (AEÜ) 66 (2012) 920–927

Fig. 9. 3rd-order leapfrog filter using CCIIs.

Fig. 11. Simulated frequency response of the filter (a) in Fig. 9, and (b) in Fig. 10.
signal level are given in the plots of Fig. 12. According to these plots
a THD equal to 1% (−40 dB) is achieved for an input signal level
equal to −13dbm (referred to 50 resistor) in the case of the filter It should be mentioned at this point that the employment of
in Fig. 9, and 13.4 dBm for the filter in Fig. 10. CFOAs offers more design versatility than that offered by the CCIIs in
The noise has been integrated within the passband of the filters the case of voltage-mode filters. This is originated from the fact that
and the derived values of the input referred noise for the filters in the presence of an extra output buffer allows the cascade connec-
Figs. 9 and 10 were −68.1 dBm and −69.6 dBm, respectively. Thus, tion of intermediate filter stages. This advantage does not present in
the predicted values of the Dynamic Range (DR) will be 55.1 dB and current mode filters, where CCIIs with multiple outputs are utilized
56.2 dB, respectively. required for the distribution of the intermediate output currents. In
The effects of MOS transistor parameters variations have been other words, the extra terminal of CFOA is redundant in this case.
studied through an appropriate corner analysis and the obtained
plots for both filters are given in Fig. 13.
In order to facilitate the reader, the derived performance results
are summarized in Table 4. According to this Table, the CFOA filter
offers significant advantages in terms of active and passive compo-
nent count, power dissipation, and noise performance. All the other
performance characteristics, including total capacitor area, linear-
ity and effects of MOS transistors variations are comparable in the
filters under consideration.

Fig. 10. 3rd-order leapfrog filter using CFOAs. Fig. 12. Linear performance of the filter (a) in Fig. 9, and (b) in Fig. 10.
 G. Raikos et al. / Int. J. Electron. Commun. (AEÜ) 66 (2012) 920–927 927

input stage which is constructed from a bulk-driven pMOS dif-

ferential pair biased by a flipped voltage follower. The provided
simulation results with regards the performance of the proposed
blocks show that they could be attractive candidates for realizing
high-performance analog processing systems with low-voltage and
low-power operation capability.

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 Update
AEUE - International Journal of Electronics and Communications
Volume 66, Issue 12, December 2012, Page 1042

DOI: https://doi.org/10.1016/j.aeue.2012.08.003
 Int. J. Electron. Commun. (AEÜ) 66 (2012) 1042

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CORRIGENDUM

Corrigendum to: “0.5 V bulk-driven analog building blocks”

[Int. J. Electron. Commun. (AEÜ) 66 (2012) 920–927]
G. Raikos ∗ , S. Vlassis, C. Phychalinos
Electronics Laboratory, Physics Department, University of Patras, GR-26504 Patras, Greece

The authors regret that an incorrect reference [21] was inadvertently published in the above article on page 8. Please see below the
corrected reference.
Khateb F, Khatib N, Kubánek D. Novel low voltage low power high-precision CCII± based on bulk-driven folded cascode OTA. Microelectron
J 2011;42:622–31.

DOI of original article: http://dx.doi.org/10.1016/j.aeue.2012.03.015.

∗ Corresponding author.
E-mail addresses: [email protected] (G. Raikos), [email protected] (S. Vlassis).

1434-8411/$ – see front matter © 2012 Elsevier GmbH. All rights reserved.
http://dx.doi.org/10.1016/j.aeue.2012.08.003