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Verilog Code of Clubbing Two Clocks

This document contains code for a clock generator module and test bench. The clock generator module uses always blocks and conditional statements to increment time values for seconds, minutes, hours, day of week and AM/PM period. The test bench instantiates the clock generator module and provides test inputs to increment the time and check the output displays the correct time values.

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suresh
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41 views4 pages

Verilog Code of Clubbing Two Clocks

This document contains code for a clock generator module and test bench. The clock generator module uses always blocks and conditional statements to increment time values for seconds, minutes, hours, day of week and AM/PM period. The test bench instantiates the clock generator module and provides test inputs to increment the time and check the output displays the correct time values.

Uploaded by

suresh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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***********************************************************************************

***********************************************************************************
*******************
clubbbing two
clocks
***********************************************************************************
***********************************************************************************
*******************
module
clock_generator(stringap,sel_two_clock,set_rt,seconds,minutes,hours,daystring,s_rt,
m_rt,h_rt,ds_rt,sa_rt,clock,reset);
input clock, reset,s_rt,m_rt,h_rt,ds_rt,set_rt,sel_two_clock,sa_rt;
output seconds,minutes,hours,daystring,stringap;
reg[5:0] seconds;
reg[5:0] minutes;
reg[4:0] hours;
reg[3*8:1]daystring;
reg[2*8:1] stringap;

wire[5:0] s_rt;
wire[5:0] m_rt;
wire[4:0] h_rt;
wire[3*8:1] ds_rt;
wire[2*8:1] sa_rt;
wire set_rt;
wire sel_two_clock;

initial
begin
seconds=6'b0;
minutes=6'b0;
hours=5'b0;
daystring="SUN";
end
//if(sel_two_clock==1'b1)
//begin
always@(posedge clock or posedge reset)
begin//1
if(sel_two_clock==1)
begin//2
if(reset==1'b1)
begin//3
seconds=0;
minutes=0;
hours=0;
daystring="SUN";
end//3
else
if(set_rt==0)
begin//4
seconds=6'b0;
minutes=6'b0;
hours=5'b0;
daystring="SUN";
end//4
if(set_rt==1)
begin//5
seconds=s_rt;
minutes=m_rt;
hours=h_rt;
daystring=ds_rt;
assign seconds=seconds+1;
if(seconds==60)
begin//6
assign seconds=0;
assign minutes=minutes+1;
if(minutes==60)
begin//7
assign minutes=0;
assign hours=hours+1;
if(hours==24)
begin//8
assign hours=0;
if(daystring=="SUN")
assign daystring="MON";
else if(daystring=="MON")
assign daystring="TUE";
else if(daystring=="TUE")
assign daystring="WED";
else if(daystring=="WED")
assign daystring="THU";
else if(daystring=="THU")
assign daystring="FRI";
else if(daystring=="FRI")
assign daystring="SAT";
else if(daystring=="SAT")
assign daystring="SUN";
end//8
end//7
end//6
end//5
end//2
//end//1
else if(sel_two_clock==0)
begin//1
//always@(posedge clock or posedge reset)
// begin//1
if(reset==1'b1)
begin//2
seconds=0;
minutes=0;
hours=0;
daystring="SUN";
stringap="AM";
end//2
else if(reset==1'b0)
begin//3
if(set_rt==0)
begin//4
seconds=0;
minutes=0;
hours=0;
daystring="SUN";
stringap="AM";
end//4
else if (set_rt==1)
begin//5
seconds=s_rt;
minutes=m_rt;
hours=h_rt;
daystring=ds_rt;
stringap=sa_rt;
//$display("%0d,%0d,%0d,%s,%s",seconds,minutes,hours,daystring,stringap);
end//5
//else
assign seconds=seconds+1;
if(seconds==60)
begin//6
assign seconds=0;
assign minutes=minutes+1;
if(minutes==60)
begin//7
assign minutes=0;
assign hours=hours+1;
if(hours==12)
begin//8
if(stringap=="AM")
assign stringap="PM";
else if(stringap=="PM")
begin//9
assign stringap="AM";

if(daystring=="SUN")
assign daystring="MON";
else if(daystring=="MON")
assign daystring="TUE";
else if(daystring=="TUE")
assign daystring="WED";
else if(daystring=="WED")
assign daystring="THU";
else if(daystring=="THU")
assign daystring="FRI";
else if(daystring=="FRI")
assign daystring="SAT";
else if(daystring=="SAT")
assign daystring="SUN";
end//9
end //8
if(hours==13)
assign hours=1;
end//7
end//6
end//3
end//1
end
endmodule
***********************************************************************************
***********************************************************************************
**********************
Test bench
***********************************************************************************
***********************************************************************************
**********************
module clock_gen_tb;
wire[5:0] seconds_tb;
wire[5:0] minutes_tb;
wire[4:0] hours_tb;
wire[3*8:1]daystring_tb;
wire[2*8:1]stringap_tb;

reg clock_tb, reset_tb;

reg [5:0] s_tb;


reg [5:0] m_tb;
reg [4:0] h_tb;
reg[3*8:1]ds_tb;
reg[2*8:1]sa_tb;
reg set_tb;
reg sel_two_clock_tb;

clock_generator dut
(.sel_two_clock(sel_two_clock_tb),.set_rt(set_tb),.seconds(seconds_tb),.minutes(min
utes_tb),.hours(hours_tb),.daystring(daystring_tb),.stringap(stringap_tb),.clock(cl
ock_tb),.reset(reset_tb),.s_rt(s_tb),.m_rt(m_tb),.h_rt(h_tb),.ds_rt(ds_tb),.sa_rt(s
a_tb));
initial clock_tb=0;
always #2 clock_tb=~clock_tb;
initial
begin
$monitor("%t; Day=%s:Hours=%0d:Minutes=%0d:Seconds=%0d %s",
$time,daystring_tb,hours_tb,minutes_tb,seconds_tb,stringap_tb);
end
initial
begin
reset_tb=1;
#50
reset_tb=0;
set_tb=1;
sel_two_clock_tb=1;
s_tb=59;
m_tb=59;
h_tb=23;
ds_tb="THU";
sa_tb="PM";
#1000
$finish;
end
endmodule

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