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Verilogcode of 12 Hour Clock

This document contains code for a 12 hour clock generator module and test bench. The clock generator module contains logic to increment the seconds, minutes, and hours registers and roll over the values to increment the day and AM/PM strings. The test bench instantiates the clock generator module and applies test inputs to set the initial time and monitors the output clocks for 12 hours of simulation time.

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suresh
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190 views3 pages

Verilogcode of 12 Hour Clock

This document contains code for a 12 hour clock generator module and test bench. The clock generator module contains logic to increment the seconds, minutes, and hours registers and roll over the values to increment the day and AM/PM strings. The test bench instantiates the clock generator module and applies test inputs to set the initial time and monitors the output clocks for 12 hours of simulation time.

Uploaded by

suresh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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***********************************************************************************

*******************************************************
12 Hour Clock Generator
***********************************************************************************
*******************************************************
module
clock_generator(seconds,minutes,hours,daystring,stringap,set_rt,ds_rt,sa_rt,h_rt,m_
rt,s_rt,clock,reset);
input clock, reset,ds_rt,sa_rt,h_rt,m_rt,s_rt,set_rt;
output seconds,minutes,hours,daystring,stringap;
reg[5:0] seconds;
reg[5:0] minutes;
reg[4:0] hours;
reg[3*8:1]daystring;
reg[2*8:1]stringap;

wire[5:0] s_rt;
wire[5:0] m_rt;
wire[4:0] h_rt;
wire[3*8:1]ds_rt;
wire[2*8:1]sa_rt;
wire set_rt;
initial
begin
seconds=6'b0;
minutes=6'b0;
hours=5'b0;
daystring="SUN";
stringap="AM";
end
always@(posedge clock or posedge reset)
begin//1
if(reset==1'b1)
begin//2
seconds=0;
minutes=0;
hours=0;
daystring="SUN";
stringap="AM";
end//2
else if(reset==1'b0)
begin//
if(set_rt==0)
begin
seconds=0;
minutes=0;
hours=0;
daystring="SUN";
stringap="AM";
end
else if (set_rt==1)
begin
seconds=s_rt;
minutes=m_rt;
hours=h_rt;
daystring=ds_rt;
stringap=sa_rt;
//$display("%0d,%0d,%0d,%s,%s",seconds,minutes,hours,daystring,stringap);
end
//else
assign seconds=seconds+1;
if(seconds==60)
begin//1
assign seconds=0;
assign minutes=minutes+1;
if(minutes==60)
begin//2
assign minutes=0;
assign hours=hours+1;
if(hours==12)
begin//3
if(stringap=="AM")
assign stringap="PM";
else if(stringap=="PM")
begin//4
assign stringap="AM";

if(daystring=="SUN")
assign daystring="MON";
else if(daystring=="MON")
assign daystring="TUE";
else if(daystring=="TUE")
assign daystring="WED";
else if(daystring=="WED")
assign daystring="THU";
else if(daystring=="THU")
assign daystring="FRI";
else if(daystring=="FRI")
assign daystring="SAT";
else if(daystring=="SAT")
assign daystring="SUN";
end//4
end //3
if(hours==13)
assign hours=1;
end//2
end//1
end
end
endmodule

***********************************************************************************
***************************************************
Test bench
***********************************************************************************
****************************************************
module clock_gen_tb;
wire[5:0] seconds_tb;
wire[5:0] minutes_tb;
wire[4:0] hours_tb;
wire[3*8:1]daystring_tb;
wire[2*8:1]stringap_tb;

reg clock_tb, reset_tb;

reg [5:0] s_tb;


reg [5:0] m_tb;
reg [4:0] h_tb;
reg[3*8:1]ds_tb;
reg[2*8:1]sa_tb;
reg set_tb;

clock_generator dut
(.set_rt(set_tb),.seconds(seconds_tb),.minutes(minutes_tb),.hours(hours_tb),.daystr
ing(daystring_tb),.stringap(stringap_tb),.clock(clock_tb),.reset(reset_tb),.s_rt(s_
tb),.m_rt(m_tb),.h_rt(h_tb),.ds_rt(ds_tb),.sa_rt(sa_tb));
initial clock_tb=0;
always #2 clock_tb=~clock_tb;
initial
begin
$monitor("%t; Day=%s:Hours=%0d:Minutes=%0d:Seconds=%0d %s",
$time,daystring_tb,hours_tb,minutes_tb,seconds_tb,stringap_tb);
end
initial
begin
reset_tb=1;
#50
reset_tb=0;
set_tb=1;
s_tb=35;
m_tb=42;
h_tb=11;
ds_tb="THU";
sa_tb="PM";
#1000
$finish;
end
endmodule

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