Intel 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

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Intel® 855GM/855GME Chipset

Graphics and Memory Controller
Hub (GMCH)
Datasheet
April 2005
Document Number: 252615-005

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 855GM/855GME Chipset GMCH may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright © 2002 – 2005, Intel Corporation
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Contents
1 Introduction ....................................................................................................................... 19
1.1 Terminology.......................................................................................................... 19
1.2 Reference Documents.......................................................................................... 21
2 Intel® 855GM/855GME Chipset GMCH Overview ............................................................ 23
2.1 System Architecture ............................................................................................. 23
2.1.1 Intel® 855GM Chipset GMCH ............................................................... 23
2.1.2 Intel® 855GME Chipset GMCH............................................................. 23
2.2 Processor Host Interface...................................................................................... 24
2.3 GMCH System Memory Interface ........................................................................ 24
2.4 Graphics Features................................................................................................ 25
2.5 Display Features .................................................................................................. 26
2.5.1 GMCH Analog Display Port .................................................................. 26
2.5.2 GMCH Integrated LVDS Port................................................................ 26
2.5.3 GMCH Integrated DVO Ports ............................................................... 26
2.6 Intel® 855GME GMCH AGP Interface .................................................................. 26
2.7 Hub Interface ........................................................................................................ 27
2.8 Address Decode Policies ..................................................................................... 27
2.9 GMCH Clocking.................................................................................................... 27
2.10 System Interrupts ................................................................................................. 28
3 Signal Descriptions ........................................................................................................... 29
3.1 Host Interface Signals .......................................................................................... 30
3.2 DDR SDRAM Interface......................................................................................... 32
3.3 AGP Interface Signals .......................................................................................... 34
3.3.1 AGP Addressing Signals ...................................................................... 34
3.3.2 AGP Flow Control Signals .................................................................... 35
3.3.3 AGP Status Signals .............................................................................. 35
3.3.4 AGP Strobes ......................................................................................... 36
3.3.5 AGP/PCI Signals-Semantics ................................................................ 36
3.4 Hub Interface Signals ........................................................................................... 39
3.5 Clocks................................................................................................................... 39
3.6 Internal Graphics Display Signals ........................................................................ 41
3.6.1 Dedicated LVDS LCD Flat Panel Interface........................................... 41
3.6.2 Digital Video Output B (DVOB) Port ..................................................... 42
3.6.3 Intel® 855GME GMCH DVO/I2C to AGP Pin Mapping ......................... 42
3.6.4 Digital Video Output C (DVOC) Port..................................................... 44
3.6.5 Analog CRT Display ............................................................................. 45
3.6.6 General Purpose Input/Output Signals................................................. 46
3.7 Voltage References, PLL Power .......................................................................... 48
4 Register Description.......................................................................................................... 51
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4.1 Conceptual Overview of the Platform Configuration Structure ............................ 51

4.2 Nomenclature for Access Attributes..................................................................... 52
4.3 Standard PCI Bus Configuration Mechanism....................................................... 53
4.4 Routing Configuration Accesses .......................................................................... 53
4.4.1 PCI Bus #0 Configuration Mechanism.................................................. 53
4.4.2 Primary PCI and Downstream Configuration Mechanism .................... 54
4.4.3 AGP/PCI_B Bus Configuration Mechanism.......................................... 54
4.5 Register Definitions .............................................................................................. 55
4.6 I/O Mapped Registers .......................................................................................... 56
4.6.1 CONFIG_ADDRESS – Configuration Address Register ...................... 56
4.6.2 CONFIG_DATA – Configuration Data Register ................................... 57
4.7 VGA I/O Mapped Registers.................................................................................. 58
4.8 Intel® 855GM/GME GMCH Host-Hub Interface Bridge Device Registers
(Device #0, Function #0) ...................................................................................... 59
4.8.1 VID – Vendor Identification Register .................................................... 60
4.8.2 DID – Device Identification Register..................................................... 60
4.8.3 PCICMD – PCI Command Register ..................................................... 61
4.8.4 PCI Status Register .............................................................................. 62
4.8.5 RID – Register Identification ................................................................. 63
4.8.6 SUBC – Sub Class Code Register ....................................................... 63
4.8.7 BCC – Base Class Code Register........................................................ 63
4.8.8 HDR – Header Type Register............................................................... 64
4.8.9 SVID – Subsystem Vendor Identification Register ............................... 64
4.8.10 SID – Subsystem Identification Register .............................................. 64
4.8.11 CAPPTR – Capabilities Pointer Register.............................................. 65
4.8.12 CAPID – Capability Identification Register (Device #0)........................ 65
4.8.13 GMC – GMCH Miscellaneous Control Register (Device #0)................ 66
4.8.14 GGC – GMCH Graphics Control Register (Device 0) .......................... 67
4.8.15 DAFC – Device and Function Control Register (Device 0) .................. 68
4.8.16 FDHC – Fixed DRAM Hole Control Register (Device #0) .................... 68
4.8.17 PAM(6:0) – Programmable Attribute Map Register (Device #0) .......... 69
4.8.18 SMRAM – System Management RAM Control Register (Device #0) .. 72
4.8.19 ESMRAMC – Extended System Management RAM Control
(Device #0)............................................................................................ 73
4.8.20 ERRSTS – Error Status Register (Device #0) ...................................... 74
4.8.21 ERRCMD – Error Command Register (Device #0) .............................. 75
4.8.22 SMICMD – SMI Error Command Register (Device #0) ........................ 76
4.8.23 SCICMD – SCI Error Command Register (Device 0)........................... 77
4.8.24 SHIC – Secondary Host Interface Control Register (Device #0).......... 78
4.8.25 ACAPID – AGP Capability Identifier Register (Device #0) ................... 79
4.8.26 AGPSTAT – AGP Status Register (Device #0) .................................... 80
4.8.27 AGPCMD – AGP Command Register (Device #0)............................... 81
4.8.28 AGPCTRL – AGP Control Register (Device #0) .................................. 82
4.8.29 AFT – AGP Functional Test Register (Device #0)................................ 82
4.8.30 APSIZE – Aperture Size (Device #0).................................................... 83
4.8.31 ATTBASE – Aperture Translation Table Base Register (Device #0) ... 84
4.8.32 AMTT – AGP Interface Multi-Transaction Timer Register (Device #0) 84
4.8.33 LPTT – Low Priority Transaction Timer Register (Device #0) .............. 85
4.8.34 HEM – Host Error Control, Status and Observation (Device #0) ......... 85
4.9 Intel® 855GM/GME GMCH Main Memory Control, Memory I/O Control Registers
(Device #0, Function #1) ...................................................................................... 86
4.9.1 VID – Vendor Identification Register .................................................... 87
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4.9.2 DID – Device Identification Register..................................................... 87

4.9.3 PCICMD – PCI Command Register ..................................................... 88
4.9.4 PCISTS – PCI Status Register ............................................................. 89
4.9.5 RID – Revision Identification Register .................................................. 90
4.9.6 SUBC – Sub-Class Code Register ....................................................... 90
4.9.7 BCC – Base Class Code Register........................................................ 90
4.9.8 HDR – Header Type Register............................................................... 91
4.9.9 SVID – Subsystem Vendor Identification Register ............................... 91
4.9.10 SID – Subsystem Identification Register .............................................. 91
4.9.11 CAPPTR – Capabilities Pointer Register.............................................. 92
4.9.12 DRB – DRAM Row (0:3) Boundary Register (Device #0) .................... 92
4.9.13 DRA – DRAM Row Attribute Register (Device #0)............................... 93
4.9.14 DRT – DRAM Timing Register (Device #0) .......................................... 94
4.9.15 PWRMG – DRAM Controller Power Management Control Register
(Device #0)............................................................................................ 98
4.9.16 DRC – DRAM Controller Mode Register (Device #0)........................... 99
4.9.17 DTC – DRAM Throttling Control Register (Device #0) ....................... 101
4.10 Intel® 855GM/GME GMCH Configuration Process Registers (Device #0,
Function #3)........................................................................................................ 105
4.10.1 VID – Vendor Identification Register .................................................. 106
4.10.2 DID – Device Identification Register................................................... 106
4.10.3 PCICMD – PCI Command Register ................................................... 106
4.10.4 PCISTS – PCI Status Register ........................................................... 107
4.10.5 RID – Revision Identification Register ................................................ 108
4.10.6 SUBC – Sub-Class Code Register ..................................................... 108
4.10.7 BCC – Base Class Code Register...................................................... 108
4.10.8 HDR – Header Type Register............................................................. 109
4.10.9 SVID – Subsystem Vendor Identification Register ............................. 109
4.10.10 ID – Subsystem Identification Register............................................... 109
4.10.11 CAPPTR – Capabilities Pointer Register............................................ 110
4.10.12 HPLLCC – HPLL Clock Control Register (Device #0)........................ 110
4.11 Intel® 852GM GMCH Integrated Graphics Device Registers (Device #2,
Function #0)........................................................................................................ 113
4.11.1 VID – Vendor Identification Register (Device #2) ............................... 114
4.11.2 DID – Device Identification Register (Device #2) ............................... 114
4.11.3 PCICMD – PCI Command Register (Device #2) ................................ 114
4.11.4 PCISTS – PCI Status Register (Device #2)........................................ 115
4.11.5 RID – Revision Identification Register (Device #2) ............................ 116
4.11.6 CC – Class Code Register (Device #2) .............................................. 116
4.11.7 CLS – Cache Line Size Register (Device #2) .................................... 116
4.11.8 MLT – Master Latency Timer Register (Device #2)............................ 117
4.11.9 HDR – Header Type Register (Device #2) ......................................... 117
4.11.10 GMADR – Graphics Memory Range Address Register (Device #2).. 117
4.11.11 MMADR – Memory Mapped Range Address Register (Device #2) ... 118
4.11.12 IOBAR – I/O Base Address Register (Device #2) .............................. 118
4.11.13 SVID – Subsystem Vendor Identification Register (Device #2).......... 119
4.11.14 SID – Subsystem Identification Register (Device #2)......................... 119
4.11.15 ROMADR – Video BIOS ROM Base Address Registers (Device #2) 119
4.11.16 INTRLINE – Interrupt Line Register (Device #2) ................................ 120
4.11.17 INTRPIN – Interrupt Pin Register (Device #2).................................... 120
4.11.18 MINGNT – Minimum Grant Register (Device #2) ............................... 120
4.11.19 MAXLAT – Maximum Latency Register (Device #2) ......................... 120
4.11.20 PMCAP – Power Management Capabilities Register (Device #2)..... 121
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4.11.21 PMCS – Power Management Control/Status Register (Device #2) ... 121
®
5 Intel 855GM/GME GMCH System Address Map .......................................................... 123
5.1 System Memory Address Ranges...................................................................... 123
5.2 DOS Compatibility Area ..................................................................................... 125
5.3 Extended System Memory Area......................................................................... 127
5.4 Main System Memory Address Range (0010_0000h to Top of Main Memory). 128
5.4.1 15-MB – 16-MB Window..................................................................... 128
5.4.2 Pre-allocated System Memory............................................................ 128
5.4.2.1 Extended SMRAM Address Range (HSEG and TSEG) ... 129
5.4.2.2 HSEG ................................................................................ 129
5.4.2.3 TSEG ................................................................................. 129
5.4.2.4 Dynamic Video Memory Technology (DVMT)................... 129
5.4.2.5 PCI Memory Address Range (Top of Main System Memory
to 4 GB) ............................................................................. 129
5.4.2.6 APIC Configuration Space (FEC0_0000h -FECF_FFFFh,
FEE0_0000h- FEEF_FFFFh) ............................................ 130
5.4.2.7 High BIOS Area (FFE0_0000h -FFFF_FFFFh)................. 130
5.4.3 System Management Mode (SMM) Memory Range .......................... 130
5.4.3.1 SMM Space Restrictions ................................................... 131
5.4.3.2 SMM Space Definition ....................................................... 131
5.4.4 System Memory Shadowing ............................................................... 132
5.4.5 I/O Address Space.............................................................................. 132
5.4.5.1 AGP/PCI I/O Address Mapping ......................................... 132
5.4.6 GMCH Decode Rules and Cross-Bridge Address Mapping............... 133
5.4.7 Hub Interface Decode Rules............................................................... 133
5.4.7.1 Hub Interface Accesses to GMCH that Cross Device
Boundaries ........................................................................ 133
5.4.7.2 AGP Interface Decode Rules ............................................ 134
6 Functional Description .................................................................................................... 137
6.1 Host Interface Overview ..................................................................................... 137
6.2 Dynamic Bus Inversion....................................................................................... 137
6.2.1 System Bus Interrupt Delivery ............................................................ 137
6.2.2 Upstream Interrupt Messages ............................................................ 138
6.3 System Memory Interface .................................................................................. 138
6.3.1 DDR SDRAM Interface Overview ....................................................... 138
6.3.2 System Memory Organization and Configuration............................... 139
6.3.2.1 Configuration Mechanism for SO-DIMMs ......................... 139
6.3.2.2 System Memory Register Programming ........................... 139
6.3.3 DDR SDRAM Performance Description ............................................. 140
6.3.3.1 Data Integrity (ECC) .......................................................... 140
6.4 Integrated Graphics Overview............................................................................ 140
6.4.1 3D/2D Instruction Processing ............................................................. 141
6.4.2 3D Engine ........................................................................................... 141
6.4.2.1 Bi-Cubic Filtering (Intel® 855GME GMCH)........................ 142
6.4.2.2 Video Mixer Rendering (Intel® 855GME GMCH) .............. 142
6.4.2.3 Setup Engine ..................................................................... 142
6.4.2.4 Viewport Transform and Perspective Divide ..................... 142
6.4.2.5 3D Primitives and Data Formats Support.......................... 143
6.4.2.6 Pixel Accurate Fast Scissoring and Clipping Operation.... 143
6.4.2.7 Backface Culling................................................................ 143
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6.4.2.8 Scan Converter.................................................................. 143

6.4.2.9 Texture Engine .................................................................. 143
6.4.2.10 Perspective Correct Texture Support................................ 144
6.4.2.11 Texture Decompression .................................................... 144
6.4.2.12 Texture Chromakey........................................................... 144
6.4.2.13 Anti-Aliasing....................................................................... 144
6.4.2.14 Texture Map Filtering ........................................................ 145
6.4.2.15 Multiple Texture Composition............................................ 145
6.4.2.16 Cubic Environment Mapping ............................................. 146
6.4.2.17 Bump Mapping .................................................................. 146
6.4.3 Raster Engine ..................................................................................... 146
6.4.3.1 Texture Map Blending ....................................................... 146
6.4.3.2 Combining Intrinsic and Specular Color Components ...... 146
6.4.3.3 Color Shading Modes........................................................ 147
6.4.3.4 Color Dithering................................................................... 147
6.4.3.5 Vertex and Per Pixel Fogging............................................ 147
6.4.3.6 Alpha Blending .................................................................. 147
6.4.3.7 Color Buffer Formats: (Destination Alpha) ........................ 148
6.4.3.8 Depth Buffer ...................................................................... 148
6.4.3.9 Stencil Buffer ..................................................................... 148
6.4.3.10 Projective Textures............................................................ 149
6.4.4 2D Engine ........................................................................................... 149
6.4.4.1 256-Bit Pattern Fill and BLT Engine .................................. 149
6.4.4.2 Alpha Stretch BLT ............................................................. 150
6.4.5 Planes and Engines ............................................................................ 150
6.4.5.1 Dual Pipe Independent Display Functionality.................... 150
6.4.6 Hardware Cursor Plane ...................................................................... 150
6.4.6.1 Cursor Color Formats........................................................ 151
6.4.6.2 Popup Plane (Second Cursor) .......................................... 151
6.4.6.3 Popup Color Formats ........................................................ 151
6.4.7 Overlay Plane ..................................................................................... 151
6.4.7.1 Multiple Overlays (Display C) ............................................ 151
6.4.7.2 Source/Destination Color/Chromakeying .......................... 151
6.4.7.3 Gamma Correction ............................................................ 152
6.4.7.4 YUV to RGB Conversion ................................................... 152
6.4.7.5 Color Control ..................................................................... 152
6.4.7.6 Dynamic Bob and Weave.................................................. 152
6.4.8 Video Functionality.............................................................................. 152
6.4.8.1 MPEG-2 Decoding ............................................................ 152
6.4.8.2 Hardware Motion Compensation....................................... 153
6.4.8.3 Sub-picture Support .......................................................... 153
6.5 Display Interface................................................................................................. 153
6.5.1 Analog Display Port Characteristics ................................................... 153
6.5.1.1 Integrated RAMDAC.......................................................... 154
6.5.1.2 DDC (Display Data Channel) ............................................ 154
6.5.2 Digital Display Interface ...................................................................... 154
6.5.2.1 Dedicated LVDS Interface................................................. 154
6.5.2.2 LVDS Interface Signals ..................................................... 155
6.5.2.3 LVDS Pair States............................................................... 155
6.5.2.4 Single Channel versus Dual Channel Mode ..................... 155
6.5.2.5 LVDS Channel Skew ......................................................... 155
6.5.2.6 SSC Support...................................................................... 155
6.5.2.7 Panel Power Sequencing .................................................. 156
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6.5.2.7.1 Panel Power Sequence States.......................... 156

6.5.2.8 Back Light Inverter Control................................................ 157
6.5.2.9 Digital Video Output Port................................................... 157
6.5.2.10 Intel 855GME GMCH AGP Interface Overview................. 158
6.5.2.11 AGP Target Operations..................................................... 158
6.5.3 AGP Transaction Ordering ................................................................. 159
6.5.4 AGP Signal Levels .............................................................................. 159
6.5.5 4X AGP Protocol................................................................................. 159
6.5.5.1 Fast Writes ........................................................................ 160
6.5.5.2 AGP FRAME# Transactions on AGP ................................ 160
6.5.6 Concurrent and Simultaneous Display ............................................... 163
7 Power and Thermal Management................................................................................... 165
7.1 General Description of Supported CPU States .................................................. 165
7.2 7.2. General Description of ACPI States............................................................ 166
7.3 Enhanced Intel SpeedStep® Technology Overview ........................................... 167
7.4 Internal Thermal Sensor..................................................................................... 167
7.4.1 Overview ............................................................................................. 167
7.4.2 Hysteresis Operation .......................................................................... 167
7.5 External Thermal Sensor Input........................................................................... 167
7.5.1 Usage.................................................................................................. 168
8 Electrical Characteristics................................................................................................. 169
8.1 Absolute Maximum Ratings................................................................................ 169
8.2 Thermal Characteristics ..................................................................................... 170
8.3 Power Characteristics ........................................................................................ 171
8.4 Signal Groups..................................................................................................... 172
8.5 DC Characteristics ............................................................................................. 176
8.5.1 General DC Characteristics ................................................................ 176
8.5.2 DAC DC Characteristics ..................................................................... 183
8.5.3 DAC Reference and Output Specifications ........................................ 184
9 Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter
Testability) ....................................................................................................................... 185
9.1 XOR Test Mode Entry ........................................................................................ 186
9.2 XOR Chain Differential Pairs.............................................................................. 187
9.3 XOR Chain Exclusion List .................................................................................. 187
9.4 XOR Chain Connectivity/Ordering ..................................................................... 188
9.4.1 VCC/VSS Voltage Groups .................................................................. 200
10 Intel® 855GM/GME GMCH Strap Pins............................................................................ 201
10.1 Strapping Configuration...................................................................................... 201
11 Ballout and Package Information .................................................................................... 203
11.1 Package Mechanical Information ....................................................................... 211
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Figures
Figure 1. Intel® 855GM GMCH Chipset System Block Diagram ...................................... 16
Figure 2. Intel® 855GME GMCH Chipset System Block Diagram .................................... 18
Figure 3. Configuration Address Register......................................................................... 56
Figure 4. Configuration Data Register .............................................................................. 57
Figure 5. PAM Registers ................................................................................................... 70
Figure 6. Simplified View of System Address Map ......................................................... 124
Figure 7. Detailed View of System Address Map ........................................................... 125
Figure 8. Intel® 855GM GMCH Graphics Block Diagram ............................................... 141
Figure 9. Panel Power Sequencing ................................................................................ 156
Figure 10. XOR–Tree Chain ........................................................................................... 185
Figure 11. XOR Chain Test Mode Entry Events Diagram .............................................. 186
Figure 12. ALLZ Test Mode Entry Events Diagram ........................................................ 186
Figure 13. Intel® 855GM/855GME GMCH Ballout Diagram (Top View)......................... 203
Figure 14. Intel® 855GM/855GME GMCH Micro-FCBGA Package Dimensions
(Top View)................................................................................................................ 211
(Side View)............................................................................................................... 212
(Bottom View) .......................................................................................................... 213
Tables
Table 1. DDR SDRAM Memory Capacity ......................................................................... 25
Table 2. Intel® 855GM/855GME GMCH Interface Clocks ................................................ 28
Table 3. Host Interface Signal Descriptions...................................................................... 30
Table 4. DDR SDRAM Interface Descriptions .................................................................. 32
Table 5. AGP Addressing Signal Descriptions ................................................................. 34
Table 6. AGP Flow Control Signals .................................................................................. 35
Table 7. AGP Status Signal Descriptions ......................................................................... 35
Table 8. AGP Strobe Descriptions .................................................................................... 36
Table 9. AGP/PCI Signals-Semantics Descriptions.......................................................... 36
Table 10. Hub Interface Signals........................................................................................ 39
Table 11. Clock Signals .................................................................................................... 39
Table 12. Dedicated LVDS LCD Flat Panel Interface Signal Descriptions....................... 41
Table 13. Digital Video Output B (DVOB) Port Signal Descriptions ................................. 42
Table 14. Intel® 855GME GMCH AGP/DVO Pin Muxing.................................................. 43
Table 15. Digital Video Output C (DVOC) Port Signal Descriptions................................. 44
Table 16. DVOB and DVOC Port Common Signal Descriptions ...................................... 44
Table 17. Analog CRT Display Signal Descriptions ......................................................... 45
Table 18. GPIO Signal Descriptions ................................................................................. 46
Table 19. Voltage References, PLL Power....................................................................... 48
Table 20. Device Number Assignment ............................................................................. 51
Table 21. Nomenclature for Access Attributes ................................................................. 52
Table 22. VGA I/O Mapped Register List ......................................................................... 58
Table 23. Index – Data Registers ..................................................................................... 58
Table 24. GMCH Configuration Space - Device #0, Function#0 ...................................... 59
Table 25. Attribute Bit Assignment.................................................................................... 69
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Table 26. PAM Registers and Associated System Memory Segments............................ 71

Table 27. Host-Hub I/F Bridge/System Memory Controller Configuration Space (Device
#0, Function#1) .......................................................................................................... 86
Table 28. Configuration Process Configuration Space (Device#0, Function #3) ........... 105
Table 29. Intel® 855GM GMCH Configurations and Some Resolution Examples.......... 111
Table 30. For Intel® 855GME GMCH Configurations and Some Resolution Examples. 112
Table 31. Integrated Graphics Device Configuration Space (Device #2, Function#0)... 113
Table 32. System Memory Segments and Their Attributes ............................................ 126
Table 33. Pre-allocated System Memory........................................................................ 128
Table 34. SMM Space Transaction Handling ................................................................. 131
Table 35. Relation of DBI Bits to Data Bits ..................................................................... 137
Table 36. Data Bytes on SO-DIMM Used for Programming DRAM Registers............... 139
Table 37. Dual Display Usage Model (Intel® 852GM GMCH) ........................................ 150
Table 38. Panel Power Sequencing Timing Parameters................................................ 157
Table 39. AGP Commands Supported by the GMCH when Acting as an AGP Target . 158
Table 40. Fast Write Initialization.................................................................................... 160
Table 41. PCI Commands Supported by the GMCH When Acting as a FRAME#
Target....................................................................................................................... 161
Table 42. Enhanced Intel SpeedStep® Technology Overview ....................................... 167
Table 43. Absolute Maximum Ratings ............................................................................ 169
Table 44. Intel® 855GM/855GME GMCH Package Thermal Resistance ....................... 170
Table 45. Power Characteristics ..................................................................................... 171
Table 46. Table Signals .................................................................................................. 173
Table 47. DC Characteristics .......................................................................................... 176
Table 48. DAC DC Characteristics: Functional Operating Range
(VCCDAC = 1.5 V ±5%)........................................................................................... 183
Table 49. DAC Reference and Output Specifications .................................................... 184
Table 50. Differential Signals in the XOR Chains ........................................................... 187
Table 51. XOR Chain Exclusion List of Pins................................................................... 187
Table 52. XOR Mapping ................................................................................................. 188
Table 53. Voltage Levels and Ball Out for Voltage Groups ............................................ 200
Table 54. Strapping Signals and Configuration .............................................................. 201
Table 55. Ballout Table ................................................................................................... 204
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Revision History
Revision Description Date

Number
001 Initial release July 2003
002 Updates include: September

2003
• Edited 855GM features under Host Bus Support
• Changed naming convention for Host Bus from Processor System Bus
(PSB) to Front Side Bus (FSB)
• Added 855GME features and system diagram to features section
• Section 1: Added disclaimer for Intel Centrino™ mobile technology
®
• Updated Reference Documents list

• Section 2: Added System architecture details for 855GM/855GME
• Section 3: Updated section with AGP Interface signal details, which is
supported by 855GME
⎯ Updated Sections 3.3.1-3.3.5 and Section 3.6
• Section 4: Added registers related to Host Interface and AGP port
• Section 5: Updated sections for AGP memory addresses
• Section 6: Incorporated 855GME features as Bi-Cubic filtering, video
mixer rendering
⎯ Added Sections 6.5.2.10 – 6.5.6 with AGP Interface overview
• Section 7: Updated Power and Thermal management with features as
system memory refresh
• Section 8: Added XOR Test Mode Entry subsection
⎯ Added Note to Voltage table to indicate 855GME nominal voltage
levels.
• Edited Package Dimensions (Bottom View) figure, row Z (original)
renamed row Y
003 Updates include: January 2004
• Added Intel Celeron M processor support

® ®
004 Updates include: May 2004
• Added Intel Pentium M processor on 90 nm process with 2-MB L2

® ®
Cache support
Updated Table 55. Ballout Table to include AGP signals
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Revision Description Date

Number
005 Updates include: April 2005
• Added new Chapter 8 Electrical Characteristics
⎯ Absolute Maximum Ratings
⎯ Thermal Characteristics
⎯ Power Characteristics
⎯ Signal Groups
⎯ DC Characteristics
• Testability moved to Chapter 9
• Intel 855GM/GME GMCH Strap Pins is now Chapter 10
Ballout and Package Information is now Chapter 11
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Intel® 855GM Chipset GMCH Features

Processor/Host Bus Support Video Stream Decoder
⎯ Intel® Pentium® M processor and Intel® ⎯ Improved hardware motion compensation
Celeron® M processor for MPEG2
⎯ 2X address, 4X data ⎯ All format decoder (18 ATSC formats)
⎯ Supports 400 MHz Front Side Bus (FSB) supported
⎯ Supports Host bus dynamic bus inversion ⎯ Dynamic Bob and Weave support for video
(DBI) streams
⎯ Supports 64-bit host data bus and 32-bit ⎯ Software DVD at 60 Fields/second and 30
addressing frames/second full screen
⎯ 8-deep in-order queue ⎯ Support for standard definition DVD (i.e.
⎯ AGTL+ bus driver technology with NTSC pixel resolution of 720x480, etc.)
integrated AGTL+ termination resistors and quality encoding at low CPU utilization
low voltage operation (Vtt = 1.05 V) Video Overlay
⎯ Supports Enhanced Intel SpeedStep® ⎯ Single high quality scalable overlay and
technology (Intel Pentium M processor second Sprite to support second overlay
⎯ Support for DPWR# signal to Intel Pentium ⎯ Multiple overlay functionality provided via
M processor and Intel Celeron M processor arithmetic stretch BLT(Block Transfer)
for FSB power management ⎯ 5-tap horizontal, 3-tap vertical filtered
Memory System scaling
⎯ Directly supports one DDR SDRAM ⎯ Multiple overlay formats
channel, 64-bits wide (72-bits with ECC) ⎯ Direct YUV from overlay to TV-out
⎯ Supports 200/266 MHz DDR SDRAM ⎯ Independent gamma correction
devices with max of two, double-sided SO- ⎯ Independent brightness / contrast/ saturation
DIMMs (four rows populated) with ⎯ Independent tint/hue support
unbuffered PC1600/PC2100 DDR SDRAM. ⎯ Destination colorkeying
⎯ Supports 128-Mbit, 256-Mbit, and 512-Mbit ⎯ Source chromakeying
technologies providing maximum capacity Multiple hardware color cursor support (32-bit
of 1 GB with x16 devices and up to 2-GB with alpha and legacy 2-bpp mode)
with high density 512-Mbit technology Accompanying I2C and DDC channels provided
⎯ All supported devices have four banks through multiplexed interface
⎯ Supports up to 16 simultaneous open pages Display
⎯ Supports page sizes of 2-kB, 4-kB, 8-kB, ⎯ Analog display support
and 16-kB. Page size is individually • 350 MHz integrated 24-bit RAMDAC
selected for every row that can drive a standard progressive
⎯ UMA support only scan analog monitor with pixel
System Interrupts resolution up to 1600x1200 at 85 Hz
⎯ Supports Intel 8259 and front side bus and up to 2048x1536 at 75 Hz
interrupt delivery mechanism ⎯ Dual independent pipe support
⎯ Supports interrupts signaled as upstream
• Concurrent: different images and native
memory writes from PCI and Hub interface
display timings on each display device
⎯ MSI sent to the CPU through the system bus
⎯ IOxAPIC in ICH4-M provides redirection • Simultaneous: same images and native
for upstream interrupts to the system bus display timings on each display device
Datasheet 13
R
⎯ DVO (DVOB and DVOC) support • Ten programmable and predefined

• Digital video out ports DVOB and monochrome patterns
DVOC with 165 MHz dot clock on • Alpha Stretch BLT (via 3D pipeline)
each 12-bit interface; two 12-bit
• Anti-aliased lines
channels can be combined to form one
dual channel 24-bit interface with an • Hardware-based BLT Clipping and
effective dot clock of 330 MHz Scissoring
• The combined DVO B/C ports as well • 32-bit Alpha Blended cursor
as individual DVO B/C ports can drive • Programmable 64 x 64 3-color
a variety of DVO devices (TV-Out Transparent cursor
Encoders, TMDS and LVDS
• Color Space Conversion
transmitters, etc.) with pixel resolution
up to 1600x1200 at 85 Hz and up to • Three Operand Raster BLTs
2048x1536 at 72 Hz. • 8-bit, 16-bit, and 32-bit color
• Compliant with DVI Specification 1.0 • ROP support
⎯ Dedicated LFP (local flat panel) LVDS • DIB translation and Linear/Tile
interface addressing
• Single- or dual-channel LVDS panel ⎯ 3D graphics engine
support up to UXGA panel resolution
• 3D setup and render engine
with frequency range from 25 MHz to
112 MHz (single channel/dual channel) • Zone rendering
• Supports data format of 18 bpp • High quality performance texture engine
• SSC support of 0.5%, 1.0%, and 2.5% • Viewpoint transform and perspective
center and down spread with external divide
SSC clock • Triangle lists, strips and fans support
• LCD panel power sequencing compliant • Indexed vertex and flexible vertex
with SPWG timing specification formats
• Compliant with ANSI/TIA/EIA –644- • Pixel accurate fast scissoring and
1995 spec clipping operation
• Integrated PWM interface for LCD • Backface culling support
backlight inverter control • Microsoft DirectX* and SGI OpenGL*
• Bi-linear panel fitting pixelization rules
⎯ Tri-view support through LFP interface, • Anti-Aliased lines support
DVO B/C port, and CRT
• Sprite points support
Internal Graphics Features
⎯ Up to 64 MB of dynamic video memory • Provides the highest sustained fill rate
allocation performance in 32-bit color and 24-bit
⎯ Display image rotation W mode
⎯ Graphics core frequency • High quality performance texture engine
⎯ Display core frequency at 133 MHz or • 266-MegaTexel/s peak performance
200 MHz
• Per pixel perspective corrected texture
⎯ Render core frequency at 100 MHz,
mapping
133 MHz, 200 MHz
⎯ 2D graphics engine • Single pass texture compositing (multi-
textures)
• Optimized 128-bit BLT engine
• Enhanced texture blending functions
14 Datasheet
R
• Twelve level of detail MIP map sizes • Z Bias support

from 1x1 to 2k x 2k • Dithering
• Numerous texture formats including 32- • Line and full-scene anti-aliasing
bit RGBA
• 16 and 24-bit Z buffering
• Alpha and Luminance maps
• 16 and 24-bit W buffering
• Texture chromakeying
• 8-bit Stencil buffering
• Bilinear, trilinear, and anisotropic MIP
map filtering • Double and triple render buffer support
• Cubic environment reflection mapping • 16 and 32-bit color
• Dot product bump-mapping • Destination alpha
• Embossed bump-mapping • Vertex cache
• DXTn texture decompression • Optimal 3D resolution supported
• FX1 texture compression • Fast Clear support
• 3D graphics rasterization enhancements • ROP support
• One Pixel per clock
Hub Interface to ICH4-M
⎯ 266 -MB/s point-to-point Hub interface to
• Flat and Gouraud shading ICH4-M
• Color alpha blending for transparency ⎯ 66 MHz base clock
• Vertex and programmable pixel fog and Power Management
atmospheric effects ⎯ SMRAM space remapping to A0000h (128-
kB)
• Color specular lighting
Datasheet 15
R
Figure 1. Intel® 855GM GMCH Chipset System Block Diagram
Intel® Pentium® M
Processor OR
CK-408 IMVP-IV
Intel® Celeron® M
VR
Processor
400 MHz FSB
DVI DVOB & DVOC
Device 1.5 V Intel® 855GM
GMCH 200/266 MHz
CRT
LVDS 732 Micro-
DDR
FCBGA
Hub Interface 1.5
Mini-PCI
ATA100 IDE (2) Intel® Intel® PRO/
Wireless
82801DBM Network
USB2.0/1.1 (6) 421 BGA Connection
PCI Bus Moon 2
(ICH4-M)
Cardbus PCI Docking
LAN
AC'97 2.2/2.3
LPC I/F SIO
FWH
Modem Codec Audio Codec KBC
16 Datasheet
R
Intel® 855GME Chipset GMCH

Features
Note: The Intel 855GME chipset GMCH has identical features to the Intel 855GM chipset GMCH
except for the additional features listed below.
Processor/Host Bus Support ⎯ Graphics Power Management

⎯ Pin and spec compatible with the Intel® • Dynamic Frequency Switching
Pentium® M processor, Intel® Pentium® M
• Memory Self-Refresh During C3
Processor on 90 nm process with 2-MB L2
® ®
Cache and Intel Celeron M processor Intel® Display Power Saving Technology
Memory System Power Management
⎯ Support for 333 MHz DDR SDRAM ⎯ Optimized Clock Gating for 3D and Display
devices with max of two double-sided SO- Engines
DIMMs (4 rows populated) with unbuffered ⎯ On-Die Thermal Sensor
PC2700 DDR SDRAM. Accelerated Graphics Port (AGP) Interface
Display ⎯ Supports a single AGP device
⎯ Dedicated LFP (local flat panel) interface ⎯ Supports AGP 2.0 including 1X,2X, and 4X
AGP data transfers and 2X/4X Fast Write
• Supports data format up to 24-bpp protocol
Internal Graphics Features ⎯ Supports only 1.5 V AGP electricals
⎯ Core Vcc = 1.2 V or 1.35 V (1.35 V needed ⎯ 32 deep AGP request queue
to support Graphics core frequency of 250 ⎯ PCI semantic (Frame# initiated) accesses to
MHz and 333 MHz DDR SDRAM devices) DDR SDRAM are snooped
⎯ Graphics core frequency ⎯ AGP semantic (PIPE# and SBA) accesses to
• Display core frequency at 133 MHz,200 DDR SDRAM are not snooped
MHz, 250 MHz ⎯ Hierarchical PCI configuration mechanism
• Render core frequency at 100 MHz, ⎯ Delayed transaction support
133 MHz, 166 MHz, 200 MHz, 250 AGP Busy/Stop Protocol
MHz
• Intel® Dual-Frequency Graphics
Technology
⎯ 3D Graphics Engine
• Enhanced Hardware Binning Instruction
Set supported
• Bi-Cubic Filtering supported
• Linear Gamma Blending for Video
Mixer Rendering (VMR)
• Video Mixer Rendering (VMR)
supported
Datasheet 17
R
Figure 2. Intel® 855GME GMCH Chipset System Block Diagram
Intel® Pentium® M
Processor OR
CK-408 Intel® Celeron® M IMVP-IV
Processor VR
400 MHz FSB

DVI/AGP DVOB/C or AGP
Device 1.5 V Intel® 855GME
GMCH 200/266/333 MHz
CRT
LVDS 732 Micro-
DDR SDRAM
FCBGA
Hub Interface 1.5
Mini-PCI
ATA100 IDE (2) Intel® Intel® PRO/
Wireless
82801DBM Network
USB2.0/1.1 (6) 421 BGA Connection
PCI Bus Moon 2
(ICH4-M)
Cardbus PCI Docking
LAN
AC'97 2.2/2.3
LPC I/F SIO
FWH
Modem Codec Audio Codec KBC
18 Datasheet
Introduction
1 Introduction
This datasheet provides Intel’s specifications for the Intel® 855GM/855GME chipset based
system.
The Intel 855GM/855GME chipset graphics and memory controller hub (GMCH) is also an Intel®
Centrino™ mobile technology component. Intel Centrino mobile technology with integrated
wireless LAN capabilities was designed specifically for wireless notebook PCs – delivering
outstanding mobile performance and enabling extended battery life, and thinner, lighter designs.
Note: Wireless connectivity and some features may require you to purchase additional software,
services or external hardware. Availability of public wireless LAN access points limited. System
performance measured by MobileMark* 2002. System performance, battery life, wireless
performance and functionality will vary depending on your specific hardware and software
configurations. See http://www.intel.com/products/centrino/moreinfo for more information.
1.1 Terminology
Term Description
AGTL+ Advanced Gunning Transceiver Logic + (AGTL+) bus
DDC Display Data Channel (standard created by VESA)
DPMS Display Power Management Signaling (standard created by VESA)
I2C Inter-IC (a two wire serial bus created by Philips)
CRT Cathode Ray Tube
LCD Liquid Crystal Display
BLI Backlight Inverter
Core The internal base logic in the Intel 855GM/GME GMCH
CPU Central Processing Unit
DBI Dynamic Bus inversion
DBL Display Brightness Link
DVO Digital Video Out
DVI* Digital Visual Interface is the interface specified by the DDWG (Digital Display
Working Group) DVI Spec. Rev. 1.0 utilizing only the Silicon Image developed
TMDS protocol
DVMT Dynamic Video Memory Technology
EDID Extended Display Identification Data
Full Reset A Full Intel 855GM/GME GMCH Reset is defined in this document when
RSTIN# is asserted
GMCH Graphics and Memory Controller Hub
Hub Interface (HI) The proprietary interconnect between the Intel 855GM/GME GMCH and the
ICH4-M component. In this document, the Hub interface cycles originating from
Datasheet 19
Introduction
Term Description
or destined for the ICH4-M are generally referred to as “Hub interface cycles.”
Hub cycles originating from or destined for the primary PCI interface on are
sometimes referred to as “Hub interface/PCI cycles”
Host This term is used synonymously with processor
IGD Integrated Graphics Device
Intel 855GM/GME Refers to the GMCH component. Throughout this datasheet, the Intel
GMCH 855GM/GME GMCH will be referred to as the GMCH.
Intel 82801DBM ICH4-M The component contains the primary PCI interface, LPC interface, USB 2.0,
ATA-100, AC’97, and other I/O functions. It communicates with the Intel
855GM/GME GMCH over a proprietary interconnect called the Hub interface.
Throughout this datasheet, the Intel 82801DBM ICH4-M component will be
referred to as the ICH4-M
Intel Pentium M Refers to the Intel Pentium M Processor and Intel Pentium M Processor
Processor on 90nm process with 2-MB L2 Cache. Intel Pentium M Processor will
reference both processors unless specified
IPI Inter Processor Interrupt
LFP Local Flat Panel
LVDS Low Voltage Differential Signals used for interfacing to LCD Flat Panels
MSI Message Signaled Interrupts. MSI allow a device to request interrupt service
via a standard memory write transaction instead of through a hardware signal
FSB Front side bus. Connection between Intel 855GM/GME GMCH and the CPU.
Also known as the Host interface
PWM Pulse Width Modulation
SSC Spread Spectrum Clocking
System Bus Processor-to-Intel 855GM/GME GMCH interface. The Enhanced mode of the
Scalable bus is the P6 Bus plus enhancements, consisting of source
synchronous transfers for address and data, and system bus interrupt delivery.
The Intel Pentium M processor, Intel Pentium M on 90nm process with 2-MB L2
Cache and Intel Celeron M processor implement a subset of Enhanced mode.
UMA Unified Memory Architecture with graphics memory for the IGD inside system
memory
VDL Video Data Link
20 Datasheet
Introduction
1.2 Reference Documents

Document Location
® ®
Intel Pentium M Processor Datasheet (252612) http://www.intel.com/design/mobile/datashts/252612.h
tm
® ®
Intel Pentium M Processor on 90 nm Process with 2- http://developer.intel.com/design/mobile/datashts/302
MB L2 Cache Datasheet (302189) 189.htm
® ®
Intel Celeron M Processor Datasheet (300302) http://www.intel.com/design/mobile/datashts/300302.h
tm
Intel® 852GM/855GM/855GME Chipset Mobile Note 1

Thermal Design Guide
PCI Local Bus Specification 2.2 http://www.pcisig.com

®
Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4- http://developer.intel.com/design/mobile/datashts/252
M) Datasheet (252337) 337.htm
®
Intel 855GM/855GME Chipset Platform Design http://www.intel.com/design/mobile/desguide/252616.
Guide (252616) htm
Advanced Configuration and Power http://www.acpi.info/

Management(ACPI) Specification 1.0b & 2.0
Advanced Power Management (APM) Specification http://www.microsoft.com/hwdev/busbios/

1.2 amp_12.htm
®
IA-32 Intel Architecture Software Developer Manual http://developer.intel.com/design/pentium4/manuals/i
Volume 3: System Programming Guide (253668) ndex_new.htm
NOTES:
1. Contact your Intel representative for the current document.
Datasheet 21
Introduction
22 Datasheet
Intel® 855GM/855GME Chipset GMCH Overview
2 Intel® 855GM/855GME Chipset

GMCH Overview
2.1 System Architecture

The Intel 855GM/855GME GMCH components provide the processor interface, DDR SDRAM
interface, display interface, and Hub interface. The Intel 855GME also has an option for AGP
external graphics port, in addition to integrated graphics support for added board flexibility
options.
2.1.1 Intel® 855GM Chipset GMCH

The Intel 855GM GMCH is in a 732-pin Micro-FCBGA package and contains the following
functionality listed below:
• AGTL+ host bus supporting 32-bit host addressing with Enhanced Intel SpeedStep®
technology support
• Supports a single channel of DDR SDRAM memory
• System memory supports DDR200/266 MHz (SSTL_2) DDR SDRAM
• Integrated graphics capabilities: Display Core frequency at 133 MHz or 200 MHz
• Render Core frequency at 100 MHz ,133 MHz, and 200 MHz
• Provides supports four display ports: one progressive scan analog monitor, dual channel
LVDS interface and two DVO port.
2.1.2 Intel® 855GME Chipset GMCH

The Intel 855GME GMCH is in a 732-pin Micro-FCBGA package and contains all features listed
above and the additional functionality list below:
• Display Core frequency at 133 MHz, 200 MHz, or 250 MHz
• Render Core frequency at 100 MHz ,133 MHz, 166 MHz, 200 MHz, or 250 MHz
• System memory supports 200/266/333- MHz (SSTL_2) DDR SDRAM.
• Enhanced Power Management Graphics features
Datasheet 23
2.2 Processor Host Interface

The Intel 855GM/855GME GMCH is optimized for the Intel Pentium M processor and Intel
Celeron M processor
Key features of the front side bus (FSB) are:

• Support for a 400 MHz system bus frequency.
• Source synchronous double pumped address (2X)
• Source synchronous quad pumped data (4X)
• Front side bus interrupt delivery
• Low voltage swing Vtt (1.05V)
• Dynamic Power Down (DPWR#) support
• Integrates AGTL+ termination resistors on all of the AGTL+ signals
• Supports 32-bit host bus addressing allowing the CPU to access the entire 4 GB of the
GMCH memory address space.
• An 8-deep, In-Order queue
• Support DPWR# signal
• Supports one outstanding defer cycle at a time to any particular I/O interface
2.3 GMCH System Memory Interface

The GMCH system memory controller directly supports the following:
• One channel of PC1600/2100 SO-DIMM DDR SDRAM memory (Intel 855GM GMCH)
• One channel of PC1600/2100/2700 SO-DIMM DDR SDRAM memory (Intel 855GME
GMCH)
• DDR SDRAM devices with densities of 128-Mb, 256-Mb, and 512-Mb technology
• Up to 1 GB (512-Mb technology) with two SO-DIMMs
• Up to 2 GB (512-Mb technology) using high density devices with two SO-DIMMs
24 Datasheet
Table 1. DDR SDRAM Memory Capacity
Technology Width System Memory System Memory

Capacity Capacity with Stacked
Memory
128 Mb 16 256 MB -
256 Mb 16 512 MB -
512 Mb 16 1 GB -
128 Mb 8 256 MB 512 MB
256 Mb 8 512 MB 1 GB
512 Mb 8 1 GB 2 GB
The GMCH system memory interface supports a thermal throttling scheme to selectively throttle
reads and/or writes. Throttling can be triggered either by the on-die thermal sensor, or by preset
write bandwidth limits. Read throttle can also be triggered by an external input pin. The memory
controller logic supports aggressive Dynamic Row Power Down features to help reduce power
and supports Address and Control line Tri-stating when DDR SDRAM is in an active power
down or in self refresh state.
The GMCH system memory architecture is optimized to maintain open pages (up to 16-kB page
size) across multiple rows. As a result, up to 16 pages across four rows is supported. To
complement this, the GMCH will tend to keep pages open within rows, or will only close a single
bank on a page miss. The GMCH supports only four bank memory technologies.
2.4 Graphics Features

The GMCH IGD provides a highly integrated graphics accelerator delivering high performance
2D, 3D, and video capabilities. With its interfaces to UMA using a DVMT configuration, an
analog display, a LVDS port, and two digital display ports (e.g. flat panel), the GMCH can
provide a complete graphics solution.
The GMCH also provides 2D hardware acceleration for block transfers of data (BLTs). The BLT
engine provides the ability to copy a source block of data to a destination and perform raster
operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination.
Performing these common tasks in hardware reduces CPU load, and thus improves performance.
High bandwidth access to data is provided through the system memory interface. The GMCH
uses Tiling architecture to increase system memory efficiency and thus maximize effective
rendering bandwidth. The Intel 855GM/855GME GMCH improves 3D performance and quality
with 3D Zone rendering technology. The Intel 855GME GMCH also supports Video Mixer
rendering, and Bi-Cubic filtering.
Datasheet 25
2.5 Display Features

The Intel 855GM/855GME GMCH has four display ports, one analog and three digital. With
these interfaces, the GMCH can provide support for a progressive scan analog monitor, a
dedicated dual channel LVDS LCD panel, and two DVO devices. Each port can transmit data
according to one or more protocols. The data that is sent out the display port is selected from one
of the two possible sources, Pipe A or Pipe B.
2.5.1 GMCH Analog Display Port

Intel 855GM/855GME GMCH has an integrated 350 MHz, 24-bit RAMDAC that can directly
drive a progressive scan analog monitor pixel resolution up to 1600x1200 at 85-Hz refresh and up
to 2048x1536 at 75-Hz refresh. The Analog display port can be driven by Pipe A or Pipe B.
2.5.2 GMCH Integrated LVDS Port

The Intel 855GM/855GME GMCH have an integrated dual channel LFP Transmitter interface to
support LVDS LCD panel resolutions up to UXGA The display pipe provides panel up-scaling to
fit a smaller source image onto a specific native panel size, as well as provides panning and
centering support. The LVDS port is only supported on Pipe B. The LVDS port can only be
driven by Pipe B, either independently or simultaneously with the Analog Display port. Spread
Spectrum Clocking is supported: center and down spread support of 0.5%, 1%, and 2.5% utilizing
an external SSC clock.
2.5.3 GMCH Integrated DVO Ports

The DVO B/C interface is compliant with the DVI Specification 1.0. When combined with a DVI
compliant external device (e.g. TMDS Flat Panel Transmitter, TV-out encoder, etc.), the GMCH
provides a high-speed interface to a digital or analog display (e.g. flat panel, TV monitor, etc.).
The DVO ports are connected to an external display device. Examples of this are TV-out
encoders, external DACs, LVDS transmitters, and TMDS transmitters. Each display port has
control signals that may be used to control, configure and/or determine the capabilities of an
external device.
The GMCH provides two DVO ports that are each capable of driving a 165 MHz pixel clock at
the DVO B or DVO C interface. When DVO B and DVO C are combined into a single DVO port,
then an effective pixel rate of 330 MHz can be achieved. The DVO B/C ports can be driven by
Pipe A or Pipe B. If driven on Pipe B, then the LVDS port must be disabled.
2.6 Intel® 855GME GMCH AGP Interface

The Intel 855GME has support for a single AGP component is supported by the AGP interface.
The AGP buffers operate only in 1.5 V mode. They are not 3.3 V tolerant.
The AGP interface supports 1X/2X/4X AGP signaling and 2X/4X Fast Writes. AGP semantic
cycles to DDR SDRAM are not snooped on the host bus. PCI semantic cycles to DDR SDRAM
are snooped on the host bus. The GMCH/MCH support PIPE# or SBA[7:0] AGP address
mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be
26 Datasheet
selected during system initialization. Both upstream and downstream addressing is limited to 32-
bits for AGP and AGP/PCI transactions. The GMCH/MCH contains a 32-deep AGP request
queue. High priority accesses are supported. All accesses from the AGP/PCI interface that fall
within the Graphics Aperture address range pass through an address translation mechanism with a
fully associative 20 entry TLB. Accesses between AGP and hub interface are limited to memory
writes originating from the hub interface destined for AGP. The AGP interface is clocked from a
dedicated 66 MHz clock (GLCKIN). The AGP-to-host/core interface is asynchronous.
The AGP interface should be powered-off or tri-stated without voltage on the interface during
ACPI S3 or APM Suspend to RAM state.
Refer to the AGP Busy and Stop Signals Specification for more information.
2.7 Hub Interface

A proprietary interconnect connects the GMCH to the ICH4-M. All communication between the
GMCH and the ICH4-M occurs over the Hub interface 1.5. The Hub interface runs at 66 MHz
(266-MB/s).
2.8 Address Decode Policies

Host initiated I/O cycles are positively decoded to the GMCH configuration space and
subtractively decoded to Hub interface. Host initiated system memory cycles are positively
decoded to DDR SDRAM and are again subtractively decoded to Hub interface if under 4 GB.
System memory accesses from Hub interface to DDR SDRAM will be snooped on the FSB.
2.9 GMCH Clocking

The GMCH has the following clock input/output pins:
• 400 MHz, spread spectrum, low voltage differential BCLK, BCLK# for front side bus (FSB)
• 66 MHz, 3.3 V GCLKIN for Hub interface buffers
• Six pairs of differential output clocks (SCK[5:0], SCK[5:0]#), 200/266 MHz, 2.5 V for
system memory interface
• 48 MHz, non-Spread Spectrum, 3.3 V DREFCLK for the Display Frequency Synthesis
• 48 MHz or 66 MHz, Spread Spectrum, 3.3 V DREFSSCLK for the Display Frequency
Synthesis
• Up to 85 MHz, 1.5 V DVOBCCLKINT for TV-Out mode
• DPMS clock for S1-M
Clock Synthesizer chips are responsible for generating the system host clocks, GMCH display
clocks, Hub interface clocks, PCI clocks, SIO clocks, and FWH clocks. The host target speed is
400 MHz. The GMCH does not require any relationship between the BCLK Host clock and the
66 MHz clock generated for Hub interface; they are asynchronous to each other. The Hub
interface runs at a constant 66 MHz base frequency. Table 2 indicates the frequency ratios
between the various interfaces that the GMCH supports.
Datasheet 27
Table 2. Intel® 855GM/855GME GMCH Interface Clocks
Interface Clock Speed CPU System Bus Samples Data Rate Data Peak
Frequency Ratio Per Clock (Mega- Width Bandwidth
samples/s) (Bytes) (MB/s)
CPU Bus 100 MHz Reference 4 400 8 3200
100 MHz 1:1 Synchronous 2 200 8 1600
DDR SDRAM 133 MHz 1:1 Synchronous 2 266 8 2128
166 MHz 1:1 Synchronous 2 333 8 2664
LVDS Flat Panel 35 MHz-112 Asynchronous 1 112 2.25 252

MHz (single
channel)
DVO B or DVO C Up to 165 MHz Asynchronous 2 330 1.5 495
DVO B+DVO C Up to 330 MHz Asynchronous 2 660 3 1980
DAC Interface 350 MHz Asynchronous 1 350 3 1050
2.10 System Interrupts

The GMCH supports both the legacy Intel 8259 Programmable Interrupt delivery mechanism and
the Intel Pentium M processor and Intel Celeron M processor FSB interrupt delivery mechanism.
The serial APIC Interrupt mechanism is not supported.
The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound Hub interface
write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the Hub
interface.
PCI MSI interrupts are generated as memory writes. The GMCH decodes upstream memory
writes to the range 0FEE0_0000h - 0FEEF_FFFFh from the Hub interface as message based
interrupts. The GMCH forwards the memory writes along with the associated write data to the
system bus as an Interrupt Message transaction. Since this address does not decode as part of
main system memory, the write cycle and the write data do not get forwarded to system memory
via the write buffer. The GMCH provides the response and HTRDY# for all Interrupt Message
cycles including the ones originating from the GMCH. The GMCH also supports interrupt
redirection for upstream interrupt memory writes.
For message based interrupts, system write buffer coherency is maintained by relying on strict
ordering of memory writes. The GMCH ensures that all memory writes received from a given
interface prior to an interrupt message memory write are delivered to the system bus for snooping
in the same order that they occur on the given interface.
28 Datasheet
Signal Descriptions
3 Signal Descriptions
This section describes the GMCH signals. These signals are arranged in functional groups
according to their associated interface. The following notations are used to describe the signal
type:
I Input pin
O Output pin
I/O Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal:
AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The GMCH integrates AGTL+ termination resistors, and supports
VTTLF of 1.05 V ± 5%. AGTL+ signals are “inverted bus” style where a low
voltage represents a logical 1.
DVO DVO buffers (1.5 V tolerant)
Hub Compatible to Hub interface 1.5
SSTL_2 Stub Series Termination Logic compatible signals (2.5 V tolerant)
LVTTL Low Voltage TTL compatible signals (3.3 V tolerant)
CMOS CMOS buffers (3.3 V tolerant)
LVDS Low Voltage Differential signal interface
Analog Analog signal interface
Ref Voltage reference signal
System Address and Data Bus signals are logically inverted signals. In other words, the actual
values are inverted of what appears on the system bus. This must be taken into account and the
addresses and data bus signals must be inverted inside the GMCH. All processor control signals
follow normal convention: A 0 indicates an active level (low voltage), and a 1 indicates an active
level (high voltage).
Datasheet 29
Signal Descriptions
3.1 Host Interface Signals

Table 3. Host Interface Signal Descriptions
Signal Name Type Description
ADS# I/O Address Strobe: The system bus owner asserts ADS# to indicate the first of two
AGTL+ cycles of a request phase. The GMCH can assert this signal for snoop cycles and
interrupt messages.
BNR# I/O Block Next Request: Used to block the current request bus owner from issuing a new
AGTL+ request. This signal is used to dynamically control the CPU bus pipeline depth.
BPRI# O Bus Priority Request: The GMCH is the only Priority Agent on the system bus. It
AGTL+ asserts this signal to obtain the ownership of the address bus. This signal has priority
over symmetric bus requests and will cause the current symmetric owner to stop
issuing new transactions unless the HLOCK# signal was asserted.
BREQ0# I/O Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal low during
AGTL+ CPURST#. The signal is sampled by the processor on the active-to-inactive transition
of CPURST#. The minimum setup time for this signal is 4 BCLKs. The minimum hold
time is 2 clocks and the maximum hold time is 20 BCLKs. BREQ0# should be tristated
after the hold time requirement has been satisfied.
During regular operation, the GMCH will use BREQ0# as an early indication for FSB
Address and Ctl input buffer and sense amp activation.
CPURST# O CPU Reset: The CPURST# pin is an output from the GMCH. The GMCH asserts
AGTL+ CPURST# while RESET# (PCIRST# from ICH4-M) is asserted and for approximately 1
ms after RESET# is deasserted. The CPURST# allows the processor to begin
execution in a known state.
Note that the ICH4-M must provide CPU strap set-up and hold-times around
CPURST#. This requires strict synchronization between GMCH, CPURST#
deassertion and ICH4-M driving the straps.
DBSY# I/O Data Bus Busy: Used by the data bus owner to hold the data bus for transfers
AGTL+ requiring more than one cycle.
DEFER# O Defer: GMCH will generate a deferred response as defined by the rules of the GMCH’s
AGTL+ Dynamic Defer policy. The GMCH will also use the DEFER# signal to indicate a CPU
retry response.
DINV[3:0]# I/O Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. Indicates if the
AGTL+ associated signals are inverted or not. DINV[3:0]# are asserted such that the number
of data bits driven electrically low (low voltage) within the corresponding 16-bit group
never exceeds 8.
DINV# Data Bits
DINV[3]# HD[63:48]#
DINV[2]# HD[47:32]#
DINV[1]# HD[31:16]#
DINV[0]# HD[16:0]#
DPSLP# I Deep Sleep #: This signal comes from the ICH4-M device, providing an indication of
C3 and C4 state control to the CPU. Deassertion of this signal is used as an early
CMOS
indication for C3 and C4 wake up (to active HPLL). Note that this is a low-voltage
CMOS buffer operating on the FSB VTT power plane.
30 Datasheet
Signal Descriptions
DRDY# I/O Data Ready: Asserted for each cycle that data is transferred.
AGTL+
HA[31:3]# I/O Host Address Bus: HA[31:3]# connects to the CPU address bus. During processor
AGTL+ cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during snoop cycles on
behalf of Hub interface. HA[31:3]# are transferred at 2X rate. Note that the address is
inverted on the CPU bus.
HADSTB[1:0]# I/O Host Address Strobe: HA[31:3]# connects to the CPU address bus. During CPU
AGTL+ cycles, the source synchronous strobes are used to transfer HA[31:3]# and
HREQ[4:0]# at the 2X transfer rate.
Strobe Address Bits
HADSTB[0]# HA[16:3]#, HREQ[4:0]#
HADSTB[1]# HA[31:17]#
HD[63:0]# I/O Host Data: These signals are connected to the CPU data bus. HD[63:0]# are
AGTL+ transferred at 4X rate. Note that the data signals are inverted on the CPU bus.
HDSTBP[3:0]# I/O Differential Host Data Strobes: The differential source synchronous strobes are
AGTL+ used to transfer HD[63:0]# and DINV[3:0]# at the 4X transfer rate.
HDSTBN[3:0]#
Strobe Data Bits
HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]#
HIT# I/O Hit: Indicates that a caching agent holds an unmodified version of the requested line.
AGTL+ Also, driven in conjunction with HITM# by the target to extend the snoop window.
HITM# I/O Hit Modified: Indicates that a caching agent holds a modified version of the requested
AGTL+ line and that this agent assumes responsibility for providing the line. Also, driven in
conjunction with HIT# to extend the snoop window.
HLOCK# I/O Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#,
AGTL+ until the negation of HLOCK# must be atomic, i.e. no Hub interface snoopable access
to system memory is allowed when HLOCK# is asserted by the CPU.
HREQ[4:0]# I/O Host Request Command: Defines the attributes of the request. HREQ[4:0]# are
AGTL+ transferred at 2X rate. Asserted by the requesting agent during both halves of the
Request Phase. In the first half the signals define the transaction type to a level of
detail that is sufficient to begin a snoop request. In the second half the signals carry
additional information to define the complete transaction type.
The transactions supported by the GMCH Host Bridge are defined in the Host Interface
section of this document.
HTRDY# O Host Target Ready: Indicates that the target of the processor transaction is able to
AGTL+ enter the data transfer phase.
Datasheet 31
Signal Descriptions
RS[2:0]# O Response Status: Indicates the type of response according to the following the table:
AGTL+
RS[2:0]# Response type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by GMCH)
100 Hard Failure (not driven by GMCH)
101 No data response
110 Implicit Write back
111 Normal data response
3.2 DDR SDRAM Interface

Table 4. DDR SDRAM Interface Descriptions
SCS[3:0]# O Chip Select: These pins select the particular DDR SDRAM components during the
SSTL_2 active state.
NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These
signals can be toggled on every rising System Memory Clock edge (SCMDCLK).
SMA[12:0] O Multiplexed Memory Address: These signals are used to provide the multiplexed row
SSTL_2 and column address to the DDR SDRAM.
SBA[1:0] O Bank Select (Memory Bank Address): These signals define which banks are selected
SSTL_2 within each DDR SDRAM row. The SMA and SBA signals combine to address every
possible location within a DDR SDRAM device.
SRAS# O DDR Row Address Strobe: SRAS# may be heavily loaded and requires tw0 DDR
SSTL_2 SDRAM clock cycles for setup time to the DDR SDRAMs. Used with SCAS# and SWE#
(along with SCS#) to define the system memory commands.
SCAS# O DDR Column Address Strobe: SCAS# may be heavily loaded and requires two clock
SSTL_2 cycles for setup time to the DDR SDRAMs. Used with SRAS# and SWE# (along with
SCS#) to define the system memory commands.
SWE# O Write Enable: Used with SCAS# and SRAS# (along with SCS#) to define the DDR
SSTL_2 SDRAM commands. SWE# is asserted during writes to DDR SDRAM. SWE# may be
heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs.
SDQ[71:0] I/O Data Lines: These signals are used to interface to the DDR SDRAM data bus.
SSTL_2
NOTE: ECC error detection is supported: by the SDQ[71:64] signals.
32 Datasheet
Signal Descriptions
SDQS[8:0] I/O Data Strobes: Data strobes are used for capturing data. During writes, SDQS is
SSTL_2 centered on data. During reads, SDQS is edge aligned with data. The following list
matches the data strobe with the data bytes.
There is an associated data strobe (DQS) for each data signal (DQ) and check bit (CB)
group.
SDQS[7] -> SDQ[63:56]
SDQS[6] -> SDQ[55:48]
SDQS[5] -> SDQ[47:40]
SDQS[4] -> SDQ[39:32]
SDQS[3] -> SDQ[31:24]
SDQS[2] -> SDQ[23:16]
SDQS[1] -> SDQ[15:8]
SDQS[0] -> SDQ[7:0]
NOTE: ECC error detection is supported by the SDQS[8] signal.
SCKE[3:0] O Clock Enable: These pins are used to signal a self-refresh or power down command to
SSTL_2 the DDR SDRAM array when entering system suspend. SCKE is also used to
dynamically power down inactive DDR SDRAM rows. There is one SCKE per DDR
SDRAM row. These signals can be toggled on every rising SCK edge.
SMAB[5,4,2,1] O Memory Address Copies: These signals are identical to SMA[5,4,2,1] and are used to
reduce loading for selective CPC(clock-per-command). These copies are not inverted.
SSTL_2
SDM[8:0] O Data Mask: When activated during writes, the corresponding data groups in the DDR
SDRAM are masked. There is one SDM for every eight data lines. SDM can be
SSTL_2
sampled on both edges of the data strobes.
NOTE: ECC error detection is supported by the SDM[8] signal.
RCVENOUT# O Clock Output: Reserved, NC.
SSTL_2
RCVENIN# O Clock Input: Reserved, NC.
SSTL_2
Datasheet 33
Signal Descriptions
3.3 AGP Interface Signals

Note: AGP interface is only supported on the Intel 855GME GMCH. Unless otherwise specified, the
voltage level for all signals in this interface is 1.5 volts.
3.3.1 AGP Addressing Signals

Table 5. AGP Addressing Signal Descriptions
GPIPE# I Pipelined Read: This signal is asserted by the AGP master to indicate a full width
AGP address is to be enqueued on by the target using the AD bus. One address is placed in
the AGP request queue on each rising clock edge while PIPE# is asserted. When
PIPE# is deasserted no new requests are queued across the AD bus.
During SBA Operation: This signal is not used if SBA (Side Band Addressing) is
selected.
During FRAME# Operation: This signal is not used during AGP FRAME# operation.
PIPE# is a sustained tri-state signal from masters (graphics controller), and is an input
to the GMCH.
GSBA[7:0] I Side-band Address: These signals are used by the AGP master (graphics controller)
AGP to pass address and command to the GMCH. The SBA bus and AD bus operate
independently. That is, transactions can proceed on the SBA bus and the AD bus
simultaneously.
During PIPE# Operation: These signals are not used during PIPE# operation.
During FRAME# Operation: These signals are not used during AGP FRAME#
operation.
NOTE: When sideband addressing is disabled, these signals are isolated (no
external/internal pull-ups are required).
Section 5 contains two mechanisms to queue requests by the AGP master. Note that the master
can only use one mechanism. The master may not switch methods without a full reset of the
system. When PIPE# is used to queue addresses the master is not allowed to queue addresses
using the SBA bus. For example, during configuration time, if the master indicates that it can use
either mechanism, the configuration software will indicate which mechanism the master will use.
Once this choice has been made, the master will continue to use the mechanism selected until the
master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic
mechanism, but rather a static decision when the device is first being configured after reset.
34 Datasheet
Signal Descriptions
3.3.2 AGP Flow Control Signals

Table 6. AGP Flow Control Signals
GRBF# I Read Buffer Full: Read buffer full indicates if the master is ready to accept previously
AGP requested low priority read data. When RBF# is asserted the GMCH is not allowed to
initiate the return low priority read data. That is, the GMCH can finish returning the data
for the request currently being serviced. RBF# is only sampled at the beginning of a
cycle.
If the AGP master is always ready to accept return read data then it is not required to
implement this signal.
GWBF# I Write-Buffer Full: indicates if the master is ready to accept Fast Write data from the
AGP GMCH. When WBF# is asserted the GMCH is not allowed to drive Fast Write data to
the AGP master. WBF# is only sampled at the beginning of a cycle.
If the AGP master is always ready to accept fast write data then it is not required to
implement this signal.
3.3.3 AGP Status Signals

Table 7. AGP Status Signal Descriptions
GST[2:0] O Status: Provides ST[2:0 Meaning

AGP information from the
arbiter to an AGP 000 Previously requested low priority read data is being
Master on what it may returned to the master
do. ST[2:0] only have 001 Previously requested high priority read data is being
meaning to the master returned to the master
when its GNT# is
asserted. When GNT# 010 The master is to provide low priority write data for a
is deasserted these previously queued write command
signals have no
011 The master is to provide high priority write data for a
meaning and must be
previously queued write command.
ignored.
100 Reserved
101 Reserved
110 Reserved
110 The master has been given permission to start a bus

transaction. The master may queue AGP requests by
asserting PIPE# or start a PCI transaction by
asserting FRAME#.
Datasheet 35
Signal Descriptions
3.3.4 AGP Strobes

Table 8. AGP Strobe Descriptions
GADSTB[0] I/O Address/Data Bus Strobe-0: provides timing for 2X and 4X data on AD[15:0] and
AGP C/BE[1:0]# signals. The agent that is providing the data will drive this signal.
GADSTB#[0] I/O Address/Data Bus Strobe-0 Complement: With AD STB0, forms a differential strobe
AGP pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals. The
agent that is providing the data will drive this signal.
GADSTB[1] I/O Address/Data Bus Strobe-1: Provides timing for 2X and 4X data on AD[31:16] and
AGP C/BE[3:2]# signals. The agent that is providing the data will drive this signal.
GADSTB#[1] I/O Address/Data Bus Strobe-1 Complement: With AD STB1, forms a differential strobe
AGP pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals in 4X
mode. The agent that is providing the data will drive this signal.
GSBSTB I Sideband Strobe: Provides timing for 2X and 4X data on the SBA[7:0] bus. It is
AGP driven by the AGP master after the system has been configured for 2X or 4X sideband
address mode.
GSBSTB# I Sideband Strobe Complement: The differential complement to the SB_STB signal. It
AGP is used to provide timing 4X mode.
3.3.5 AGP/PCI Signals-Semantics

For transactions on the AGP interface carried using AGP FRAME# protocol these signals operate
similarly to their semantics in the PCI 2.1 specification, as defined below.
Table 9. AGP/PCI Signals-Semantics Descriptions
GFRAME# I/O G_FRAME: Frame.

AGP
During PIPE# and SBA Operation: Not used by AGP SBA and PIPE# operations.
During Fast Write Operation: Used to frame transactions as an output during Fast
Writes.
During FRAME# Operation: G_FRAME# is an output when the GMCH acts as an

initiator on the AGP Interface. G_FRAME# is asserted by the GMCH to indicate the
beginning and duration of an access. G_FRAME# is an input when the GMCH acts as
a FRAME#-based AGP target. As a FRAME#-based AGP target, the GMCH latches
the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which GMCH
samples FRAME# active.
36 Datasheet
Signal Descriptions
GIRDY# I/O G_IRDY#: Initiator Ready.

AGP
During PIPE# and SBA Operation: Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
During FRAME# Operation: G_IRDY# is an output when GMCH acts as a FRAME#-

based AGP initiator and an input when the GMCH acts as a FRAME#-based AGP
target. The assertion of G_IRDY# indicates the current FRAME#-based AGP bus
initiator's ability to complete the current data phase of the transaction.
During Fast Write Operation: In Fast Write mode, G_IRDY# indicates that the AGP-
compliant master is ready to provide all write data for the current transaction. Once
G_IRDY# is asserted for a write operation, the master is not allowed to insert wait
states. The master is never allowed to insert a wait state during the initial data transfer
(32 bytes) of a write transaction. However, it may insert wait states after each 32-byte
block is transferred.
GTRDY# I/O G_TRDY#: Target Ready.

AGP
During PIPE# and SBA Operation: Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
During FRAME# Operation: G_TRDY# is an input when the GMCH acts as an AGP
initiator and is an output when the GMCH acts as a FRAME#-based AGP target. The
assertion of G_TRDY# indicates the target’s ability to complete the current data phase
of the transaction.
During Fast Write Operation: In Fast Write mode, G_TRDY# indicates the AGP-
compliant target is ready to receive write data for the entire transaction (when the
transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes.
The target is allowed to insert wait states after each block (32 bytes) is transferred on
write transactions.
GSTOP# I/O G_STOP#: Stop.

AGP
During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA
operation.
During FRAME# Operation: G_STOP# is an input when the GMCH acts as a

FRAME#-based AGP initiator and is an output when the GMCH acts as a FRAME#-
based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on
the AGP interface.
GDEVSEL# I/O G_ DEVSEL#: Device Select.

AGP
During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA
operation.
During FRAME# Operation: G_DEVSEL#, when asserted, indicates that a FRAME#-

based AGP target device has decoded its address as the target of the current access.
The GMCH asserts G_DEVSEL# based on the DDR SDRAM address range being
accessed by a PCI initiator. As an input, G_DEVSEL# indicates whether the AGP
master has recognized a PCI cycle to it.
GREQ# I G_REQ#: Request.

AGP
During SBA Operation: This signal is not used during SBA operation.
During PIPE# and FRAME# Operation: G_REQ#, when asserted, indicates that the
AGP master is requesting use of the AGP interface to run a FRAME#- or PIPE#-based
operation.
Datasheet 37
Signal Descriptions
GGNT# O G_GNT#: Grant.

AGP
During SBA, PIPE# and FRAME# Operation: G_GNT#, along with the information on
the ST[2:0] signals (status bus), indicates how the AGP interface will be used next.
Refer to the AGP Interface Specification, Revision 2.0 for further explanation of the
ST[2:0] values and their meanings.
GAD[31:0] I/O G_AD[31:0]: Address/Data Bus.

AGP
During PIPE# and FRAME# Operation: The G_AD[31:0] signals are used to transfer
both address and data information on the AGP interface.
During SBA Operation: The G_AD[31:0] signals are used to transfer data on the AGP
interface.
GCBE#[3:0] I/O Command/Byte Enable.

AGP
During FRAME# Operation: During the address phase of a transaction, the
G_CBE[3:0]# signals define the bus command. During the data phase, the
G_CBE[3:0]# signals are used as byte enables. The byte enables determine which
byte lanes carry meaningful data. The commands issued on the G_CBE# signals
during FRAME#-based AGP transactions are the same G_CBE# command described
in the PCI 2.2 specification.
During PIPE# Operation: When an address is enqueued using PIPE#, the C/BE#
signals carry command information. The command encoding used during PIPE#-based
AGP is different than the command encoding used during FRAME#-based AGP cycles
(or standard PCI cycles on a PCI bus).
During SBA Operation: These signals are not used during SBA operation.
GPAR I/O Parity.

AGP
During FRAME# Operation: G_PAR is driven by the GMCH when it acts as a
FRAME#-based AGP initiator during address and data phases for a write cycle, and
during the address phase for a read cycle. G_PAR is driven by the GMCH when it acts
as a FRAME#-based AGP target during each data phase of a FRAME#-based AGP
memory read cycle. Even parity is generated across G_AD[31:0] and G_CBE[3:0]#.
During SBA and PIPE# Operation: This signal is not used during SBA and PIPE#
operation.
PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP
interface logic within the GMCH. The AGP agent will also typically use PCIRST# provided by
the ICH4-M as an input to reset its internal logic.
38 Datasheet
Signal Descriptions
3.4 Hub Interface Signals

Table 10. Hub Interface Signals
HL[10:0] I/O Packet Data: Data signals used for HI read and write operations.
Hub
HLSTB I/O Packet Strobe: One of two differential strobe signals used to transmit or receive
packet data over HI.
Hub
HLSTB# I/O Packet Strobe Complement: One of two differential strobe signals used to transmit or
receive packet data over HI.
Hub
3.5 Clocks
Table 11. Clock Signals
Host Processor Clocking
BCLK I Differential Host Clock In: These pins receive a buffered host clock from the
external clock synthesizer. This clock is used by all of the GMCH logic that are in
BCLK# CMOS
the Host clock domain (Host, Hub and system memory). The clock is also the
reference clock for the graphics core PLL. This is a low voltage differential input.
System Memory Clocking
SCK[5:0] O Differential DDR SDRAM Clock: SCK and SCK# pairs are differential clock
outputs. The crossing of the positive edge of SCK and the negative edge of SCK# is
SSTL_2
used to sample the address and control signals on the DDR SDRAM. There are 3
pairs to each SO-DIMM.
NOTE: ECC error detection is supported by the SCK[2] and SCK[5] signals.
SCK[5:0]# O Complementary Differential DDR SDRAM Clock: These are the complimentary
differential DDR SDRAM clock signals.
SSTL_2
NOTE: ECC error detection is supported by the SCK[2]# and SCK[5]# signals.
DVO/Hub Input Clocking
GCLKIN I Input Clock: 66 MHz, 3.3 V input clock from external buffer DVO/Hub interface.
CMOS
DVO Clocking
DVOBCLK O Differential DVO Clock Output: These pins provide a differential pair reference
DVOBCLK# clock that can run up to 165 MHz.
DVO
DVOBCLK corresponds to the primary clock out.
DVOBCLK# corresponds to the primary complementary clock out.
DVOBCLK and DVOBCLK# should be left as NC (“Not Connected”) if the DVO B

port is not implemented.
Datasheet 39
Signal Descriptions
DVOCCLK O Differential DVO Clock Output: These pins provide a differential pair reference
DVOCCLK# clock that can run up to 165 MHz.
DVO
DVOCCLK corresponds to the primary clock out.
DVOCCLK# corresponds to the primary complementary clock out.
DVOCCLK and DVOCCLK# should be left as NC (“Not Connected”) if the DVO C

port is not implemented.
DVOBCCLKINT I DVOBC Pixel Clock Input/Interrupt: This signal may be selected as the reference
input to either dot clock PLL (DPLL) or may be configured as an interrupt input. A
DVO
TV-out device can provide the clock reference. The maximum input frequency for
this signal is 85 MHz.
DVOBC Pixel Clock Input: When selected as the dot clock PLL (DPLL) reference
input, this clock reference input supports SSC clocking for DVO LVDS devices.
DVOBC Interrupt: When configured as an interrupt input, this interrupt can support
either DVOB or DVOC.
DVOBCCLKINT needs to be pulled down if the signal is NOT used.
DPMS I Display Power Management Signaling: This signal is used only in mobile systems
to act as the DREFCLK in certain power management states(i.e. Display Power
DVO
Down Mode); DPMS Clock is used to refresh video during S1-M. Clock Chip is
powered down in S1-M. DPMS should come from a clock source that runs during
S1-M and needs to be 1.5 V. So, an example would be to use a 1.5 V version of
SUSCLK from ICH4-M.
DAC Clocking
DREFCLK I Display Clock Input: This pin is used to provide a 48 MHz input clock to the
Display PLL that is used for 2D/Video and DAC.
LVTTL
LVDS LCD Flat Panel Clocking
DREFSSCLK I Display SSC Clock Input: This pin provides a 48 MHz or 66 MHz input clock (SSC
or non-SSC) to the Display PLL B.
LVTTL
40 Datasheet
Signal Descriptions
3.6 Internal Graphics Display Signals

The IGD has support for a dedicated LVDS LCD Flat Panel Interface, DVOB/C interfaces, and an
Analog CRT port.
3.6.1 Dedicated LVDS LCD Flat Panel Interface

Table 12. Dedicated LVDS LCD Flat Panel Interface Signal Descriptions
Name Type Voltage Description
ICLKAP O 1.25 V ±225 mV Channel A differential clock pair output (true): 245–800 MHz
LVDS
ICLKAM O 1.25 V ±225 mV Channel A differential clock pair output (compliment): 245–
800 MHz.
LVDS
IYAP[3:0] O 1.25 V ±225 mV Channel A differential data pair 3:0 output (true): 245–800 MHz.
LVDS
IYAM[3:0] O 1.25 V ±225 mV Channel A differential data pair 3:0 output (compliment): 245–
800 MHz.
LVDS
ICLKBP O 1.25 V ±225 mV Channel B differential clock pair output (true): 245–800 MHz.
LVDS
ICLKBM O 1.25 V ±225 mV Channel B differential clock pair output (compliment): 245–
800 MHz.
LVDS
IYBP[3:0] O 1.25 V ±225 mV Channel B differential data pair 3:0 output (true): 245–800 MHz.
LVDS
IYBM[3:0] O 1.25 V ± 225 mV Channel B differential data pair 3:0 output (compliment): 245–
800 MHz.
LVDS
Datasheet 41
Signal Descriptions
3.6.2 Digital Video Output B (DVOB) Port

Table 13. Digital Video Output B (DVOB) Port Signal Descriptions
Name Type Description
DVOBD[11:0] O DVOB Data: This data bus is used to drive 12-bit RGB data on each edge of the
differential clock signals, DVOBCLK and DVOBCLK#. This provides 24-bits of data per
DVO
clock period. In dual channel mode, this provides the lower 12-bits of pixel data.
DVOBD[11:0] should be left as left as NC (“Not Connected”) if not used.
DVOBHSYNC O Horizontal Sync: HSYNC signal for the DVOB interface.
DVO DVOBHSYNC should be left as left as NC (“Not Connected”) if not used.
DVOBVSYNC O Vertical Sync: VSYNC signal for the DVOB interface.
DVO DVOBVSYNC should be left as left as NC (“Not Connected”) if the signal is NOT used
when using internal graphics device.
DVOBBLANK# O Flicker Blank or Border Period Indication: DVOBBLANK# is a programmable output

pin driven by the GMCH.
DVO
When programmed as a blank period indication, this pin indicates active pixels excluding
the border. When programmed as a border period indication, this pin indicates active pixel
including the border pixels.
DVOBBLANK# should be left as left as NC (“Not Connected”) if not used.
DVOBFLDSTL I TV Field and Flat Panel Stall Signal. This input can be programmed to be either a TV
Field input from the TV encoder or Stall input from the flat panel.
DVO
DVOB TV Field Signal: When used as a Field input, it synchronizes the overlay field with
the TV encoder field when the overlay is displaying an interleaved source.
DVOB Flat Panel Stall Signal: When used as the Stall input, it indicates that the pixel
pipeline should stall one horizontal line. The signal changes during horizontal blanking.
The panel fitting logic, when expanding the image vertically, uses this.
DVOBFLDSTL needs to be pulled down if not used.
3.6.3 Intel® 855GME GMCH DVO/I2C to AGP Pin Mapping

The GMCH will mux a DVODETECT signal with the GPAR signal on the AGP bus. This signal
will act as a strap and indicate whether the interface is in AGP or DVO mode. The GMCH has an
internal 8.2-k pull-up on this signal that will naturally pull it high. If an AGP graphics device is
present, the signal will be pulled low at the AGP graphics device and the AGP/DVO mux select
bit in the SHIC register will be set to AGP mode. Boards that do not use an AGP graphics device
should have a pull-down resistor on DVODETECT if they have digital display devices connected
to the AGP/DVO interface. SBA[7:0] will act as straps for an ADDID. When an AGP graphics
device is present, DVODETECT=1 (AGP mode),
42 Datasheet
Signal Descriptions
Table 14. Intel® 855GME GMCH AGP/DVO Pin Muxing
DVO MODE AGP MODE DVO MODE AGP MODE DVO MODE AGP MODE
DVOBD[0] GAD[3] DVOCD[0] GAD[19] MI2CCLK GIRDY#
DVOBD[1] GAD[2] DVOCD[1] GAD[20] MI2CDATA GDEVSEL#
DVOBD[2] GAD[5] DVOCD[2] GAD[21] MDVICLK GTRDY#
DVOBD[3] GAD[4] DVOCD[3] GAD[22] MDVIDATA GFRAME#
DVOBD[4] GAD[7] DVOCD[4] GAD[23] MDDCCDATA GAD[15]
DVOBD[5] GAD[6] DVOCD[5] GCBE#[3] MDDCCLK GSTOP#
DVOBD[6] GAD[8] DVOCD[6] GAD[25] DVOBCINT# GAD[30]
DVOBD[7] GCBE#[0] DVOCD[7] GAD[24] DVOBCCLKINT GAD[13]
DVOBD[8] GAD[10] DVOCD[8] GAD[27] ADDID[7] GSBA[7]
DVOBCLK GADSTB[0] DVOCCLK GADSTB[1] ADDID[3] GSBA[3]
DVOBCLK# GADSTB#[0] DVOCCLK# GADSTB#[1] ADDID[2] GSBA[2]
DVOBHSYNC GAD[0] DVOCHSYNC GAD[17] ADDID[1] GSBA[1]
DVOBVSYNC GAD[1] DVOCVSYNC GAD[16] ADDID[0] GSBA[0]
DVOBBLANK# GCBE#[1] DVOCBLANK# GAD[18] DVODETECT GPAR
DVOBFLDSTL GAD[14] DVOCFLDSTL GAD[31] DPMS GPIPE#
Datasheet 43
Signal Descriptions
3.6.4 Digital Video Output C (DVOC) Port

Table 15. Digital Video Output C (DVOC) Port Signal Descriptions
DVOCD[11:0] O DVOC Data: This data bus is used to drive 12-bit RGB data on each edge of the
differential clock signals, DVOCCLK and DVOCCLK#. This provides 24-bits of data per
DVO
clock period. In dual channel mode, this provides the upper 12-bits of pixel data.
DVOCD[11:0] should be left as left as NC (“Not Connected”) if not used.
DVOCHSYNC O Horizontal Sync: HSYNC signal for the DVOC interface.
DVO DVOCHSYNC should be left as left as NC (“Not Connected”) if not used.
DVOCVSYNC O Vertical Sync: VSYNC signal for the DVOC interface.
DVO DVOCVSYNC should be left as left as NC (“Not Connected”) if the signal is NOT used
when using internal graphics device.
DVOCBLANK# O Flicker Blank or Border Period Indication: DVOCBLANK# is a programmable output

pin driven by the GMCH.
DVO
When programmed as a blank period indication, this pin indicates active pixels excluding
the border. When programmed as a border period indication, this pin indicates active pixel
including the border pixels.
DVOCBLANK# should be left as left as NC (“Not Connected”) if not used.
DVOCFLDSTL I TV Field and Flat Panel Stall Signal. This input can be programmed to be either a TV
Field input from the TV encoder or Stall input from the flat panel.
DVO
DVOC TV Field Signal: When used as a Field input, it synchronizes the overlay field with
the TV encoder field when the overlay is displaying an interleaved source.
DVOC Flat Panel Stall Signal: When used as the Stall input, it indicates that the pixel
pipeline should stall one horizontal line. The signal changes during horizontal blanking.
The panel fitting logic, when expanding the image vertically, uses this.
DVOCFLDSTL needs to be pulled down if not used.
Table 16. DVOB and DVOC Port Common Signal Descriptions
DVOBCINTR# I DVOBC Interrupt: This pin is used to signal an interrupt, typically used to indicate a hot
plug or unplug of a digital display.
DVO
ADDID[7:0] I ADDID[7:0]: These pins are used to communicate to the Video BIOS when an external
device is interfaced to the DVO port.
DVO
Note: Bit[7] needs to be strapped low when an on-board DVO device is present. The other
pins should be left as NC.
DVODETECT I DVODETECT: This strapping signal indicates to the GMCH whether a DVO device is
present or not. When a DVO device is connected, then DVODETECT = 0.
DVO
44 Datasheet
Signal Descriptions
3.6.5 Analog CRT Display

Table 17. Analog CRT Display Signal Descriptions
Pin Name Type Description
VSYNC O CRT Vertical Synchronization: This signal is used as the vertical sync signal.
CMOS
HSYNC O CRT Horizontal Synchronization: This signal is used as the horizontal sync signal.
CMOS
RED O Red (Analog Video Output): This signal is a CRT Analog video output from the internal
color palette DAC. The DAC is designed for a 37.5 Ω equivalent load on each pin (e.g.,
Analog
75 Ω resistor on the board, in parallel with the 75 Ω CRT load).
RED# O Red# (Analog Output): Tied to ground.
Analog
GREEN O Green (Analog Video Output): This signal is a CRT analog video output from the internal
Analog
GREEN# O Green# (Analog Output): Tied to ground.
Analog
BLUE O Blue (Analog Video Output): This signal is a CRT Analog video output from the internal
Analog
BLUE# O Blue# (Analog Output): Tied to ground.
Analog
Datasheet 45
Signal Descriptions
3.6.6 General Purpose Input/Output Signals

Table 18. GPIO Signal Descriptions
GPIO I/F Total Type Comments
RSTIN# I Reset: Primary Reset, Connected to PCIRST# of ICH4-M.
CMOS
PWROK I Power OK: Indicates that power to GMCH is stable.
CMOS
AGPBUSY# O AGPBUSY: Output of the GMCH IGD to the ICH4-M, which indicates that certain graphics
activity is taking place. It will indicate to the ACPI software not to enter the C3 state. It will also
CMOS
cause a C3/C4 exit if C3/C4 was being entered, or was already entered when AGPBUSY# went
active. Not active when the IGD is in any ACPI state other than D0.
EXTTS_0 I External Thermal Sensor Input: This signal is an active low input to the GMCH and is used to
monitor the thermal condition around the system memory and is used for triggering a read
CMOS
throttle. The GMCH can be optionally programmed to send a SERR, SCI, or SMI message to
the ICH4-M upon the triggering of this signal.
LCLKCTLA O SSC Chip Clock Control: Can be used to control an external clock chip with SSC control.
CMOS
LCLKCTLB O SSC Chip Data Control: Can be used to control an external clock chip for SSC control.
CMOS
PANELVDDEN O LVDS LCD Flat Panel Power Control: This signal is used enable power to the panel interface.
CMOS
PANELBKLTEN O LVDS LCD Flat Panel Backlight Enable: This signal is used to enable the backlight inverter
(BLI).
CMOS
PANELBKLTCTL O LVDS LCD Flat Panel Backlight Brightness Control: This signal is used as the Pulse Width
Modulated (PWM) control signal to control the backlight inverter.
CMOS
DDCACLK I/O CRT DDC Clock: This signal is used as the DDC clock signal between the CRT monitor and
the GMCH.
CMOS
DDCADATA I/O CRT DDC Data: This signal is used as the DDC data signal between the CRT monitor and the
GMCH.
CMOS
DDCPCLK I/O Panel DDC Clock: This signal is used as the DDC clock signal between the LFP and the
GMCH.
CMOS
DDCPDATA I/O Panel DDC Data: This signal is used as the DDC data signal between the LFP and the GMCH.
CMOS
MI2CCLK I/O DVO I2C Clock: This signal is used as the I2C_CLK for a digital display (i.e. TV-Out Encoder,
TMDS transmitter). This signal is tri-stated during a hard reset.
DVO
MI2CDATA I/O DVO I2C Data: This signal is used as the I2C_DATA for a digital display (i.e. TV-Out Encoder,
TMDS transmitter). This signal is tri-stated during a hard reset.
DVO
46 Datasheet
Signal Descriptions
GPIO I/F Total Type Comments
MDVICLK I/O DVI DDC Clock: This signal is used as the DDC clock for a digital display connector (i.e.
primary digital monitor). This signal is tri-stated during a hard reset.
DVO
MDVIDATA I/O DVI DDC Data: The signal is used as the DDC data for a digital display connector (i.e. primary
digital monitor). This signal is tri-stated during a hard reset.
DVO
MDDCDATA I/O DVI DDC Clock: The signal is used as the DDC data for a digital display connector (i.e.
secondary digital monitor). This signal is tri-stated during a hard reset.
DVO
MDDCCLK I/O DVI DDC Data: The signal is used as the DDC clock for a digital display connector (i.e.
secondary digital monitor). This signal is tri-stated during a hard reset.
DVO
Datasheet 47
Signal Descriptions
3.7 Voltage References, PLL Power

Table 19. Voltage References, PLL Power
Host Processor
HXRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers.
HYRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers.
HXSWING Analog Host Voltage Swing (RCOMP reference voltage): These signals provide a reference
voltage used by the FSB RCOMP circuit.
HYSWING Analog Host Voltage Swing (RCOMP reference voltage): These signals provide a reference
voltage used by the FSB RCOMP circuit.
HDVREF[2:0] Ref Analog Host Data (input buffer) VREF: Reference voltage input for the data signals of the
Host AGTL+ Interface. Input buffer differential amplifier to determine a high versus low
input voltage.
HAVREF Ref Analog Host Address (input buffer) VREF: Reference voltage input for the address signals
of the Host AGTL+ Interface. This signal is connected to the input buffer differential
amplifier to determine a high versus low input voltage.
HCCVREF Ref Analog Host Common Clock (Command input buffer) VREF: Reference voltage input for
the common clock signals of the Host AGTL+ Interface. This signal is connected to the
input buffer differential amplifier to determine a high versus low input voltage.
VTTLF Power FSB Power Supply: VTTLF is the low frequency connection from the board. This
signal is the primary connection of power for GMCH.
VTTHF Power FSB Power Supply: VTTHF is the high frequency supply. It is for direct connection
from an internal package plane to a capacitor placed immediately adjacent to the
GMCH.
NOTE: Not to be connected to power rail.
System Memory
SMRCOMP Analog System Memory RCOMP: This signal is used to calibrate the memory I/O buffers.
SMVREF_0 Ref Analog Memory Reference Voltage (Input buffer VREF):Reference voltage input for Memory
Interface.
Input buffer differential amplifier to determine a high versus low input voltage.
SMVSWINGH Ref Analog RCOMP reference voltage: This is connected to the RCOMP buffer differential
amplifier and is used to calibrate the I/O buffers.
SMVSWINGL Ref Analog RCOMP reference voltage: This is connected to the RCOMP buffer differential
amplifier and is used to calibrate the I/O buffers.
VCCSM Power Power supply for Memory I/O.
VCCQSM Power Power supply for system memory clock buffers.
VCCASM Power Power supply for system memory logic running at the core voltage (isolated supply, not
connected to the core).
Hub Interface
HLRCOMP Analog Hub Interface RCOMP: This signal is connected to a reference resistor in order to
calibrate the buffers.
48 Datasheet
Signal Descriptions
PSWING Analog RCOMP reference voltage: This is connected to the RCOMP buffer differential
amplifier and is used to calibrate the buffers.
HLVREF Ref Input buffer VREF: Input buffer differential amplifier to determine a high versus low
input voltage.
Analog
VCCHL Power Power supply for Hub interface buffers
DVO
DVORCOMP Analog Compensation for DVO: This signal is used to calibrate the DVO I/O buffers.
Analog
GVREF Ref Analog Input buffer VREF: Input buffer differential amplifier to determine a high versus low
input voltage.
VCCDVO Power Power supply for DVO.
GPIO
VCCGPIO Power Power supply for GPIO buffers
DAC
REFSET Ref Resistor Set: Set point resistor for the internal color palette DAC.
Analog
VCCADAC Power Power supply for the DAC
VSSADAC Power Ground supply for the DAC
LVDS
LIBG Analog LVDS reference current: signal connected to reference resistor.
VCCDLVDS Power Digital power supply.
VCCTXLVDS Power Data/Clk Tx power supply.
VCCALVDS Power Analog power supply.
VSSALVDS Power Ground supply for LVDS.
Clocks
VCCAHPLL Power Power supply for the Host PLL.
VCCAGPLL Power Power supply for the Hub/DVO PLL.
VCCADPLLA Power Power supply for the display PLL A.
VCCADPLLB Power Power supply for the display PLL B.
Core
VCC Power Power supply for the core.
VSS Power Ground supply for the chip.
Datasheet 49
Signal Descriptions
50 Datasheet
Register Description
4 Register Description
4.1 Conceptual Overview of the Platform Configuration

Structure
The Intel 855GM GMCH and ICH4-M are physically connected by Hub interface. From a
configuration standpoint, the Hub interface is logically PCI bus #0. As a result, all devices
internal to the GMCH and ICH4-M appear to be on PCI bus #0. The system’s primary PCI
expansion bus is physically attached to the ICH4-M and from a configuration perspective, appears
to be a hierarchical PCI bus behind a PCI-to-PCI bridge and therefore has a programmable PCI
Bus number. Note that the primary PCI bus is referred to as PCI_A in this document and is not
PCI bus #0 from a configuration standpoint. For the Intel 855GME GMCH, the AGP appears to
system software to be real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus #0.
The GMCH contains two PCI devices within a single physical component. The configuration
registers for the two devices are mapped as devices residing on PCI bus #0.
Device #0: Host-Hub Interface Bridge/DDR SDRAM Controller. Logically this appears as a PCI
device residing on PCI bus #0. Physically, Device #0 contains the standard PCI registers, DDR
SDRAM registers, the Graphics Aperture Controller registers, HI Control registers and other
GMCH specific registers. Device #0 is divided into the following functions:
Function #0: Host Bridge Legacy registers including Graphics Aperture Control registers, HI
Configuration registers and Interrupt Control registers
Function #1: DDR SDRAM Interface Registers
Function #3: Intel Configuration Process Registers
Device #2: Integrated Graphics Controller. Logically this appears as a PCI device residing on PCI
bus #0. Physically Device #2 contains the Configuration registers for 2D, 3D, and display
functions.
Table 20 shows the Device # assignment for the various internal GMCH devices.
Table 20. Device Number Assignment
GMCH Function Bus #0, Device#
Host-Hub interface, DDR SDRAM I/F, Legacy control Device #0
Host-to-AGP Bridge (Virtual PCI-to-PCI) Device #1 (Intel 855GME GMCH Only)
Integrated Graphics Controller (IGD) Device #2
Datasheet 51
4.2 Nomenclature for Access Attributes

Table 21 provides the nomenclature for the access attributes.
Table 21. Nomenclature for Access Attributes

RO Read Only. If a register is Read Only, Writes to this register have no effect.
R/W Read/Write. A register with this attribute can be Read and Written.
R/W/L Read/Write/Lock. A register with this attribute can be Read, Written, and Locked.
R/WC Read/Write Clear. A register bit with this attribute can be Read and Written.
However, a Write of a 1 clears (sets to 0) the corresponding bit and a Write of a 0
has no effect.
R/WO Read/Write Once. A register bit with this attribute can be Written to only once after
power up. After the first Write, this bit becomes Read Only.
L Lock. A register bit with this attribute becomes Read Only after a Lock bit is set.
Reserved Bits Some of the GMCH registers described in this section contain Reserved bits. These
bits are labeled "Reserved”. Software must deal correctly with fields that are
Reserved. On Reads, software must use appropriate masks to extract the defined
bits and not rely on Reserved bits being of any particular value. On Writes, software
must ensure that the values of Reserved bit positions are preserved. That is, the
values of Reserved bit positions must first be Read, Merged with the new values for
other bit positions and then Written back. Note the software does not need to
perform Read, Merge, and Write operations for the Configuration Address register.
Reserved Registers In addition to Reserved bits within a register, the GMCH contains address locations
in the configuration space of the Host-Hub Interface Bridge entity that are marked
either "Reserved" or “Intel Reserved”. The GMCH responds to accesses to
“Reserved” address locations by completing the Host cycle. When a “Reserved”
register location is Read, in certain cases, a zero value can be returned (“Reserved”
registers can be 8-bit, 16-bit, or 32-bit in size) or a non-zero value can be returned.
In certain cases, Writes to “Reserved” registers may have no effect on the GMCH or
may cause system failure. Registers that are marked as “Intel Reserved” must not
be modified by system software.
Default Value upon Upon Reset, the GMCH sets all of its internal configuration registers to
a Reset predetermined default states. Some register values at Reset are determined by
external strapping options. The default state represents the minimum functionality
feature set required to successfully bring up the system. Hence, it does not
represent the optimal system configuration. It is the responsibility of the system
initialization software (usually BIOS) to properly determine the DDR SDRAM
configurations, operating parameters and optional system features that are
applicable, and to program the GMCH registers accordingly.
S SW Semaphore.
A physical PCI Bus #0 does not exist. The Hub interface and the internal devices in the GMCH
and ICH4-M logically constitute PCI Bus #0 to configuration software
52 Datasheet
4.3 Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based “configuration space” that allows each device to contain up to
eight functions with each function containing up to 256, 8-bit configuration registers. The PCI
Specification defines two bus cycles to access the PCI Configuration Space: Configuration Read
and Configuration Write. Memory and I/O spaces are supported directly by the CPU.
Configuration Space is supported by a mapping mechanism implemented within the GMCH. The
PCI 2.2 specification defines two mechanisms to access Configuration Space: Mechanism #1 and
Mechanism #2. The GMCH supports only Mechanism #1.
The Configuration Access Mechanism makes use of the CONFIG_ADDRESS register (at I/O
address 0CF8h though 0CFBh) and CONFIG_DATA register (at I/O address 0CFCh though
0CFFh). To reference a Configuration register a Dword I/O Write cycle is used to place a value
into CONFIG_ADDRESS that specifies the PCI Bus, the device on that bus, the function within
the device, and a specific Configuration register of the device function being accessed.
CONFIG_ADDRESS[31] must be a 1 to enable a Configuration cycle. CONFIG_DATA then
becomes a window into the four Bytes of Configuration Space specified by the contents of
CONFIG_ADDRESS. Any Read or Write to CONFIG_DATA will result in the GMCH
translating the CONFIG_ADDRESS into the appropriate Configuration cycle.
The GMCH is responsible for translating and routing the CPU’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH Configuration registers
and to the Hub interface, or AGP_PCI_B.
4.4 Routing Configuration Accesses

The GMCH supports one bus interface: the Hub interface. PCI Configuration cycles are
selectively routed to this interface. The GMCH is responsible for routing PCI Configuration
cycles to the proper interface. PCI configuration cycles to the ICH4-M internal devices, and
Primary PCI (including downstream devices) are routed to the ICH4-M via the Hub interface.
AGP/PCI_B configuration cycles are routed to AGP. The AGP/PCI_B interface is treated as a
separate PCI bus from the configuration point of view. Routing of configuration AGP/PCI_B is
controlled via the standard PCI-to-PCI bridge mechanism using information contained within the
Primary bus number, the Secondary bus number, and the Subordinate bus number registers of the
corresponding PCI-to-PCI bridge device.
4.4.1 PCI Bus #0 Configuration Mechanism

The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, then the
Configuration cycle is targeting a PCI Bus #0 device.
The Host-Hub Interface Bridge entity within the GMCH is hardwired as Device #0 on PCI Bus
#0.
Configuration cycles to any of the GMCH’s internal devices are confined to the GMCH and not
sent over Hub interface. Accesses to disabled GMCH internal devices will be forwarded over the
Hub interface as Type 0 Configuration cycles.
Datasheet 53
4.4.2 Primary PCI and Downstream Configuration Mechanism

If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the Host-
AGP/PCI_B device’s Secondary bus number register or greater than the value in the Host-
AGP/PCI_B device’s Subordinate bus number register, the GMCH will generate a Type 1 Hub
interface Configuration Cycle. A[1:0] of the Hub interface request packet for the Type 1
configuration cycle will be “01”. This Hub interface configuration cycle will be sent over Hub
interface.
If the cycle is forwarded to the ICH4-M via Hub interface, the ICH4-M compares the non-zero
Bus Number with the Secondary bus number and Subordinate bus number registers of its PCI-to-
PCI bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH4-
M’s Hub interfaces, or a downstream PCI bus.
4.4.3 AGP/PCI_B Bus Configuration Mechanism

From the chip-set configuration perspective, AGP/PCI_B is seen as PCI bus interfaces residing on
a Secondary Bus side of the “virtual” PCI-to-PCI bridges referred to as the GMCH Host-
PCI_B/AGP bridge. On the Primary bus side, the “virtual” PCI-to-PCI bridge is attached to PCI
Bus #0. Therefore the Primary bus number register is hardwired to “0”. The “virtual” PCI-to-PCI
bridge entity converts Type #1 PCI Bus Configuration cycles on PCI Bus #0 into Type 0 or Type
1 configuration cycles on the AGP/PCI_B interface. Type 1 configuration cycles on PCI Bus #0
that have a Bus number that matches the Secondary bus number of the GMCH ’s “virtual” Host-
to-PCI_B/AGP bridge will be translated into Type 0 configuration cycles on the PCI_B/AGP
interface. The GMCH will decode the Device Number field [15:11] and assert the appropriate
GAD signal as an IDSEL in accordance with the PCI-to-PCI Bridge Type 0 configuration
mechanism.
If the Bus Number is non-zero, greater than the value programmed into the Secondary bus
number register, and less than or equal to the value programmed into the Subordinate bus number
register, the configuration cycle is targeting a PCI bus downstream of the targeted interface. The
GMCH will generate a Type 1 PCI configuration cycle on PCI_B/AGP.
To prepare for mapping of the configuration cycles on AGP/PCI_B, the initialization software
will go through the following sequence:
1. Scan all devices residing on the PCI Bus #0 using Type 0 configuration accesses.
2. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will
configure the secondary bus of the bridge with the appropriate number and scan further down
the hierarchy. This process will include the configuration of the “virtual” PCI-to-PCI bridges
within the GMCH used to map the AGP device’s address spaces in a software specific
manner.
Note: Although initial AGP platform implementations will not support hierarchical buses residing
below AGP, this specification still must define this capability in order to support PCI-66
compatibility. Note also that future implementations of the AGP devices may support hierarchical
PCI or AGP-like buses coming out of the root AGP device.
54 Datasheet
4.5 Register Definitions

The GMCH contains four sets of software accessible registers accessed via the Host CPU I/O
Address Space, and they are as follows:
• Control registers: I/O Mapped into the CPU I/O Space, which control access to PCI
Configuration Space via Configuration Mechanism #1 in the PCI 2.2 specification.
• Internal Configuration registers: residing within the GMCH, they are partitioned into two
logical device register sets (“logical” since they reside within the single physical device). The
first register set is dedicated to Host-HI Bridge functionality (i.e. DDR SDRAM
configuration, other chip-set operating parameters and optional features). The second register
block is for the integrated graphics functions.
• Internal Memory Mapped Configuration registers: reside in the GMCH Device #0.
• Internal Memory Mapped Configuration registers and Legacy VGA registers: reside in
the GMCH Device #2 that controls the Integrated Graphics Controller.
The GMCH internal registers (I/O Mapped and Configuration registers) are accessible by the Host
CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the
exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-byte
numeric fields use “Little Endian Byte Ordering” (i.e., lower addresses contain the least
significant parts of the field).
Reserved Bits
Some of the GMCH registers described in this section contain Reserved bits. These bits are
labeled “Reserved”. Software must deal correctly with fields that are Reserved. On Reads,
software must use appropriate Masks to extract the defined bits and not rely on Reserved bits
being any particular value. On Writes, software must ensure that the values of Reserved bit
positions are preserved. That is, the values of Reserved bit positions must first be Read, Merged
with the new values for other bit positions and then Written back.
Note: The software does not need to perform Read, Merge, and Write operations for the Configuration
Address register.
Default Value upon Reset

Upon a Full Reset, the GMCH sets all of its Internal Configuration registers to a predetermined
default state. Some register values at Reset are determined by external strapping options. The
default state represents the minimum functionality feature set required to successfully bring up the
system. Hence, it does not represent the optimal system configuration. It is the responsibility of
the system initialization software (usually BIOS) to properly determine the DDR SDRAM
configurations, operating parameters, and optional system features that are applicable and to
program the GMCH registers accordingly.
Datasheet 55
4.6 I/O Mapped Registers

The GMCH contains two registers that reside in the CPU I/O Address Space: the Configuration
Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA)
Register. The Configuration Address Register enables/disables the Configuration Space and
determines what portion of Configuration Space is visible through the Configuration Data
window.
4.6.1 CONFIG_ADDRESS – Configuration Address Register

I/O Address: 0CF8h Accessed as a Dword
Default Value: 00000000h
Access: Read/Write
Size: 32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a Dword. A Byte or Word
reference will “pass through” the Configuration Address Register and the Hub interface, onto the
PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device
Number, Function Number, and Register Number for which a subsequent configuration access is
intended.
Figure 3. Configuration Address Register
31 30 24 23 16 15 11 10 8 7 2 1 0 Bit
0 R 0 0 0 0 R Default
Reserved
Register Number
Function Number
Device Number
Bus Number
Reserved
Enable
56 Datasheet
Bit Description
31 Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI Configuration Space are
enabled. If this bit is Reset to 0, accesses to PCI Configuration Space are disabled.
30:24 Reserved
23:16 Bus Number: When the Bus Number is programmed to 00h, the target of the Configuration Cycle is
a Hub interface agent (GMCH, ICH4-M, etc.).
The Configuration Cycle is forwarded to Hub interface if the Bus Number is programmed to 00h
and the GMCH is not the target (the device number is >= 2).
15:11 Device Number: This field selects one agent on the PCI Bus selected by the Bus Number. When
the Bus Number field is 00 the GMCH decodes the Device Number field. The GMCH is always
Device Number 0 for the Host-Hub interface bridge entity. Therefore, when the Bus Number =0 and
the Device Number=0-1 the internal GMCH devices are selected.
For Bus Numbers resulting in Hub interface Configuration cycles, the GMCH propagates the device
number field as A[15:11].
10:8 Function Number: This field is mapped to A[10:8] during Hub interface Configuration cycles. This
allows the configuration registers of a particular function in a multi-function device to be accessed.
The GMCH ignores Configuration cycles to its internal Devices if the function number is not equal
to 0.
7:2 Register Number: This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address register. This field is mapped to A[7:2]
during Hub interface Configuration cycles.
1:0 Reserved
4.6.2 CONFIG_DATA – Configuration Data Register

I/O Address: 0CFCh
Access: Read/Write
Size: 32 bits
CONFIG_DATA is a 32-bit Read/Write window into Configuration Space. The portion of

Configuration Space that is referenced by CONFIG_DATA is determined by the contents of
CONFIG_ADDRESS.
Figure 4. Configuration Data Register
31 0 Bit
0 Default
Configuration Data Window
Datasheet 57
Bit Descriptions
31:0 Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, then any I/O access to
the CONFIG_DATA register will be mapped to Configuration Space using the contents of
CONFIG_ADDRESS.
4.7 VGA I/O Mapped Registers

If Device #2 is enabled, and Function #0 within Device #2 is enabled for VGA, and IO_EN is set
within Function #0 then GMCH claims a set of I/O registers for legacy VGA function. Table 22
lists direct CPU Access registers and Table 23 lists registers that are Index – Data registers that
are used to access Internal VGA registers.
Table 22. VGA I/O Mapped Register List
Name Function Read @ Write @
ST00 VGA Input Status Register 0 3C2h ⎯
ST01 VGA Input Status Register 1 3BAh/3Dah ⎯
FCR VGA Feature Control Register 3CAh 3BAh/3DAh
MSR VGA Miscellaneous Status/Output Register 3CCh 3C2h
Table 23. Index – Data Registers
Name Function Index IO Data IO
SRX Sequencer Registers 3C4 3C5
GRX Graphics Controller Registers 3CE 3CF
ARX Attribute Control Registers 3C0 3C0: Write
3C1: Read
DACMASK Pixel Data Mask Register -- 3C6h
DACSTATE DAC State Register -- 3C7 Read Only
DACRX Palette Read Index Register 3C7 Write Only --
DACWX Palette Write Index Register 3C8 Write Only
DACDATA Palette Data Register 3C9
CRX CRT Registers 3B4/3D4 3B5/3D5
(MDA/CGA) (MDA/CGA)
58 Datasheet
4.8 Intel® 855GM/GME GMCH Host-Hub Interface Bridge

Device Registers (Device #0, Function #0)
Table 24 summarizes the configuration space for Device #0, Function#0.
Table 24. GMCH Configuration Space - Device #0, Function#0
Register Name Register Register Register Default Value Access

Symbol Start End
Vendor Identification VID 00 01 8086h RO
Device Identification DID 02 03 3580h RO
PCI Command PCICMD 04 05 0006h RO,R/W
PCI Status PCISTS 06 07 0090h RO,R/WC
Revision Identification RID 08 08 02h RO
Sub-Class Code SUBC 0A 0A 00h RO
Base Class Code BCC 0B 0B 06h RO
Header Type HDR 0E 0E 80h RO
Subsystem Vendor Identification SVID 2C 2D 0000h R/WO
Subsystem Identification SID 2E 2F 0000h R/WO
Capabilities Pointer CAPPTR 34 34 40h RO
Capability Identification CAPID 40 44 84_A105_0009h RO
GMCH Misc. Control GMC 50 51 0000h R/W
GMCH Graphics Control GGC 52 53 0030h R/W
Device and Function Control DAFC 54 55 0000h R/W
Fixed Dram Hole Control FDHC 58 58 00h R/W
Programmable Attribute Map PAM (6:0) 59 5F 00h Each R/W
System Management RAM SMRAM 60 60 02h R/W/L

Control
Extended System Management ESMRAMC 61 61 38h R/W/L

RAM Control
Error Status ERRSTS 62 63 0000h R/WC
Error Command ERRCMD 64 65 0000h R/W
SMI Command SMICMD 66 66 00h R/W
SCI Command SCICMD 67 67 00h R/W
Secondary Host Interface Control SHIC 74 77 00006010h RO, R/W

Register
AGP Capability Identifier ACAPID A0 A3 00200002h RO
AGP Status Register AGPSTAT A4 A7 1F000217h RO
Datasheet 59

Symbol Start End
AGP Command AGPCMD A8 AB 0000 0000h RO, R/W
AGP Control AGPCTRL B0 B1 0000h RO, R/W
AGP Functional Test AFT B2 B3 E9F0h R/W, R/WC
Aperture Translation Table Base ATTBASE B8 BB 00000000h RO, R/W
AGP Interface Multi Transaction AMTT BC BC 00h R/W

Timer
Low Priority Transaction Timer LPTT BD BD 00h R/W
Host Error Control/Status/Obs HEM F0 F3 00000000h RO, R/W
4.8.1 VID – Vendor Identification Register

Address Offset: 00-01h
Access: Read Only
Size: 16 bits
The VID Register contains the vendor identification number. This 16-bit register, combined with
the Device Identification Register, uniquely identifies any PCI device. Writes to this register have
no effect.
Bit Description
15:0 Vendor Identification (VID): This register field contains the PCI standard identification for Intel.
4.8.2 DID – Device Identification Register

Access: Read Only
Size: 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI
device. Writes to this register have no effect.
Bit Description
15:0 Device Identification Number (DID): This is a 16-bit value assigned to the GMCH Host-Hub interface
bridge, Device #0.
60 Datasheet
4.8.3 PCICMD – PCI Command Register

Access: Read Only, Read/Write
Size: 16 bits
Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not
implemented.
Bit Descriptions
15:10 Reserved
9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-
back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0. Writes
to this bit position have no affect.
8 SERR Enable (SERRE): This bit is a global enable bit for Device #0 SERR messaging. The GMCH
does not have an SERR# signal, but communicates the SERR# condition by sending an SERR
message to the ICH4-M.
1 = Enable. GMCH is enabled to generate SERR messages over Hub interface for specific Device #0
error conditions that are individually enabled in the ERRCMD register. The error status is reported in the
ERRSTS and PCISTS registers.
0= SERR message is not generated by the GMCH for Device #0.
NOTE: This bit only controls SERR messaging for the Device #0. Device #1 has its own SERRE bit to
control error reporting for error conditions occurring on Device #1. The two control bits are used in a
logical OR manner to enable the SERR Hub interface message mechanism.
7 Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the GMCH,
and this bit is hardwired to 0. Writes to this bit position have no effect.
6 Parity Error Enable (PERRE): PERR# is not implemented by GMCH and this bit is hardwired to 0.
Writes to this bit position have no effect.
5 VGA Palette Snoop Enable (VGASNOOP): The GMCH does not implement this bit and it is hardwired
to a 0. Writes to this bit position have no effect.
4 Memory Write and Invalidate Enable (MWIE): The GMCH will never issue memory write and
invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect.
3 Special Cycle Enable (SCE): The GMCH does not implement this bit and it is hardwired to a 0. Writes
to this bit position have no effect.
2 Bus Master Enable (BME): The GMCH is always enabled as a master on HI. This bit is hardwired to a
1. Writes to this bit position have no effect.
1 Memory Access Enable (MAE): The GMCH always allows access to main system memory. This bit is
not implemented and is hardwired to 1. Writes to this bit position have no effect.
0 I/O Access Enable (IOAE): This bit is not implemented in the GMCH and is hardwired to a 0. Writes to
this bit position have no effect.
Datasheet 61
4.8.4 PCI Status Register

Access: Read Only, Read/WriteClear
Size: 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI
Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does
not physically reside on PCI_A many of the bits are not implemented.
Bit Description
15 Detected Parity Error (DPE): The GMCH does not implement this bit and it is hardwired to a 0. Writes
14 Signaled System Error (SSE): R/WC. This bit is set to 1 when GMCH Device #0 generates an SERR
message over HI for any enabled Device #0 error condition. Device #0 error conditions are enabled in
the PCICMD and ERRCMD registers. Device #0 error flags are read/reset from the PCISTS or ERRSTS
registers. Software sets SSE to 0 by writing a 1 to this bit.
13 Received Master Abort Status (RMAS): R/WC. This bit is set when the GMCH generates a HI request
that receives a Master Abort completion packet or Master Abort Special Cycle. Software clears this bit
by writing a 1 to it.
12 Received Target Abort Status (RTAS): R/WC. This bit is set when the GMCH generates a HI request
that receives a Target Abort completion packet or Target Abort Special Cycle. Software clears this bit by
writing a 1 to it. If bit 6 in the ERRCMD is set to a one and an Serr# special cycle is generated on the HI
bus.
11 Signaled Target Abort Status (STAS): The GMCH will not generate a Target Abort HI completion
packet or Special Cycle. This bit is not implemented in the GMCH and is hardwired to a 0. Writes to this
bit position have no effect.
10:9 DEVSEL Timing (DEVT): These bits are hardwired to “00”. Writes to these bit positions have no affect.
Device #0 does not physically connect to PCI_A. These bits are set to “00” (fast decode) so that the
GMCH does not limit optimum DEVSEL timing for PCI_A.
8 Master Data Parity Error Detected (DPD): PERR signaling and messaging are not implemented by the
GMCH therefore this bit is hardwired to 0. Writes to this bit position have no effect.
7 Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no effect.
Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-back
capability) so that the GMCH does not limit the optimum setting for PCI_A.
6:5 Reserved
4 Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration software that this
device/function implements a list of new capabilities. A list of new capabilities is accessed via register
CAPPTR at configuration address offset 34h.
3:0 Reserved
62 Datasheet
4.8.5 RID – Register Identification

Address Offset: 08h
Default Value: 02h
Access: Read Only
Size: 8 bits
This register contains the revision number of the GMCH Device #0. These bits are read only and
writes to this register have no effect.
Bit Description
7:0 Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification
number for the GMCH Device #0.
4.8.6 SUBC – Sub Class Code Register

Address Offset: 0Ah
Default Value: 00h
Access: Read Only
Size: 8 bits
This register contains the Sub-Class Code for the GMCH Device #0. This code is 00h indicating a
Host Bridge device.
Bit Description
7:0 Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which the
GMCH falls. The code is 00h indicating a Host Bridge.
4.8.7 BCC – Base Class Code Register

Address Offset: 0Bh
Default Value: 06h
Access: Read Only
Size: 8 bits
This register contains the Base Class code of the GMCH Device #0. This code is 06h indicating a
Bridge device.
Bit Description
7:0 Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH.
This code has the value 06h, indicating a Bridge device.
Datasheet 63
4.8.8 HDR – Header Type Register

Address Offset: 0Eh
Default Value: 80h
Access: Read Only
Size: 8 bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit Description
7:0 PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device. If
Functions other than 0 are disabled, this field returns a 00 to indicate that the GMCH is a single function
device with standard header layout. Writes to this location have no effect.
4.8.9 SVID – Subsystem Vendor Identification Register

Address Offset: 2C-2Dh
Access: Read/Write Once
Size: 16 bits
This value is used to identify the vendor of the subsystem.
Bit Description
15:0 Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate the
vendor of the system board. After it has been written once, it becomes Read Only.
4.8.10 SID – Subsystem Identification Register

Address Offset: 2E-2Fh
Size: 16 bits
This value is used to identify a particular subsystem.
Bit Description
15:0 Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has been
written once, it becomes Read Only.
64 Datasheet
4.8.11 CAPPTR – Capabilities Pointer Register

Bit Description
7:0 Pointer to the offset of the first capability ID register block: In this case the first capability is the
Product-Specific Capability, which is located at offset 40h.
4.8.12 CAPID – Capability Identification Register (Device #0)

Address Offset: 40h – 44h
Default: chipset dependent
Access: Read Only
Size 40 bits
The Capability Identification Register uniquely identifies chipset capabilities as defined in the
table below. The bits in this register are intended to define a capability ceiling for each feature,
not a capability select. The capability selection for each feature is implemented elsewhere. The
mechanism to select the capability for each feature must comprehend these Capability registers
and not allow a selected setting above the ceiling specified in these registers. The BIOS must read
this register to identify the part and comprehend the capabilities specified within when
configuring the effected portions of the GMCH.
The default setting, in most cases, allows the maximum capability. Exceptions are noted in the
individual bits. This register is Read Only. Writes to this register have no effect.
Bit Description
39:37 Capability ID [2:0]:
000 = Intel 855GME GMCH
001-011 = Reserved
100 = Intel 855GM GMCH
101-111 = Reserved
36:28 Reserved
27:24 CAPREG Version: This field has the value 0001b to identify the first revision of the CAPREG definition.
23:16 Cap_length: This field has the value 05h indicating the structure length.
15:0 Reserved
Datasheet 65
4.8.13 GMC – GMCH Miscellaneous Control Register (Device #0)

Address Offset: 50–51h
Access: Read/Write
Size: 16 bits
Bit Description
15:10 Reserved
9 Reserved
8 RRBAR Access Enable—R/W:
1 = Enables the RRBAR space.

0 = Disable
7:1 Reserved
0 MDA Present (MDAP)—R/W:
This bit should not be set when the VGA Enable bit is not set. If the VGA enable bit is set, then accesses
to IO address range x3BCh–x3BFh are forwarded to Hub interface. If the VGA enable bit is not set then
accesses to IO address range x3BCh–x3BFh are treated just like any other IO accesses. MDA
resources are defined as the following:
Memory: 0B0000h – 0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to Hub
interface even if the reference includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGA MDA Behavior
0 0 All References to MDA and VGA go to Hub interface (Default)
0 1 Reserved
1 0 All References to VGA go to PCI.

MDA-only references (I/O address 3BF and aliases)
will go to Hub interface.
1 1 VGA References go to PCI; MDA References

go to Hub interface
66 Datasheet
4.8.14 GGC – GMCH Graphics Control Register (Device 0)

Access: Read/Write
Size: 16 bits
Bit Description
15:7 Reserved
6:4 Graphics Mode Select (GMS): This field is used to select the amount of Main system memory that is
pre-allocated to support the Internal Graphics Device in VGA (non-linear) and Native (linear) modes. The
BIOS ensures that system memory is pre-allocated only when Internal Graphics is enabled.
000 = No system memory pre-allocated. Device #2 (IGD) does not claim VGA cycles (Memory and I/O),
and the Sub-Class Code field within Device #2 Function #0 Class Code register is 80.
001 = DVMT (UMA) mode, 1 MB of system memory pre-allocated for frame buffer.
All other combinations reserved.
3:2 Reserved
1 IGD VGA Disable (IVD):
1 = Disable. Device #2 (IGD) does not claim VGA Memory and I/O Mem cycles, and the Sub-Class
Code field within Device #2 Function #0 Class Code register is 80.
0 = Enable. Device #2 (IGD) claims VGA Memory and I/O cycles, the Sub-Class Code within Device #2
Class Code register is 00.
0 Reserved
Datasheet 67
4.8.15 DAFC – Device and Function Control Register (Device 0)

Access: Read/Write
Size: 16 bits
This 16-bit register controls the visibility of devices and functions within the GMCH to
configuration software.
Bit Description
15:8 Reserved
7 Device #2 Disable:
1 = Disabled.
0 = Enabled.
6:3 Reserved
2 Device #0 Function #3 Disable:
1 = Disable Function #3 registers within Device #0 and all associated DDR SDRAM and I/O ranges.
0 = Enable Function #3 within Device #0.
1 Reserved
0 Device #0 Function #1 Disable:
1 = Disable Function #1 within Device #0.
0 = Enable Function #1 within Device #0.
4.8.16 FDHC – Fixed DRAM Hole Control Register (Device #0)

Address Offset: 58h
Default Value: 00h
Access: Read/Write
Size: 8 bits
This 8-bit register controls a single fixed DDR SDRAM hole: 15–16 MB.
Bit Description
7 Hole Enable (HEN): This field enables a memory hole in DDR SDRAM space. Host cycles matching an
enabled hole are passed onto ICH4-M through Hub interface. The GMCH will ignore Hub interface cycles
matching an enabled hole.
NOTE: A selected hole is not re-mapped.
0 = None
1 = 15 MB–16 MB (1MBs)
6:0 Reserved
68 Datasheet
4.8.17 PAM(6:0) – Programmable Attribute Map Register (Device

#0)
Address Offset: 59–5Fh
Default Value: 00h Each
Attribute: Read/Write
Size: 4 bits/register, 14 registers
The GMCH allows programmable DDR SDRAM attributes on 13 Legacy system memory
segments of various sizes in the 640 kB –1 MB address range. Seven Programmable Attribute
Map (PAM) registers are used to support these features. Cacheability of these areas is controlled
via the MTRR registers in the P6 processor. Two bits are used to specify system memory
attributes for each system memory segment. These bits apply to both Host and Hub interface
initiator accesses to the PAM areas. These attributes are:
• RE - Read Enable. When RE = 1, the CPU Read accesses to the corresponding system
memory segment are claimed by the GMCH and directed to main system memory.
Conversely, when RE = 0, the Host Read accesses are directed to PCI0.
• WE - Write Enable. When WE = 1, the Host Write accesses to the corresponding system
memory segment are claimed by the GMCH and directed to main system memory.
Conversely, when WE = 0, the Host Write accesses are directed to PCI0.
The RE and WE attributes permit a system memory segment to be Read Only, Write Only,
Read/Write, or Disabled. For example, if a system memory segment has RE = 1 and WE = 0, the
segment is Read Only.
Each PAM register controls two regions, typically 16 kB in size. Each of these regions has a 4-bit
field. The 4 bits that control each region have the same encoding and are defined in the following
table.
Table 25. Attribute Bit Assignment
Bits [7, 3] Bits [6, 2] Bits [5, 1] Bits [4, 0] Description

Reserved Reserved WE RE
X X 0 0 Disabled. DDR SDRAM is disabled and all

accesses are directed to Hub interface. The
GMCH does not respond as a Hub interface
target for any Read or Write access to this area.
X X 0 1 Read Only. Reads are forwarded to DDR

SDRAM and Writes are forwarded to Hub
interface for termination. This Write protects the
corresponding DDR SDRAM segment. The
GMCH will respond as a Hub interface target for
Read accesses but not for any Write accesses.
X X 1 0 Write Only. Writes are forwarded to DDR

SDRAM and Reads are forwarded to the Hub
interface for termination. The GMCH will
respond as a Hub interface target for Write
accesses but not for any Read accesses.
Datasheet 69
Bits [7, 3] Bits [6, 2] Bits [5, 1] Bits [4, 0] Description

Reserved Reserved WE RE
X X 1 1 Read/Write. This is the normal operating mode

of main system memory. Both Read and Write
cycles from the host are claimed by the GMCH
and forwarded to DDR SDRAM. The GMCH will
respond as a Hub interface target for both Read
and Write accesses.
As an example, consider a BIOS that is implemented on the Expansion bus. During the
initialization process, the BIOS can be shadowed in main system memory to increase the system
performance. When BIOS is shadowed in main system memory, it should be copied to the same
address location. To shadow the BIOS, the attributes for that address range should be set to Write
Only. The BIOS is shadowed by first doing a Read of that address. This Read is forwarded to the
Expansion bus. The Host then does a Write of the same address, which is directed to main system
memory. After the BIOS is shadowed, the attributes for that system memory area are set to Read
Only so that all Writes are forwarded to the Expansion bus. Figure 5 and Table 26 show the PAM
registers and the associated attribute bits.
Figure 5. PAM Registers
Offset
PAM6 5Fh
PAM5 5Eh
PAM4 5Dh
PAM3 5Ch
PAM2 5Bh
PAM1 5Ah
PAM0 59h
7 6 5 4 3 2 1 0
R R WE RE R R WE RE
Reserved Read Enable (R/W)

Reserved 1=Enable
0=Disable
Write Enable (R/W)
1=Enable Write Enable (R/W)
0=Disable 1=Enable
0=Disable
Read Enable (R/W )
1=Enable Reserved
0=Disable Reserved
pam
70 Datasheet
Table 26. PAM Registers and Associated System Memory Segments
PAM Reg Attribute Bits System Memory Segment Comments Offset
PAM0[3:0] Reserved 59h
PAM0[7:4] R R WE RE 0F0000h–0FFFFFh BIOS Area 59h
PAM1[3:0] R R WE RE 0C0000h–0C3FFFh ISA Add-on BIOS 5Ah
PAM1[7:4] R R WE RE 0C4000h–0C7FFFh ISA Add-on BIOS 5Ah
PAM2[3:0] R R WE RE 0C8000h–0CBFFFh ISA Add-on BIOS 5Bh
PAM2[7:4] R R WE RE 0CC000h–0CFFFFh ISA Add-on BIOS 5Bh
PAM3[3:0] R R WE RE 0D0000h–0D3FFFh ISA Add-on BIOS 5Ch
PAM3[7:4] R R WE RE 0D4000h–0D7FFFh ISA Add-on BIOS 5Ch
PAM4[3:0] R R WE RE 0D8000h–0DBFFFh ISA Add-on BIOS 5Dh
PAM4[7:4] R R WE RE 0DC000h–0DFFFFh ISA Add-on BIOS 5Dh
PAM5[3:0] R R WE RE 0E0000h–0E3FFFh BIOS Extension 5Eh
PAM5[7:4] R R WE RE 0E4000h–0E7FFFh BIOS Extension 5Eh
PAM6[3:0] R R WE RE 0E8000h–0EBFFFh BIOS Extension 5Fh
PAM6[7:4] R R WE RE 0EC000h–0EFFFFh BIOS Extension 5Fh
For details on overall system address mapping scheme see the Address Decoding section of this
document.
DOS Application Area (00000h–9FFFh)
The DOS area is 640 kB in size and it is further divided into two parts. The 512-kB area at 0 to
7FFFFh is always mapped to the main system memory controlled by the GMCH, while the 128-
kB address range from 080000 to 09FFFFh can be mapped to PCI0 or to main DDR SDRAM. By
default this range is mapped to main system memory and can be declared as a main system
memory hole (accesses forwarded to PCI0) via GMCH’s FDHC Configuration register.
Video Buffer Area (A0000h–BFFFFh)
Attribute Bits do not control this 128-kB area. The Host-initiated cycles in this region are always
forwarded to either PCI0 or PCI2 unless this range is accessed in SMM mode. Routing of
accesses is controlled by the Legacy VGA Control Mechanism of the “Virtual” PCI-PCI Bridge
Device embedded within the GMCH.
This area can be programmed as SMM area via the SMRAM register. When used as an SMM
space, this range can not be accessed from the Hub interface.
Expansion Area (C0000h–DFFFFh)
This 128-kB area is divided into eight 16-kB segments that can be assigned with different
attributes via PAM Control register as defined in Figure 5 and Table 26.
Datasheet 71
Extended System BIOS Area (E0000h–EFFFFh)
This 64-kB area is divided into four 16-kB segments that can be assigned with different attributes
via PAM Control register as defined in Figure 5 and Table 26.
System BIOS Area (F0000h–FFFFFh)
This area is a single 64-kB segment that can be assigned with different attributes via PAM
Control register as defined in Figure 5 and Table 26.
4.8.18 SMRAM – System Management RAM Control Register

(Device #0)
Address Offset: 60h
Default Value: 02h
Access: Read/Write/Lock, Read Only
Size: 8 bits
The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are
treated. The Open, Close, and Lock Bits function only when G_SMRAME Bit is set to a 1. Also,
the Open Bit must be Reset before the LOCK Bit is set.
Bit Description
7 Reserved
6 SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space DDR SDRAM is
made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM
space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When
D_LCK is set to a 1, D_OPEN is Reset to 0 and becomes Read Only.
5 SMM Space Closed (D_CLS): When D_CLS = 1 SMM Space, DDR SDRAM is not accessible to data
references, even if SMM decode is active. Code references may still access SMM space DDR
SDRAM. This will allow SMM software to reference “through” SMM space to update the display even
when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1
are not set at the same time. D_CLS applies to all SMM spaces (Cseg, Hseg, and Tseg).
4 SMM Space Locked (D_LCK): When D_LCK is set to 1, then D_OPEN is Reset to 0 and D_LCK,
D_OPEN, G_SMRAME, C_BASE_SEG, GMS, DRB, DRA, H_SMRAM_EN, TSEG_SZ and TSEG_EN
become Read Only. D_LCK can be set to 1 via a normal Configuration Space Write but can only be
cleared by a Full Reset. The combination of D_LCK and D_OPEN provide convenience with security.
The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to “lock down”
SMM space in the future so that no application software (or BIOS itself) can violate the integrity of
SMM space, even if the program has knowledge of the D_OPEN function.
3 Global SMRAM Enable (G_SMRAME): If set to a 1, then Compatible SMRAM functions is enabled,
providing 128 kB of DDR SDRAM accessible at the A0000h address while in SMM (ADS# with SMM
decode). To enable Extended SMRAM function this bit must be set to 1, refer to the section on SMM
for more details. Once D_LCK is set, this bit becomes Read Only.
2:0 Compatible SMM Space Base Segment (C_BASE_SEG)—RO: This field indicates the location of
SMM space. “SMM DRAM” is not remapped. It is simply “made visible” if the conditions are right to
access SMM space, otherwise the access is forwarded to Hub interface. C_BASE_SEG is hardwired
to 010 to indicate that the GMCH supports the SMM space at A0000h–BFFFFh.
72 Datasheet
4.8.19 ESMRAMC – Extended System Management RAM Control

(Device #0)
Address Offset: 61h
Default Value: 38h
Access: Read/Write/Lock
Size: 8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM Space. The
Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory
Space that is above 1 MB.
Bit Description
7 H_SMRAM_EN (H_SMRAME): Controls the SMM Memory Space location (i.e., above 1 MB or below
1 MB). When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM Memory Space
is enabled. SMRAM accesses from 0FEDA0000h to 0FEDBFFFFh are remapped to DDR SDRAM
address 000A0000h to 000BFFFFh.
Once D_LCK is set, this bit becomes Read Only.
6 E_SMRAM_ERR (E_SMERR): This bit is set when CPU accesses the defined DDR SDRAM ranges
in Extended SMRAM (High system memory and T-segment) while not in SMM Space. It is software’s
responsibility to clear this bit. The software must Write a 1 to this bit to clear it.
5 SMRAM_Cache (SM_CACHE): GMCH forces this bit to 1.
4 SMRAM_L1_EN (SM_L1): GMCH forces this bit to 1.
3 SMRAM_L2_EN (SM_L2): GMCH forces this bit to 1.
2:1 Reserved
0 TSEG_EN (T_EN): Enabling of SMRAM Memory (TSEG, 1 Mbytes of additional SMRAM Memory) for
Extended SMRAM Space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to
appear in the appropriate physical address space.
Once D_LCK is set, this bit becomes Read Only.
Datasheet 73
4.8.20 ERRSTS – Error Status Register (Device #0)

Access: Read/Write Clear
Size: 16 bits
This register is used to report various error conditions via Hub Interface Special cycles. An
SERR, SMI, or SCI Error Hub Interface Special cycle may be generated on a zero to one
transition of any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD
registers respectively.
Bit Description
15:14 Reserved
13 FSB Strobe Glitch Detected (FSBAGL): When this bit is set to 1 the GMCH has detected a glitch on
one of the FSB strobes. Writing a 1 to it clears this bit.
12 GMCH Software Generated Event for SMI:
1 = This indicates the source of the SMI was a Device #2 Software Event.
0 = Software must Write a 1 to clear this bit.
11 GMCH Thermal Sensor Event for SMI/SCI/SERR:
1 = Indicates that a GMCH Thermal Sensor trip has occurred and an SMI, SCI or SERR has been
generated. Note that the status bit is set only if a message is sent based on Thermal event enables
in Error Command, SMI Command and SCI Command registers. Note that a Trip Point can
generate one of SMI, SCI or SERR interrupts (two or more per event is illegal). Multiple Trip Points
can generate the same interrupt. If software chooses this mode, then subsequent Trips may be lost.
0 = Software must Write a 1 to clear this status bit. If this bit is set, then an interrupt message will not
be sent on a new Thermal Sensor event.
10 Reserved
9 LOCK to non-DDR SDRAM Memory Flag (LCKF)—R/WC:
1 = Indicates that a CPU initiated LOCK cycle targeting non-DDR SDRAM Memory Space occurred.
0 = Software must Write a 1 to clear this status bit
8 Received Refresh Timeout—R/WC:
1 = This bit is set when 1024 memory core refresh are Queued up.
0 = Software must Write a 1 to clear this status bit.
7 DRAM Throttle Flag (DTF)—R/WC:
1 = Indicates that the DDR SDRAM Throttling condition occurred.
6 Reserved
5 Received Unimplemented Special Cycle Hub Interface Completion Packet FLAG (UNSC)—R/WC:
1 = Indicates that the GMCH initiated a Hub interface request that was terminated with an
Unimplemented Special Cycle completion packet.
4:0 Reserved
74 Datasheet
4.8.21 ERRCMD – Error Command Register (Device #0)

Access: Read/Write
Size: 16 bits
This register enables various errors to generate a SERR Hub Interface Special cycle. Since the
GMCH does not have a SERR# signal, SERR messages are passed from the GMCH to the ICH4-
M over Hub interface. The actual generation of the SERR message is globally enabled for
Device #0 via the PCI Command register.
Note: An error can generate one and only one Hub Interface Error Special cycle. It is software’s
responsibility to make sure that when an SERR error message is enabled for an error condition,
SMI and SCI error messages are disabled for that same error condition.
Bit Description
15:14 Reserved
13 SERR on FSB Strobe Glitch: When this bit is asserted, the GMCH will generate a HI SERR message
when a glitch is detected on one of the FSB strobes.
12 Reserved
11 SERR on GMCH Thermal Sensor Event:
1 = The GMCH generates a SERR Hub Interface Special cycle on a Thermal Sensor Trip that requires
an SERR. The SERR must not be enabled at the same time as the SMI/SCI for a Thermal Sensor
Trip event.
10 Reserved
9 SERR on LOCK to non-DDR SDRAM Memory:
1 = The GMCH generates an SERR Hub Interface Special cycle when a CPU initiated LOCK
transaction targeting non-DDR SDRAM Memory Space occurs.
0 = Reporting of this condition is disabled.
8 SERR on DDR SDRAM Refresh timeout:
1 = The GMCH generates an SERR Hub Interface Special cycle when a DDR SDRAM Refresh timeout
occurs.
7 SERR on DDR SDRAM Throttle Condition:
1 = The GMCH generates an SERR Hub Interface Special cycle when a DDR SDRAM Read or Write
Throttle condition occurs.
6 SERR on Receiving Target Abort on Hub Interface:
1 = The GMCH generates an SERR Hub Interface Special cycle when a GMCH originated Hub
interface cycle is terminated with a Target Abort.
Datasheet 75
Bit Description
5 SERR on Receiving Unimplemented Special Cycle Hub Interface Completion Packet:
1 = The GMCH generates an SERR Hub Interface Special cycle when a GMCH initiated Hub interface
request is terminated with a Unimplemented Special cycle completion packet.
4:2 Reserved
1 SERR on Multiple-bit ECC Error:
1 = For systems that support ECC, this field must be set to 1.
0 = Reserved
0 SERR on Single-bit ECC Error:
0 = Reserved
4.8.22 SMICMD – SMI Error Command Register (Device #0)

Address Offset: 66h
Default Value: 00h
Access: Read/Write
Size: 8 bits
This register enables various errors to generate an SMI Hub Interface Special cycle. When an
Error Flag is set in the ERRSTS register, it can generate a SERR, SMI, or SCI Hub Interface
Special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively.
responsibility to make sure that when an SMI Error Message is enabled for an error condition,
SERR, and SCI Error Messages are disabled for that same error condition.
Bit Description
7:4 Reserved
3 SMI on GMCH Thermal Sensor Trip:
1 = An SMI Hub Interface Special cycle is generated by GMCH when the Thermal Sensor Trip requires
an SMI. A Thermal Sensor Trip Point cannot generate more than one special cycle.
2 Reserved
1 SMI on Multiple-bit ECC Error:
0 = Reserved
0 SMI on Single-bit ECC Error:
0 = Reserved
76 Datasheet
4.8.23 SCICMD – SCI Error Command Register (Device 0)

Address Offset: 67h
Default Value: 00h
Access: Read/Write
Size: 8 bits
This register enables various errors to generate a SCI Hub Interface Special cycle. When an Error
Flag is set in the ERRSTS register, it can generate a SERR, SMI, or SCI Hub Interface Special
cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively.
responsibility to make sure that when an SCI error message is enabled for an error condition,
SERR and SMI Error Messages are disabled for that same error condition.
Bit Description
7:4 Reserved
3 SCI on GMCH Thermal Sensor Trip:
1 = An SCI Hub Interface Special cycle is generated by GMCH when the Thermal Sensor Trip requires
an SCI. A Thermal Sensor Trip Point cannot generate more than one special cycle.
2 Reserved
1 SCI on Multiple-bit ECC Error:
0 = For systems that do not support ECC, this field must be 0.
0 SCI on Single-bit ECC Error:
0 = For systems that do not support ECC, this field must be 0.
Datasheet 77
4.8.24 SHIC – Secondary Host Interface Control Register (Device

#0)
Size: 32 bits
Bit Description
31 Reserved
30 BREQ0# Control of FSB Address and Control bus power management:
0 = Disable FSB address and control bus power management.
1 = Enable FSB address and control bus power management.
29:28 Reserved
27 On Die Termination (ODT) Gating Disable:
0 = Enable.
1 = Disable.
26:7 Reserved
6 FSB Data Bus Power Management Control:
0 = FSB Data Bus Power Management disabled (Default).
1 = FSB Data Bus Power Management enabled
5 Reserved
4:3 DPWR# Control.
00 = DPWR# pin is always asserted.
10 = DPWR# pin is asserted at least 2 clocks before read data is returned to the processor on the FSB
(2 clocks before DRDY# asserted). This is default setting.
01 = DPWR# is always de-asserted.
11 = Reserved
2 C2 state GMCH FSB Interface Power Management Control:
0 = Power Management Disabled in C2 state
1 = Power Management Enabled in C2 state
78 Datasheet
Bit Description
1 AGP/DVO Mux Strap (Read only)

Specifies the use of AGP bus muxed with DVO. This bit is defined at Reset by a strap on the
G_PAR/DVO_DETECT signal. By default the AGP bus pulls this signal high. The presence of an DVO
device pulls this signal low. The presence of a DVO device disables Device #1 and associated memory
and io spaces are disabled. In addition, sets the Next_Pointer = 00h in the capability register, converts
APBASE to read only, and disables Aperture Global Access. Also prevents VGA memory and IO
decodes to the AGP interface.
If AGP capability is limited (disabled), then the AGP pins are dedicated to internal graphics DVO
functionality.
If AGP capability is available, then based on this strap, the AGP interface is used for AGP functionality
or DVO functionality based on this strap.
1= AGP.
0 = DVO
0 Reserved
4.8.25 ACAPID – AGP Capability Identifier Register (Device #0)

Address Offset: A0-A3h
Access: Read Only
Size: 32 bits
This register provides standard identifier for AGP capability.
Bit Description
31:24 Reserved
23:20 Major AGP Revision Number. These bits provide a major revision number of AGP specification to
which this version of GMCH conforms. These bits are set to the value 0010b to indicate AGP Rev. 2.x.
19:16 Minor AGP Revision Number. These bits provide a minor revision number of AGP specification to
which this version of GMCH conforms. This is set to 0000b (i.e., implying Rev x.0)
Together with major revision number this field identifies GMCH as an AGP REV 2.0 compliant device.
15:8 Next Capability Pointer. AGP capability is the last capability described via the capability pointer
mechanism and therefore these bits are set to 00h to indicate the end of the capability linked list.
7:0 AGP Capability ID. This field identifies the linked list item as containing AGP registers. This field has
the value 02h as assigned by the PCI SIG.
Datasheet 79
4.8.26 AGPSTAT – AGP Status Register (Device #0)

Address Offset: A4–A7h
Default Value: 1F000217h
Access: Read Only
Size: 32 bits
This register reports AGP device capability/status.
Bit Description
31:24 Request (RQ). Indicates a maximum of 32 outstanding AGP command requests can be handled by the
GMCH .
Default =1Fh to allow a maximum of 32 outstanding AGP command requests.
23:10 Reserved
9 Side Band Addressing (SBA). Indicates that the GMCH supports side band addressing.
8:6 Reserved
5 Address Support Above 4 GB (4 GB). Indicates that the GMCH does not support addresses greater
than 4 gigabytes.
4 Fast Writes.
1 = The GMCH supports Fast Writes from the CPU to the AGP master. (Default)
3 Reserved
2:0 RATE. After reset the GMCH reports its data transfer rate capability. Bit 0 identifies if AGP device
supports 1X data transfer mode, bit 1 identifies if AGP device supports 2X data transfer mode, bit 2
identifies if AGP device supports 4X data transfer mode. 1X , 2X , and 4X data transfer modes are
supported by the GMCH and therefore this bit field has a Default Value = 111.
NOTE: The selected data transfer mode applies to both AD bus and SBA bus.
80 Datasheet
4.8.27 AGPCMD – AGP Command Register (Device #0)

Address Offset: A8–ABh
Access: Read/Write
Size: 32 bits
This register provides control of the AGP operational parameters.
Bit Description
31:10 Reserved
9 Side Band Addressing Enable (SBA_EN). When this bit is set to 1, the side band addressing
mechanism is enabled.
8 AGP Enable.
0 = Disable. When this bit is reset to 0, the GMCH will ignore all AGP operations, including the sync
cycle. Any AGP operations received while this bit is set to 1 will be serviced even if this bit is reset
to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being
delivered in 1X mode, the command will be issued.
1 = Enable. The GMCH will respond to AGP operations delivered via PIPE#, or to operations
delivered via SBA if the AGP Side Band Enable bit is also set to 1.
7:6 Reserved
5 Address Support Above 4 GB Enable (4 GB_EN). The GMCH as an AGP target does not support
addressing greater than 4 gigabytes.
4 Fast Write Enable.
1 = Enable. GMCH AGP master supports Fast Writes.
0 = Disable (Default). Fast Writes are disabled.
3 Reserved
2:0 Data Rate. The settings of these bits determine the AGP data transfer rate. One (and only one) bit in
this field must be set to indicate the desired data transfer rate. Bit 0: 1X, Bit 1: 2X, Bit 2: 4X. The same
bit must be set on both master and target.
Configuration software will update this field by setting only one bit that corresponds to the capability of
AGP master (after that capability has been verified by accessing the same functional register within the
AGP masters configuration space.)
NOTE: The selected data transfer mode applies to both AD bus and SBA bus.
Datasheet 81
4.8.28 AGPCTRL – AGP Control Register (Device #0)

Address Offset: B0–B1h
Access: Read/Write
Size: 16 bits
This register provides for additional control of the AGP interface.
Bit 7 is visible to the operating system and must be retained in this position.
Bit Description
15:8 Reserved
7 GTLB Enable (and GTLB Flush Control).
NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs).
This bit must not be changed through memory mapped configuration register access space.
6:0 Reserved
4.8.29 AFT – AGP Functional Test Register (Device #0)

Address Offset: B2–B3h
Default Value: E9F0h
Access: Read/Write, Read/WriteClear
Size: 16 bits
This register provides for additional control of the AGP interface.
Bit Description
15:11 Retry Timer Time-Out Count (RTTOC): These bits control the retry time-out period (for initial data
phase) for the purpose of enhancing the system testability. These bits correspond to value loaded into
retry timer. Default value is 11101b (29d) for retry clock count of 32d (value +3).
10 PCI Write Streaming Disable (PCIBWSD): When this bit is set to ‘1’, PCI_B writes to DDR SDRAM
are disconnected at a 32 byte cache line boundary (write streaming is disabled). When this bit is set to
‘0’ (default), write streaming is enabled.
9 PCI Read Buffer Disable.
1 = When set to “1” the PCI Read Buffering mechanism is disabled. In this mode all data prefetched
and buffered for a PCI to DDR SDRAM read will be discarded when that read transaction terminates.
This bit defaults to “0”.
8:4 AGP/PCI1 Discard Timer Time-out Count. These bits control the length of AGP/PCI1 Delayed
Transaction discard time-out for the purpose of enhancing the system testability. Default value is
11111b (31d) for a discard count of 1024d ((value+1)*32).
3 PCI_B Write Combining Disable (PCIBWCD): When this bit is set to ‘1’, write combining is disabled
for host bus writes targeting the PCI_B bus (depends on configuration). When this bit is ‘0’ (default),
write combining is enabled.
82 Datasheet
Bit Description
2 AGP/PCI1 Discard Timer Disable.
0 = Enable (default). Enables the Discard Timer for the delayed transactions on the PCI1/AGP
interface (initiated by the AGP agent using PCI protocol). The counter starts once the delayed
transaction request is ready to complete as far as GMCH is concerned (i.e., read data is pending on
the top of AGP Outbound queue). If the AGP agent (using PCI protocol) does not repeat the
transaction before the counter expires after 2^10 clocks (66 MHz) the GMCH will delete the delayed
transaction from its queue and set the Discard Timer Status bit.
1= Disable. The discard timer is disabled.
1 AGP/PCI Discard Timer Status (AGPDTS): R/WC When set to 1 this bit indicates that a delayed
transaction on PCI_B has been discarded due to DT timer expiration. When set this bit can be cleared
by writing it with 1.
0 Reserved
4.8.30 APSIZE – Aperture Size (Device #0)

Address Offset: B4h
Default Value: 00h
Access: Read/Write
Size: 8 bits
This register determines the effective size of the Graphics Aperture used for a particular GMCH
configuration. This register can be updated by the GMCH -specific BIOS configuration sequence
before the PCI standard bus enumeration sequence. If the register is not updated then a default
value will select an aperture of maximum size (i.e., 256 MB). The size of the table that will
correspond to a 256 MB aperture is not practical for most applications and therefore these bits
must be programmed to a smaller practical value that will force adequate address range to be
requested via APBASE register from the PCI configuration software.
Bit Description
7:6 Reserved
5:0 Graphics Aperture Size (APSIZE). Each bit in APSIZE[5:4] operates on similarly ordered bits in
APBASE[27:26] of the Aperture Base configuration register. When a particular bit of this field is 0 it
forces the similarly ordered bit in APBASE[27:26] to behave as 0. When a particular bit of this field is set
to 1 it allows corresponding bit of the APBASE[27:26] to be read/write accessible.
Only the following combinations are allowed when the Aperture is enabled:
Bits[5:4] Aperture Size
11 64 MB
10 128 MB
00 256 MB
Default for APSIZE[5:4]=00b forces default APBASE[27:26] =00b (i.e. all bits respond as hardwired to 0).
This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:4]=11b
enables APBASE[27:26] as read/write programmable providing a minimum size of 64 MB.
3:0: Reserved set to zero for software compatibility.
Datasheet 83
4.8.31 ATTBASE – Aperture Translation Table Base Register

(Device #0)
Address Offset: B8–BBh
Access: Read/Write
Size: 32 bits
This register provides the starting address of the Graphics Aperture Translation Table Base
located in the main DDR SDRAM. This value is used by the GMCH’s Graphics Aperture address
translation logic (including the GTLB logic) to obtain the appropriate address translation entry
required during the translation of the aperture address into a corresponding physical DDR
SDRAM address. The ATTBASE register may be dynamically changed.
The address provided via ATTBASE is 4 kB aligned.
Bit Description
31:12 This field contains a pointer to the base of the translation table used to map memory space addresses
in the aperture range to addresses in main memory.
11:0 Reserved
4.8.32 AMTT – AGP Interface Multi-Transaction Timer Register

(Device #0)
Address Offset: BCh
Default Value: 00h
Access: Read/Write
Size: 8 bits
AMTT is an 8-bit register that controls the amount of time that the GMCH ’s arbiter allows
AGP/PCI master to perform multiple back-to-back transactions. The GMCH ’s AMTT
mechanism is used to optimize the performance of the AGP master (using PCI semantics) that
performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence
it can not use long burst transfers). The AMTT mechanism applies to the CPU-AGP/PCI
transactions as well and it guarantees to the CPU a fair share of the AGP/PCI interface bandwidth.
The number of clocks programmed in the AMTT represents the guaranteed time slice (measured
in 66- MHz clocks) allotted to the current agent (either AGP/PCI master or Host bridge) after
which the AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and
disables this function. The AMTT value can be programmed with 8 clock granularity. For
example, if the AMTT is programmed to 18h, then the selected value corresponds to the time
period of 24 AGP (66 MHz) clocks.
Bit Description
7:3 Multi-Transaction Timer Count Value. The number programmed in these bits represents the
guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the current agent (either
AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another agent.
2:0 Reserved.
84 Datasheet
4.8.33 LPTT – Low Priority Transaction Timer Register (Device #0)

Address Offset: BDh
Default Value: 00h
Access: Read/Write
Size: 8 bits
LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the
minimum tenure on the AGP for low priority data transaction (both reads and writes) issued using
PIPE# or SB mechanisms.
The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in
66 MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does
not necessarily apply to a single transaction but it can span over multiple low-priority transactions
of the same type. After this time expires the AGP arbiter may grant the bus to another agent if
there is a pending request. The LPTT does not apply in the case of high-priority request where
ownership is transferred directly to high-priority requesting queue. The default value of LPTT is
00h and disables this function. The LPTT value can be programmed with 8 clock granularity. For
example, if the LPTT is programmed to 10h, then the selected value corresponds to the time
period of 16 AGP (66 MHz) clocks.
Bit Description
7:3 Low Priority Transaction Timer Count Value. The number of clocks programmed in these bits
represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the
current low priority AGP transaction data transfer state.
2:0 Reserved.
4.8.34 HEM – Host Error Control, Status and Observation (Device

#0)
Address Offset: F0–F3h
Access: Read/Write, RO
Size: 32 bits
Bit Description
31 Detected HADSTB1# Glitch (ASTB1GL): This bit is set when the GMCH has detected a glitch on
address strobe HADSTB1#. Software must write a 1 to clear this status bit.
30 Detected HADSTB0# Glitch (ASTB0GL): This bit is set when the GMCH has detected a glitch on
address strobe HADSTB0#. Software must write a 1 to clear this status bit.
29 Detected HDSTB3# Glitch (DSTB3GL): This bit is set when the GMCH has detected a glitch on data
strobe pair HDSTB3#. Software must write a 1 to clear this status bit.
Datasheet 85
4.9 Intel® 855GM/GME GMCH Main Memory Control,

Memory I/O Control Registers (Device #0, Function
#1)
The following table shows the GMCH Configuration Space for Device #0, Function #1. See
Section 4.2f or access nomenclature.
Table 27. Host-Hub I/F Bridge/System Memory Controller Configuration Space (Device #0,
Function#1)

Symbol Start End
DRAM Row 0-3 Boundary DRB 40 43 00000000h RW
DRAM Row 0-3 Attribute DRA 50 51 7777h RW
DRAM Timing DRT 60 63 18004425h RW
DRAM Controller Power PWRMG 68 6B 00000000h R/W

Management Control
Dram Controller Mode DRC 70 73 00000081h R/W
DRAM Throttle Control DTC A0 A3 00000000h R/W/L
86 Datasheet

Access: Read Only
Size: 16 bits
The VID Register contains the vendor identification number. This 16-bit register combined with
the Device Identification Register uniquely identifies any PCI device. Writes to this register have
no effect.
Bit Description
15:0 Vendor Identification (VID): This register field contains the PCI standard identification for Intel.

Access: Read Only
Size: 16 bits
Bit Description
15:0 Device Identification Number (DID): This is a 16-bit value assigned to the GMCH Host– HI Bridge
Function #1 (3584h).
Datasheet 87

Size: 16 bits
Since Intel chipset Device #0 does not physically reside on PCI_A, many of the bits are not
implemented.
Bit Description
15:10 Reserved
to this bit position have no affect.
8 SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the GMCH and this
bit is hardwired to 0. Writes to this bit position have no effect.
4 Memory Write and Invalidate Enable (MWIE): The GMCH will never issue Memory Write and
Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect.
1 Memory Access Enable (MAE): The GMCH always allows access to main system memory. This bit is
not implemented and is hardwired to 1. Writes to this bit position have no effect.
88 Datasheet
4.9.4 PCISTS – PCI Status Register

Size: 16 bits
Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does
not physically reside on PCI_A, many of the bits are not implemented.
Bit Description
14 Signaled System Error (SSE): The GMCH does not implement this bit and it is hardwired to a 0.
13 Received Master Abort Status (RMAS): The GMCH does not implement this bit and it is hardwired to
a 0. Writes to this bit position have no effect.
12 Received Target Abort Status (RTAS): The GMCH does not implement this bit and it is hardwired to a
11 Signaled Target Abort Status (STAS): The GMCH does not implement this bit and it is hardwired to a
10:9 DEVSEL Timing (DEVT): These bits are hardwired to “00”. Writes to these bit positions have no affect.
Device #0 does not physically connect to PCI_A. These bits are set to “00” (fast decode) so that the
8 Master Data Parity Error Detected (DPD): The GMCH does not implement this bit and it is hardwired
6:5 Reserved
device/function does not implement new capabilities.
Default Value = 0
3:0 Reserved
Datasheet 89
4.9.5 RID – Revision Identification Register

Address Offset: 08h
Default Value: 02h
Access: Read Only
Size: 8 bits
This register contains the revision number of the Intel 855GM/GME GMCH Device #0. These
bits are Read Only and Writes to this register have no effect.
Bit Description
number for the GMCH Device #0.
4.9.6 SUBC – Sub-Class Code Register

Address Offset: 0Ah
Default Value: 80h
Access: Read Only
Size: 8 bits
This register contains the Sub-Class code for the Intel 855GM/GME GMCH Device #0. This code
is 80h indicating Other Peripheral device.
Bit Descriptions
7:0 Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Peripheral device into
which the GMCH Function #1 falls. The code is 80h indicating Other Peripheral device.

Address Offset: 0Bh
Default Value: 08h
Access: Read Only
Size: 8 bits
This register contains the Base Class code of the Intel 855GM/GME GMCH Device #0 Function
#1. This code is 08h indicating Other Peripheral device.
Bit Description
7:0 Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH.
This code has the value 08h, indicating Other Peripheral device.
90 Datasheet

Address Offset: 0Eh
Default Value: 80h
Access: Read Only
Size: 8 bits
this location.
Bit Description
7:0 PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device.
Reads and Writes to this location have no effect.

Size: 16 bits
Bit Description
vendor of the system board. After it has been written once, it becomes Read Only.
4.9.10 SID – Subsystem Identification Register

Size: 16 bits
Bit Description
Written once, it becomes Read Only.
Datasheet 91

Address Offset: 34h
Default Value: 00h
Access: Read Only
Size: 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in
the capability list.
Bit Description
7:0 Pointer to the offset of the first capability ID register block: In this case there are no capabilities,
therefore these bits are hardwired to 00h to indicate the end of the capability linked list.
4.9.12 DRB – DRAM Row (0:3) Boundary Register (Device #0)

Default Value: 00h each
Access: Read/Write
Size: 8 bits each
The DDR SDRAM Row Boundary Register defines the upper boundary address of each DDR
SDRAM row with a granularity of 32-MB. Each row has its own single-byte DRB register. For
example, a value of 1 in DRB0 indicates that 32-MB of DDR SDRAM has been populated in the
first row. Since the GMCH supports a total of four rows of system memory, DRB0-3 are used.
The registers from 44h-4Fh are Reserved for DRBs 4-15.
Row0: 40h
Row1: 41h
Row2: 42h
Row3: 43h
44h to 4Fh is reserved.
DRB0 = Total system memory in Row0 (in 32 -MB increments)

DRB1 = Total system memory in Row0 + Row1 (in 32 -MB increments)
DRB2 = Total system memory in Row0 + Row1 + Row2 (in 32 -MB increments)
DRB3 = Total system memory in Row0 + Row1 + Row2 + Row3 (in 32- MB increments)
Each Row is represented by a Byte. Each Byte has the following format.
Bit Description
7:0 DDR SDRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses for each
DDR SDRAM row. This 8-bit value is compared against a set of address lines to determine the upper
address limit of a particular row. Also the minimum system memory supported is 64-MB in 64-Mb
granularity; hence bit 0 of this register must be programmed to a zero.
92 Datasheet
4.9.13 DRA – DRAM Row Attribute Register (Device #0)

Default Value: 77h Each
Access: Read/Write
Size: 8 bits
The DDR SDRAM Row Attribute Register defines the page sizes to be used when accessing
different pairs of Rows. Each Nibble of information in the DRA registers describes the page size
of a pair of Rows:
Row0, 1: 50h
Row2, 3: 51h
52h-5Fh: Reserved.
7 6 4 3 2 0
R Row attribute for Row1 R Row Attribute for Row0
7 6 4 3 2 0
R Row attribute for Row3 R Row Attribute for Row2
Bit Description
7 Reserved
6:4 Row Attribute for odd-numbered Row: This field defines the page size of the corresponding row.
000: Reserved
001: 4 kB
010: 8 kB
011: 16 kB
111: Not Populated
Others: Reserved
3 Reserved
2:0 Row Attribute for even-numbered Row: This field defines the page size of the corresponding row.
000: Reserved
001: 4 kB
010: 8 kB
011: 16 kB
111: Not Populated
Others: Reserved
Datasheet 93
4.9.14 DRT – DRAM Timing Register (Device #0)

Access: Read/Write
Size: 32 bits
This register controls the timing of the DDR SDRAM controller.
Bit Description
31 DDR Internal Write to Read Command delay (tWTR):
The tWTR is a std. DDR SDRAM timing parameter with a value of 1 CK for CL=2 and 2.5. The tWTR is
used to time RD command after a WR command (to same Row):
0: tWTR is set to 1 Clock (CK), used for DDR SDRAM CL=2 or 2.5
1: Reserved
30 DDR Write Recovery time (tWR):
Write recovery time is a std. DDR timing parameter with the value of 15 ns. It should be set to 2 CK when
DDR200 is used. The tWR is used to time PRE command launch after a WR command, when DDR
SDRAM components are populated.
0: tWR is set to 2 Clocks (CK)
1: tWR is set to 3 Clocks (CK)
29:28 Back To Back Write-Read commands spacing (DDR different Rows/Bank):
This field determines the WR-RD command spacing, in terms of common clocks for DDR SDRAM based
on the following formula: DQSS + 0.5xBL + TA (WR-RD) – CL
DQSS: is time from Write command to data and is always 1 CK
BL: is Burst Length and can be set to 4.
TA (WR-RD): is required DQ turn-around, can be set to 1 or 2 CK
CL: is CAS Latency, can be set to 2 or 2.5
Examples of usage:
For BL=4, with single DQ turn-around and CL=2, this field must be set to 2 CK (1+2+1-2)
Encoding CK between WR and RD commands
00: 4
01: 3
10: 2
11: Reserved
94 Datasheet
Bit Description
27:26 Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This field
determines the RD-WR command spacing, in terms of common clocks based on the following formula:
CL + 0.5xBL + TA (RD-WR) – DQSS
DQSS: is time from Write command to data and is always 1 CK
BL: is Burst Length which is set to 4
TA (RD-WR): is required DQ turn-around, can be set to 1, 2 or 3 CK
CL: is CAS latency, can be set to 2 or 2.5
Examples of usage:
For BL=4, with single DQ turn-around and CL=2, this field must be set to 4 CK (2+2+1-1)
Encoding CK between RD and WR commands
00: 7
01: 6
10: 5
11: 4
NOTE: Since reads in DDR SDRAM cannot be terminated by Writes, the Space between commands is
not a function of Cycle Length but of Burst Length.
25 Back To Back Read-Read commands spacing (DDR, different Rows):
This field determines the RD-RD Command Spacing, in terms of common clocks based on the following
formula: 0.5xBL + TA(RD-RD)
BL: is Burst Length and can be set to 4.
TA (RD-RD): is required DQ turn-around, can be set to 1 or 2 CK
Examples of usage:
For BL=4, with single DQ turn-around, this field must be set to 3 CK (2+1)
Encoding CK between RD and RD commands
0: 4
1: 3
NOTE: Since a Read to a different row does not terminate a Read, the Space between commands is not
a function of Cycle Length but of Burst Length.
24:15 Reserved
Datasheet 95
Bit Description
14:12 Refresh Cycle Time (tRFC):
Refresh Cycle Time is measured for a given row from REF command (to perform a refresh) until
following ACT to same row (to perform a Read or Write). It is tracked separately from tRC for DDR
SDRAM.
Current DDR SDRAM spec requires tRFC of 75 ns (DDR266) and 80 ns (DDR200). Therefore, this field
will be set to 8 clocks for DDR200, 10 clocks for DDR266.
Encoding tRFC
000: 14 clocks
001: 13 clocks
010: 12 clocks
011: 11 clocks
100: 10 clocks
101: 9 clocks
110: 8 clocks
111: 7 clocks
11 Activate to Precharge delay (tRAS), MAX:
This bit controls the maximum number of clocks that a DDR SDRAM bank can remain open. After this
time period, the system memory Controller will guarantee to pre-charge the bank. Note that this time
period may or may not be set to overlap with time period that requires a refresh to happen.
The DDR SDRAM Controller includes a separate tRAS-MAX counter for every supported bank. With a
maximum of four rows and four banks per row, there are 16 counters.
0: 120 micro-seconds
1: Reserved.
10:9 Activate to Precharge delay (tRAS), MIN:
This bit controls the number of DDR SDRAM clocks for tRAS MIN
00: 8 Clocks
01: 7 Clocks
10: 6 Clocks
11: 5 Clocks
8:7 Reserved
6:5 CAS# Latency (tCL):
Encoding DDR SDRAM CL
00: 2.5
01: 2
10: Reserved
11: Reserved
4 Reserved
96 Datasheet
Bit Description
3:2 DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks inserted between a
Row Activate command and a Read or Write command to that row.
Encoding tRCD
00: 4 DDR SDRAM Clocks (DDR 333 SDRAM)
01: 3 DDR SDRAM Clocks
11: Reserved
1:0 DDR SDRAM RAS# Precharge (tRP): This bit controls the number of clocks that are inserted between
a row precharge command and an activate command to the same row.
Encoding tRP
00: 4 DDR SDRAM Clocks (DDR 333 SDRAM)
11: Reserved
Datasheet 97
4.9.15 PWRMG – DRAM Controller Power Management Control

Register (Device #0)
Address Offset: 68h-6Bh
Access: Read/Write
Size: 32 bits
Bit Description
31:24 Reserved
23:20 Row State Control: This field determines the number of clocks the System Memory Controller will
remain in the idle state before it begins pre-charging all pages or powering down rows.
- PDEn: Power Down Enable
- PCEn: Page Close Enable
- TC: Timer Control
PDEn(23): PCEn(22): TC(21:20) Function
0 0 XX All Disabled
0 1 XX Reserved
1 0 XX Reserved
1 1 00 Immediate Precharge and Powerdown
1 1 01 Reserved
1 1 10 Precharge and Power Down after 16 DDR SDRAM Clocks
1 1 11 Precharge and Power Down after 64 DDR SDRAM Clocks
19:16 Reserved
15 Self Refresh GMCH Memory Interface Data Bus Power Management Optimization Enable:
0 = Enable
1 = Disable
14 CS# Signal Drive Control:
0 = Enable CS# Drive Control, based on rules described in DRC bit 12.
1 = Disable CS# Drive Control, based on rules described in DRC bit 12.
13 Self Refresh GMCH Memory Interface Data Bus Power Management:
0 = In Self Refresh Mode GMCH Power Management is Enabled.
1 = In Self Refresh Mode the GMCH Power Management is Disabled.
12 Dynamic Memory Interface Power Management:
0 = Dynamic Memory Interface Power Management Enabled.
1 = Dynamic Memory Interface Power Management Disabled.
98 Datasheet
Bit Description
11 Rcven DLL shutdown disable:
0 = Normal operation. RCVEN DLL is turned off when the corresponding SO-DIMM is unpopulated.
1 = RCVEN DLL is turned on irrespective of SO-DIMM population.
10 ECC SO-DIMM Clock tri-state Disable:
0 = When DDR SDRAM ECC is not enabled, the ECC clocks (i.e., SCK2/SCK2#, SCK5/SCK5#,) are
tri- stated.
1 = When DDR SDRAM ECC is enabled, the ECC clocks (i.e., SCK2/SCK2#, SCK5/SCK5#,) are
treated just like the other clocks.
9:1 Reserved
0 Power State S1/S3 Refresh Control:
0 = Normal Operation, Pending refreshes are not completed before entering Self Refresh for S1/S3.
1 = All Pending Refreshes plus one extra is performed before entering Self Refresh for S1/S3.
4.9.16 DRC – DRAM Controller Mode Register (Device #0)

Access: RO, Read/Write
Size: 32 bits
Bit Description
31:30 Revision Number (REV): Reflects the revision number of the format used for DDR SDRAM register
definition (Read Only).
29 Initialization Complete (IC): This bit is used for communication of software state between the Memory
Controller and the BIOS. BIOS sets this bit to 1 after initialization of the DDR SDRAM Memory Array is
complete. Setting this bit to a 1 enables DDR SDRAM Refreshes. On power up and S3 exit, the BIOS
initializes the DDR SDRAM array and sets this bit to a 1. This bit works in combination with the RMS bits
in controlling Refresh state:
IC Refresh State
0 OFF
1 ON
28:24 Reserved
23:22 Number of Channels (CHAN): Reflects that GMCH supports only one system memory channel.
00 One channel is populated appropriately
Others: Reserved
21:20 DDIM DDR SDRAM Data Integrity Mode:
00: No-ECC. No read-merge-write on partial writes. ECC data sense-amps are disabled and the data
output
is tristate (Default).
01: ECC
XX: Reserved
Datasheet 99
Bit Description
19:16 Reserved
15 RAS Lock-Out Enable: Set to a 1 if all populated rows support RAS Lock-Out. Defaults to 0.
If this bit is set to a 1 the DDR SDRAM Controller assumes that the DDR SDRAM guarantees tRAS min
before an auto precharge (AP) completes (Note: An AP is sent with a Read or a Write command). Also,
the DDR SDRAM Controller does not issue an activate command to the auto pre-charged bank for tRP.
If this bit is set to a 0 the DDR SDRAM Controller does not schedule an AP if tRAS min is not met.
14:13 Reserved
12 Address Tri-state enable (ADRTRIEN): When set to a 1, the SDRAM Controller will tri-state the MA,
CMD, and CS# (only when all CKEs are deasserted). Note that when CKE to a row is deasserted, fast
chip select assertion is not permitted by the hardware. CKEs deassert based on Idle Timer and/or max
row count control.
0:- Address Tri-state Disabled
1:- Address Tri-state Enabled
11:10 Reserved
9:7 Refresh Mode Select (RMS): This field determines whether Refresh is enabled and, if so, at what rate
Refreshes will be executed.
000: Refresh disabled
001: Refresh enabled. Refresh interval 15.6 µsec
010: Refresh enabled. Refresh interval 7.8 µsec
011: Reserved.
111: Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other: Reserved
Any change in the programming of this field Resets the Refresh counter to zero. This function is for
testing purposes, it allows test program to align refresh events with the test and thus improve failure
repeatability.
6:4 Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM Interface. The
special modes are intended for initialization at power up.
000: Post Reset State – When the GMCH exits Reset (power-up or otherwise), the mode select field is
cleared to 000. Software is not expected to Write this value, however if this value is Written, there are no
side effects (no Self Refresh or any other special DDR SDRAM cycle).
During any Reset sequence, while power is applied and Reset is active, the GMCH deasserts all CKE
signals. After internal Reset is deasserted, CKE signals remain deasserted until this field is written to a
value different than 000. On this event, all CKE signals are asserted.
During Suspend (S3, S4), GMCH internal signal triggers DDR SDRAM Controller to flush pending
commands and enter all rows into Self-Refresh mode. As part of Resume sequence, GMCH will be
Reset , which will clear this bit field to 000 and maintain CKE signals deasserted. After internal Reset is
deasserted, CKE signals remain deasserted until this field is Written to a value different than 000. On this
event, all CKE signals are asserted.
During Entry to other low power states (C3, S1-M), GMCH internal signal triggers DDR SDRAM
Controller to flush pending commands and enter all rows in S1 and relevant rows in C3 (Based on
RPDNC3) into Self-Refresh mode. During exit to Normal mode, the GMCH signal triggers DDR SDRAM
Controller to Exit Self-Refresh and Resume Normal operation without S/W involvement.
001: NOP Command Enable – All CPU cycles to DDR SDRAM result in a NOP command on the DDR
SDRAM interface.
010: All Banks Pre-charge Enable – All CPU cycles to DDR SDRAM result in an All Banks Precharge
command on the DDR SDRAM interface.
100 Datasheet
Bit Description
011: Mode Register Set Enable – All CPU cycles to DDR SDRAM result in a Mode Register set
command on the DDR SDRAM Interface. Host address lines are mapped to DDR SDRAM address lines
in order to specify the command sent. Host address HA[13:3] are mapped to Memory address
SMA[11,9:0]. SMA3 must be driven to 1 for interleave wrap type.
For Double Data Rate

MA[6:4] needs to be driven based on the value programmed in the CAS# Latency field.
CAS Latency MA[6:4]
1.5 Clocks 001
2.0 Clocks 010
2.5 Clocks 110
SMA[7] should always be driven to a 0.

SMA[8] Should be driven to a 1 for DLL Reset and 1 for Normal Operation.
SMA[12:9] must be driven to 00000.
BIOS must calculate and drive the correct host address for each row of Memory such that the correct
command is driven on the SMA[12:0] lines. Note that SMAB[5,4,2,1]# are inverted from SMA[5,4,2,1];
BIOS must account for this.
100: Extended Mode Register Set Enable – All CPU cycles to DDR SDRAM result in an “Extended
Mode register set” command on the DDR SDRAM Interface. Host address lines are mapped to DDR
SDRAM address lines in order to specify the command sent. Host address lines are mapped to DDR
SDRAM address lines in order to specify the command sent. Host address HA[13:3] are mapped to
Memory address SMA[11,9:0]. SMA[0] = 0 for DLL enable and 1 for DLL disable. All the other SMA lines
are driven to 0’s. Note that SMAB[5,4,2,1]# are inverted from SMA[5,4,2,1]; BIOS must account for this.
101: Reserved
110: CBR Refresh Enable – In this mode all CPU cycles to DDR SDRAM result in a CBR cycle on the
DDR SDRAM interface
111: Normal operation
3:0 Reserved
4.9.17 DTC – DRAM Throttling Control Register (Device #0)

Offset Address: A0–A3h
Access: Read/Write/Lock
Size: 32 bits
Throttling is independent for system memory banks, GMCH Writes, and Thermal Sensor Trips.
Read and Write Bandwidth is measured independently for each bank. If the number of Octal -
Words (16 bytes) Read/Written during the window defined below (Global DDR SDRAM
Sampling Window: GDSW) exceeds the DDR SDRAM Bandwidth Threshold, then the DDR
SDRAM Throttling mechanism will be invoked to limit DDR SDRAM Reads/Writes to a lower
bandwidth checked over smaller time windows. The throttling will be active for the remainder of
the current GDSW and for the next GDSW after which it will return to Non-Throttling mode. The
throttling mechanism accounts for the actual bandwidth consumed during the sampling window,
by reducing the allowed bandwidth within the smaller throttling window based on the bandwidth
Datasheet 101
consumed during the sampling period. Although bandwidth from/to independent rows and
GMCH Write bandwidth is measured independently, once Tripped all transactions except high
priority graphics Reads are subject to throttling.
Bit Description
31:28 DDR SDRAM Throttle Mode (TMODE):
Four bits control which mechanisms for Throttling are enabled in an “OR” fashion. Counter-based
Throttling is lower priority than Thermal Trips Throttling when both are enabled and Tripped. Counter-
based trips point Throttling values and Thermal-based Trip Point Throttling values are specified in this
register.
If the counter and thermal mechanisms for either Rank or GMCH are both enabled, Throttle settings
for the one that Trips first is used until the end of the second gdsw.
[Rank Counter, GMCH Write Counter, Rank Thermal Sensor, GMCH Thermal Sensor]
0000 = Throttling turned off. This is the default setting. All Counters are off.
0001 = Only GMCH Thermal Sensor based Throttling is enabled. If GMCH Thermal Sensor is
Tripped, Write Throttling begins based on the setting in WTTC.
0010 = Only Rank Thermal Sensor based Throttling is enabled. When the external SO-DIMM
Thermal sensor is Tripped, DDR SDRAM Throttling begins based on the setting in RTTC.
0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the external SO-
DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on the setting in RTTC. If the
GMCH Thermal Sensor is Tripped, Write Throttling begins based on the setting in WTTC.
0100 = Only the GMCH Write Counter mechanism is enabled. When the length of write transfers
programmed (GDSW * WCTC) is reached, DRAM throttling begins based on the setting in WCTC..
0101 = GMCH Thermal Sensor and GMCH Write DDR SDRAM Counter mechanisms are both
enabled. If the GMCH Write DDR SDRAM Counter mechanism threshold is reached, DDR SDRAM
Throttling begins based on the setting in WCTC. If the GMCH Thermal Sensor is tripped, DDR
SDRAM Throttling begins based on the setting in WTTC. If both threshold mechanisms are tripped,
the DDR SDRAM Throttling begins based on the settings in WTTC.
0110 = Rank Thermal Sensor and GMCH Write DDR SDRAM Counter mechanisms are both
enabled. If the GMCH Write DDR SDRAM Counter mechanism threshold is reached, DDR SDRAM
Throttling begins based on setting in WCTC. If the external SO-DIMM Thermal Sensor is tripped, Rank
DDR SDRAM throttling begins based on the setting in RTTC.
0111 = Similar to 0101 for Writes and when the Rank Thermal Sensor is tripped, DDR SDRAM
Throttling begins based on the setting in RTTC.
1000 = Only Rank Counter mechanism is enabled. When the length of read transfers programmed
(GDSW * RCTC) is reached, DRAM throttling begins based on the setting in RCTC
1001 = Rank Counter mechanism is enabled and GMCH Thermal Sensor based throttling are both
enabled. If GMCH thermal sensor is tripped, write throttling begins based on the setting in WTTC. If
the rank counter mechanism is tripped, DRAM throttling begins based on the setting in RCTC.
1010 = Rank Thermal Sensor and Rank DDR SDRAM Counter mechanisms are both enabled. If the
rank DDR SDRAM Counter mechanism threshold is reached, DDR SDRAM Throttling begins based
on the setting in RCTC. If the external SO-DIMM Thermal Sensor is tripped, DRAM Throttling begins
based on the setting in RTTC.
1011 = Similar to 1010 and if the GMCH Thermal Sensor is tripped, Write Throttling begins based
on the setting in WTTC.
1111 = Rank and GMCH Thermal Sensor based Throttling and Rank and GMCH Write Counter
based Throttling are enabled. If both the Write Counter and GMCH Thermal Sensor based
mechanisms are tripped, DDR SDRAM Throttling begins based on the setting allowed in WTTC. If
both the Rank Counter and Rank Thermal Sensor based mechanisms are tripped, DDR SDRAM
Throttling begins based on the setting allowed in RTTC.
102 Datasheet
Bit Description
27:24 Read Counter Based Power Throttle Control (RCTC): These bits select the Counter based Power
Throttle Bandwidth Limits for Read operations to system memory.
R/W, RO if Throttle Lock.
0h = 85%
1h = 70%
2h = 65%
3h = 60%
4h = 55%
5h = 50%
6h = 45%
7h = 40%
8h = 35%
9h = 30%
Ah = 20%
B-Fh = Reserved
23:20 Write Counter Based Power Throttle Control (WCTC): These bits select the counter based Power
Throttle Bandwidth Limits for Write operations to system memory.
R/W, RO if Throttle Lock
0h = 85%
1h = 70%
2h = 65%
3h = 60%
4h = 55%
5h = 50%
6h = 45%
7h = 40%
8h = 35%
9h = 30%
Ah = 20%
B-Fh = Reserved
Datasheet 103
Bit Description
19:16 Read Thermal Based Power Throttle Control (RTTC): These bits select the Thermal Sensor based
Power Throttle Bandwidth Limits for Read operations to system memory.
R/W, RO if Throttle Lock.
0h = 85%
1h = 70%
2h = 65%
3h = 60%
4h = 55%
5h = 50%
6h = 45%
7h = 40%
8h = 35%
9h = 30%
Ah = 20%
B-Fh = Reserved
15:12 Write Thermal Based Power Throttle Control (WTTC): These bits select the Thermal based Power
Throttle Bandwidth Limits for Write operations to system memory.
R/W, RO if Throttle Lock
0h = 85%
1h = 70%
2h = 65%
3h = 60%
4h = 55%
5h = 50%
6h = 45%
7h = 40%
8h = 35%
9h = 30%
Ah = 20%
B-Fh = Reserved
11 Counter Based Throttle Lock (CTLOCK): This bit secures RCTC and WCTC. This bit defaults to 0.
Once a 1 is written to this bit, RCTC and WCTC (including CTLOCK) become Read-Only.
10 Thermal Throttle Lock (TTLOCK): This bit secures the DDR SDRAM Throttling Control register. This
bit defaults to 0. Once a 1 is written to this bit, all of the configuration register bits in DTC (including
TTLOCK) except CTLOCK, RCTC and WCTC become Read-Only.
9 Thermal Power Throttle Control fields Enable:
0 = RTTC and WTTC are not used. RCTC and WTCT are used for both Counter and Thermal based
Throttling.
1 = RTTC and WTTC are used for Thermal based Throttling.
104 Datasheet
Bit Description
8 High Priority Stream Throttling Enable:
Normally High Priority Streams are not Throttled when either the counter based mechanism or
Thermal Sensor mechanism demands Throttling.
0 = Normal operation.
1 = Block High priority streams during Throttling.
7:0 Global DDR SDRAM Sampling Window (GDSW): This 8-bit value is multiplied by 4 to define the
length of time in milliseconds (0–1020) over which the number of Octal Words (16 bytes) Read/Written
is counted and Throttling is imposed. Note that programming this field to 00h disables system memory
throttling.
Recommended values are between 0.25 and 0.75 seconds.
4.10 Intel® 855GM/GME GMCH Configuration Process

Registers (Device #0, Function #3)
See Section 4.2 for access nomenclature. Table 28 summarizes all Device#0, Function #3
registers.
Table 28. Configuration Process Configuration Space (Device#0, Function #3)
Register Register Register

Register Name Default Value Access
Symbol Start End
HPLL Clock Control HPLLCC C0 C1 00h RO
Datasheet 105

the Device Identification register uniquely identifies any PCI device. Writes to this register have
no effect.
Bit Description
15:0 Vendor Identification (VID): This register field contains the PCI standard identification for 8086h.

Access: Read Only
Size: 16 bits
Bit Description
15:0 Device Identification Number (DID): This is a 16-bit value assigned to the Intel 855GM/GME GMCH
Host-HI Bridge Function #3 (3585h).

Size: 16 bits
Since Intel 855GM/GME GMCH Device #0 does not physically reside on PCI_A many of the bits
are not implemented.
Bit Description
15:10 Reserved
8 SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the GMCH and this
bit is hardwired to 0. Writes to this bit position have no effect.
106 Datasheet
Bit Description
4 Memory Write and Invalidate Enable (MWIE): The GMCH will never issue Memory Write and
Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect.
1 Memory Access Enable (MAE): The GMCH always allows access to Main Memory. This bit is not
implemented and is hardwired to 1. Writes to this bit position have no effect.
4.10.4 PCISTS – PCI Status Register

Size: 16 bits
Interface. Bit 14 is Read/Write clear. All other bits are Read Only. Since GMCH Device #0 does
not physically reside on PCI_A many of the bits are not implemented.
Bit Description
14 Signaled System Error (SSE): The GMCH does not implement this bit and it is hardwired to a 0.
13 Received Master Abort Status (RMAS): The GMCH does not implement this bit and it is hardwired to
a 0. Writes to this bit position have no effect.
12 Received Target Abort Status (RTAS): The GMCH does not implement this bit and it is hardwired to a
11 Signaled Target Abort Status (STAS): The GMCH does not implement this bit and it is hardwired to a
10:9 DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit positions have no affect.
Device #0 does not physically connect to PCI_A. These bits are set to "00" (fast decode) so that the
8 Master Data Parity Error Detected (DPD): The GMCH does not implement this bit and it is hardwired
6:5 Reserved
device/function does not implement new capabilities.
3:0 Reserved
Datasheet 107
4.10.5 RID – Revision Identification Register

Address Offset: 08h
Default Value: 02h
Access: Read Only
Size: 8 bits
This register contains the revision number of the Intel 855GM/GME GMCH. These bits are Read
Only and Writes to this register have no effect.
Bit Description
number for the GMCH.
4.10.6 SUBC – Sub-Class Code Register

Address Offset: 0Ah
Default Value: 80h
Access: Read Only
Size: 8 bits
This register contains the Sub-Class Code for the Intel 855GM/GME GMCH Device #0. This
code is 80h indicating a peripheral device.
Bit Description
7:0 Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which GMCH
falls. The code is 80h indicating other peripheral device.

Address Offset: 0Bh
Default Value: 08h
Access: Read Only
Size: 8 bits
This register contains the Base Class Code of the Intel 855GM/GME GMCH Device #0 Function
#3. This code is 08h indicating a peripheral device.
Bit Description
7:0 Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class code for the GMCH.
This code has the value 08h, indicating other peripheral device.
108 Datasheet

Address Offset: 0Eh
Default Value: 80h
Access: Read Only
Size: 8 bits
this location.
Bit Description
7:0 PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device. If
Functions other than #0 are disabled this field returns a 00 to indicate that the GMCH is a single
function device with standard header layout. The default is 80 Reads and Writes to this location have no
effect.

Size: 16 bits
Bit Description
vendor of the system board. After it has been Written once, it becomes Read Only.
4.10.10 ID – Subsystem Identification Register

Size: 16 bits
Bit Description
Written once, it becomes Read Only.
Datasheet 109

Address Offset: 34h
Default Value: 00h
Access: Read Only
Size: 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in
the capability list.
Bit Description
7:0 Pointer to the offset of the first capability ID register block: In this case there are no capabilities
therefore these bits are hardwired to 00h to indicate the end of the capability-linked list.
4.10.12 HPLLCC – HPLL Clock Control Register (Device #0)

Address Offset: C0–C1h
Default Value: 00h
Access: Read Only
Size: 16 bits
Bit Description
15:11 Reserved
10 HPLL VCO Change Sequence Initiate Bit:
Software must Write a 0 to clear this bit and then Write a 1 to initiate sequence again.
9 Hphase Reset Bit:
1 = Assert
0 = Deassert (default)
8 Reserved
7:2 Reserved
1:0 HPLL Clock Control:
Software is allowed to update this register.
See
Table 29 below.
110 Datasheet
Table 29. Intel® 855GM GMCH Configurations and Some Resolution Examples
Straps Read FSB System GFX Core LVDS Port DVO Port CRT Port
Through Rate Memory Clock(Low)
HPLLCC[2:0]: Frequency
D0:F3:Regist
er Offset C0- GFX Core
C1h, bits[2:0] Clock
(High)
000 400 266 MHz 133 MHz 1400x1050 @ 60 1400x1050@75 Hz 1400x1050@ 85 Hz

MHz Hz DCLK = 155 MHz DCLK = 177 MHz
DCLK = 108 MHz
1600x1200@60 Hz 1600x1200@85-Hz
DCLK = 162 MHz DCLK = 229 MHz
200 MHz 1600x1200 @ 60 1600x1200@85 Hz 1600x1200@85-Hz

Hz DCLK = 229- MHz DCLK = 229 MHz
DCLK = 162 MHz
2048x1536@72 Hz 2048x1536@75 Hz
001 400 200 MHz 100 MHz 1024x768 @ 60 Hz 1400x1050@85 Hz 1400x1050@ 85 Hz
MHz DCLK = 65 MHz DCLK = 177 MHz DCLK = 177 MHz
1920x1080@60 Hz 1920x1080@ 60 Hz
200 MHz 1600x1200 @ 60 1600x1200@85 Hz 1600x1200@85 Hz
Hz DCLK = 229 MHz DCLK = 229 MHz
DCLK = 162 MHz
2048x1536@72 Hz 2048x1536@75 Hz
010 400 200 MHz 100 MHz 1024x768 @ 60 Hz 1400x1050@85 Hz 1400x1050@ 85 Hz
MHz DCLK = 65 MHz DCLK = 177 MHz DCLK = 177 MHz
1920x1080@60 Hz 1920x1080@ 60 Hz
133 MHz 1400x1050 @ 60 1400x1050@75-Hz 1400x1050@85 Hz
Hz DCLK = 155 MHz DCLK = 177 MHz
DCLK = 108 MHz
1600x1200@60 Hz 1600x1200@85 Hz
Datasheet 111
Table 30. For Intel® 855GME GMCH Configurations and Some Resolution Examples
Straps Read FSB System GFX Core LVDS Port DVO Port VGA Port
Through Rate Memory Clock(Low)
HPLLCC[2:0]: Frequency
D0:F3:Register
Offset C0-C1h, GFX Core
bits[2:0] Clock (High)
000 400 266 MHz 133 MHz N/A N/A N/A

MHz
200 MHz 1600x1200@6 1600x1200@ 85 1600x1200@85
0 Hz Hz Hz
DCLK = 162 DCLK = 229 MHz DCLK = 229 MHz

MHz
2048x1536@ 72 2048x1536 @ 75
Hz Hz
001 400 200 MHz 100 MHz N/A N/A N/A

MHz
200 MHz 1600x1200 1600x1200@85H 1600x1200 @ 85
@60 Hz z Hz

MHz
2048x1536 @ 72 2048x1536
Hz @75Hz
010 400 200 MHz 100 MHz N/A N/A N/A

MHz
133 MHz 1400x1050@6 1400x1050 @ 75 1400x1050@ 85
0Hz Hz Hz

MHz
1600x1200 @ 60 1600x1200 @ 85
Hz Hz
111 400 333 MHz 166 MHz N/A N/A N/A

MHz
250 MHz 1600x1200@6 1600x1200 @ 85 1600x1200 @ 85
0Hz Hz Hz

MHz
2048x1536@ 72 2048x1536@ 75
Hz Hz
Note: The maximum calculated display pipe dot clocks were used to select supporting
resolutions/refresh rates from the VESA table. Memory bandwidth, simultaneous functions, and
VGA mode support were not accounted for in determining the resolutions supported. In all cases,
only single pipe was used to determine the resolution supported – LVDS is only supported on a
Single Wide Pipe B, and DVO and VGA resolution.
112 Datasheet
4.11 Intel® 852GM GMCH Integrated Graphics Device

Registers (Device #2, Function #0)
This section contains the PCI configuration registers listed in order of ascending offset address.
Device #2 incorporates Function #0. See Section 4.2 for access nomenclature.
Note: C0F0 = Copy of Function #0 and U1F1 = Unique in Function #1.
Table 31. Integrated Graphics Device Configuration Space (Device #2, Function#0)
Register Name Register Address Register Default Access Regs in

Symbol Offset End Value Function#1
Vendor Identification VID 00h 01h 8086h RO C0F0
Device Identification DID 02h 03h 3582h RO C0F0
PCI Command PCICMD 04h 05h 0000h RO,R/W U1F1
PCI Status PCISTS 06h 07h 0090h RO U1F1
Revision Identification RID 08h 08h 02h RO C0F0
Class Code CC 09h 0Bh 030000h RO U1F1
Cache Line Size CLS 0Ch 0Ch 00h RO C0F0
Master Latency Timer MLT 0Dh 0Dh 00h RO C0F0
Header Type HDR 0Eh 0Eh 00h RO C0F0
Graphics Memory Range GMADR 10h 13h 00000008h RO,R/W U1F1

Address
Memory Mapped Range MMADR 14h 17h 00000000h RO,R/W U1F1

Address
IO Range IOBAR 18h 1Bh 00000001h RO,R/W ⎯
Subsystem Vendor ID SVID 2Ch 2Dh 0000h R/WO C0F0
Subsystem ID SID 2Eh 2Fh 0000h R/ WO C0F0
Video Bios ROM Base ROMADR 30h 33h 00000000h RO C0F0

Address
Interrupt Line INTRLINE 3Ch 3Ch 00h RO in F ⎯

#1,R/W
Interrupt Pin INTRPIN 3Dh 3Dh 01h RO, ⎯

Reserved In
F#1
Minimum Grant MINGNT 3Eh 3Eh 00h RO C0F0
Maximum Latency MAXLAT 3Fh 3Fh 00h RO C0F0
Power Management PMCAP D2h D3h 0221h RO C0F0

Capabilities
Power Management PMCS D4h D5h 0000h RO,R/W U1F1

Control
Datasheet 113
4.11.1 VID – Vendor Identification Register (Device #2)

Address Offset: 00−01h
Access Attributes: Read Only
Size: 16 bits
the Device Identification Register uniquely identifies any PCI device. Writes to this register have
no effect.
Bit Description
15:0 Vendor Identification Number: This is a 16-bit value assigned to Intel.
4.11.2 DID – Device Identification Register (Device #2)

Access Attributes: Read Only
Size: 16 bits
Bit Description
15:0 Device Identification Number: This is a 16-bit value assigned to the GMCH IGD (3582h).
4.11.3 PCICMD – PCI Command Register (Device #2)

Default: 0000h
Size: 16 bits
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD register in the IGD disables the IGD PCI compliant master accesses to main system
memory.
Bit Description
15:10 Reserved
9 Fast Back-to-Back (FB2B)⎯RO
8 SERR# Enable (SERRE) ⎯RO
7 Address/Data Stepping⎯RO
6 Parity Error Enable (PERRE) ⎯RO
5 Video Palette Snooping (VPS) ⎯RO
4 Memory Write and Invalidate Enable (MWIE) ⎯RO
3 Special Cycle Enable (SCE) ⎯RO
114 Datasheet
Bit Description
2 Bus Master Enable (BME) ⎯R/W: This bit determines if the IGD is to function as a PCI compliant
master.
0= Disable IGD bus mastering (default).
1 = Enable IGD bus mastering.
1 Memory Access Enable (MAE) ⎯R/W: This bit controls the IGD’s response to System Memory Space
accesses.
0= Disable (default).
1 = Enable.
0 I/O Access Enable (IOAE) ⎯R/W: This bit controls the IGD’s response to I/O Space accesses.
0 = Disable (default).
1 = Enable.
4.11.4 PCISTS – PCI Status Register (Device #2)

Access: Read Only
Size: 16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and
PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the
IGD.
Bit Description
15 Detected Parity Error (DPE): Since the IGD does not detect parity, this bit is always set to 0.
14 Signaled System Error (SSE) – RO
13 Received Master Abort Status (RMAS) – RO
12 Received Target Abort Status (RTAS) – RO
11 Signaled Target Abort Status (STAS) – RO
10:9 DEVSEL# Timing (DEVT) – RO
8 Data Parity Detected (DPD) – RO
7 Fast Back-to-Back (FB2B) – RO
6 User Defined Format (UDF) – RO
5 66 MHz PCI Capable (66C) – RO
4 CAP LIST: This bit is set to 1 to indicate that the register at 34h provides an offset into the Function’s PCI
Configuration Space containing a pointer to the location of the first item in the list.
3:0 Reserved
Datasheet 115
4.11.5 RID – Revision Identification Register (Device #2)

Address Offset: 08h
Default Value: 02h
Access: Read Only
Size: 8 bits
This register contains the revision number of the IGD. These bits are Read Only and Writes to
this register have no effect.
Bit Description
7:0 Revision Identification Number: This is an 8-bit value that indicates the revision identification number for
the GMCH.
4.11.6 CC – Class Code Register (Device #2)

Address Offset: 09−0Bh
Access: Read Only
Size: 24 bits
This register contains the device programming interface information related to the Sub-Class code
and Base Class code definition for the IGD. This register also contains the Base Class code and
the function sub-class in relation to the Base Class code.
Bit Description
23:16 Base Class Code (BASEC): 03=Display controller
15:8 Sub-Class Code (SCC):
Function 0: 00h=VGA compatible or 80h=Non VGA
Function 1: 80h=Non VGA
7:0 Programming Interface (PI): 00h=Hardwired as a Display controller.
4.11.7 CLS – Cache Line Size Register (Device #2)

Address Offset: 0Ch
Default Value: 00h
Access: Read only
Size: 8 bits
The IGD does not support this register as a PCI slave.
Bit Description
7:0 Cache Line Size (CLS) – RO
116 Datasheet
4.11.8 MLT – Master Latency Timer Register (Device #2)

Address Offset: 0Dh
Default Value: 00h
Access: Read Only
Size: 8 bits
The IGD does not support the programmability of the master latency timer because it does not
perform bursts.
Bit Description
7:0 Master Latency Timer Count Value – RO
4.11.9 HDR – Header Type Register (Device #2)

Address Offset: 0Eh
Default Value: 00h
Access: Read Only
Size: 8 bits
This register contains the Header Type of the IGD.
Bit Description
7 Multi Function Status (MFunc): Indicates if the device is a multi-function device.
6:0 Header Code (H): This is a 7-bit value that indicates the Header code for the IGD. This code has the
value 00h, indicating a type 0 configuration space format.
4.11.10 GMADR – Graphics Memory Range Address Register

(Device #2)
Access: Read/Write, Read Only
Size: 32 bits
IGD graphics system memory base address is specified in this register.
Bit Description
31:27 Memory Base Address⎯R/W: Set by the OS, these bits correspond to address signals [31:26].
26 128-MB Address Mask – RO: 0 indicates 128-MB address
25:4 Address Mask⎯RO: Indicates (at least) a 32-MB address range.
3 Prefetchable Memory⎯RO: Enable prefetching.
2:1 Memory Type⎯RO: Indicate 32-bit address.
0 Memory/IO Space⎯RO: Indicate System Memory Space.
Datasheet 117
4.11.11 MMADR – Memory Mapped Range Address Register

(Device #2)
Size: 32 bits
This register requests allocation for the IGD registers and instruction ports. The allocation is for
512-kB and the base address is defined by bits [31:19].
Bit Description
31:19 Memory Base Address⎯R/W: Set by the OS, these bits correspond to address signals [31:19].
18:4 Address Mask⎯RO: Indicate 512-kB address range.
3 Prefetchable Memory⎯RO: Prevents prefetching.
2:1 Memory Type⎯RO: Indicates 32-bit address.
0 Memory / IO Space⎯RO: Indicates System Memory space.
4.11.12 IOBAR – I/O Base Address Register (Device #2)

Address offset: 18-1Bh
Default: 00000001h
Access: Read/Write
Size: 16-bits
This register provides the Base offset of the I/O registers within Device #2. Bits 15:3 are
programmable allowing the I/O Base to be located anywhere in 16-bit I/O Address Space. Bits 2:1
are fixed and return zero, bit 0 is hardwired to a one indicating that 8-bytes of I/O space are
decoded.
Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set.
Access is disallowed in PM states D1-D3 or if IO Enable is clear or if Device #2 is turned off or if
internal graphics is disabled. Note that access to this IO BAR is independent of VGA
functionality within Device #2. Also note that this mechanism is available only through Function
#0 of Device#2 and is not duplicated in Function #1.
If accesses to this I/O bar are allowed, then the GMCH claims all 8-bit, 16-bit, or 32-bit I/O
cycles from the CPU that falls within the 8B claimed.
Bit Description
31:16 Reserved
15:3 IO Base Address⎯R/W: Set by the OS, these bits correspond to address signals [15:3].
2:1 Memory Type⎯RO: Indicates 32-bit address.
0 Memory / IO Space⎯RO
118 Datasheet
4.11.13 SVID – Subsystem Vendor Identification Register (Device

#2)
Address Offset: 2C−2Dh
Size: 16 bits
Bit Description
15:0 Subsystem Vendor ID: This value is used to identify the vendor of the subsystem. This register should
be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register
can only be cleared by a reset.
4.11.14 SID – Subsystem Identification Register (Device #2)

Address Offset: 2E−2Fh
Size: 16 bits
Bit Description
15:0 Subsystem Identification: This value is used to identify a particular subsystem. This field should be
programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can
only be cleared by a reset.
4.11.15 ROMADR – Video BIOS ROM Base Address Registers

(Device #2)
Access: Read Only
Size: 32 bits
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0’s.
Bit Description
31:18 ROM Base Address⎯RO
17:11 Address Mask⎯RO: Indicates 256-kB address range.
10:1 Reserved
0 ROM BIOS Enable⎯RO: Indicates ROM not accessible.
Datasheet 119
4.11.16 INTRLINE – Interrupt Line Register (Device #2)

Address Offset: 3Ch
Default Value: 00h
Access: Read/Write
Size: 8 bits
Bit Description
7:0 Interrupt Connection: Used to communicate interrupt line routing information. POST software Writes
the routing information into this register as it initializes and configures the system. The value in this
register indicates which input of the System Interrupt controller that the device’s interrupt pin is connected
to.
4.11.17 INTRPIN – Interrupt Pin Register (Device #2)

Address Offset: 3Dh
Default Value: 01h
Access: Read Only
Size: 8 bits
Bit Description
7:0 Interrupt Pin: As a single function device, the IGD specifies INTA# as its interrupt pin. 01h=INTA#. For
Function #1, this register is set to 00h.
4.11.18 MINGNT – Minimum Grant Register (Device #2)

Address Offset: 3Eh
Default Value: 00h
Access: Read Only
Size: 8 bits
Bit Description
7:0 Minimum Grant Value: The IGD does not burst as a PCI compliant master.
4.11.19 MAXLAT – Maximum Latency Register (Device #2)

Address Offset: 3Fh
Default Value: 00h
Access: Read Only
Size: 8 bits
Bit Description
7:0 Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it needs to
access the PCI bus.
120 Datasheet
4.11.20 PMCAP – Power Management Capabilities Register (Device

#2)
Address Offset: D2h−D3h
Access: Read Only
Size: 16 bits
Bit Description
15:11 PME Support: This field indicates the power states in which the IGD may assert PME#. Hardwired to 0
to indicate that the IGD does not assert the PME# signal.
10:6 Reserved
5 Device Specific Initialization (DSI): Hardwired to 1 to indicate that special initialization of the IGD is
required before generic class device driver is to use it.
4 Auxiliary Power Source: Hardwired to 0.
3 PME Clock: Hardwired to 0 to indicate IGD does not support PME# generation.
2:0 Version: Hardwired to 001b to indicate there are 4 bytes of power management registers implemented.
4.11.21 PMCS – Power Management Control/Status Register

(Device #2)
Address Offset: D4h−D5h
Size: 16 bits
Bit Description
15 PME_Status ⎯RO: This bit is 0 to indicate that IGD does not support PME# generation from D3 (cold).
14:9 Reserved
8 PME_En⎯RO: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
7:2 Reserved
1:0 PowerState⎯R/W: This field indicates the current power state of the IGD and can be used to set the
IGD into a new power state. If software attempts to Write an unsupported state to this field, Write
operation must complete normally on the bus, but the data is discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally Reset to initial values.
Bits[1:0] Power State
00 D0 Default
01 D1
10 D2 Not Supported
11 D3
Datasheet 121
122 Datasheet
Intel® 855GM/GME GMCH System Address Map
5 Intel® 855GM/GME GMCH System

Address Map
A system based on the GMCH supports 4 GB of addressable system memory space and
64 kB+3B of addressable I/O space. The I/O and system memory spaces are divided by system
configuration software into regions. The system memory ranges are useful either as system
memory or as specialized system memory, while the I/O regions are used solely to control the
operation of devices in the system.
When the GMCH receives a Write request whose address targets an invalid space, the data is
ignored. For Reads, the GMCH responds by returning all zeros on the requesting interface.
5.1 System Memory Address Ranges

The GMCH provides a maximum system memory of 2-GB. The GMCH does not remap APIC
memory space and does not limit DDR SDRAM space in hardware. It is the BIOS or system
designer’s responsibility to limit system memory population so that adequate PCI High
BIOS and APIC memory space can be allocated. Figure 6 and Figure 7 depict the system
memory address map in a simplified form and provide details on mapping specific system
memory regions as defined and supported by the GMCH.
Datasheet 123
Figure 6. Simplified View of System Address Map
4 GB
PCI
Mem ory
Address Graphic
Range ( Local)
Memory
Top of the
M ain Mem ory
Main Independently
Mem ory Program mable
Address Non-Overlapping
Range Mem ory W indows
0
GMCH System Memory Space
124 Datasheet
Figure 7. Detailed View of System Address Map
4 GB max
TOM 0FFFFFh SBIOS 1 MB
Upper
BIOS Area
0F0000h (64 kB)
Extended 960 kB
0EFFFFh SBIOS Lower
PCI Memory
BIOS Area ( 64
Range 0E0000h kB) 16 kB x 4
1 GB 0DFFFFh
Expansion 896 kB
Card
16 MB BIOS and
Buffer Area
Optional ISA (128 kB)
Hole 16 kBx8
15 MB
0C0000h
0BFFFFh
Standard 768 kB
PCI/ISA
DOS Video
Memory
Compatibility (SMM
1 MB Memory Memory)
128 kB
DOS
Compatibility 0A0000h 640 kB
Memory 640 kB 09FFFFh
DOS Area
0B
000000h
5.2 DOS Compatibility Area

This compatibility region is divided into the following address regions:
• 0 – 640-kB DOS Area
• 640 – 768-kB Video Buffer Area
• 768 – 896 kB in 16-kB sections (total of eight sections) - expansion area
• 896 – 960 kB in 16-kB sections (total of four sections) - extended system BIOS area
• 960 kB – 1-MB system BIOS area
There are 16 system memory segments in the compatibility area. Thirteen of the system memory
ranges can be enabled or disabled independently for both Read and Write cycles.
Datasheet 125
Table 32. System Memory Segments and Their Attributes
System Memory Attributes Comments

Segments
000000H - 09FFFFH Fixed - always mapped to main 0 to 640 kB – DOS Region

DDR SDRAM
0A0000H - 0BFFFFH Mapped to Hub interface or IGD - Video Buffer (physical DDR SDRAM
configurable as SMM space configurable as SMM space)
0C0000H - 0C3FFFH WE(Write Enable) RE (Read Add-on BIOS

Enable)
0C4000H - 0C7FFFH WE RE Add-on BIOS
0C8000H - 0CBFFFH WE RE Add-on BIOS
0CC000H - 0CFFFFH WE RE Add-on BIOS
0D0000H - 0D3FFFH WE RE Add-on BIOS
0D4000H - 0D7FFFH WE RE Add-on BIOS
0D8000H - 0DBFFFH WE RE Add-on BIOS
0DC000H - 0DFFFFH WE RE Add-on BIOS
0E0000H - 0E3FFFH WE RE BIOS Extension
0E4000H - 0E7FFFH WE RE BIOS Extension
0E8000H - 0EBFFFH WE RE BIOS Extension
0EC000H - 0EFFFFH WE RE BIOS Extension
0F0000H - 0FFFFFH WE RE BIOS Area
DOS Area (000000h-09FFFFh)

The DOS area is 640-kB in size and is always mapped to the main system memory controlled by
the GMCH.
Legacy VGA Ranges (0A0000h-0BFFFFh)

The legacy 128-kB VGA memory range A0000h-BFFFFh (VGA Frame Buffer) can be mapped to
IGD (Device #2) and to the Hub interface depending on the programming of the VGA steering
bits. Priority for VGA mapping is constant in that the GMCH always decodes internally mapped
devices first. Internal to the GMCH, decode precedence is always given to IGD. The GMCH
always positively decodes internally mapped devices, namely the IGD. Subsequent decoding of
regions mapped to the Hub interface depends on the Legacy VGA configurations bits (VGA
Enable and MDAP). This region is also the default for SMM space.
Compatible SMRAM Address Range (0A0000h-0BFFFFh)

When compatible SMM space is enabled, SMM-mode CPU accesses to this range are routed to
physical DDR SDRAM at this address. Non-SMM-mode CPU accesses to this range are
considered to be to the video buffer area as described above. Hub interface originated cycles to
enabled SMM space are not allowed and are considered to be to the video buffer area.
126 Datasheet
Monochrome Display Adapter (MDA) Range (0B0000h - 0B7FFFh)

Legacy support requires the ability to have a second graphics controller (monochrome) in the
system. Accesses in the standard VGA range are forwarded to IGD and the Hub interface
(depending on configuration bits). Since the monochrome adapter may be mapped to anyone of
these devices, the GMCH must decode cycles in the MDA range and forward them either to IGD
or to Hub interface. This capability is controlled by a VGA steering bits and the legacy
configuration bit (MDAP bit). In addition to the system memory range B0000h to B7FFFh, the
GMCH decodes IO cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3Bah, and 3BFh and forwards them to the
either the IGD or the Hub interface.
Expansion Area (0C0000h-0DFFFFh)

This 128-kB ISA Expansion region is divided into eight, 16-kB segments. Each segment can be
assigned one of four Read/Write states: read-only, write-only, read/write, or disabled. Typically,
these blocks are mapped through GMCH and are subtractively decoded to ISA space. System
memory that is disabled is not remapped.
Extended System BIOS Area (0E0000h-0EFFFFh)

This 64-kB area is divided into four, 16-kB segments. Each segment can be assigned independent
read and write attributes so it can be mapped either to main DDR SDRAM or to Hub interface.
Typically, this area is used for RAM or ROM. System memory segments that are disabled are not
remapped elsewhere.
System BIOS Area (0F0000h-0FFFFFh)

This area is a single 64-kB segment. This segment can be assigned Read and Write attributes. It
is by default (after Reset) Read/Write disabled and cycles are forwarded to Hub interface. By
manipulating the Read/Write attributes, the GMCH can “shadow” BIOS into the main DDR
SDRAM. When disabled, this segment is not remapped.
5.3 Extended System Memory Area

This system memory area covers 100000h (1 MB) to FFFFFFFFh (4 GB-1) address range and it
is divided into the following regions:
• Main system memory from 1 MB to the top of system memory.
• PCI Memory space from the top of system memory to 4 GB with two specific ranges.
• APIC Configuration Space from FEC0_0000h (4 GB–20 MB) to FECF_FFFFh (4 GB–19
MB -1) and FEE0_0000h (4 GB–18 MB) to FEEF_FFFFh (4 GB–17 MB-1).
• High BIOS area from 4 GB to 4 GB - 2 MB
Datasheet 127
5.4 Main System Memory Address Range (0010_0000h

to Top of Main Memory)
The address range from 1 MB to the top of main system memory is mapped to main DDR
SDRAM address range controlled by the GMCH. The GMCH will forward all accesses to
addresses within this range to the DDR SDRAM unless a hole in this range is created using the
fixed hole as controlled by the FDHC register. Accesses within this hole are forwarded to Hub
interface.
The GMCH provides a maximum DDR SDRAM address decode space of 4-GB. The GMCH
does not remap APIC memory space. The GMCH does not limit DDR SDRAM address space in
hardware.
5.4.1 15-MB – 16-MB Window

A hole can be created at 15 MB-16 MB as controlled by the fixed hole enable (FDHC register) in
Device 0 space. Accesses within this hole are forwarded to the Hub interface. The range of
physical DDR SDRAM disabled by opening the hole is not remapped to the Top of the memory –
that physical DDR SDRAM space is not accessible. This 15 MB-16 MB hole is an optionally
enabled ISA hole. Video accelerators originally used this hole. Validation and customer SV teams
also use it for some of their test cards. That is why it is being supported. There is no inherent
BIOS request for the 15-16 hole.
5.4.2 Pre-allocated System Memory

Voids of physical addresses that are not accessible as general system memory and reside within
system memory address range (< TOM) are created for SMM-mode and legacy VGA graphics
compatibility. It is the responsibility of BIOS to properly initialize these regions. The number
of UMA options has been extended. Allocation is at a fixed address in terms of rigid positioning
of UMA system memory ÆTOM-TSEG-UMA(size), but it is mapped at any available address by
a PCI allocation algorithm. GMADR and MMADR are requested through BARs.
The following table details the location and attributes of the regions.
Table 33. Pre-allocated System Memory
System Memory Segments Attributes Comments
00000000H - 03E7FFFFH R/W Available system memory 62.5 -MB
03E80000H - 03F7FFFFH R/W Pre-allocated Graphics VGA memory
1-MB (or 4/8/16/32- MB) when IGD is

enabled
03F80000H - 03FFFFFFH SMM Mode Only - CPU Reads TSEG Address Range
03F80000H - 03FFFFFFH SMM Mode Only - CPU Reads TSEG Pre-allocated system memory
128 Datasheet
5.4.2.1 Extended SMRAM Address Range (HSEG and TSEG)

The HSEG and TSEG SMM transaction address spaces reside in this extended system memory
area.
5.4.2.2 HSEG
SMM mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non-
SMM mode CPU accesses to enabled HSEG are considered invalid are terminated immediately
on the FSB. The exceptions to this rule are Non-SMM mode Write Back cycles that are remapped
to SMM space to maintain cache coherency. Hub interface originated cycles to enabled SMM
space are not allowed. Physical DDR SDRAM behind the HSEG transaction address is not
remapped and is not accessible.
5.4.2.3 TSEG
TSEG is 1-MB in size and is at the top of physical system memory. SMM mode CPU accesses to
enabled TSEG access the physical DDR SDRAM at the same address. Non-SMM mode CPU
accesses to enabled TSEG are considered invalid and are terminated immediately on the FSB. The
exceptions to this rule are Non-SMM-mode Write Back cycles that are directed to the physical
SMM space to maintain cache coherency. Hub interface originated cycles that enable SMM space
are not allowed.
The size of the SMRAM space is determined by the USMM value in the SMRAM register. When
the extended SMRAM space is enabled, non-SMM CPU accesses and all other accesses in this
range are forwarded to the Hub interface. When SMM is enabled the amount of system memory
available to the system is equal to the amount of physical DDR SDRAM minus the value in the
TSEG register.
5.4.2.4 Dynamic Video Memory Technology (DVMT)

The IGD supports DVMT in a non-graphics system memory configuration. DVMT is a
mechanism that manages system memory and the internal graphics device for optimal graphics
performance. DVMT-enabled software drivers, working with the memory arbiter and the
operating system, utilize the system memory to support 2D graphics and 3D applications. DVMT
dynamically responds to application requirements by allocating the proper amount of display and
texturing memory.
5.4.2.5 PCI Memory Address Range (Top of Main System Memory to 4 GB)
The address range from the top of main DDR SDRAM to 4-GB (top of physical system memory
space supported by the GMCH) is normally mapped via the Hub interface to PCI.
As an internal graphics configuration, there are two exceptions to this rule.

1. The first exception is addresses decoded to the graphics memory range. One per function in
device #2.
2. The second exception is addresses decoded to the system memory mapped range of the
Internal Graphics device. One per function in device #2. Both exception cases are forwarded
to the Internal Graphics device.
3. As an AGP configuration, there are two exceptions to this rule:
Datasheet 129
⎯ Addresses decoded to the AGP Memory Window defined by the

MBASE,MLIMIT,PMBASE, and PMLIMIT registers are mapped to AGP.
⎯ Addresses decoded to the Graphics Aperture range defined by the APBASE and APSIZE
registers are mapped to the main DDR SDRAM.
There are two sub-ranges within the PCI Memory address range defined as APIC configuration
space and High BIOS Address range. As an Internal Graphics device, the Graphics Memory range
and the Memory mapped range of the Internal Graphics device MUST NOT overlap with these
two ranges. These ranges are described in detail in the following paragraphs.
5.4.2.6 APIC Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000h-

FEEF_FFFFh)
This range is reserved for APIC configuration space that includes the default I/O APIC
configuration space. The default Local APIC configuration space is FEE0_0000h to
FEEF_0FFFh.
CPU accesses to the Local APIC configuration space do not result in external bus activity since
the Local APIC configuration space is internal to the CPU. However, an MTRR must be
programmed to make the Local APIC range uncacheable (UC). The Local APIC base address in
each CPU should be relocated to the FEC0_0000h (4 GB-20 MB) to FECF_FFFFh range so that
one MTRR can be programmed to 64-kB for the Local and I/O APICs. The I/O APIC(s) usually
resides in the ICH4-M portion of the chip-set or as a stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC
will be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where x is I/O
APIC unit number 0 through F(hex). This address range will be normally mapped to Hub
interface.
The address range between the APIC configuration space and the High BIOS (FED0_0000h to
FFDF_FFFFh) is always mapped to the Hub interface.
5.4.2.7 High BIOS Area (FFE0_0000h -FFFF_FFFFh)

The top 2-MB of the Extended Memory region is reserved for System BIOS (High BIOS),
extended BIOS for PCI devices, and the A20 alias of the system BIOS. CPU begins execution
from the High BIOS after reset. This region is mapped to Hub interface so that the upper subset of
this region aliases to 16 MB to 256-kB range. The actual address space required for the BIOS is
less than 2-MB but the minimum CPU MTRR range for this region is 2-MB so that full 2-MB
must be considered.
5.4.3 System Management Mode (SMM) Memory Range

The GMCH supports the use of main system memory as System Management RAM (SMM
RAM) enabling the use of System Management mode. The GMCH supports three SMM options:
Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment
(TSEG). System Management RAM space provides a system memory area that is available for the
SMI handler’s and code and data storage. This system memory resource is normally hidden from
the system OS so that the processor has immediate access to this system memory space upon entry
to SMM. The GMCH provides three SMRAM options:
• Below 1-MB option that supports compatible SMI handlers.
130 Datasheet
• Above 1-MB option that allows new SMI handlers to execute with Write-back cacheable
SMRAM.
• Above 1-MB solutions require changes to compatible SMRAM handlers code to properly
execute above 1 MB.
Note: Hub interface is not allowed to access the SMM space.
5.4.3.1 SMM Space Restrictions

If any of the following conditions are violated the results of SMM accesses are unpredictable and
may cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• High or TSEG SMM transaction address space must not overlap address space assigned to
DDR SDRAM or to any PCI devices (including Hub interface and graphics devices). This is
a BIOS responsibility.
• Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available.
This is a BIOS responsibility.
5.4.3.2 SMM Space Definition

SMM space is defined by its addressed SMM space and its DDR SDRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the CPU to access SMM
space. DDR SDRAM SMM space is defined as the range of physical DDR SDRAM locations
containing the SMM code. SMM space can be accessed at one of three transaction address ranges:
Compatible, High, and TSEG. The Compatible and TSEG SMM space is not remapped and
therefore the addressed and DDR SDRAM SMM space is the same address range. Since the High
SMM space is remapped the addressed and DDR SDRAM SMM space is a different address
range. Note that the High DDR SDRAM space is the same as the Compatible Transaction
Address space Table 34 describes three unique address ranges:
1. Compatible Transaction Address (Adr C)
2. High Transaction Address (Adr H)
3. TSEG Transaction Address (Adr T)
These abbreviations are used later in Table 34.
Table 34. SMM Space Transaction Handling
SMM Space Enabled Transaction Address Space (Adr) DRAM Space (DRAM)
Compatible (C) A0000h to BFFFFh A0000h to BFFFFh
High (H) 0FEDA0000h to 0FEDBFFFFh A0000h to BFFFFh
TSEG (T) (TOM-TSEG_SZ) to TOM (TOM-TSEG_SZ) to TOM
Datasheet 131
5.4.4 System Memory Shadowing

Any block of system memory that can be designated as Read-Only or Write-Only can be
“shadowed” into GMCH DDR SDRAM. Typically this is done to allow ROM code to execute
more rapidly out of main DDR SDRAM. ROM is used as a Read-Only during the copy process
while DDR SDRAM at the same time is designated Write-Only. After copying, the DDR
SDRAM is designated Read-Only so that ROM is shadowed. CPU bus transactions are routed
accordingly.
5.4.5 I/O Address Space

The GMCH does not support the existence of any other I/O devices beside itself on the CPU bus.
The GMCH generates Hub interface or PCI bus cycles for all CPU I/O accesses that it does not
claim. Within the Host bridge the GMCH contains two internal registers in the CPU I/O space,
Configuration Address register (CONFIG_ADDRESS) and the Configuration Data register
(CONFIG_DATA). These locations are used to implement Configuration Space Access
Mechanism and as described in the Configuration register section.
The CPU allows 64 kB +3 B to be addressed within the I/O space. The GMCH propagates the
CPU I/O address without any translation on to the destination bus and therefore provides
addressability for 64 k+3 B locations. Note that the upper three locations can be accessed only
during I/O address wrap-around when CPU bus A16# address signal is asserted. A16# is asserted
on the CPU bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or
0FFFFh. A16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) is consumed by the
internal graphics device if it is enabled. The mechanisms for internal graphics IO decode and the
associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to
the Hub interface. The GMCH will not post I/O Write cycles to IDE.
5.4.5.1 AGP/PCI I/O Address Mapping

The GMCH can be programmed to direct non-memory (I/O) accesses to the AGP bus interface
when CPU initiated I/O cycle addresses are within the AGP I/O address range. This range is
controlled via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in
GMCH Device #1 configuration space.
Address decoding for this range is based on the following concept. The top 4 bits of the respective
I/O Base and I/O Limit registers correspond to address bits A[15:12] of an I/O address. For the
purpose of address decoding, the GMCH assumes that lower 12 address bits A[11:0] of the I/O
base are zero and that address bits A[11:0] of the I/O limit address are FFFh. This forces the I/O
address range alignment to 4-kB boundary and produces a size granularity of 4 kB.
The GMCH positively decodes I/O accesses to AGP I/O address space as defined by the
following equation:
I/O_Base_Address * CPU I/O Cycle Address * I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration software and it
depends on the size of I/O space claimed by the AGP device.
132 Datasheet
The GMCH also forwards accesses to the Legacy VGA I/O ranges according to the settings in the
Device #1 configuration registers BCTRL (VGA Enable) and PCICMD1 (IOAE1), unless a
second adapter (monochrome) is present on the Hub interface/PCI (or ISA). The presence of a
second graphics adapter is determined by the MDAP configuration bit. When MDAP is set, the
GMCH will decode legacy monochrome IO ranges and forward them to the Hub interface. The
IO ranges decoded for the monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh.
Note: The GMCH Device #1 I/O address range registers defined above are used for all I/O space
allocation for any devices requiring such a window on AGP. These devices would include the
AGP device, PCI-66MHz/3.3V agents, and multifunctional AGP devices where one or more
functions are implemented as PCI devices.
The PCICMD1 register can disable the routing of I/O cycles to the AGP.
5.4.6 GMCH Decode Rules and Cross-Bridge Address Mapping

The address map described above applies globally to accesses arriving on any of the three
interfaces i.e. Host bus, IGD, and Hub interface.
5.4.7 Hub Interface Decode Rules

The GMCH accepts accesses from Hub interface to the following address ranges:
• All Memory Read and Write accesses to Main DDR SDRAM including PAM region (except
SMM space)
• All Memory Read/Write accesses to the Graphics Aperture (DRAM) defined by APBASE
and APSIZE.
• All Hub interface memory write accesses to AGP memory range defined by MBASE,
MLIMIT, PMBASE, and PMLIMIT.
• Memory writes to VGA range.
All Memory Reads from the Hub interface A that are targeted > 4-GB system memory range will
be terminated with Master Abort completion, and all Memory Writes (>4-GB) from the Hub
interface will be ignored.
Hub interface system memory accesses that fall elsewhere within the system memory range are
considered invalid and will be remapped to system memory address 0h, snooped on the Host Bus,
and dispatched to DDR SDRAM. Reads will return all 1’s with Master Abort completion. Writes
will have BE’s deasserted and will terminate with Master Abort if completion is required. I/O
cycles will not be accepted. They are terminated with Master Abort completion packets.
5.4.7.1 Hub Interface Accesses to GMCH that Cross Device Boundaries

Hub interface accesses are limited to 256 B (Bytes) but have no restrictions on crossing address
boundaries. A single Hub interface request may therefore span device boundaries (DDR SDRAM)
or cross from valid addresses to invalid addresses (or visa versa). The GMCH does not support
transactions that cross device boundaries. For Reads and for Writes requiring completion, the
GMCH will provide separate completion status for each naturally aligned 32-B or 64-B block. If
the starting address of a transaction hits a valid address, the portion of a request that hits that
Datasheet 133
target device (DDR SDRAM) will complete normally. The remaining portion of the access that
crosses a device boundary (targets a different device than that of the starting address) or hits an
invalid address will be remapped to system memory address 0h, snooped on the Host Bus, and
dispatched to DDR SDRAM. Reads will return all 1’s with Master Abort completion. Writes will
have BE’s (Byte Enable) deasserted and will terminate with Master Abort if completion is
required.
If the starting address of a transaction hits an invalid address the entire transaction will be
remapped to system memory address 0h, snooped on the Host Bus, and dispatched to DDR
SDRAM. Reads will return all 1’s with Master Abort completion. Writes will have BE’s
deasserted and will terminate with Master Abort if completion is required.
5.4.7.2 AGP Interface Decode Rules

Cycles Initiated Using PCI Protocol
The GMCH does not support any AGP/PCI access targeting Hub interface. The GMCH will claim
AGP/PCI initiated memory read and write transactions decoded to the main DDR SDRAM range
or the Graphics Aperture range. All other memory read and write requests will be master-aborted
by the AGP/PCI initiator as a consequence of GMCH not responding to a transaction.
Under certain conditions, the GMCH restrict access to the DOS Compatibility ranges governed by
the PAM registers by distinguishing access type and destination bus. The GMCH accept
AGP/PCI write transactions to the compatibility ranges if the PAM designates DDR SDRAM as
write-able. If accesses to a range are not write enabled by the PAM, the GMCH does not respond
and the cycle will result in a master-abort. The GMCH accept AGP/PCI read transactions to the
compatibility ranges if the PAM designates DDR SDRAM as readable. If accesses to a range are
not read enabled by the PAM, the GMCH does not respond and the cycle will result in a master-
abort.
If agent on AGP/PCI issues an I/O or PCI Special Cycle transaction, the GMCH will not respond
and cycle will result in a master-abort. The GMCH will accept PCI configuration cycles to the
internal GMCH devices as part of the PCI configuration/co-pilot mode mechanism.
Cycles Initiated Using AGP Protocol
All cycles must reference main memory i.e. main DDR SDRAM address range (excluding PAM)
or Graphics Aperture range (also physically mapped within DDR SDRAM but using different
address range). AGP accesses to the PAM region from 640K -to- 1M are not allowed. AGP
accesses to SMM space are not allowed. AGP initiated cycles that target DDR SDRAM are not
snooped on the host bus, even if they fall outside of the AGP aperture range.
If a cycle is outside of a valid main memory range then it will terminate as follows:
• Reads: Remap to memory address 0h, return data from address 0h, and set the IAAF error
flag.
• Writes:Remapped to memory address 0h with BE’s de-asserted (effectively dropped “on the
floor”) and set the IAAF error flag.
AGP Accesses to GMCH that Cross Device Boundaries
For FRAME# accesses, when an AGP or PCI master gets disconnected it will resume at the new
address which allows the cycle to be routed to or claimed by the new target. Therefore accesses
134 Datasheet
should be disconnected by the target on potential device boundaries. The GMCH will disconnect
AGP/PCI transactions on 4-kB boundaries.
AGPPIPE# and SBA accesses are limited to 256 bytes and must hit DDR SDRAM. AGP accesses
are dispatched to DDR SDRAM on naturally aligned 32 byte block boundaries. The portion of the
request that hits a valid address will complete normally. The portion of a read access that hits an
invalid address will be remapped to address 0h, return data from address 0h, and set the IAAF
error flag. The portion of a write access that hits an invalid address will be remapped to memory
address 0h with BE’s deasserted (effectively dropped “on the floor”) and set the IAAF error flag.
Datasheet 135
136 Datasheet
Functional Description
6 Functional Description
6.1 Host Interface Overview

The GMCH front side bus uses source synchronous transfer for the address and data signals. The
address signals are double pumped and two addresses can be generated every bus clock. At
100 MHz bus frequency, the two address signals run at 200 MHz for a maximum address queue
rate of 50-M addresses/sec. The data is quad pumped and an entire 64-B cache line can be
transferred in two bus clocks. At 100 MHz bus frequency, the data signals run at 400 MHz for a
maximum bandwidth of 3.2- GB/s. The GMCH supports a 8-deep IOQ (In-Order-Queue) using
the Intel Pentium M processor or Intel Celeron M processor.
6.2 Dynamic Bus Inversion

The GMCH supports dynamic bus inversion (DBI) when driving and receiving data from the Host
Bus. DBI limits the number of data signals that are driven to a low voltage on each quad pumped
data phase. This decreases the power consumption of the GMCH. DINV[3:0]# indicates if the
corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:
Table 35. Relation of DBI Bits to Data Bits
DINV[3:0] Data Bits
DINV[0]# HD[15:0]#
DINV[1]# HD[31:16]#
DINV[2]# HD[47:32]#
DINV[3]# HD[63:48]#
Whenever the CPU or the GMCH drives data, each 16-bit segment is analyzed. If more than eight
of the 16 signals would normally be driven low on the bus the corresponding DINV# signal will
be asserted and the data will be inverted prior to being driven on the bus. Whenever the CPU or
the GMCH receives data it monitors DINV[3:0]# to determine if the corresponding data segment
should be inverted.
6.2.1 System Bus Interrupt Delivery

The Intel Pentium M processor and Intel Celeron M processor support system bus interrupt
delivery. It does not support the APIC serial bus interrupt delivery mechanism. Interrupt related
messages are encoded on the system bus as Interrupt Message transactions. System bus interrupts
may originate from the processor on the system bus, or from a downstream device on the Hub
interface.
Datasheet 137
In a GMCH platform, the ICH4-M contains IOxAPICs and its interrupts are generated as
upstream Hub interface Memory Writes. Furthermore, PCI 2.2 defines MSI’s (Message Signaled
Interrupts) that are also in the form of Memory Writes. A PCI 2.2 device may generate an
interrupt as an MSI cycle on its PCI bus instead of asserting a hardware signal to the IOxAPIC.
The MSI may be directed to the IOxAPIC, which in turn generates an interrupt as an upstream
Hub interface memory write. Alternatively the MSI may be directed directly to the system bus.
The target of an MSI is dependent on the address of the interrupt Memory Write. The GMCH
forwards inbound Hub interface memory writes to address 0FEEx_xxxxh, to the system bus as
Interrupt Message transactions.
6.2.2 Upstream Interrupt Messages

The GMCH accepts message based interrupts from its Hub interface and forwards them to the
system bus as Interrupt Message transactions. The Interrupt Messages presented to the GMCH are
in the form of Memory Writes to address 0FEEx_xxxxh. At the Hub interface, the Memory Write
Interrupt Message is treated like any other Memory Write; it is either posted into the inbound data
buffer (if space is available) or retried (if data buffer space is not immediately available). Once
posted, the Memory Write from the Hub interface, to address 0FEEx_xxxxh, is decoded as a
cycle that needs to be propagated by the GMCH to the front side bus as an Interrupt Message
transaction.
6.3 System Memory Interface
6.3.1 DDR SDRAM Interface Overview

The GMCH supports DDR SDRAM at 200/266 MHz and includes the following support:
• Up to 1 GB of PC1600/PC2100 DDR SDRAM
• Up to 2 GB (high density) of PC1600/PC2100 DDR SDRAM
• PC1600/2100 unbuffered 200-pin DDR SDRAM SO-DIMMs
• Configurable optional ECC
• Maximum of two SO-DIMMs, single-sided and/or double-sided
The 2-bank select lines SBA[1:0] and the 13 Address lines SMA[12:0] allow the GMCH to
support 64-bit wide SO-DIMMs using 128-Mb, 256-Mb, and 512-Mb DDR SDRAM technology.
While address lines SMA[9:0] determine the starting address for a burst, burst length can only be
4. Four chip selects SCS[3:0]# lines allow a maximum of two rows of single-sided DDR SDRAM
SO-DIMMs and four rows of double-sided DDR SDRAM SO-DIMMs.
The GMCH main system memory controller targets CAS latencies of 2 and 2.5 for DDR
SDRAM. The GMCH provides refresh functionality with a programmable rate (normal DDR
SDRAM rate is 1 refresh/15.6 s). For write operations of less than a full cache line, GMCH will
perform a cache-line read and into the write buffer and perform byte-wise write-merging in the
write buffer.
138 Datasheet
6.3.2 System Memory Organization and Configuration
6.3.2.1 Configuration Mechanism for SO-DIMMs

Detection of the type of DDR SDRAM installed on the SO-DIMM is supported via Serial
Presence Detect mechanism as defined in the JEDEC 200-pin SO- DIMM specification.
Before any cycles to the system memory interface can be supported, the GMCH DDR SDRAM
registers must be initialized. The GMCH must be configured for operation with the installed
system memory types. Detection of system memory type and size is done via the System
Management Bus (SMB) interface on the ICH4-M. This two-wire bus is used to extract the DDR
SDRAM type and size information from the Serial Presence Detect port on the DDR SDRAM
SO-DIMMs. DDR SDRAM SO-DIMMs contain a 5-pin Serial Presence Detect interface,
including SCL (serial clock), SDA (serial data) and SA[2:0]. Devices on the SMBus have a 7-bit
address. For the DDR SDRAM SO-DIMMs, the upper four bits are fixed at 1010b. The lower
three bits are strapped on the SA[2:0] pins. SCL and SDA are connected directly to the System
Management bus on the ICH4-M. Thus data is read from the Serial Presence Detect port on the
SO-DIMMs via a series of I/O cycles to the south bridge. The BIOS needs to determine the size
and type of system memory used for each of the rows of system memory in order to properly
configure the GMCH system memory interface.
For SMBus Configuration and Access of the Serial Presence Detect Ports, refer to the Intel®
82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet (252337) for more details.
6.3.2.2 System Memory Register Programming

This section provides an overview of how the required information for programming the DDR
SDRAM registers is obtained from the Serial Presence Detect ports on the SO-DIMMs. The
Serial Presence Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength,
row Type (on a row by row basis), DDR SDRAM Timings, row sizes and row page sizes. Table
36 lists a subset of the data available through the on board Serial Presence Detect ROM on each
SO-DIMM.
Table 36. Data Bytes on SO-DIMM Used for Programming DRAM Registers
Byte Function
2 System Memory Type (DDR SDRAM)
3 Number of row addresses, not counting Bank Addresses
4 Number of Column Addresses
5 Number of SO-DIMM banks
11 ECC, No ECC
12 Refresh Rate/Type
17 Number Banks on each Device
Table 36 is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes collectively
provide enough data for programming the GMCH DDR SDRAM registers.
Datasheet 139
6.3.3 DDR SDRAM Performance Description

The overall system memory performance is controlled by the DDR SDRAM timing register,
pipelining depth used in GMCH, system memory speed grade and the type of DDR SDRAM used
in the system. Besides this, the exact performance in a system is also dependent on the total
system memory supported, external buffering and system memory array layout. The most
important contribution to overall performance by the system memory controller is to minimize the
latency required to initiate and complete requests to system memory, and to support the highest
possible bandwidth (full streaming, quick turn-arounds). One measure of performance is the total
flight time to complete a cache line request. A true discussion of performance really involves the
entire chipset, not just the system memory controller.
6.3.3.1 Data Integrity (ECC)

The GMCH supports single-bit Error Correcting Code (or Error Checking and Correcting) and
multiple-bit EC (Error Checking) on the Main Memory interface. The GMCH generate an 8-bit
code word for each 64-bit Qword of memory and performs two Qword writes at a time so two 8-
bit codes are sent with each write. Since the code word covers a full Qword, writes of less than a
Qword require a read-merge-write operation. Consider a Dword write to memory. In this case,
when in ECC mode, GMCH will read the Qword where the addressed Dword will be written,
merge in the new Dword, generate a code covering the new Qword and finally write the entire
Qword and code back to memory. Any correctable (single-bit) errors detected during the initial
Qword read are corrected before merging the new Dword. GMCH also supports another data
integrity mode, EC (Error Checking) mode. In this mode, the GMCH generates and stores a code
for each Qword of memory. It then checks the code for reads from memory but does not correct
any errors that are found.
6.4 Integrated Graphics Overview

The Intel 855GM/855GME GMCH provides a highly integrated graphics accelerator and PCI set
while allowing a flexible Integrated System Graphics solution.
Note: Intel 855GME GMCH can support an AGP discrete graphics controller.
140 Datasheet
Figure 8. Intel® 855GM GMCH Graphics Block Diagram
DDR/SDRAM
Memory Control
Overlay DAC
Pipe A
Sprite
Video Engine
(MPEG2 Decode) LVDS
Cursor
Cntl
Alpha Mux
2D Engine Cursor Blend/ Port
Gamma/ DVOB
3D Engine Primary CRC Pipe B
Instr./ Display
Setup/Transform
Data DVOC
Scan Conversion Secondary
Display
Texture Engine
Raster Engine Display C
2nd Overlay
High bandwidth access to data is provided through the system memory port. The GMCH uses a
tiling architecture to minimize page miss latencies and thus maximize effective rendering
bandwidth.
6.4.1 3D/2D Instruction Processing

The GMCH contains an extensive set of instructions that control various functions including 3D
rendering, BLT operations, display, MPEG decode acceleration, and overlay. The 3D instructions
set 3D pipeline states and control the processing functions. The 2D instructions provide an
efficient method for invoking BLT operations.
6.4.2 3D Engine
The 3D engine of the GMCH has been designed with a deeply pipelined architecture, where
performance is maximized by allowing each stage of the pipeline to simultaneously operate on
different primitives or portions of the same primitive. The GMCH supports the following:
• Perspective-corrected Texture mapping
• Multitexturing
• Embossed and Dot-Product Bump mapping
• Cubic Environment Maps
Datasheet 141
• Bilinear, Trilinear, and Anisotropic MIP map filtering
• Gouraud shading and Flat shading
• Alpha-blending
• Per-Vertex and per- pixel fog
• Z/W buffering
These features are independently controlled via a set of 3D instructions. The 3D pipeline
subsystem performs the 3D rendering acceleration. The main blocks of the pipeline are the Setup
Engine, Scan Converter, Texture Pipeline, and Raster Pipeline. A typical programming sequence
would be to send instructions to set the state of the pipeline followed by rendering instructions
containing 3D primitive vertex data.
6.4.2.1 Bi-Cubic Filtering (Intel® 855GME GMCH)

Bi-Cubic filtering is an alternate method to Bi-Linear filtering. The filter (blend factor) is
determined by the relative distance between the pixel center and the nearest 4 texel (2X2). This
method provides a significant level of filtering and looks very crisp on a display. This method
also creates a smooth motion of texture as it traverses across the display.
6.4.2.2 Video Mixer Rendering (Intel® 855GME GMCH)

VMR refers to the ability to blend any data format/source with other displayable content. It allows
3D, video/DVD, 2D bitmap and closed caption to be mixed together. VMR works mainly as a
front-end processor, thereby reducing dependence on video ports and overlays
6.4.2.3 Setup Engine

The GMCH 3D setup engine takes the input data associated with each vertex of a 3D primitive
and computes the various parameters required for scan conversion. In formatting this data, the
GMCH maintains sub-pixel accuracy. The per-vertex data is converted into gradients that can be
used to interpolate the data at any pixel within a polygon (colors, alpha, Z or W depth, fog, and
texture coordinates). The pixels covered by a polygon are identified and per-pixel texture
addresses are calculated.
6.4.2.4 Viewport Transform and Perspective Divide

A 3D-geometry pipeline typically involves transformation of vertices from model space to
clipping space followed by clip test and clipping. Lighting can be performed during the
transformation or at any other point in the pipeline. After clipping, the next stage involves
perspective divide followed by transformation to the viewport or screen space. The GMCH can
support viewport transform and perspective divide portion of the 3D geometry pipeline in
hardware.
142 Datasheet
6.4.2.5 3D Primitives and Data Formats Support

The 3D primitives rendered by the GMCH are points, lines, discrete triangles, line strips, triangle
strips, triangle fans, and polygons. In addition to this, the GMCH supports DirectX’s* Flexible
Vertex Format* (FVF), which enables the application to specify a variable length parameter list,
obviating the need for sending unused information to the hardware. Strips, Fans, and Indexed
Vertices as well as FVF improves delivered vertex rate to the setup engine significantly.
6.4.2.6 Pixel Accurate Fast Scissoring and Clipping Operation

The GMCH supports clipping to a scissoring rectangle within the drawing window. The GMCH
clipping and scissoring in hardware reduce the need for software to process polygons, and thus
improves performance. During the setup stage, the GMCH clips polygons to the drawing window.
The scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger
region than the hardware renders to. The scissor rectangle is pixel accurate, and independent of
line and point width. The GMCH supports a single scissor box rectangle.
6.4.2.7 Backface Culling

As part of the setup, the GMCH can discard polygons from further processing, if they are either
facing away from or towards the user’s viewpoint. This operation, referred to as Back Face
Culling is accomplished based on the clockwise or counter-clockwise orientation of the vertices
on a primitive. This can be enabled or disabled by the driver.
6.4.2.8 Scan Converter

The Scan Converter takes the vertex and edge information identifies all pixels that are affected by
features being rendered. It works on a per-polygon basis, and one polygon may be entering the
pipeline while calculations finish on another.
6.4.2.9 Texture Engine

The GMCH allows an image pattern or video to be placed on the surface of a 3D polygon. The
texture engine performs texture color or chromakey matching texture filtering (anisotropic,
trilinear, and bilinear) and YUV to RGB conversion.
As texture sizes increase beyond the bounds of graphics memory, executing textures from
graphics memory becomes impractical. Every rendering pass would require copying each and
every texture in a scene from system memory to graphics memory, then using the texture, and
finally overwriting the local memory copy of the texture by copying the next texture into graphics
memory. The GMCH, using Intel’s Direct Memory Execution model, simplifies this process by
rendering each scene using the texture located in system memory. The GMCH includes a cache
controller to avoid frequent memory fetches of recently used texture data.
Datasheet 143
6.4.2.10 Perspective Correct Texture Support

A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon.
A texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in
perspective, it is important that texture be mapped in perspective as well. Without perspective
correction, texture is distorted when an object recedes into the distance. Perspective correction
involves a compute-intensive “per-pixel-divide” operation on each pixel. Perspective correction is
necessary for realistic 3D graphics.
6.4.2.11 Texture Decompression

As the textures’ average size gets larger with higher color depth and multiple textures become the
norm, it becomes increasingly important to provide support for compressed textures.
Microsoft DirectX* supports Texture Compression/Decompression to reduce the bandwidth

required to deliver textures. The GMCH supports several compressed texture formats (DirectX:
DXT1, DXT2, DXT3, DXT4, DXT5) and OpenGL FXT1 formats.
6.4.2.12 Texture Chromakey

Chromakey is a method for removing a specific color or range of colors from a texture map
before it is applied to an object. For nearest texture filter modes, removing a color simply makes
those portions of the object transparent (the previous contents of the back buffer show through).
For linear texture filtering modes, the texture filter is modified if only the non-nearest neighbor
texels match the key (range).
Chromakeying can be performed for both paletted and non-paletted textures, and removes texels
that fall within a specified color range. The Chromakey mode refers to testing the ARGB or YUV
components to see if they fall between high and low state variable values. If the color of a texel
contribution is in this range and chromakey is enabled, then this contribution is removed from the
resulting pixel color.
6.4.2.13 Anti-Aliasing
Aliasing is one of the artifacts that degrade image quality. In its simplest manifestation, aliasing
causes the jagged staircase effects on sloped lines and polygon edges. Another artifact is the
moiré patterns, which occur as a result of the fact that there is very small number of pixels
available on screen to contain the data of a high-resolution texture map.
Full scene anti-aliasing uses super-sampling, which means that the image is rendered internally at
a higher resolution than it is displayed on screen. The GMCH renders internally at 1600x1200,
reads the image as a texture, and finally down-samples (via a Bilinear filter) to the screen
resolution of 640x480 and 800x600. Full scene anti-aliasing removes jaggies at the edges.
144 Datasheet
6.4.2.14 Texture Map Filtering

Many texture-mapping modes are supported. Perspective correct mapping is always performed.
As the map is fitted across the polygon, the map can be tiled, mirrored in either the U or V
directions, or mapped up to the end of the texture and no longer placed on the object (this is
known as clamp mode). The way a texture is combined with other object attributes is also
definable.
The GMCH supports up to 12 Levels-of-Detail (LODs) ranging in size from 2048x2048 to 1X1
texels. (A texel is defined as a texture map element.) Included in the texture processor is a texture
cache, which provides efficient MIP-mapping.
The GMCH supports seven types of texture filtering:

• Nearest (also known as Point filtering): Texel with coordinates nearest to the desired pixel is
used. (This is used if only one LOD is present.)
• Linear (also known as Bilinear filtering): A weighted average of a 2x2 area of texels
surrounding the desired pixel is used. (This is used if only one LOD is present.)
• Nearest MIP Nearest (also known as Point filtering): This is used if many LODs are present.
The nearest LOD is chosen and the texel with coordinates nearest to the desired pixel are
used.
• Linear MIP Nearest (Bilinear MIP mapping): This is used if many LODs are present. The
nearest LOD is chosen and a weighted average of a 2x2 area of texels surrounding the
desired pixel is used (four texels). This is also referred to as Bilinear MIP Mapping.
• Nearest MIP Linear (Point MIP mapping): This is used if many LODs are present. Two
appropriate LODs are selected and within each LOD the texel with coordinates nearest to the
desired pixel are selected. The Final texture value is generated by linear interpolation
between the two texels selected from each of the MIP Maps.
• Linear MIP Linear (Trilinear MIP mapping): This is used if many LODs are present. Two
appropriate LODs are selected and a weighted average of a 2X2 area of texels surrounding
the desired pixel in each MIP Map is generated (four texels per MIP Map). The Final texture
value is generated by linear interpolation between the two texels generated for each of the
MIP Maps. Trilinear MIP Mapping is used minimize the visibility of LOD transitions across
the polygon.
• Anisotropic MIP Nearest (Anisotropic filtering): This filter can be used when textured object
pixels map back to significantly non-square regions of the texture (e.g., when the texture is
scaled in one screen direction than the other screen direction).
• Both DirectX and OpenGL (Rev.1.1) allow support for all these filtering modes.
6.4.2.15 Multiple Texture Composition

The GMCH also performs multiple texture composition. This allows the combination of two or
greater MIP maps to produce a new one with new LODs and texture attributes in a single or
iterated pass. The setup engine supports up to four texture map coordinates in as single pass. The
GMCH allows up to two Bilinear MIP Maps or a single Trilinear MIP Map to be composited in a
single pass. Greater than two Bilinear MIP Maps or more than one Trilinear MIP Map would
require multiple passes. The actual blending or composition of the MIP Maps is done in the raster
engine. The texture engine provides the required texels including blending information.
Datasheet 145
Flexible vertex format support allows multi-texturing because it makes it possible to pass more
than one texture in the vertex structure.
6.4.2.16 Cubic Environment Mapping

Environment maps allow applications to render scenes with complex lighting and reflections
while significantly decreasing CPU load. There are several methods to generate environment
maps such as spherical, circular and cubic. The GMCH supports cubic reflection mapping over
spherical and circular since it is the best choice to provide real-time environment mapping for
complex lighting and reflections.
Cubic Mapping supports a texture map for each of the 6 cube faces. These can be generated by
pointing a camera with a 90-degree field-of-view in the appropriate direction. Per-vertex vectors
(normal, reflection or refraction) are interpolated across the polygon and the intersection of these
vectors with the cube texture faces are calculated. Texel values are then read from the intersection
point on the appropriate face and filtered accordingly.
6.4.2.17 Bump Mapping

The GMCH only supports embossed and dot product bump mapping, not environment bump
mapping.
6.4.3 Raster Engine

The Raster engine is where the color data such as fogging, specular RGB, texture map blending,
etc. is processed. The final color of the pixel is calculated and the RGB value combined with the
corresponding components resulting from the Texture engine. These textured pixels are modified
by the specular and fog parameters. These specular highlighted, fogged, textured pixels are color
blended with the existing values in the frame buffer. In parallel, stencil, alpha, and depth buffer
tests are conducted which will determine whether the Frame and Depth buffers will be updated
with the new pixel values.
6.4.3.1 Texture Map Blending

Multiple textures can be blended together in an iterative process and applied to a primitive. The
GMCH allows up to four distinct or shared texture coordinates and texture maps to be specified
onto the same polygon. Also, the GMCH supports a texture coordinate set to access multiple
texture maps. State variables in multiple textures are bound to texture coordinates, texture map or
texture blending.
6.4.3.2 Combining Intrinsic and Specular Color Components

The GMCH allows an independently specified and interpolated specular RGB attribute to be
added to the post-texture blended pixel color. This feature provides a full RGB specular highlight
to be applied to a textured surface, permitting a high quality reflective colored lighting effect not
available in devices which apply texture after the lighting components have been combined. If the
specular-add state variable is disabled, only the resultant colors from the map blending are used.
If this state variable is enabled, the specular RGB color is added to the RGB values from the
output of the map blending.
146 Datasheet
6.4.3.3 Color Shading Modes

The Raster engine supports the Flat and Gouraud shading modes. These shading modes are
programmed by the appropriate state variables issued through the command stream.
• Flat shading is performed by smoothly interpolating the vertex intrinsic color components
(Red, Green, Blue), Specular (R, G, B), Fog, and Alpha to the pixel, where each vertex color
has the same value. The setup engine substitutes one of the vertex’s attribute values for the
other two vertices attribute values thereby creating the correct flat shading terms. This
condition is set up by the appropriate state variables issued prior to rendering the primitive.
• Gouraud shading is performed by smoothly interpolating the vertex intrinsic color
components (Red, Green, Blue). Specular (RGB), Fog, and Alpha to the pixel, where each
vertex color has a different value.
6.4.3.4 Color Dithering

Color Dithering in the GMCH helps to hide color quantization errors for 16-bit color buffers.
Color Dithering takes advantage of the human eye’s propensity to average the colors in a small
area. Input color, alpha, and fog components are converted from 8-bit components to 5-bit or 6-bit
component by dithering. Dithering is performed on blended textured pixels. In 32-bit mode,
dithering is not performed.
6.4.3.5 Vertex and Per Pixel Fogging

Fogging is used to create atmospheric effects such as low visibility conditions in flight simulator-
type games. It adds another level of realism to computer-generated scenes. Fog can be used for
depth cueing or hiding distant objects. With fog, distant objects can be rendered with fewer
details (less polygons), thereby improving the rendering speed or frame rate. Fog is simulated by
attenuating the color of an object with the fog color as a function of distance, and the greater the
distance, the higher the density (lower visibility for distant objects). There are two ways to
implement the fogging technique: per-vertex (linear) fogging and per-pixel (non-linear) fogging.
The per-vertex method interpolates the fog value at the vertices of a polygon to determine the fog
factor at each pixel within the polygon. This method provides realistic fogging as long as the
polygons are small. With large polygons (such as a ground plane depicting an airport runway), the
per-vertex technique results in unnatural fogging.
The GMCH supports both types of fog operations, vertex and per pixel. If fog is disabled, the
incoming color intensities are passed unchanged to the destination blend unit. If fog is enabled,
the incoming pixel color is blended with the fog color based on a fog coefficient on a per pixel
basis.
6.4.3.6 Alpha Blending

Alpha blending in the GMCH adds the material property of transparency or opacity to an object.
Alpha blending combines a source pixel color and alpha component with a destination pixel color
and alpha component. For example, this is so that a glass surface on top (source) of a red surface
(destination) would allow much of the red base color to show through.
Blending allows the source and destination color values to be multiplied by programmable factors
and then combined via a programmable blend function. The combined and independent selection
of factors and blend functions for color and alpha is supported.
Datasheet 147
6.4.3.7 Color Buffer Formats: (Destination Alpha)

The Raster engine supports 8-bit, 16-bit, and 32-bit Color Buffer formats. The 8-bit format is used
to support planar YUV4:2:0 format, which is used only in Motion Compensation and Arithmetic
Stretch format. The bit format of Color and Z is allowed to mix.
The GMCH can support an 8-bit destination alpha in 32-bit mode. Destination alpha is supported
in 16-bit mode in 1:5:5:5 or 4:4:4:4 format. The GMCH does not support general 3D rendering to
8-bit surfaces. 8-bit destinations are supported for operations on planar YUV surfaces (e.g.,
stretch BLTs) where each 8-bit color component is written in a separate pass. The GMCH also
supports a mode where both U and V planar surfaces can be operated on simultaneously.
The frame buffer of the GMCH contains at least two hardware buffers - the Front Buffer (display
buffer) and the Back Buffer (rendering buffer). While the back buffer may actually coincide with
(or be part of) the visible display surface, a separate (screen or window-sized) back buffer is
typically used to permit double-buffered drawing. That is, the image being drawn is not visible
until the scene is complete and the back buffer made visible or copied to the front buffer via a 2D
BLT operation. Rendering to one buffer and displaying from the other buffer removes image
tearing artifacts. Additionally, more than two back buffers (e.g., triple-buffering) can be
supported.
6.4.3.8 Depth Buffer

The Raster Engine is able to read and write from this buffer and use the data in per fragment
operations that determine resultant color and depth value of the pixel for the fragment are to be
updated or not.
Typical applications for entertainment or visual simulations with exterior scenes require far/near
ratios of 1000 to 10000. At 1000, 98% of the range is spent on the first 2% of the depth. This can
cause hidden surface artifacts in distant objects, especially when using 16-bit depth buffers. A 24-
bit Z-buffer provides 16 million Z-values as opposed to only 64 k with a 16-bit Z-buffer. With
lower Z-resolution, two distant overlapping objects may be assigned the same Z-value. As a
result, the rendering hardware may have a problem resolving the order of the objects, and the
object in the back may appear through the object in the front.
By contrast, when w (or eye-relative z) is used, the buffer bits can be more evenly allocated
between the near and far clip planes in world space. The key benefit is that the ratio of far and
near is no longer an issue, and allows applications to support a maximum range of miles, yet still
get reasonably accurate depth buffering within inches of the eye point. The selection of depth
buffer size is relatively independent of the color buffer. A 16-bit Z/W or 24-bit Z/W buffer can be
selected with a 16-bit color buffer. Z buffer is not supported in 8-bit mode.
6.4.3.9 Stencil Buffer

The Raster engine provides 8-bit stencil buffer storage in 32-bit mode and the ability to perform
stencil testing. Stencil testing controls 3D drawing on a per pixel basis and conditionally
eliminates a pixel on the outcome of a comparison between a stencil reference value and the value
in the stencil buffer at the location of the source pixel being processed. They are typically used in
multipass algorithms to achieve special effects, such as decals, outlining, shadows, and
constructive solid geometry rendering.
One of three possible stencil operations is performed when stencil testing is enabled. The stencil
operation specifies how the stencil buffer is modified when a fragment passes or fails the stencil
148 Datasheet
test. The selection of the stencil operation to be performed is based upon the result of the stencil
test and the depth test. A stencil write mask is also included that controls the writing of particular
bits into the stencil buffer. It selects between the destination value and the updated value on a per-
bit basis. The mask is 8-bit wide.
6.4.3.10 Projective Textures

The GMCH supports two simultaneous projective textures at full rate processing. These textures
require three floating-point texture coordinates to be included in the FVF format. Projective
textures enable special effects such as projecting spot light textures obliquely onto walls, etc.
6.4.4 2D Engine
The GMCH provides an extensive set of 2D instructions and 2D HW acceleration for block
transfers of data (BLTs). The BLT engine provides the ability to copy a source block of data to a
destination and perform operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern,
and/or another destination. The Stretch BLT engine is used to move source data to a destination
that need not be the same size, with source transparency. Performing these common tasks in
hardware reduces CPU load, and thus improves performance.
6.4.4.1 256-Bit Pattern Fill and BLT Engine

Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft* Windows*.
The GMCH BLT Engine provides hardware acceleration of block transfers of pixel data for many
common Windows operations. The term BLT refers to a block transfer of pixel data between
system memory locations. The BLT engine can be used for the following:
• Move rectangular blocks of data between system memory locations
• Data alignment
• Perform logical operations (raster ops)
The rectangular block of data does not change as it is transferred between system memory
locations. Data to be transferred can consist of regions of system memory, patterns, or solid color
fills. A pattern will always be 8x8 pixels wide and may be 8-bits, 16-bits, or 32-bits per pixel.
The GMCH BLT engine has the ability to expand monochrome data into a color depth of 8 bits,
16 bits, or 32 bits. BLTs can be either opaque or transparent. Opaque transfers, move the data
specified to the destination. Transparent transfers compare destination color to source color and
write according to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the BLT
overlaps with the source system memory location, the GMCH can specify which area in system
memory to begin the BLT transfer. Hardware is included for all 256 raster operations (source,
pattern, and destination) defined by Microsoft*, including transparent BLT.
The GMCH has instructions to invoke BLT operations, permitting software to set up instruction
buffers and use batch processing as described in the Instruction Processing section. The GMCH
can perform hardware clipping during BLTs.
Datasheet 149
6.4.4.2 Alpha Stretch BLT

The stretch BLT function can stretch source data in the X and Y directions to a destination larger
or smaller than the source. Stretch BLT functionality expands a region of system memory into a
larger or smaller region using replication and interpolation. The stretch BLT function also
provides format conversion and data alignment.
6.4.5 Planes and Engines

The GMCH display can be functionally delineated into planes and engines (pipes and ports). A
plane consists of rectangular shaped image that has characteristics such as source, size, position,
method, and format. These planes get attached to source surfaces, which are rectangular system
memory surfaces with a similar set of characteristics. They are also associated with a particular
destination pipe.
A pipe consists of a set of planes that will be combined with a timing generator. A port is the
destination for the result of the pipe. The GMCH supports one Analog Output Port, one LVDS
LCD Flat Panel Port, and two DVO ports. In conclusion, planes are associated with pipes and
pipes are associated with ports.
6.4.5.1 Dual Pipe Independent Display Functionality

The display consists of two display pipes, A and B. Pipes have a set of planes that are assigned to
them as sources. The analog display port may only use Pipe A or Pipe B, the DVO B or C ports
may use either Pipe A or Pipe B, and the Internal LVDS interface may only use Pipe B. This
limits the resolutions available on a digital display when an analog CRT is active.
Table 37. Dual Display Usage Model (Intel® 852GM GMCH)
Display Pipe A Display Pipe B
CRT Internal LVDS
DVO B or C or Both CRT
CRT DVO B or C or Both
DVO B or C or Both Internal LVDS
CRT/DVO B or C or Both (No TV Support) Internal LVDS
6.4.6 Hardware Cursor Plane

The GMCH supports two hardware cursors. The cursor plane is one of the simplest display
planes. With a few exceptions, has a fixed size of 64 x 64 and a fixed Z-order (top). In legacy
modes, cursor can cause the display data below it to be inverted. In the alpha blend mode, true
color cursor data can be alpha blended into the display stream. It can be assigned to either display
pipe A or display pipe B and dynamically flipped from one to the other when both are running.
150 Datasheet
6.4.6.1 Cursor Color Formats

Color data can be in an indexed format or a true color format. Indexed data uses the entries in the
four-entry cursor palette to convert the two-bit index to a true color format before being passed to
the blenders. The index can optionally specify that a cursor pixel be transparent or cause an
inversion of the pixel value below it or one of two colors from the cursor palette. Blending of
YUV or RGB data is only supported with planes that have data of the same format.
6.4.6.2 Popup Plane (Second Cursor)

The popup plane is used for control functions in mobile applications. Only the hardware cursor
has a higher Z-order precedence over the hardware icon. In standard modes (non-VGA) either
cursor A or cursor B can be used as a Popup Icon. For VGA modes, 32-bpp data format is not
supported.
6.4.6.3 Popup Color Formats

Source color data for the popup is in an indexed format. Indexed data uses the entries in the four-
entry cursor palette to convert the two-bit index to a true color format before being passed to the
blenders. Blending of color data is only supported with data of the same format.
6.4.7 Overlay Plane

The overlay engine provides a method of merging either video capture data (from an external
Video Capture device) or data delivered by the CPU, with the graphics data on the screen.
6.4.7.1 Multiple Overlays (Display C)

A single overlay plane and scalar is implemented. This overlay plane can be connected to the
primary display, secondary display or in bypass mode. In the default mode, it appears on the
primary display. The overlay may be displayed in a multi-monitor scenario for single-pipe
simultaneous displays only. Picture-in-Picture feature is supported via software through the
arithmetic stretch BLT.
6.4.7.2 Source/Destination Color/Chromakeying

Overlay source/destination chromakeying enables blending of the overlay with the underlying
graphics background. Destination color-/chromakeying can be used to handle occluded portions
of the overlay window on a pixel-by-pixel basis that is actually an underlay. Destination color
keying supports a specific color (8-bit or 15-bit) mode as well as 32-bit alpha blending.
Source color/chromakeying is used to handle transparency based on the overlay window on a

pixel-by-pixel basis. This is used when “blue screening” an image to overlay the image on a new
background later.
Datasheet 151
6.4.7.3 Gamma Correction

To compensate for overlay color intensity loss, the overlay engine supports independent gamma
correction. This allows the overlay data to be converted to linear data or corrected for the display
device when not blending.
6.4.7.4 YUV to RGB Conversion

The format conversion can be bypassed in the case of RGB source data.
6.4.7.5 Color Control

Color control provides a method of changing the color characteristics of the pixel data. It is
applied to the data while in YUV format and uses input parameters such as brightness, saturation,
hue (tint) and contrast. This feature is supplied for the overlay only and works in YUV formats
only.
6.4.7.6 Dynamic Bob and Weave

Interlaced data that originates from a video camera creates two fields that are temporally offset by
1/60 of a second. There are several schemes to de-interlace the video stream: line replication,
vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the
previous field and inserts them into the current field to construct the frame – this is known as
weaving. This is the best solution for images with little motion; however, showing a frame that
consists of the two fields will have serration or feathering of moving edges when there is motion
in the scene. Vertical filtering or “Bob” interpolates adjacent lines rather replicating the nearest
neighbor. This is the best solution for images with motion however, it will have reduced spatial
resolution in areas that have no motion and introduce jaggies. In absence of any other de-
interlacing, these form the baseline and are supported by the GMCH.
6.4.8 Video Functionality

The GMCH supports MPEG-2 decoding hardware, sub-picture support and DTV.
6.4.8.1 MPEG-2 Decoding

The GMCH MPEG2 Decoding supports Hardware Motion Compensation (HWMC). The GMCH
can accelerate video decoding for the following video coding standards:
• MPEG-2 support
• MPEG-1: Full feature support
• H.263 support
• MPEG-4: Only supports some features in the simple profile
The GMCH HWMC interface is optimized for Microsoft’s* VA or API. Hardware Video
Acceleration API (HVA) is a generic DirectDraw and DirectShow interface supported in
Windows XP, Windows 2000 and Windows 98 Millennium to provide video decoding
acceleration. Direct VA is the open standard implementation of HVA, which is natively supported
by the GMCH hardware.
152 Datasheet
6.4.8.2 Hardware Motion Compensation

The HWMC process consists of reconstructing a new picture by predicting (either forward,
backward, or bi-directional) the resulting pixel colors from one or more reference pictures. The
GMCH receives the video stream and implements Motion Compensation and subsequent steps in
hardware. Performing Motion Compensation in hardware reduces the processor demand of
software-based MPEG-2 decoding, and thus improves system performance.
6.4.8.3 Sub-picture Support

Sub-picture is used for two purposes: Subtitles for movie captions, which are superimposed on a
main picture, and for menus to provide some visual operation environments for the user.
DVD allows movie subtitles to be recorded as sub-pictures. On a DVD disc, it is called subtitle
because it has been prepared for storing captions. Since the disc can have a maximum of 32 tracks
for subtitles, they can be used for various applications, for example, as Subtitles in different
languages.
There are two kinds of menus, the System menus and other In-Title menus. First, the System
menus are displayed and operated at startup of or during the playback of the disc or from the stop
state. Second, In-Title menus can be programmed as a combination of Sub-picture and Highlight
commands to be displayed during playback of the disc.
The GMCH supports sub-picture for DVD by mixing the two video streams via alpha blending.
Unlike color keying, alpha blending provides a softer effect and each pixel that is displayed is a
composite between the two video stream pixels. The GMCH can utilize four methods when
dealing with sub-pictures. This flexibility means that the GMCH can work with all sub-picture
formats.
6.5 Display Interface

The GMCH has four dedicated display ports: an Analog CRT port, the Internal LVDS interface,
and two Digital display ports, DVOB and C. DVOB and C can support TV-out encoders, external
DACs, LVDS transmitters, and TMDS transmitters. Each display port has control signals that
may be used to control, configure and/or determine the capabilities of an external device. The data
that is sent out the display ports are selected from one of the two possible sources, display pipe A
or display pipe B, except for the LVDS port which can only be driven on Pipe B.
The GMCH’s digital display port is capable of driving a 165 MHz pixel clock on a single DVO
port, or 330 MHz pixel clock by combining DVOB and DVOC.
6.5.1 Analog Display Port Characteristics

The Analog display port provides an RGB signal output along with an HSYNC and VSYNC
signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to
the analog port. The intended target device is for a CRT based monitor with a VGA connector.
Datasheet 153
6.5.1.1 Integrated RAMDAC

The display function contains a 350 MHz, integrated, 24-bit, RAM-based Digital-to-Analog
Converter (RAMDAC) that transforms up to 2048X1536 digital pixels at a maximum refresh rate
of 75 Hz. Three, 8-bit DACs provide the R, G, and B signals to the monitor.
6.5.1.2 DDC (Display Data Channel)

DDC is defined by VESA. It allows communication between the host system and display. Both
configuration and control information can be exchanged allowing plug-and-play systems to be
realized. Support for DDC 1 and 2 is implemented.
6.5.2 Digital Display Interface
6.5.2.1 Dedicated LVDS Interface

The GMCH has a dedicated ANSI/TIA/EIA –644-1995 Specification compliant dual channel LFP
LVDS interface that can support TFT panel resolutions up to UXGA with a maximum pixel
format of 18 bpp (with SSC supported frequency range from 35 MHz to 112 MHz (single
channel/dual channel).
The display pipe selected by the LVDS display port is programmed with the panel timing
parameters that are determined by installed panel specifications or read from an onboard EDID
ROM. The programmed timing values are then “locked” into the registers to prevent unwanted
corruption of the values. From that point on, the display modes are changed by selecting a
different source size for that pipe, programming the VGA registers, or selecting a source size and
enabling the VGA. The timing signals will remain stable and active through mode changes. These
mode changes include VGA to VGA, VGA to HiRes, HiRes to VGA, and HiRes to HiRes.
The transmitter can operate in a variety of modes and supports several data formats. The serializer
supports 6-bit or 8-bit color and single or dual channel operating modes. The display stream from
the display pipe is sent to the LVDS transmitter port at the dot clock frequency, which is
determined by the panel timing requirements. The output of LVDS is running at a fixed multiple
of the dot clock frequency, which is determined by the mode of operation; single or dual channel.
Depending on configuration and mode, a single channel can take 18-bits of RGB pixel data plus 3
bits of timing control (HSYNC/VSYNC/DE) and output them on three differential data pair
outputs; or 24 bits of RGB plus 3 bits of timing control output on four differential data pair
outputs. A dual channel interface converts 36 bits or 48 bits of color information plus the 3 bits of
timing control and outputs it on six or eight sets of differential data outputs.
This display port is normally used in conjunction with the pipe functions of panel scaling and a 6-
bit to 8-bit dither. This display port is also used in conjunction with the panel power sequencing
and additional associated functions.
When enabled, the LVDS constant current drivers consume significant power. Individual pairs or
sets of pairs can be selected to be powered down when not used. When disabled, individual or
sets of pairs will enter a low power state. When the port is disabled all pairs enters a low power
mode. The panel power sequencing can be set to override the selected power state of the drivers
during power sequencing.
154 Datasheet
6.5.2.2 LVDS Interface Signals

LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical
standard only defining driver output characteristics and receiver input characteristics. There are
two LVDS transmitter channels (channel A and channel B) in the LVDS interface. Each channel
consists of four data pairs and a clock pair. The interface consists of a total of ten differential
signal pairs of which eight are data and two are clocks. The phase locked transmit clock is
transmitted in parallel with the data being sent out over the data pairs and over the LVDS clock
pair.
Each channel supports transmit clock frequency ranges from 35 MHz to 112 MHz, which
provides a throughput of up to 784 Mbps on each data output and up to 112 MHz on the input.
When using both channels, they each operate at the same frequency each carrying a portion of the
data. The maximum pixel rate is increased to 224 MHz but may be limited to less than that due to
restrictions elsewhere in the circuit.
The LVDS Port Enable bit enables or disables the entire LVDS interface. When the port is
disabled, it will be in a low power state. Once the port is enabled, individual driver pairs will be
disabled based on the operating mode. Disabled drivers can be powered down for reduced power
consumption or optionally fixed to forced 0’s output.
6.5.2.3 LVDS Pair States

The LVDS pairs can be put into one of the following five states: powered down tri-state, powered
down Zero Volts, common mode, send zeros, or active. When in the active state, several data
formats are supported. When in powered down state, the circuit enters a low power state and
drives out 0 V or tri-states on both the output pins for the entire channel. The common mode tri-
state is both pins of the pair set to the common mode voltage. When in the send zeros state, the
circuit is powered up but sends only zero for the pixel color data regardless what the actual data is
with the clock lines and timing signals sending the normal clock and timing data.
6.5.2.4 Single Channel versus Dual Channel Mode

Both single channel and dual channel modes are available to allow interfacing to either single or
dual channel panel interfaces. This LVDS port can operate in single channel or dual channel
mode. Dual channel mode uses twice the number of LVDS pairs and transfers the pixel data at
twice the rate of the single channel. In general, one channel will be used for even pixels and the
other for odd pixel data. The first pixel of the line is determined by the display enable going
active and that pixel will be sent out channel A. All horizontal timings for active, sync, and blank
will be limited to be on two pixel boundaries in the two channel modes.
6.5.2.5 LVDS Channel Skew

When in dual channel mode, the two channels must meet the panel requirements with respect to
the inter channel skew.
6.5.2.6 SSC Support

The GMCH is designed to tolerate 0.5%, 1.0%, and 2.5% down/center spread at a modulation rate
from 30-50 kHz triangle. An external SSC clock synthesizer can be used to provide the
48/66 MHz reference clock into the GMCH Pipe B PLL.
Datasheet 155
6.5.2.7 Panel Power Sequencing

This section provides details for the power sequence timing relationship of the panel power, the
backlight enable and the LVDS data timing delivery. In order to meet the panel power timing
specification requirements, two signals, PANELVDDEN and PANELBKLTEN are provided to
control the timing sequencing function of the panel and the backlight power supplies.
6.5.2.7.1 Panel Power Sequence States
A defined power sequence is recommended when enabling the panel or disabling the panel. The
set of timing parameters can vary from panel to panel vendor, provided that they stay within a
predefined range of values. The panel VDD power, the backlight on/off state and the LVDS clock
and data lines are all managed by an internal power sequencer.
A requested power-up sequence is only allowed to begin after the power cycle delay time
requirement T4 is met.
Figure 9. Panel Power Sequencing
T4 T1+T2 T5 TX T3 T4
Panel
On
Panel VDD
Enable
Panel
BackLight
Enable
Off Off
Valid
Clock/Data Lines
Power On Sequence from off state and

Power Off Sequence after full On
156 Datasheet
Table 38. Panel Power Sequencing Timing Parameters
Panel Power Sequence Timing Parameters

Name
Spec Name From To
T1+T2 Vdd On to LVDS Active .1 Vdd LVDS Active
Panel Vdd must be on for a minimum time before the LVDS data
stream is enabled.
T5 Backlight LVDS Active Backlight on
LVDS data must be enabled for a minimum time before the backlight
is turned on.
TX Backlight State Backlight Off LVDS off
Backlight must be disabled for a minimum time before the LVDS

data stream is stopped.
T3 LVDS State LVDS Off Start power

off
Data must be off for a minimum time before the panel VDD is turned
off.
T4 Power cycle Delay Power Off Power On

Sequence
When panel VDD is turned from On to Off, a minimum wait must be
Start
satisfied before the panel VDD is enabled again.
6.5.2.8 Back Light Inverter Control

The GMCH offers integrated PWM for TFT panel Backlight Inverter control. Other methods of
control are specified below:
• SMBus-based Backlight Brightness Control
• GMBus-based Backlight Brightness Control
• PWM – based Backlight Brightness Control
• DBL(Display Brightness Link) –to- VDL (Video Data Link) Power Sequencing.
6.5.2.9 Digital Video Output Port

The GMCH has the capability to support additional digital display devices (e.g. TMDS
transmitter, LVDS transmitter or TV-out encoder) through its digital video output port. DVOB
and C can each deliver a 165 MHz dot clock on each of their 12-bit interfaces, or 330 MHz dot
clock on a combined 24-bit interface.
The digital display port consists of a digital data bus, VSYNC, HSYNC, and BLANK# signals.
The data bus can operate only in a 12-bit mode. Embedded sync information or HSYNC and
VSYNC signals can optionally provide the basic timing information to the external device and the
BLANK# signal indicates which clock cycles contain valid data. The BLANK# signal can be
optionally selected to include the border area of the timing. The VSYNC and HSYNC signals can
be disabled when embedded sync information is to be used or to support DPMS. Optionally a
STALL signal can cause the next line of data to not be sent until the STALL signal is removed.
Datasheet 157
Optionally the FIELD pin can indicate to the overlay which field is currently being displayed at
the display device.
6.5.2.10 Intel 855GME GMCH AGP Interface Overview

The GMCH support 1.5 V AGP 1X/2X/4X devices. The AGP signal buffers are 1.5 V
drive/receive (buffers are not 3.3 V tolerant). The GMCH support 2X/4X source synchronous
clocking transfers for read and write data, and sideband addressing. The GMCH also support 2X
and 4X clocking for Fast Writes initiated from the GMCH (on behalf of the processor).
AGP PIPE# or SBA[7:0] transactions to DRAM do not get snooped and are, therefore, not
coherent with the processor caches. AGP FRAME# transactions to DRAM are snooped. AGP
PIPE# and SBA[7:0] accesses to and from the hub interface are not supported. AGP FRAME#
access from an AGP master to the hub interface is also not supported. Only the AGP FRAME
memory writes from the hub interface are supported.
6.5.2.11 AGP Target Operations

As an initiator, the GMCH does not initiate cycles using AGP enhanced protocols. The GMCH
supports AGP cycles targeting interface to main memory only. The GMCH supports interleaved
AGP PIPE#] and AGP FRAME#, or AGP SBA[7:0] and AGP FRAME# transactions.
Table 39. AGP Commands Supported by the GMCH when Acting as an AGP Target
GMCH Host Bridge

AGP Command C/BE[3:0]#
Encoding
Cycle Destination Response as PCIx Target
Read 0000 Main Memory Low Priority Read
0000 The Hub interface Complete locally with random data; does not go
to the hub interface
Hi-Priority Read 0001 Main Memory High Priority Read
0000 The Hub interface Complete locally with random data; does not go
Reserved 0010 N/A No Response
Write 0100 Main Memory Low Priority Write
0100 The Hub interface Cycle goes to DRAM with BE’s inactive; does
not go to the hub interface
Hi-Priority Write 0101 Main Memory High Priority Write
0101 The Hub interface Cycle goes to DRAM with BE’s inactive; does
not go to the hub interface
Long Read 1000 Main Memory Low Priority Read
The Hub interface Complete locally with random data; does not go
158 Datasheet
GMCH Host Bridge

AGP Command C/BE[3:0]#
Encoding
Cycle Destination Response as PCIx Target
Hi-Priority Long 1001 Main Memory High Priority Read

Read
The Hub interface Complete locally with random data; does not go
Flush 1010 GMCH Complete with QW of Random Data
Fence 1100 GMCH No Response - Flag inserted in GMCH request

queue
NOTE: N/A refers to a function that is not applicable.
As a target of an AGP cycle, the GMCH supports all the transactions targeted at main memory
(summarized in the table above). The GMCH supports both normal and high-priority, read and
write requests. The GMCH does not support AGP cycles to the hub interface. PIPE# and SBA
cycles are assumed not to require coherency management and all AGP initiator accesses to main
memory using AGP PIPE# or SBA protocol are treated as non-snoopable cycles. These accesses
are directed to the AGP aperture in main memory that is programmed as either uncacheable (UC)
memory or write combining (WC) in the processor’s MTRRs.
6.5.3 AGP Transaction Ordering

The GMCH observes transaction ordering rules as defined by the AGP Interface Specification
Rev 2.0.
6.5.4 AGP Signal Levels

The 4X data transfers use 1.5 V signaling levels as described in the AGP Interface Specification
Rev 2.0. The GMCH supports 1X/2X data transfers using 1.5 V signaling levels.
6.5.5 4X AGP Protocol

In addition to the 1X and 2X AGP protocol, the GMCH supports 4X AGP read and write data
transfers and 4X sideband address generation. The 4X operation is compliant with AGP 2.0
specification.
The GMCH indicates that it supports 4X data transfers through RATE[2] (bit 2) of the AGP
Status Register. When DATA_RATE[2] of the AGP Command Register is set to 1 during system
initialization, the GMCH performs AGP read/write data transactions using 4X protocol. This bit is
not dynamic. Once this bit is set during initialization, the data transfer rate will not change.
Datasheet 159
The 4X data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4X
data transfer protocol is identical to 1X/2X protocol. In 4X mode 16 bytes of data are transferred
on every 66 MHz clock edge. The minimum throttleable block size remains four, 66 MHz clocks,
which means 64 bytes of data are transferred per block. Three additional signal pins are required
to implement the 4X data transfer protocol. These signal pins are complementary data transfer
strobes for the AD bus (2) and the SBA bus (1).
6.5.5.1 Fast Writes

The GMCH supports 2X and 4X Fast Writes from the GMCH to the graphics controller on AGP.
Fast Write operation is compliant with the AGP 2.0 specification.
The GMCH will not generate Fast Back to Back (FB2B) cycles in 1X mode, but will generate
FB2B cycles in 2X and 4X Fast Write modes.
To use the Fast Write protocol, the Fast Write Enable configuration bit, AGPCMD[FWEN] (bit 4
of the AGP Command Register), must be set to 1.
Memory writes originating from the host or from the hub interface use the Fast Write protocol
when it is both capability enabled and enabled. The data rate used to perform the Fast Writes is
dependent on the bits set in the AGP Command Register bits 2:0 (DATA_RATE). If bit 2 of the
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 4X strobing. If bit 1 of
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 2X strobing. If bit 0 of
AGPCMD[DATA_RATE] field is 1, Fast Writes are disabled and data transfers occur using
standard PCI protocol. Note that only one of the three DATA_RATE bits may be set by
initialization software. This is summarized in the following table.
Table 40. Fast Write Initialization
FWEN DATA_RATE DATA_RATE DATA_RATE GMCH =>AGP Master Write

[2] [1] [0] Protocol
0 X x x 1X
1 0 0 1 1X
1 0 1 0 2X Strobing
1 1 0 0 4X Strobing
6.5.5.2 AGP FRAME# Transactions on AGP

The GMCH accepts and generates AGP FRAME# transactions on the AGP bus. The GMCH
guarantees that AGP FRAME# accesses to DRAM are kept coherent with the processor caches by
generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not supported.
GMCH Initiator and Target Operations

Table 41 summarizes GMCH target operation for AGP FRAME# initiators. The cycles can be
either destined to main memory or the hub interface.
160 Datasheet
Table 41. PCI Commands Supported by the GMCH When Acting as a FRAME# Target
GMCH
PCI Command C/BE[3:0]# Encoding
Cycle Destination Response as A FRAME#
Target
Interrupt Acknowledge 0000 N/A No Response
Special Cycle 0001 N/A No Response
I/O Read 0010 N/A No Response
I/O Write 0011 N/A No Response
Memory Read 0110 Main Memory Read
0110 The Hub interface No Response
Memory Write 0111 Main Memory Posts Data
Configuration Read 1010 N/A No Response
Configuration Write 1011 N/A No Response
Memory Read Multiple 1100 Main Memory Read
Dual Address Cycle 1101 N/A No Response
Memory Read Line 1110 Main Memory Read
Memory Write and 1111 Main Memory Posts Data

Invalidate
NOTE: N/A refers to a function that is not applicable.
As a target of an AGP FRAME# cycle, the GMCH only supports the following transactions:
• Memory Read, Memory Read Line, and Memory Read Multiple. These commands are
supported identically by the GMCH. The GMCH does not support reads of the hub interface
bus from AGP.
• Memory Write and Memory Write and Invalidate. These commands are aliased and
processed identically. The GMCH does not support writes to the hub interface bus from
AGP.
• Other Commands. Other commands such as I/O R/W and Configuration R/W are not
supported by the GMCH as a target and result in master abort.
• Exclusive Access. The GMCH does not support PCI locked cycles as a target.
Datasheet 161
• Fast Back-to-Back Transactions. GMCH as a target supports fast back-to-back cycles from an
AGP FRAME# initiator.
As an initiator of AGP FRAME# cycle, the GMCH only supports the following transactions:
• Memory Read and Memory Read Line. GMCH supports reads from host to AGP. GMCH
does not support reads from the hub interface to AGP.
• Memory Read Multiple. This command is not supported by the GMCH as an AGP FRAME#
initiator.
• Memory Write. GMCH initiates AGP FRAME# cycles on behalf of the host or the hub
interface. GMCH does not issue Memory Write and Invalidate as an initiator. GMCH does
not support write merging or write collapsing. GMCH allows non-snoopable write
transactions from the hub interface to the AGP bus.
• I/O Read and Write. I/O read and write from the host are sent to the AGP bus. I/O base and
limit address range for AGP bus are programmed in AGP FRAME# configuration registers.
All other accesses that do not correspond to this programmed address range are forwarded to
the hub interface.
• Exclusive Access. GMCH does not issue a locked cycle on the AGP bus on behalf of either
the host or the hub interface. The hub interface and host locked transactions to AGP are
initiated as unlocked transactions by the GMCH on the AGP bus.
• Configuration Read and Write. Host Configuration cycles to AGP are forwarded as Type 1
Configuration Cycles.
• Fast Back-to-Back Transactions. GMCH as an initiator does not perform fast back-to-back
cycles.
GMCH Retry/Disconnect Conditions

The GMCH generates retry/disconnect according to the AGP Specification rules when being
accessed as a target from the AGP FRAME# device.
Delayed Transaction
When an AGP FRAME#-to-DRAM read cycle is retried by the GMCH, it is processed internally
as a Delayed Transaction.
The GMCH supports the delayed transaction mechanism on the AGP target interface for the
transactions issued using AGP FRAME# protocol. This mechanism is compatible with the PCI
2.1 Specification. The process of latching all information required to complete the transaction,
terminating with retry, and completing the request without holding the master in wait-states is
called a delayed transaction. The GMCH latches the address and command when establishing a
Delayed Transaction. The GMCH generates a Delayed transaction on the AGP only for AGP
FRAME# to DRAM read accesses. The GMCH does not allow more than one Delayed
transaction access from AGP at any time.
162 Datasheet
6.5.6 Concurrent and Simultaneous Display

The GMCH has two independent pipes, each with its own timing generator and dot clock, and
thus is able to support two displays concurrently. Windows 98* and Windows 2000* have
enabled support for multi-monitor display. There are two types of multi-monitor solutions:
concurrent and simultaneous. Concurrent displays different data on two screens whereas
simultaneous displays the same information on both displays. The GMCH also supports a
combination of concurrent and simultaneous displays.
Datasheet 163
164 Datasheet
Power and Thermal Management
7 Power and Thermal Management

The Intel 855GM/855GME GMCH chipset platform is intended to be compliant with the
following specifications and technologies:
• APM Rev 1.2
• PCI Power Management Rev 1.0
• PC’99, Rev 1.0, PC’99A, and PC’01, Rev 1.0
• ACPI 1.0b and 2.0 support
• ACPI S0, S1-M, S3, S4, S5, C0, C1, C2, C3 states
• Internal Graphics Adapter D0, D1, D3 (Hot/Cold)
• On Die Thermal sensor, enabling core and system memory Write Thermal throttling for
prevention of catastrophic thermal conditions
• External Thermal sensor input pin
• Enabling SO-DIMM Thermal throttling
• The GMCH also reduces I/O power dynamically, by disabling sense amps on input buffers,
as well as tristating output buffers when possible
• Dynamic Clock Power Down reduces power in all modes of operation
• System memory Self-Refresh in C3 state (Intel 855GME GMCH)
• Enhanced Intel SpeedStep technology (using Intel Pentium M processor)
• Flat Panel Power Sequencing
• Intel 855GM/GME GMCH reduces I/O power dynamically by disabling sense amps on the
input buffers, as well as tri-stating the output buffers when possible
7.1 General Description of Supported CPU States

C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK is
deasserted, and the processor core is active. The processor can service snoops and maintain cache
coherency in this state.
C1 (Auto Halt): The first level of power reduction occurs when the processor executes an Auto-
Halt instruction. This stops the execution of the instruction stream and reduces the processor’s
power consumption. The processor can service snoops and maintain cache coherency in this state.
C2 (Stop Grant): To enter this low power state, STPCLK is asserted. The processor can still
service snoops and maintain cache coherency in this state.
C3 (Sleep or Deep Sleep): In these states the processor clock is stopped. The GMCH assumes
that no Hub interface cycles (except special cycles) will occur while the GMCH is in this state.
The processor cannot snoop its caches to maintain coherency while in the C3 state. The GMCH
Datasheet 165
will transition from the C0 state to the C3 state when software reads the Level 3 Register. This is
an ACPI defined register but BIOS or APM (via BIOS) can use this facility when entering a low
power state. The Host Clock PLL within the GMCH can be programmed to be shut off for
increased power savings and the GMCH uses the DPSLP signal input for this purpose.
C4 (Deeper Sleep): The C4 state appears to the GMCH as identical to the C3 state, but in this
state the processor core voltage is lowered. There are no internal events in GMCH for the C4 state
that differ from the C3 state. (C4 state not supported by Intel Celeron M processor)
7.2 7.2. General Description of ACPI States

• Internal Graphics Adapter:
• D0 Full on, display active
• D1 Low power state, low latency recovery. No display, system memory retained
• D3 Hot – All state lost other than PCI config. system memory lost (optionally)
• D3 Cold – Power off
CPU:
• C0 Full On
• C1 Auto Halt
• C2 Stop Clock. Clk to CPU still running. Clock stopped to CPU core.
• C3 Deep Sleep. Clock to CPU stopped.
• C4 Deeper Sleep. Same as C3 with reduced voltage on the CPU.
System States:
• G0/S0 Full On
• G1/S1-M Power On Suspend (POS). System Context Preserved
• G1/S2 Not supported.
• G1/S3 Suspend to RAM (STR). Power and context lost to chipset.
• G1/S4 Suspend to Disk (STD). All power lost (except wakeup on ICH4-M)
• G2/S5 Soft off. Total reboot.
166 Datasheet
7.3 Enhanced Intel SpeedStep® Technology Overview

With Enhanced Intel SpeedStep technology the processor core voltage changes and allows true
CPU core frequency changes versus only clock throttling.
Table 42. Enhanced Intel SpeedStep® Technology Overview

® ®
CPU Intel Pentium M processor
Benefit Over Non-power Additional lower voltages and frequencies

Managed CPU
Transition Prompt OS based on CPU load demand, thermal control, or user event based
CPU Availability CPU unavailability can be restricted to ~250 µs (CPU dependent) by s/w
7.4 Internal Thermal Sensor

This section describes the new on-die Thermal sensor capability.
7.4.1 Overview
The Thermal sensor functions are provided below:
Catastrophic Trip Point: This trip point is programmed through the BIOS during initialization.
This trip point is set at the temperature at which the GMCH should be shut down immediately
with minimal software support. The settings for this are lockable.
High Temperature Trip Point: This trip point is nominally 14ºC below the Catastrophic trip
point. The BIOS can be programmed to provide an interrupt when it is crossed in either direction.
Upon the trip event, Hardware Throttling may be enabled when the temperature is exceeded.
7.4.2 Hysteresis Operation

Hysteresis provides a small amount of positive feedback to the Thermal sensor circuit to prevent a
trip point from flipping back and forth rapidly when the temperature is right at the trip point.
7.5 External Thermal Sensor Input

An External Thermal sensor with a serial interface may be placed next to DDR SDRAM SO-
DIMM (or any other appropriate platform location), or a remote Thermal Diode may be placed
next to the SO-DIMM (or any other appropriate platform location) and connected to the External
Thermal sensor. Intel advises that the External Thermal sensor contains some form of hysteresis,
since none is provided by the GMCH hardware.
The external sensor can be connected to the ICH4-M via the SMBus interface to allow
programming and setup by BIOS software over the serial interface. The External sensor’s output
Datasheet 167
should include an Active-Low Open-Drain signal indicating an Over-Temp condition, which

remains asserted for as long as the Over-Temp Condition exists, and deasserts when temperature
has returned to within normal operating range. This External sensor output will be connected to
the GMCH input (EXTTS_0) and will trigger a Preset Interrupt and/or Read-Throttle on a level-
sensitive basis.
Additional External Thermal sensor’s outputs, for multiple sensors, can be wire-OR'ed together
allow signaling from multiple sensors located physically separately. Software can, if necessary,
distinguish which SO-DIMM(s) is the source of the over-temp through the serial interface.
However, since the SO-DIMM(s) will be located on the same System Memory Bus Data lines,
any GMCH-based Read Throttle will apply equally.
Note: The use of external sensors that include an internal pull-up resistor on the open-drain Thermal trip
output is discouraged. However, it may be possible depending on the size of the pull-up and the
voltage of the sensor. Please refer to the Intel® Pentium® M Processor, Intel® Celeron® M
Processor, and Intel® 855GM/855GME GMCH Platform Design Guide.
7.5.1 Usage
External sensor(s) used for dynamic temperature feedback control:
• Sensor on SO-DIMMs, which can be used to dynamically control read throttling.
168 Datasheet
Electrical Characteristics
8 Electrical Characteristics
8.1 Absolute Maximum Ratings

Table 43 lists the Intel 855GM/855GME GMCH maximum environmental stress ratings.
Functional operation at the absolute maximum and minimum is neither implied nor guaranteed.
Functional operating parameters are listed in the AC and DC tables.
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operating beyond the “operating conditions” is not recommended
and extended exposure beyond “operating conditions” may affect reliability.
Table 43. Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
Intel 855GM/855GME GMCH Common
Tdie Die Temperature under Bias 0 105 °C 1
Tstorage Storage Temperature -55 150 °C 2
VCC 1.2 V Core Supply Voltage with respect to VSS -0.3 1.65 V
VTTLF 1.05 V AGTL+ buffer DC Input Voltage with respect -0.3 1.55 V
to VSS
VCCHL 1.2 V Hub Interface Supply Voltage with respect to -0.3 1.65 V
VSS
VCCADAC 1.5 V DAC Supply Voltage with respect to VSS -0.3 1.65 V
VCCDVO 1.5 V Supply Voltage with respect to VSS -0.3 1.65 V
VCCDLVDS 1.5 V LVDS Digital power supply -0.3 1.65 V
VCCTXLVDS 2.5 V LVDS Data/Clock Transmitter Supply Voltage -0.3 3.25 V

with respect to VSS
VCCALVDS 1.5 V LVDS Analog Supply voltage with respect to -0.3 1.65 V
VSS
VCCSM 2.5 V DDR System Memory Data Buffers Supply -0.3 3.25 V
Voltage with respect to VSS
VCCQSM 2.5 V DDR System Memory Clock Buffers Supply -0.3 3.25 V
Voltage with respect to VSS
VCCASM 1.2 V DDR System Memory Logic Supply Voltage -0.3 1.65 V
(DDR 200/266 (not connected to Core) with respect to VSS
SDRAM)
VCCGPIO 3.3 V GPIO Supply Voltage with respect to VSS -0.3 3.6 V
Datasheet 169
Symbol Parameter Min Max Unit Notes
VCCAHPLL, Power supply for the Host PLL, Power Supply for the -0.3 1.65 V
VCCAGPLL, Hub PLL, Power supply for the Display PLL A, Power
VCCADPLLA, supply for the Display PLL B, respectively
VCCADPLLB
Intel 855GME GMCH Only
VCC 1.35 V Core Supply Voltage with respect to VSS -0.3 1.65 V
VCCHI 1.35 V Hub Interface Supply Voltage with respect to -0.3 1.65 V
VSS
VCCASM 1.35 V DDR SDRAM System Memory Logic Supply -0.3 1.65 V
(DDR333 Voltage (not connected to Core) with respect to VSS
SDRAM)
VCCAHPLL, Power supply for the Host PLL, Power Supply for the -0.3 1.65 V
VCCAGPLL, Hub PLL, Power supply for the Display PLL A, Power
VCCADPLLA, supply for the Display PLL B, respectively
VCCADPLLB
NOTES:
1. Functionality is not guaranteed for parts that exceed Tdie temperature above 105 °C. Full performance
may be affected if the on-die thermal sensor is enabled. Please refer to the Intel®
852GM/855GM/855GME Chipset Mobile Thermal Design Guide for supplementary details.
2. Possible damage to the GMCH may occur if the GMCH temperature exceeds 150 °C. Intel does not
guarantee functionality for parts that have exceeded temperatures above 150 °C due to spec
violation.
8.2 Thermal Characteristics

The Intel 855GM/855GME GMCH is designed for operation at die temperatures between 0°C and
105 °C. The thermal resistance of the package is given in Table 44.
Table 44. Intel® 855GM/855GME GMCH Package Thermal Resistance
Parameter Airflow Velocity in Meters/Second
0 m/s 1 m/s
Ψjt (°C/Watt)** 0.5 1.8
Θja (°C/Watt)** 20.0 17.3
NOTE: ** Estimate
170 Datasheet
8.3 Power Characteristics

Table 45. Power Characteristics
Symbol Parameter Min Typ Max Unit Notes
Intel 855GM GMCH Only
TDPTyp Thermal Design Power < 3.2 W
Intel 855GME GMCH Only
TDPTyp (max Thermal Design Power (Internal < 4.3 W

performance) Graphics)
TDPTyp (max Thermal Design Power (AGP Discrete < 3.2 W

performance) Graphics)
IVCCmax 1.35 V Core Supply Current 2.24 A
IVCCHI 1.35 V Hub Interface Supply Current 0.09 A
IVCCASM 1.35 V DDR SDRAM System Memory 0.09 A

DLL Supply Current (DDR333 SDRAM)
Intel 855GM/855GME GMCH Common
IGTL 1.05 V Intel® Pentium® M Processor 0.69 A

AGTL+ Supply Current and 1.05 V
Dothan Processor AGTL+ Supply
Current
IVCCmax 1.2 V Core Supply Current 1.29 A
IVCCDLVDS 1.5 V LVDS (Digital) Supply Current 0.04 A
IVCCALVDS 1.5 V LVDS (Analog) Supply Current 0.07 A
IVCCTXLVDS 2.5 V LVDS (I/O) Supply Current 0.05 A
IVCCDAC 1.5 V DAC Supply Current 0.07 A
IVCC1_5_DVO 1.5 V DVO/AGP Supply Current 0.09 A
IVCCHI 1.2 V Hub Interface Supply Current 0.09 A
IVCCGPIO 3.3 V GPIO Supply Current 0.02 A
IVCCSM 2.5 V DDR SDRAM System Memory 1.60 A

Data Buffer Supply Current (DDR266
SDRAM)
2.5 V DDR SDRAM System Memory 1.80 A

Data Buffer Supply Current (DDR333
SDRAM for Intel 855GME GMCH only)
IVCCASM 1.2 V DDR SDRAM System Memory 0.24 A

DLL Supply Current (DDR266 SDRAM)
Datasheet 171
Symbol Parameter Min Typ Max Unit Notes
IVCCQSM 2.5 V DDR SDRAM System Memory 0.14 A

Clock Buffers Supply Current (DDR266
SDRAM)
2.5 V DDR SDRAM System Memory 0.18 A

Clock Buffers Supply Current (DDR333
SDRAM)
ISUS_VCCSM 2.5 V DDR SDRAM System Memory 1 mA

Interface Standby Supply Current
ISMVREF_0 1.25 V DDR SDRAM System Memory 0.05 mA

Interface Reference Voltage Supply
Current
ISUS_SMVREF_0 1.25 V DDR SDRAM System Memory 0.05 mA

Interface Reference Voltage Standby
Supply Current
ITTRC/RCOMP 1.25 V DDR SDRAM System Memory 40 mA

Interface Resister Compensation
Voltage Supply Current
ISUS_TTRC 1.25 V DDR SDRAM System Memory 0 mA

Interface Resister Compensation
Voltage Standby Supply Current
NOTE: This spec is the Thermal Design Power and is the estimated maximum possible expected power
generated in a component by a realistic application. It is based on extrapolations in both hardware and
software technology over the life of the component. It does not represent the expected power
generated by a power virus. Studies by Intel indicate that no application will cause thermally significant
power dissipation exceeding this specification, although it is possible to concoct higher power synthetic
workloads that write but never read. Under realistic read/write conditions, this higher power workload
can only be transient and is accounted in the Icc (Max) spec.
8.4 Signal Groups

The signal description includes the type of buffer used for the particular signal:
Signal Type Description
AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The Intel 855GM/855GME GMCH integrate most AGTL+ termination
resistors
DVO/AGP DVO buffers, these are 1.5 V tolerant.
Hub Compatible to Hub Interface 1.5
SSTL_2 Stub Series Termination Logic compatible signals (2.5 V tolerant)
LVTTL Low Voltage TTL compatible signals (3.3 V tolerant)
CMOS CMOS buffers (3.3 V tolerant)
LVDS Low Voltage Differential signal interface
Analog Analog signal interface
Ref Voltage reference signal
172 Datasheet
Table 46. Table Signals
Signal Signal Type Signals Notes

Group
Host Interface Signal Groups
(a) AGTL+ ADS#, BNR#, BREQ0#,DBSY#, DRDY#, DINV[3:0]#,

HA[31:3]#, HADSTB[1:0]#, HD[63:0]#,HDSTBP[3:0]#,
Input/Outputs
HDSTBN[3:0]#, HIT#, HITM#, HREQ[4:0]#, HLOCK#
(b) AGTL+ BPRI#, CPURST#, DEFER#, HTRDY#, RS[2:0]#, DPWR#

Common Clock
Outputs
(d) Analog/Ref HAVREF, HCCVREF, HDVREF[2:0], HXSWING,

Host Miscellaneous HYSWING, HXRCOMP, HYRCOMP
Signals
(c) AGTL+ DPSLP#, HLOCK#

Asynchronous Input
DVO Signal Groups
(e) DVO DVOBCCLKINT, DVOCFLDSTL, DVOBCINTR#,

Inputs DVOBFLDSTL, ADDID[7:0], DVODETECT
(f) DVO DVOCD[11:0], DVOCHSYNC, DVOCVSYNC,

Outputs DVOCBLANK#, DVOBD[11:0], DVOBHSYNC,
DVOBVSYNC, DVOBBLANK#
(e),(f) DVO MI2CCLK, MI2CDATA, MDVICLK, MDVIDATA,

DDC/I2C Input/Output MDDCDATA, MDDCCLK
(g) Analog/Ref GVREF, DVORCOMP

DVO Miscellaneous
Signals
AGP Signal Groups
(m1) AGP I/O AD_STB0, AD_STB0#, AD_STB1, AD_STB1#,

G_FRAME#, G_IRDY#, G_TRDY#, G_STOP#,
G_DEVSEL#, G_AD[31:0], G_CBE[3:0]#, G_PAR
(m2) AGP Input PIPE#, SBA[7:0], RBF#, WBF#, SBSTB, SBSTB#, G_REQ#
(m3) AGP Output GST[2:0], G_GNT#
LVDS Signal Groups
(h) LVDS IYAP[3:0], IYAM[3:0], IYBP[3:0], IYBM[3:0]

LVDS Outputs
(i) Analog LIBG

LVDS Miscellaneous
DAC Signal Groups
(j) CMOS/Analog RED, RED#, GREEN, GREEN#, BLUE, BLUE#

DAC Outputs
(k) Analog/Ref REFSET

DAC Miscellaneous
Datasheet 173

Group
Hub Interface Signal Groups
(l) CMOS HL[10:0], HLSTB, HLSTB#
HI Inputs/Outputs
(m) Analog/Ref HLRCOMP, PSWING, HLVREF
HI Miscellaneous
DDR SDRAM Interface Signal Groups
(n) SSTL_2 SDQ[63:0], SDQS[7:0]

DDR Input/Outputs
(o) SSTL_2 SCS[3:0]#, SMA[12:0], SBA[1:0], SRAS#, SCAS#, SWE#,

DDR Outputs SCKE[3:0], SMAB[5,4,2,1], SDM[7:0]
(p) Analog/Ref SMVREF_0, SMVSWINGH, SMVSWINGL, SMRCOMP

DDR Miscellaneous
Clocks, Reset, and Miscellaneous Signal Groups
(q) CMOS RSTIN#(3.3V), PWROK, EXTTS_0

Inputs
(r) CMOS AGPBUSY#,PANELVDDEN, PANELBKLTEN,

Outputs PANELBKLTCTL, LCLKCTLA, LCLKCTLB, HSYNC,
VSYNC
2
(q),(r) CMOS DDC/I C DDCADATA, DDCPDATA, DDCACLK, DDCPCLK
Input/Outputs
(t) CMOS GCLKIN

Clock Inputs
(u) CMOS SCK[5:0], SCK[5:0]#

Clock Outputs
(w) 1.5 V DPMS

Clock Inputs
(x) DVO DVOCCLK, DVOCCLK#, DVOBCLK, DVOBCLK#

Clock Outputs
(z) CMOS BCLK, BCLK#

Low Voltage Differential
Inputs
(a1) LVTTL DREFCLK, DREFSSCLK

Inputs
(b1) LVDS ICLKAP, ICLKAM, ICLKBP, ICLKBM

Clock Outputs
I/O Buffer Supply Voltages/Grounds (Intel 855GME GMCH Only)
(n1) 1.35 V VCC

Core
(p1) 1.35 V VCCHL

Hub Interface
(s1) 1.35 V VCCAGPLL, VCCAHPLL, VCCADPLLA, VCCADPLLB

PLL
174 Datasheet

Group
(q1) 1.35V VCCASM

DDR SDRAM DLL
Supply
I/O Buffer Supply Voltages/Grounds (Intel 855GM/855GME GMCH Common)
(m1) AGTL+ VTTLF

Power Supply
(d1) 1.2 V VCC

Core
(e1) 1.2 V VCCHL

Hub Interface
(f1) 1.2 V VCCAGPLL, VCCAHPLL, VCCADPLLA, VCCADPLLB

PLL
(g1) 2.5 V VCCSM, VCCQSM

DDR SDRAM Supply
(g1) 1.2V VCCASM

DDR SDRAM DLL
Supply
(h1) 1.5 V VCCDVO

DVO Supply
(i1) 1.5 V VCCADAC

DAC Supply
(j1) 3.3 V VCCGPIO

GPIO Supply
(k1) 1.5 V VCCDLVDS

LVDS Digital Supply
(k1) 2.5 V VCCTXLVDS

LVDS Data/CLK
Transmitter Supply
(k1) 1.5 V VCCALVDS

LVDS Analog Supply
Datasheet 175
8.5 DC Characteristics
8.5.1 General DC Characteristics

Table 47. DC Characteristics
Symbol Signal Parameter Min Nom Max Unit Notes

Group
Supply Voltages (Intel 855GME GMCH Only)
VCC (n1) Core Voltage 1.28 1.35 1.42 V
VCCHL (p1) HI I/O Supply 1.28 1.35 1.42 V

Voltage
VCCASM (q1) DDR SDRAM 1.28 1.35 1.42 V

I/O Supply
Voltage
VCCAGPLL (s1) PLL Supply 1.28 1.35 1.42 V

VCCAHPLL Voltage
VCCADPLLA
VCCADPLLB
Supply Voltages (Intel 855GM/855GME GMCH Common)
VTTLF (m1) AGTL+ Power 1.0 1.05 1.1 V

Supply
VCCSM (g1) DDR SDRAM 2.375 2.5 2.625 V

I/O Supply
VCCQSM
Voltage
VCCASM (g1) DDR SDRAM 1.14 1.2 1.26 V

I/O Supply
Voltage
VCCHL (e1) HI I/O Supply 1.14 1.2 1.26 V

Voltage
VCCAGPLL (f1) PLL Supply 1.14 1.2 1.26 V

VCCAHPLL Voltage
VCCADPLLA
VCCADPLLB
VCC (d1) Core Voltage 1.14 1.2 1.26 V
VCCDVO (h1) DVO I/O 1.425 1.5 1.575 V

Voltage
VCCDLVDS (k1) Digital LVDS 1.425 1.5 1.575 V

Supply
Voltage
VCCTXLVDS (k1) Data/Clock 2.375 2.5 2.625 V

Transmitter
LVDS Supply
Voltage
176 Datasheet

Group
VCCALVDS (k1) Analog LVDS 1.425 1.5 1.575 V

Supply
Voltage
VCCADAC (i1) DAC Supply 1.425 1.5 1.575 V

Voltage
VCCGPIO (j1) CMOS 3.135 3.3 3.465 V

Supply
Voltage
Reference Voltages
HAVREF (d) Host Address (0.66 x 0.66 x (0.66 x V

and VTTLF) – VTTLF VTTLF)+
Reference 2% 2%
Voltage
HDVREF[2:0] (d) Host Data (0.66 x 0.66 x (0.66 x V

Reference VTTLF) – VTTLF VTTLF)+
Voltage 2% 2%
HCCVREF (d) Host Common (0.66 x 0.66 x (0.66 x V

Clock Voltage VTTLF) – VTTLF VTTLF)+
2% 2%
HXSWING (d) Host (0.33 x 0.33 x (0.33 x V

Compensation VTTLF)– VTTLF VTTLF) +
HYSWING
Reference 2% 2%
Voltage
HLVREF (m) Hub Interface 0.343 0.350 0.357 V

Reference
Voltage
SMVREF_0 (p) DDR 0.49 x 0.5 x 0.51 x V

Reference VCCSM VCCSM VCCSM
Voltage
GVREF (g) DVO 0.73 0.75 0.77 V

Reference
Voltage
PSWING (m) RCOMP 0.8 – 2% 0.8 0.8 + 2% V

Buffer
Differential
Amp
Reference
Voltage
SMVSWINGH (p) System (VCCSM* VCCSM * (VCCSM* V

Memory 0.8)-2% 0.8 0.8) + 2%
RCOMP
Buffer
Differential
Amp
Reference
Voltage
Datasheet 177

Group
SMVSWINGL (p) System (VCCSM VCCSM * (VCCSM * V

Memory * 0.2) - 2 0.2 0.2) + 2%
RCOMP %
Buffer
Differential
Amp
Reference
Voltage
Host Interface
VIL_H (a), (c) Host AGTL+ -0.10 0 (0.66 x V

Input Low VTTLF) –
Voltage 0.1
VIH_H (a),(c) Host AGTL+ (0.66 x VTT VTTLF+ V

Input High VTTLF) + 0.1
Voltage 0.1
VOL_H (a),(b) Host AGTL+ (0.33 x V

Output Low VTTLF) +
Voltage 0.1
VOH_H (a),(b) Host AGTL+ VTTLF- VTTLF V

Output High 0.1
Voltage
IOL_H (a),(b) Host AGTL+ VTTLFma mA Rttmin

Output Low x/0.75Rtt =45 
Current min
ILEAK_H (a),(c) Host AGTL+ 2 µA VOL<

Input Leakage Vpad<
Current VTTL
F, 2
CPAD (a),(c) Host AGTL+ 1 1.1 1.3 pF

Input
Capacitance
CPCKG (a),(c) Host AGTL+ 1 2 2.5 pF 1

Input
Capacitance
(common
clock)
DDR Interface
VIL(DC) (n) DDR SDRAM SMVREF V

Input Low – 0.15
Voltage
VIH(DC) (n) DDR SDRAM SMVREF V

Input High + 0.15
Voltage
VIL(AC) (n) DDR SDRAM SMVREF V

Input Low – 0.31
Voltage
178 Datasheet

Group
VIH(AC) (n) DDR SDRAM SMVREF V

Input High + 0.31
Voltage
VOL (o), (u) DDR SDRAM 0.6 V

Output Low
Voltage
VOH (o), (u) DDR SDRAM 1.9 V

Output High
Voltage
IOL (o), (u) DDR SDRAM 30 mA

Output Low
Current
IOH (o), (u) DDR SDRAM -30 mA

Output High
Current
ILeak (n) Input Leakage ±10 µA

Current
CPAD (n) DDR SDRAM 4 5 6 PF

Input/Output
Pin
Capacitance
CPCKG (n) DDR SDRAM 1 2 3 PF 1

Input/Output
Pin
Capacitance
1.5V AGP Interface
VIL_A (m1), (m2) AGP Input GVREF – V

Low Voltage 0.15
VIH_A (m1), (m2) AGP Input GVREF+ V

High Voltage 0.15
VOL_A (m1), (m3) AGP Output 0.225 V

Low Voltage
VOH_A (m1), (m3) AGP Output 1.275 V

High Voltage
IOL_A (m1), (m3) AGP Output 6.9 mA @0.15

Low Current VDDQ
IOH_A (m1), (m3) AGP Output -6.9 mA @.85

High Current VDDQ
ILEAK_A (m1), (m2) AGP Input ±10 µA 0<Vin

Leakage <
Current VCCD
VO
CPAD (m1), (m2) AGP Input 3 3.5 4 pF FC=1

Capacitance MHz
CPCKG (m1), (m2) AGP Input 1 2 3 pF 1

Capacitance
Datasheet 179

Group
1.5 V DVO Interface: Functional Operating Range (VCC=1.5 V± 5%)
DVO Input GVREF –

VIL_DVO (e), (w) V
Low Voltage 0.15
DVO Input GVREF+

VIH_DVO (e), (w) V
High Voltage 0.15
DVO Output
VOL_DVO (f), (x) 0.225 V
Low Voltage
DVO Output
VOH_DVO (f), (x) 1.275 V
High Voltage
DVO Output @0.15

IOL_DVO (f), (x) 6.9 MA
Low Current VDDQ
DVO Output @.85

IOH_DVO (f), (x) -6.9 MA
High Current VDDQ
0<Vin
DVO Input
<
ILEAK_DVO (e), (w) Leakage ±10 µA
VCCD
Current
VO
DVO Input FC=1

C PAD (e), (w) 3 3.5 4 PF
Capacitance MHz
DVO Input Pin

CPCKG (e), (w) 1 2 3 PF
Capacitance
1.2 V & 1.35 V Hub Interface
VIL_HI (l) Hub Interface HLVREF - V

Input Low 0.1
Voltage
VIH_HI (l) Hub Interface HLVREF V

Input High + 0.1
Voltage
VOL_HI (l) Hub Interface 0.05 V IOL= 1

Output Low mA
Voltage
VOH_HI (l) Hub Interface 0.75 V IOH = 1

Output High mA
Voltage
IOL_HI (l) Hub Interface 1 MA @VOL_

Output Low HI max
Current
IOH_HI (l) Hub Interface -1 mA @VOH_

Output High HI max
Current
ILEAK_HI (l) Hub Interface ±10 µA 0<Vin

Input Leakage <
Current VCCH
L
180 Datasheet

Group
CPAD (l) Hub Interface 2 3 4 pF

Input
Capacitance
CPCKG (l) Hub Interface 1 2 3 pF

Input
Capacitance
LVDS Interface: Functional Operating Range (VCC=2.5 V±5%)

Differential
VOD (h), (b1) 250 345 450 mV
Output Voltage
Change in VOD
between
∆VOD (h), (b1) 50 mV
Complimentary
Output States
VOS (h), (b1) Offset Voltage 1.125 1.25 1.375 V
Change in VOS
between
∆VOS (h), (b1) 50 mV
Complimentary
Output States
Output Short
IOs (h), (b1) -3.5 -10 mA
Circuit Current
Output TRI-
IOZ (h), (b1) STATE ±1 ±10 µA
Current
Miscellaneous Signals
VIL (q) Input Low 0.80 V

Voltage
(CMOS
Inputs)
VIH (q) Input High 2.0 V

Voltage
(CMOS
Inputs)
VOL (r) Output Low 0.1 x V IOL=

Voltage VCC 1 mA
(CMOS
Outputs)
VOH (r) Output High 0.9 x V IOH =

Voltage VCC 1 mA,
(CMOS 7
Outputs)
IOL (r) Output Low 1 mA @VO

Current L_HI
(CMOS max
Outputs)
IOH (r) Output High -1 mA @VO

Current H_HI
(CMOS min
Outputs)
Datasheet 181

Group
ILEAK (q) Input Leakage ±10 µA 0<Vin

Current <
VCCH
(CMOS
L
Inputs)
Cpad (a1) Input 1 1.25 1.5 pF

Capacitance
(LVTTL
Inputs)
CPCKG (q) Input 1 2 3 pF 1

Capacitance
(CMOS
Inputs)
CPAD (q) Input 2.5 3.05 3.6 pF

Capacitance
(CMOS
Inputs)
CPCKG (q) Input 1 2 3 PF 1

Capacitance
(CMOS
Inputs)
VIL (z) Input Low -0.15 0 V

Voltage
(CMOS Low
Voltage
Differential)
VIH (z) Input High 0.660 0.710 0.850 V

Voltage
(CMOS Low
Voltage
Differential)
VCROSS (z) Crossing 0.25 0.35 0.55 V

Voltage
(CMOS Low
Voltage
Differential)
CPAD (z) Input 1 1.1 1.2 pF

Capacitance
(CMOS Low
Voltage
Differential)
CPCKG (z) Input 1 2 3 pF 1

Capacitance
(CMOS Low
Voltage
Differential)
VIL (t), (a1) Input Low 0.8 V

Voltage
(CMOS/LVTT
L CLK Inputs)
182 Datasheet

Group
VIH (t), (a1) Input High 2.0 V

Voltage
(CMOS/LVTT
L CLK Inputs)
CPAD (t) Input 1 1.25 1.5 pF

Capacitance
(CMOS CLK
Inputs)
CPCKG (t) Input 1 2 3 pF 1

Capacitance
(CMOS CLK
Inputs)
NOTES:
1. CPCKG is the trace capacitance in the GMCH/MCH package.
8.5.2 DAC DC Characteristics

Table 48. DAC DC Characteristics: Functional Operating Range (VCCDAC = 1.5 V ±5%)
Parameter Min Typical Max Units Notes
DAC Resolution 8 Bits (1)
Max Luminance (full-scale) 0.665 0.700 0.770 V (1, 2, 4) white video level voltage
Min Luminance 0.000 V (1, 3, 4) black video level voltage
LSB Current 73.2 µA (4, 5)
Integral Linearity (INL) 0 +2.0 LSB (1, 6)
Differential Linearity (DNL) -1.0 +1.0 LSB (1, 6)
Video channel-channel voltage

6 % (7)
amplitude mismatch
Monotonicity Guaranteed
NOTES:
1. Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of Analog
Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. Max steady-state amplitude
3. Min steady-state amplitude
4. Defined for a double 75- termination.
5. Set by external reference resistor value.
6. INL and DNL measured and calculated according to VESA Video Signal Standards.
7. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage)
Note: Refer to the Intel® Pentium® M Processor and Intel® 855GM/855GME Chipset Platform Design
Guide for interconnect length specifications.
Datasheet 183
8.5.3 DAC Reference and Output Specifications

Table 49. DAC Reference and Output Specifications
Parameter Min Typical Max Units Notes
Reference resistor 124 127 130 Ω 1% tolerance, 1/16 W
R,G,B termination resistor 75 Ω (1) 1% tolerance, 1/16 W
Video Filter Ferrite Bead 75 Ω @ 100- MHz, (each R,G,B output)
Video Filter Capacitors 3.3 pF Two capacitors per R,G,B output
NOTES:
1. VESA Video Signal Standard
2. Complement DAC channel output termination resistors are only required for differential video routing to
the VGA connector.
184 Datasheet
Video Filter Capacitors and Ferrite Bead Arranged in a
PI Configuration (One PI Filter Testability)
9 Video Filter Capacitors and Ferrite

Bead Arranged in a
PI Configuration (One PI Filter
Testability)
In the Intel 855GM/GME GMCH, testability for automated test equipment (ATE) board level
testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with
one input pin connected to it. The XOR Chain test mode is used by product engineers during
manufacturing and OEMs during board level connectivity tests. The main purpose of this test
mode is to detect connectivity shorts between adjacent pins and to check proper bonding between
I/O pads and I/O pins.
Figure 10. XOR–Tree Chain
VCC1_2
XOR
Out
Input Input Input Input Input

xor.vsd
The algorithm used for in–circuit test is as follows:

1. Drive all input pins to an initial logic level 1. Observe the output corresponding to scan chain
being tested.
2. Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin,
from its initial logic level to the opposite logic level. Observe the output changes with each
pin toggle
Datasheet 185
9.1 XOR Test Mode Entry

Figure 11. XOR Chain Test Mode Entry Events Diagram
p o w e ro k
VSYNC D o n 't c a r e
HSYNC D o n 't c a r e
LC LKC TLA D o n 't c a r e
R S T IN # ( P C I r e s e t)
NOTE: HSYNC and LCLKCTLA = XOR Chain Test Mode Activation; No clock is required for XOR Chain Test
Mode. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A minimum
of 10 ns VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.
Figure 12. ALLZ Test Mode Entry Events Diagram
p o w e ro k
D o n 't c a r e
VSYNC
HSYNC D o n 't c a r e
LC LKC TLA D o n 't c a r e
R S T IN # ( P C I r e s e t)
NOTE: VSYNC and LCLKCTLA = ALL Z Test Mode Activation; No clock is required for ALLZ Test Mode
Activation. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A
minimum of 10 ns VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.
186 Datasheet
9.2 XOR Chain Differential Pairs

Table 50 provides differential signals in the XOR chains that must be treated as pairs. Pin1 and
Pin2 as shown below need to drive to the opposite value always.
Table 50. Differential Signals in the XOR Chains
Pin1 Pin2 XOR Chain
DVOCCLK# DVOCCLK DVO XOR 2
HLSTB# HLSTB HUB XOR
9.3 XOR Chain Exclusion List

See Table 51 for a list of pins that are not included in the XOR chains (excluding all
VCC/VSS/VTT).
Note: Connectivity column is used to identify what need to be driven on that particular pin during XOR
chain test mode.
Table 51. XOR Chain Exclusion List of Pins
Item# IN/OUT Ball Pin/VHDL I/O Type Voltage Connectivity
1 IN Y3 GCLKIN PLL CLK 3.3 0
2 - W1 HLVREF Analog 1/3 VCCHL 0.4
3 - T2 HLRCOMP Analog N/A N/A
4 - U2 PSWING Analog N/A N/A
1/2 0.75
5 - F1 GVREF Analog VCCDVO
6 - D1 DVORCOMP Analog N/A N/A
7 IN J11 PWROK CMOS 3.3 N/A
8 IN B7 DREFCLK PLL CLK 3.3 0
9 - E8 REFSET Analog N/A N/A
10 - C9 BLUE Analog N/A N/A
11 - D9 BLUE# Analog N/A N/A
12 - C8 GREEN Analog N/A N/A
13 - D8 GREEN# Analog N/A N/A
14 A7 RED Analog N/A N/A
15 - A8 RED# Analog N/A N/A
16 - D12 LVREFH Analog 1.1 1.1
17 - A10 LIBG Analog N/A N/A
Datasheet 187
Item# IN/OUT Ball Pin/VHDL I/O Type Voltage Connectivity
18 - B12 LVBG Analog N/A N/A
19 - F12 LVREFL Analog 1.1 1.1
20 IN B17 DREFSSCLK PLL CLK 3.3 0
21 - J17 HDVREF[2] Analog 2/3 VTTLF 1.0
22 - B20 HXRCOMP Analog N/A N/A
23 - B18 HXSWING Analog N/A N/A
24 - J21 HDVREF[1] Analog 2/3 VTTLF 1.0
25 IN AD29 BCLK# Diff 0.7 0
26 IN AE29 BCLK Diff 0.7 0.7
27 - K21 HDVREF[0] Analog 2/3 VTTLF 1.0
28 - Y28 HCCVREF Analog 2/3 VTTLF 1.0
29 - Y22 HAVREF Analog 2/3 VTTLF 1.0
30 - H28 HYRCOMP Analog N/A N/A
31 - K28 HYSWING Analog N/A N/A
32 IN D28 RSTIN# CMOS 3.3 N/A
33 - AJ24 SMVREF_0 Analog 1/2 VCCSM 1.25
34 - AB1 SMRCOMP Analog N/A N/A
9.4 XOR Chain Connectivity/Ordering

The following tables contain the ordering for all of the Intel 855GM/GME GMCH XOR chains
and pin to ball mapping information:
Table 52. XOR Mapping
XOR Chain DVO 1
DVO IN/OUT Ball Pin/VHDL I/O Type Voltage

XOR Out
OUT AB5 SMA[12] SSTL_2 2.5
1 INOUT T6 RSVD DVO 1.5
2 INOUT T5 RSVD DVO 1.5
3 INOUT T7 MDDCDATA DVO 1.5
4 INOUT R3 RSVD DVO 1.5
8 INOUT P2 RSVD DVO 1.5
188 Datasheet
11 INOUT P6 RSVD N/A N/A
12 INOUT P5 RSVD N/A N/A
13 INOUT N2 RSVD N/A N/A
15 INOUT M1 RSVD N/A N/A
19 INOUT M3 DVOBCCLKINT DVO 1.5
20 INOUT L2 RSVD N/A N/A
21 INOUT P7 MDDCCLK DVO 1.5
22 INOUT N6 MI2CDATA DVO 1.5
23 INOUT M6 MDVIDATA DVO 1.5
24 INOUT N7 MDVICLK DVO 1.5
25 INOUT L7 DVODETECT DVO 1.5
26 INOUT K7 MI2CCLK DVO 1.5
27 OUT B2 RSVD N/A N/A
28 IN B3 RSVD N/A N/A
XOR Chain DVO 2
DVO IN/OUT Ball Pin/VHDL I/O Type Voltage

XOR Out
OUT AD5 SMA[11] SSTL_2 2.5
1 INOUT L3 DVOCBLANK# DVO 1.5
2 INOUT K1 DVOCD[1] DVO 1.5
3 INOUT L4 RSVD DVO N/A
4 INOUT L5 DVOCVSYNC DVO 1.5
8 INOUT J2 DVOCCLK# DVO 1.5
9 INOUT J3 DVOCCLK DVO 1.5
10 INOUT H2 DVOCD[6] DVO 1.5
11 INOUT J5 DVOCD[5] DVO 1.5
13 INOUT J6 DVOCD[4] DVO 1.5
14 INOUT K6 DVOCHSYNC DVO 1.5
Datasheet 189
17 INOUT H5 DVOCFLDSTL DVO 1.5
19 INOUT G2 DVOBCINT# DVO 1.5
20 INOUT G3 DVOCD[11] DVO 1.5
21 IN D2 RSVD N/A N/A
23 IN F4 ADDID[5] DVO 1.5
26 IN E2 ADDID[3] DVO 1.5
28 IN F3 RSVD N/A N/A
29 IN F2 RSVD N/A N/A
30 OUT C2 RSVD N/A N/A
32 OUT C3 GST[1] DVO 1.5
33 OUT C4 GST[0] DVO 1.5
34 IN G5 ADDID[4] DVO 1.5
35 IN G6 ADDID[6] DVO 1.5
36 IN D5 DPMS DVO 1.5
XOR Chain FSB 1
IN/OUT Ball Pin I/O Type Voltage

XOR Out
OUT AC19 SMA[10] SSTL_2 2.5
1 INOUT D16 HD[62]# AGTL+ 1.5
2 INOUT C16 HD[60]# AGTL+ 1.5
3 INOUT G16 HD[58]# AGTL+ 1.5
5 INOUT E17 HD[61]# AGTL+ 1.5
7 INOUT F17 HD[56]# AGTL+ 1.5
8 INOUT B19 HD[57]# AGTL+ 1.5
9 INOUT E18 HDSTBP[3]# AGTL+ 1.5
10 INOUT D18 HDSTBN[3]# AGTL+ 1.5
190 Datasheet
17 INOUT G19 DINV[3]# AGTL+ 1.5
25 INOUT B25 DINV[2]# AGTL+ 1.5
29 INOUT E21 HDSTBP[2]# AGTL+ 1.5
30 INOUT E22 HDSTBN[2]# AGTL+ 1.5
39 OUT M27 RS[2]# AGTL+ 1.5
40 OUT P28 BPRI# AGTL+ 1.5
41 OUT AA22 DPWR# AGTL+ 1.5
42 INOUT AA26 HADSTB[1]# AGTL+ 1.5
XOR Chain FSB 2
XOR Out IN/OUT Ball Pin I/O Type Voltage
1 INOUT E25 DINV[1]# AGTL+ 1.5
Datasheet 191
8 INOUT D26 HDSTBP[1]# AGTL+ 1.5
9 INOUT C27 HDSTBN[1]# AGTL+ 1.5
18 INOUT H23 HD[19]# AGTL+ 1.5
20 INOUT K23 HD[11]# AGTL+ 1.5
21 INOUT J23 HD[14]# AGTL+ 1.5
29 INOUT L23 HD[7]# AGTL+ 1.5
31 INOUT K27 HDSTBP[0]# AGTL+ 1.5
32 INOUT J28 HDSTBN[0]# AGTL+ 1.5
33 INOUT J25 DINV[0]# AGTL+ 1.5
39 OUT M28 DEFER# AGTL+ 1.5
40 OUT N23 RS[0]# AGTL+ 1.5
41 OUT P26 RS[1]# AGTL+ 1.5
42 INOUT T26 HADSTB[0]# AGTL+ 1.5
192 Datasheet
XOR Chain FSB 3

XOR Out
1 OUT F15 CPURST# AGTL+ 1.5
2 IN Y23 DPSLP# CMOS 1.5
3 INOUT N27 HIT# AGTL+ 1.5
4 INOUT N28 HITM# AGTL+ 1.5
5 INOUT N25 BNR# AGTL+ 1.5
6 INOUT N24 DRDY# AGTL+ 1.5
7 IN P27 HLOCK# AGTL+ 1.5
8 INOUT M23 BREQ0# AGTL+ 1.5
9 OUT M25 HTRDY# AGTL+ 1.5
10 INOUT M26 DBSY# AGTL+ 1.5
11 INOUT L28 ADS# AGTL+ 1.5
12 INOUT R28 HREQ[0]# AGTL+ 1.5
13 INOUT P25 HREQ[1]# AGTL+ 1.5
14 INOUT T28 HA[5]# AGTL+ 1.5
15 INOUT R27 HA[6]# AGTL+ 1.5
17 INOUT R24 HA[9]# AGTL+ 1.5
19 INOUT U28 HA[10]# AGTL+ 1.5
20 INOUT P23 HA[3]# AGTL+ 1.5
23 INOUT V27 HA[14]# AGTL+ 1.5
26 INOUT T23 HREQ[4]# AGTL+ 1.5
32 INOUT Y26 HA[30]# AGTL+ 1.5
33 INOUT W28 HA[28]# AGTL+ 1.5
Datasheet 193
37 INOUT Y25 HA[21] AGTL+ 1.5
41 INOUT AA27 HA[22]# AGTL+ 1.5
43 INOUT AB28 HA[31]# AGTL+ 1.5
44 INOUT AB27 HA[29]# AGTL+ 1.5
45 INOUT AA28 HA[27] AGTL+ 1.5
XOR Chain GPIO

XOR Out
1 OUT G8 PANELBKLTCTL CMOS 3.3
2 OUT F8 PANELBKLTEN CMOS 3.3
3 OUT C6 LCLKCTLB CMOS 3.3
4 IN D6 EXTTS_0 CMOS 3.3
5 OUT F7 AGPBUSY# CMOS 3.3
7 INOUT C5 DDCPDATA CMOS 3.3
8 INOUT B4 DDCPCLK CMOS 3.3
9 OUT H10 HSYNC CMOS 3.3
10 OUT A5 PANELVDDEN CMOS 3.3
11 INOUT B6 DDCACLK CMOS 3.3
12 OUT J9 VSYNC CMOS 3.3
13 INOUT G9 DDCADATA CMOS 3.3
14 OUT H9 LCLKCTLA CMOS 3.3
XOR Chain HUB

XOR Out
1 INOUT W2 HL[4] HL1.5 1.2
2 INOUT W6 HL[5] HL1.5 1.2
3 INOUT W7 HL[7] HL1.5 1.2
4 INOUT V6 HL[6] HL1.5 1.2
5 INOUT W3 HLSTB HL1.5 1.2
6 INOUT V2 HLSTB# HL1.5 1.2
194 Datasheet
7 IN V5 Hl[9] HL1.5 1.2
8 INOUT V4 HL[10] HL1.5 1.2
9 INOUT V3 HL[3] HL1.5 1.2
10 INOUT U4 HL[1] HL1.5 1.2
11 INOUT U3 HL[2] HL1.5 1.2
12 INOUT U7 HL[0] HL1.5 1.2
13 OUT T3 HL[8] HL1.5 1.2
XOR Chain LVDS

XOR Out
1 INOUT F10 ICLKBP LVDS 1.5
2 INOUT E10 ICLKBM LVDS 1.5
3 INOUT G10 IYBP[3] LVDS 1.5
4 INOUT G11 IYBM[3] LVDS 1.5
5 INOUT G12 IYBP[0] LVDS 1.5
6 INOUT H12 IYBM[0] LVDS 1.5
7 INOUT E11 IYBP[1] LVDS 1.5
8 INOUT E12 IYBM[1] LVDS 1.5
9 INOUT C11 IYBP[2] LVDS 1.5
10 INOUT C12 IYBM[2] LVDS 1.5
11 INOUT E13 ICLKAP LVDS 1.5
12 INOUT D14 ICLKAM LVDS 1.5
13 INOUT B13 IYAP[3] LVDS 1.5
14 INOUT C13 IYAM[3] LVDS 1.5
15 INOUT F14 IYAP[0] LVDS 1.5
16 INOUT G14 IYAM[0] LVDS 1.5
17 INOUT C14 IYAP[2] LVDS 1.5
18 INOUT C15 IYAM[2] LVDS 1.5
19 INOUT E14 IYAP[1] LVDS 1.5
20 INOUT E15 IYAM[1] LVDS 1.5
XOR Chain SM1
DDR Ball Pin I/O Type Voltage

SDRAM
XOR Out IN/OUT
OUT AD23 SCS[0]# SSTL_2 2.5
1 INOUT AE27 SDQ[62] SSTL_2 2.5
2 INOUT AD27 SDQ[63] SSTL_2 2.5
3 INOUT AF26 SDQ[61] SSTL_2 2.5
Datasheet 195
4 INOUT AG26 SDQ[60] SSTL_2 2.5
5 OUT AC25 SCS[3]# SSTL_2 2.5
6 OUT AD24 SDM[6] SSTL_2 2.5
7 INOUT AH24 SDQS[6] SSTL_2 2.5
8 OUT AD25 SWE# SSTL_2 2.5
9 OUT AC18 SMA[0] SSTL_2 2.5
12 CLK AC26 SCK[1] SSTL_2 2.5
13 CLK AB23 SCK[4] SSTL_2 2.5
14 CLK AA3 SCK[5] SSTL_2 2.5
16 CLK AB2 SCK[0] SSTL_2 2.5
18 OUT AH15 SDM[8] SSTL_2 2.5
19 INOUT AF17 RSVD N/A N/A
20 INOUT AF16 RSVD N/A N/A
21 INOUT AG16 RSVD N/A N/A
22 INOUT AE15 RSVD N/A N/A
23 INOUT AH14 RSVD N/A N/A
25 INOUT AD15 SDQS[8] SSTL_2 2.5
27 INUT AG14 RSVD N/A N/A
29 OUT AE9 SDM[2] SSTL_2 2.5
30 OUT AC7 SCKE[0] SSTL_2 2.5
31 INOUT AG2 SDQS[0] SSTL_2 2.5
XOR Chain SM2
DDR Ball Pin I/O Type Voltage

SDRAM
XOR Out IN/OUT
OUT AD26 SCS[1]# SSTL_2 2.5
196 Datasheet
6 INOUT AH26 SDQ[56] SSTL_2 2.5
15 INOUT AE21 SDQS[5] SSTL_2 2.5
17 OUT AD20 SBA[1] SSTL_2 2.5
18 OUT AD22 SBA[0] SSTL_2 2.5
19 OUT AC21 SRAS# SSTL_2 2.5
20 OUT AC15 RCVENOUT# SSTL_2 2.5
21 INOUT AC16 RCVENIN# SSTL_2 2.5
22 CLK AB24 SCK[4]# SSTL_2 2.5
25 CLK AA2 SCK[0]# SSTL_2 2.5
26 CLK AD2 SCK[3]# SSTL_2 2.5
27 CLK AD4 SCK[2]# SSTL_2 2.5
28 OUT AD10 SMAB[5] SSTL_2 2.5
29 OUT AD14 SMA[1] SSTL_2 2.5
30 OUT AD16 SMAB[1] SSTL_2 2.5
32 OUT AF11 SMAB[4] SSTL_2 2.5
33 OUT AC12 SMAB[2] SSTL_2 2.5
34 OUT AC13 SMA[5] SSTL_2 2.5
35 INOUT AE12 SDQS[3] SSTL_2 2.5
Datasheet 197
42 OUT AB7 SCKE[1] SSTL_2 2.5
XOR Chain SM 3
DDR SDRAM Ball Pin I/O Type Voltage

IN/OUT
XOR Out
OUT AC22 SCS[2]# SSTL_2 2.5
1 OUT AC24 SCAS# SSTL_2 2.5
198 Datasheet
Datasheet 199
9.4.1 VCC/VSS Voltage Groups

Table 53. Voltage Levels and Ball Out for Voltage Groups
Name Voltage Level Ballout
VCC 1.2 (855GM) H14,J15,N14,N16,P13,P15,P17,R14,R16,T13,T15,

1.35 (855GME)
T17,U14,U16,W21,AA15,AA17,AA19
VCCADAC 1.5 A9,B9
VCCDVO 1.5 E1,E4,E6,H7,J1,J4,J8,K9,L8,M4,M8,M9,N1,N8,P9,R8
VCCASM 1.2 (855GM)

1.35 (855GME) AD1,AF1
VCCDLVDS 1.5 B14,B15,G13,J13
VCCGPIO 3.3 A3,A4
VCCHL 1.2 (855GM)

1.35 (855GME) U6,U8,V1,V7,V9,W5,W8,Y1
VCCQSM 2.5 AJ6,AJ8
VCCSM 2.5 Y4,Y7,Y9,AA6,AA8,AA11,AA13,AB3,AB6,AB8,AB10,

AB12,AB14,AB16,AB18,AB20,AB22,AC1,AC29,AF3,
AF6,AF9,AF12,AF15,AF18,AF21,AF24,AF27,AF29,
AG1,AG29,AJ5,AJ9,AJ13,AJ17,AJ21,AJ25
VCCTXLVDS 2.5 A12,B10,D10,F9
VTTHF 1.5 A22,A24,H29,M29,V29
VTTLF 1.5 A18,A20,A26,F29,G15,H16,H18,H20,H22,J19,K29,L21,

M22,N21,P22,R21,T22,U21,V22,Y29,AB29
VSS GND A13,A17,A19,A21,A23,A25,A27,B5,B24,C1,C7,C10,C22,C29,
D4,D11,D13,D15,D17,D19,D21,D23,D25,D28,E7,E9,E28,E29,
F11,F13,F16,F18,F20,F22,F24,F27,G1,G4,G7,G26,G29,H8,H11,
H13,H15,H17,H19,H21,H24,J7,J10,J12,J14,J16,J18,J20,J22,J26,
J29,K4,K8,K24,L1,L6,L9,L22,L26,L29,M7,M21,M24,N4,N9,N13,
N15,N17,N22,N26,N29,P8,P14,P16,P21,P24,R2,R7,R9,R13,R15,
R17,R22,R26,T4,T8,T9,T14,T16,T21,T24,U1,U5,U9,U13,U15,
U17,U22,U26,U29,V8,V21,V24,W4,W9,W22,W26,W29,Y5,Y6,
Y8,Y21,AA1,AA4,AA7,AA10,AA12,AA14,AA16,AA18,AA20,
AA21,AA23,AA24,AA25,AA29,AB9,AB11,AB13,AB15,AB17,
AB19,AB21,AB26,AC4,AC8,AC11,AC14,AC17,AC20,AC23,
AC27,AC28,AE1,AE4,AE7,AE10,AE13,AE16,AE19,AE22,AE25,
AE28,AG3,AG6,AG9,AG12,AG15,AG18,AG21,AG24,AG27,AJ1,
AJ3,AJ7,AJ10,AJ11,AJ12,AJ18,AJ20,AJ23,AJ26,AJ27
200 Datasheet
Intel® 855GM/GME GMCH Strap Pins
10 Intel® 855GM/GME GMCH Strap

Pins
10.1 Strapping Configuration

Table 54. Strapping Signals and Configuration
Pin Name Strap Description Configuration I/F Type Buffer Type
HSYNC XOR Chain Test Low = Normal Ops (Default) GPIO OUT
High = XOR Test On
VSYNC ALL Z Test Low = Normal Ops (Default) GPIO OUT

High = AllZ Test On
LCLKCTLB VTT Voltage Select High = 1.05 V – Intel Pentium GPIO OUT
M Processor / Intel Celeron M
Processor
DVODETECT DVO Select (If Low = DVO (Default) DVO BI

DVODETECT=0 during
High = Reserved
Reset, ADDID[7:0] is
latched to the ADDID
(1)
Register)
(1)
GST[2] Clock Config: Bit_2 Please refer to Device #0 DVO Out:
Function #3 (HPLLCC
0) Before CPURST#, there is
Register) for proper GST[2:0]
internal pull-down
settings
GST[1] Clock Config: Bit_1
(1) 1) Just out of CPURST#:
These pins are Hi-Z
2) C3: these pins are Hi-Z
3) S1-M: these pins are Hi-Z
GST[0] Clock Config: Bit_0

(1) 4) Internal GFX D1/D3: these
pins are Hi-Z
5) S3: these pins are Power

down
6) S4/S5: these pins are

Power down
NOTES:
1. External pull-ups/downs will be required on the board to enable the non-default state of the straps.
Note: All strap signals are sampled with respect to the leading edge of the Intel 855GM/GME GMCH
PWROK In signal.
Datasheet 201
Intel® 855GM/GME GMCH Strap Pins
202 Datasheet
Ballout and Package Information
11 Ballout and Package Information

Figure 13. Intel® 855GM/855GME GMCH Ballout Diagram (Top View)
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SMVREF SMVSWI SMVSWI VCCQS VCCQS

AJ NC NC VSS VSS VCCSM VSS VCCSM VSS VSS VCCSM VCCSM VSS VSS VSS VCCSM VSS VCCSM NC VSS NC VSS AJ
_0 NGL NGH M M
AH NC SDM[7] SDQS[7] SDQ[56] SDQ[51] SDQS[6] SDQ[49] SDQ[43] SDQ[46] SDQ[40] SDQ[45] SDQ[38] SDQS[4] SDQ[32] SDM[8] SDQ[68] SDQ[31] SDM[3] SDQ[25] SDQ[24] SDQ[18] SDQS[2] SDQ[20] SDQ[15] SDQS[1] SDQ[13] SDQ[7] SDQ[3] NC AH
AG VCCSM SDQ[58] VSS SDQ[60] SDQ[55] VSS SDQ[52] SDQ[47] VSS SDQ[41] SDQ[39] VSS SDQ[33] SDQ[67] VSS SDQ[64] SDQ[26] VSS SDQ[28] SDQ[19] VSS SDQ[17] SDQ[10] VSS SDQ[9] SDQ[6] VSS SDQS[0] VCCSM AG
VCCAS
AF VCCSM SDQ[59] VCCSM SDQ[61] SDQ[54] VCCSM SDQ[53] SDQ[42] VCCSM SDQ[44] SDQ[34] VCCSM SDQ[71] SDQ[70] VCCSM SDQ[27] SDQ[30] VCCSM SMAB[4] SDQ[22] VCCSM SDQ[16] SDQ[14] VCCSM SDQ[12] SDQ[2] VCCSM SDQ[0] AF
M
AE BCLK VSS SDQ[62] SDQ[57] VSS SDQ[50] SDQ[48] VSS SDQS[5] SDQ[35] VSS SDQ[37] SDQ[66] VSS SDQ[69] SDQ[65] VSS SDQS[3] SDQ[23] VSS SDM[2] SDQ[11] VSS SDM[1] SDM[0] VSS SDQ[1] SDQ[5] VSS AE
VCCAS
AD BCLK# RSTIN# SDQ[63] SCS[1]# SW E# SDM[6] SCS[0]# SBA[0] SDM[5] SBA[1] SDM[4] SDQ[36] SMA[3] SMAB[1] SDQS[8] SMA[1] SMA[2] SDQ[29] SMA[4] SMAB[5] SDQ[21] SMA[6] SMA[7] SDQ[8] SMA[11] SCK[2]# SDQ[4] SCK[3]# AD
M
RCVENI RCVEN
AC VCCSM VSS VSS SCK[1] SCS[3]# SCAS# VSS SCS[2]# SRAS# VSS SMA[10] SMA[0] VSS VSS SMA[5] SMAB[2] VSS SCKE[3] SCKE[2] VSS SCKE[0] SMA[8] SMA[9] VSS SCK[2] SCK[3] VCCSM AC
N# OUT#
SMRCO
AB VTTLF HA[31]# HA[29]# VSS SCK[1]# SCK[4]# SCK[4] VCCSM VSS VCCSM VSS VCCSM VSS VCCSM VSS VCCSM VSS VCCSM VSS VCCSM VSS VCCSM SCKE[1] VCCSM SMA[12] SCK[5]# VCCSM SCK[0] AB
MP
HADSTB
AA VSS HA[27]# HA[22]# VSS VSS VSS DPWR# VSS VSS VCC VSS VCC VSS VCC VSS VCCSM VSS VCCSM VSS NC VCCSM VSS VCCSM RSVD VSS SCK[5] SCK[0]# VSS AA
[1]#
HCCVRE VCCAGP
Y VTTLF HA[26]# HA[30]# HA[21]# HA[17]# DPSLP# HAVREF VSS VCCSM VSS VCCSM VSS VSS VCCSM GCLKIN VCCHL Y
F LL
W VSS HA[28]# HA[25]# VSS HA[20]# HA[23]# HA[24]# VSS VCC VSS VCCHL HL[7] HL[5] VCCHL VSS HLSTB HL[4] HLVREF W
V VTTHF HA[11]# HA[14]# HA[16]# HA[18]# VSS HA[19]# VTTLF VSS VCCHL VSS VCCHL HL[6] HL[9] HL[10] HL[3] HLSTB# VCCHL V
U VSS HA[10]# HA[12]# VSS HA[15]# HA[8]# HA[7]# VSS VTTLF VSS VCC VSS VCC VSS VSS VCCHL HL[0] VCCHL VSS HL[1] HL[2] PSWING VSS U
HADSTB HREQ[4] MDDCD DVOBHS DVOBVS HLRCO

T HA[5]# HA[13]# HA[4]# VSS VTTLF VSS VCC VSS VCC VSS VCC VSS VSS VSS HL[8] T
[0]# # ATA YNC YNC MP
HREQ[0] HREQ[3] HREQ[2] VCCDV DVOBD[ DVOBD[ DVOBD[ DVOBD[

R HA[6]# VSS HA[9]# VSS VTTLF VSS VCC VSS VCC VSS VSS VSS VSS R
# # # O 2] 1] 3] 0]
HREQ[1] VCCDV MDDCC DVOBD[ DVOBD[ DVOBCL DVOBCL DVOBD[

P BPRI# HLOCK# RS[1]# VSS HA[3]# VTTLF VSS VCC VSS VCC VSS VCC VSS P
# O LK 4] 5] K# K 7]
VCCDV MDVICL MI2CDA DVOBD[ DVOBD[ DVOBD[ VCCDV

N VSS HITM# HIT# VSS BNR# DRDY# RS[0]# VSS VTTLF VSS VCC VSS VCC VSS VSS VSS N
O K TA 6] 9] 8] O
VCCDV VCCDV MDVIDA DVOBD[ VCCDV DVOBC DVOBFL DVOBD[

M VTTHF DEFER# RS[2]# DBSY# HTRDY# VSS BREQ0# VTTLF VSS VSS M
O O TA 11] O CLKINT DSTL 10]
VCCDV DVODET DVOCVS DVOCBL DVOBBL

L VSS ADS# HD[6]# VSS HD[8]# HD[3]# HD[7]# VSS VTTLF VSS VSS RSVD VSS L
O ECT YNC ANK# ANK#
HYSWIN HDSTBP HDVREF VCCDV MI2CCL DVOCH DVOCD[ DVOCD[ DVOCD[ DVOCD[
K VTTLF HD[13]# HD[2]# VSS HD[11]# HD[0]# VSS VSS K
G [0]# [0] O K SYNC 0] 2] 3] 1]
HDSTBN HDVREF HDVREF VCCDLV VCCDV DVOCD[ DVOCD[ VCCDV DVOCCL DVOCCL VCCDV
J VSS HD[4]# VSS DINV[0]# HD[9]# HD[14]# VSS VSS VTTLF VSS VSS VCC VSS VSS PWROK VSS VSYNC VSS J
[0]# [1] [2] DS O 4] 5] O K K# O
HYRCO LCLKCT VCCDV DVOCD[ DVOCFL DVOCD[ DVOCD[ DVOCD[ DVOCD[

H VTTHF HD[1]# HD[15]# HD[10]# VSS HD[19]# VTTLF VSS VTTLF VSS VTTLF VSS VTTLF VSS VCC VSS IYBM[0] VSS HSYNC VSS H
MP LA O 10] DSTL 9] 8] 6] 7]
VCCDLV DDCADA PANELB DVOCD[ DVOBCI

G VSS HD[5]# HD[12]# VSS HD[21]# HD[24]# HD[30]# HD[27]# HD[33]# HD[40]# DINV[3]# HD[48]# HD[51]# HD[58]# VTTLF IYAM[0] IYBP[0] IYBM[3] IYBP[3] VSS ADDID[6] ADDID[4] VSS VSS G
DS TA KLTCTL 11] NTR#
CPURST VCCTXL PANELB AGPBUS

F VTTLF HD[22]# VSS HD[17]# HD[16]# VSS HD[44]# VSS HD[45]# VSS HD[53]# VSS HD[56]# VSS IYAP[0] VSS RSVD VSS ICLKBP ADDID[7] ADDID[1] ADDID[5] RSVD RSVD GVREF F
# VDS KLTEN Y#
HDSTBN HDSTBP HDSTBP VCCDV VCCDV VCCDV

E VSS VSS HD[20]# HD[29]# DINV[1]# HD[38]# HD[41]# HD[50]# HD[49]# HD[61]# HD[59]# IYAM[1] IYAP[1] ICLKAP IYBM[1] IYBP[1] ICLKBM VSS REFSET VSS ADDID[0] ADDID[2] ADDID[3] E
[2]# [2]# [3]# O O O
VCCAHP HDSTBP HDSTBN VCCTXL EXTTS_ DVORC

D VSS HD[23]# VSS HD[39]# VSS HD[36]# VSS HD[52]# VSS VSS HD[62]# VSS ICLKAM VSS RSVD VSS BLUE# GREEN# RSVD DPMS VSS RSVD RSVD D
LL [1]# [3]# VDS 0 OMP
HDSTBN LCLKCT DDCPDA

C VSS HD[25]# HD[28]# HD[37]# HD[34]# HD[35]# VSS HD[47]# HD[46]# HD[54]# HD[63]# HD[55]# HD[60]# IYAM[2] IYAP[2] IYAM[3] IYBM[2] IYBP[2] VSS BLUE GREEN VSS GST[0] GST[1] GST[2] VSS C
[1]# LB TA
HXRCO HXSWIN DREFSS VCCADP VCCDLV VCCDLV VSSALV VCCTXL VCCADA VSSADA DREFCL DDCACL DDCPCL
B NC HD[31]# HD[18]# HD[26]# DINV[2]# VSS HD[43]# HD[42]# HD[32]# HD[57]# IYAP[3] RSVD VSS RSVD RSVD NC B
MP G CLK LLB DS DS DS VDS C C K K K
VCCTXL VCCALV VCCADA VCCADP PANELV VCCGPI VCCGPI

A NC NC VSS VTTLF VSS VTTHF VSS VTTHF VSS VTTLF VSS VTTLF VSS VSS LIBG RED# RED NC A
VDS DS C LLA DDEN O O
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Datasheet 203
Table 55. Ballout Table
Row Column Signal Name Row Column Signal Name Row Column Signal Name
E 5 GSBA0/ADDID[0] L 2 GCBE#/DVOBBLANK# H 4 GAD26/DVOCD[9]
F 5 GSBA1/ADDID[1] M 3 GAD13/DVOBCCLKINT H 5 GAD31/DVOCFLDSTL
E 3 GSBA2/ADDID[2] G 2 GAD30/DVOBCINTR# K 6 GAD17/DVOCHSYNC
E 2 GSBA3/ADDID[3] P 3 GADSTB0/DVOBCLK L 5 GAD16/DVOCVSYNC
G 5 GSBA4/ADDID[4] P 4 GADSTB#0/DVOBCLK# L 7 GPAR/DVODETECT
F 4 GSBA5/ADDID[5] R 3 GAD3/DVOBD[0] D 1 DVORCOMP
G 6 GSBA6/ADDID[6] R 5 GAD2/DVOBD[1] D 6 EXTTS_0
F 6 GSBA7/ADDID[7] M 1 GAD12/DVOBD[10] Y 3 GCLKIN
L 28 ADS# M 5 GAD11/DVOBD[11] C 8 GREEN
F 7 AGPBUSY# R 6 GAD5/DVOBD[2] D 8 GREEN#
AE 29 BCLK R 4 GAD4/DVOBD[3] F 1 GVREF
AD 29 BCLK# P 6 GAD7/DVOBD[4] U 28 HA[10]#
C 9 BLUE P 5 GAD6/DVOBD[5] V 28 HA[11]#
D 9 BLUE# N 5 GAD8/DVOBD[6] U 27 HA[12]#
N 25 BNR# P 2 GCBE#0/DVOBD[7] T 27 HA[13]#
P 28 BPRI# N 2 GAD10/DVOBD[8] V 27 HA[14]#
M 23 BREQ0# N 3 GAD9/DVOBD[9] U 25 HA[15]#
F 15 CPURST# M 2 GAD14/DVOBFLDSTL V 26 HA[16]#
M 26 DBSY# T 6 GAD0/DVOBHSYNC Y 24 HA[17]#
B 6 DDCACLK T 5 GAD1/DVOBVSYNC V 25 HA[18]#
G 9 DDCADATA L 3 GAD18/DVOCBLANK# V 23 HA[19]#
B 4 DDCPCLK J 3 GADSTB1/DVOCCLK W 25 HA[20]#
C 5 DDCPDATA J 2 GADSTB#1/DVOCCLK# Y 25 HA[21]#
M 28 DEFER# K 5 GAD19/DVOCD[0] AA 27 HA[22]#
J 25 DINV[0]# K 1 GAD20/DVOCD[1] W 24 HA[23]#
E 25 DINV[1]# H 6 GAD29/DVOCD[10] W 23 HA[24]#
B 25 DINV[2]# G 3 GAD28/DVOCD[11] W 27 HA[25]#
G 19 DINV[3]# K 3 GAD21/DVOCD[2] Y 27 HA[26]#
D 5 GPIPE#/DPMS K 2 GAD22/DVOCD[3] AA 28 HA[27]#
Y 23 DPSLP# J 6 GAD23/DVOCD[4] W 28 HA[28]#
AA 22 DPWR# J 5 GCBE#3/DVOCD[5] AB 27 HA[29]#
N 24 DRDY# H 2 GAD25/DVOCD[6] P 23 HA[3]#
B 7 DREFCLK H 1 GAD24/DVOCD[7] Y 26 HA[30]#
B 17 DREFSSCLK H 3 GAD27/DVOCD[8] AB 28 HA[31]#
Datasheet 204
T 25 HA[4]# B 21 HD[32]# L 25 HD[8]#
T 28 HA[5]# G 21 HD[33]# J 24 HD[9]#
R 27 HA[6]# C 24 HD[34]# J 28 HDSTBN[0]#
U 23 HA[7]# C 23 HD[35]# C 27 HDSTBN[1]#
U 24 HA[8]# D 22 HD[36]# E 22 HDSTBN[2]#
R 24 HA[9]# C 25 HD[37]# D 18 HDSTBN[3]#
T 26 HADSTB[0]# E 24 HD[38]# K 27 HDSTBP[0]#
AA 26 HADSTB[1]# D 24 HD[39]# D 26 HDSTBP[1]#
Y 22 HAVREF J 27 HD[4]# E 21 HDSTBP[2]#
Y 28 HCCVREF G 20 HD[40]# E 18 HDSTBP[3]#
K 22 HD[0]# E 23 HD[41]# K 21 HDVREF[0]
H 27 HD[1]# B 22 HD[42]# J 21 HDVREF[1]
H 25 HD[10]# B 23 HD[43]# J 17 HDVREF[2]
K 23 HD[11]# F 23 HD[44]# N 27 HIT#
G 27 HD[12]# F 21 HD[45]# N 28 HITM#
K 26 HD[13]# C 20 HD[46]# U 7 HL[0]
J 23 HD[14]# C 21 HD[47]# U 4 HL[1]
H 26 HD[15]# G 18 HD[48]# V 4 HL[10]
F 25 HD[16]# E 19 HD[49]# U 3 HL[2]
F 26 HD[17]# G 28 HD[5]# V 3 HL[3]
B 27 HD[18]# E 20 HD[50]# W 2 HL[4]
H 23 HD[19]# G 17 HD[51]# W 6 HL[5]
K 25 HD[2]# D 20 HD[52]# V 6 HL[6]
E 27 HD[20]# F 19 HD[53]# W 7 HL[7]
G 25 HD[21]# C 19 HD[54]# T 3 HL[8]
F 28 HD[22]# C 17 HD[55]# V 5 HL[9]
D 27 HD[23]# F 17 HD[56]# P 27 HLOCK#
G 24 HD[24]# B 19 HD[57]# T 2 HLRCOMP
C 28 HD[25]# G 16 HD[58]# W 3 HLSTB
B 26 HD[26]# E 16 HD[59]# V 2 HLSTB#
G 22 HD[27]# L 27 HD[6]# W 1 HLVREF
C 26 HD[28]# C 16 HD[60]# R 28 HREQ[0]#
E 26 HD[29]# E 17 HD[61]# P 25 HREQ[1]#
L 24 HD[3]# D 16 HD[62]# R 23 HREQ[2]#
G 23 HD[30]# C 18 HD[63]# R 25 HREQ[3]#
B 28 HD[31]# L 23 HD[7]# T 23 HREQ[4]#
Datasheet 205
H 10 HSYNC AH 29 NC D 2 RSVD
M 25 HTRDY# B 29 NC C 2 GST[2]
B 20 HXRCOMP A 29 NC B 2 RSVD
B 18 HXSWING AJ 28 NC D 7 RSVD
H 28 HYRCOMP A 28 NC AD 22 SBA[0]
K 28 HYSWING AA 9 NC AD 20 SBA[1]
D 14 ICLKAM AJ 4 NC AC 24 SCAS#
E 13 ICLKAP AJ 2 NC AB 2 SCK[0]
E 10 ICLKBM A 2 NC AA 2 SCK[0]#
F 10 ICLKBP AH 1 NC AC 26 SCK[1]
G 14 IYAM[0] B 1 NC AB 25 SCK[1]#
E 15 IYAM[1] G 8 PANELBKLTCTL AC 3 SCK[2]
C 15 IYAM[2] F 8 PANELBKLTEN AD 4 SCK[2]#
C 13 IYAM[3] A 5 PANELVDDEN AC 2 SCK[3]
F 14 IYAP[0] U 2 PSWING AD 2 SCK[3]#
E 14 IYAP[1] J 11 PWROK AB 23 SCK[4]
C 14 IYAP[2] AC 16 RCVENIN# AB 24 SCK[4]#
B 13 IYAP[3] AC 15 RCVENOUT# AA 3 SCK[5]
H 12 IYBM[0] A 7 RED AB 4 SCK[5]#
E 12 IYBM[1] A 8 RED# AC 7 SCKE[0]
C 12 IYBM[2] E 8 REFSET AB 7 SCKE[1]
G 11 IYBM[3] N 23 RS[0]# AC 9 SCKE[2]
G 12 IYBP[0] P 26 RS[1]# AC 10 SCKE[3]
E 11 IYBP[1] M 27 RS[2]# AD 23 SCS[0]#
C 11 IYBP[2] AD 28 RSTIN# AD 26 SCS[1]#
G 10 IYBP[3] F 12 RSVD AC 22 SCS[2]#
H 9 LCLKCTLA D 12 RSVD AC 25 SCS[3]#
C 6 LCLKCTLB B 12 RSVD AE 5 SDM[0]
A 10 LIBG AA 5 RSVD AE 6 SDM[1]
P 7 GSTOP#/MDDCCLK L 4 RSVD AE 9 SDM[2]
T 7 GAD15/MDDCDATA C 4 GST[0] AH 12 SDM[3]
N 7 GTRDY#/MDVICLK F 3 RSVD AD 19 SDM[4]
M 6 GFRAME#/MDVIDATA D 3 RSVD AD 21 SDM[5]
K 7 GIRDY#/MI2CCLK C 3 GST[1] AD 24 SDM[6]
N 6 GDEVSEL#/MI2CDATA B 3 RSVD AH 28 SDM[7]
AJ 29 NC F 2 RSVD AH 15 SDM[8]
206 Datasheet
AF 2 SDQ[0] AG 20 SDQ[41] AG 2 SDQS[0]
AE 3 SDQ[1] AF 22 SDQ[42] AH 5 SDQS[1]
AG 7 SDQ[10] AH 22 SDQ[43] AH 8 SDQS[2]
AE 8 SDQ[11] AF 20 SDQ[44] AE 12 SDQS[3]
AF 5 SDQ[12] AH 19 SDQ[45] AH 17 SDQS[4]
AH 4 SDQ[13] AH 21 SDQ[46] AE 21 SDQS[5]
AF 7 SDQ[14] AG 22 SDQ[47] AH 24 SDQS[6]
AH 6 SDQ[15] AE 23 SDQ[48] AH 27 SDQS[7]
AF 8 SDQ[16] AH 23 SDQ[49] AD 15 SDQS[8]
AG 8 SDQ[17] AE 2 SDQ[5] AC 18 SMA[0]
AH 9 SDQ[18] AE 24 SDQ[50] AD 14 SMA[1]
AG 10 SDQ[19] AH 25 SDQ[51] AC 19 SMA[10]
AF 4 SDQ[2] AG 23 SDQ[52] AD 5 SMA[11]
AH 7 SDQ[20] AF 23 SDQ[53] AB 5 SMA[12]
AD 9 SDQ[21] AF 25 SDQ[54] AD 13 SMA[2]
AF 10 SDQ[22] AG 25 SDQ[55] AD 17 SMA[3]
AE 11 SDQ[23] AH 26 SDQ[56] AD 11 SMA[4]
AH 10 SDQ[24] AE 26 SDQ[57] AC 13 SMA[5]
AH 11 SDQ[25] AG 28 SDQ[58] AD 8 SMA[6]
AG 13 SDQ[26] AF 28 SDQ[59] AD 7 SMA[7]
AF 14 SDQ[27] AG 4 SDQ[6] AC 6 SMA[8]
AG 11 SDQ[28] AG 26 SDQ[60] AC 5 SMA[9]
AD 12 SDQ[29] AF 26 SDQ[61] AD 16 SMAB[1]
AH 2 SDQ[3] AE 27 SDQ[62] AC 12 SMAB[2]
AF 13 SDQ[30] AD 27 SDQ[63] AF 11 SMAB[4]
AH 13 SDQ[31] AG 14 SDQ[64] AD 10 SMAB[5]
AH 16 SDQ[32] AE 14 SDQ[65] AB 1 SMRCOMP
AG 17 SDQ[33] AE 17 SDQ[66] AJ 24 SMVREF_0
AF 19 SDQ[34] AG 16 SDQ[67] AJ 19 SMVSWINGH
AE 20 SDQ[35] AH 14 SDQ[68] AJ 22 SMVSWINGL
AD 18 SDQ[36] AE 15 SDQ[69] AC 21 SRAS#
AE 18 SDQ[37] AH 3 SDQ[7] AD 25 SWE#
AH 18 SDQ[38] AF 16 SDQ[70] W 21 VCC
AG 19 SDQ[39] AF 17 SDQ[71] AA 19 VCC
AD 3 SDQ[4] AD 6 SDQ[8] AA 17 VCC
AH 20 SDQ[40] AG 5 SDQ[9] T 17 VCC
Datasheet 207
P 17 VCC E 6 VCCDVO AA 13 VCCSM
U 16 VCC M 4 VCCDVO AF 12 VCCSM
R 16 VCC J 4 VCCDVO AB 12 VCCSM
N 16 VCC E 4 VCCDVO AA 11 VCCSM
AA 15 VCC N 1 VCCDVO AB 10 VCCSM
T 15 VCC J 1 VCCDVO AJ 9 VCCSM
P 15 VCC E 1 VCCDVO AF 9 VCCSM
J 15 VCC A 4 VCCGPIO Y 9 VCCSM
U 14 VCC A 3 VCCGPIO AB 8 VCCSM
R 14 VCC V 9 VCCHL AA 8 VCCSM
N 14 VCC W 8 VCCHL Y 7 VCCSM
H 14 VCC U 8 VCCHL AF 6 VCCSM
T 13 VCC V 7 VCCHL AB 6 VCCSM
P 13 VCC U 6 VCCHL AA 6 VCCSM
B 9 VCCADAC W 5 VCCHL AJ 5 VCCSM
A 9 VCCADAC Y 1 VCCHL Y 4 VCCSM
A 6 VCCADPLLA V 1 VCCHL AF 3 VCCSM
B 16 VCCADPLLB AJ 8 VCCQSM AB 3 VCCSM
Y 2 VCCAGPLL AJ 6 VCCQSM AG 1 VCCSM
D 29 VCCAHPLL AG 29 VCCSM AC 1 VCCSM
A 11 VCCALVDS AF 29 VCCSM A 12 VCCTXLVDS
AF 1 VCCASM AC 29 VCCSM D 10 VCCTXLVDS
AD 1 VCCASM AF 27 VCCSM B 10 VCCTXLVDS
B 15 VCCDLVDS AJ 25 VCCSM F 9 VCCTXLVDS
B 14 VCCDLVDS AF 24 VCCSM AA 29 VSS
J 13 VCCDLVDS AB 22 VCCSM W 29 VSS
G 13 VCCDLVDS AJ 21 VCCSM U 29 VSS
P 9 VCCDVO AF 21 VCCSM N 29 VSS
M 9 VCCDVO AB 20 VCCSM L 29 VSS
K 9 VCCDVO AF 18 VCCSM J 29 VSS
R 8 VCCDVO AB 18 VCCSM G 29 VSS
N 8 VCCDVO AJ 17 VCCSM E 29 VSS
M 8 VCCDVO AB 16 VCCSM C 29 VSS
L 8 VCCDVO AF 15 VCCSM AE 28 VSS
J 8 VCCDVO AB 14 VCCSM AC 28 VSS
H 7 VCCDVO AJ 13 VCCSM E 28 VSS
208 Datasheet
D 28 VSS U 22 VSS R 17 VSS
AJ 27 VSS R 22 VSS N 17 VSS
AG 27 VSS N 22 VSS H 17 VSS
AC 27 VSS L 22 VSS D 17 VSS
F 27 VSS J 22 VSS A 17 VSS
A 27 VSS F 22 VSS AE 16 VSS
AJ 26 VSS C 22 VSS AA 16 VSS
AB 26 VSS AG 21 VSS T 16 VSS
W 26 VSS AB 21 VSS P 16 VSS
U 26 VSS AA 21 VSS J 16 VSS
R 26 VSS Y 21 VSS F 16 VSS
N 26 VSS V 21 VSS AG 15 VSS
L 26 VSS T 21 VSS AB 15 VSS
J 26 VSS P 21 VSS U 15 VSS
G 26 VSS M 21 VSS R 15 VSS
AE 25 VSS H 21 VSS N 15 VSS
AA 25 VSS D 21 VSS H 15 VSS
D 25 VSS A 21 VSS D 15 VSS
A 25 VSS AJ 20 VSS AC 14 VSS
AG 24 VSS AC 20 VSS AA 14 VSS
AA 24 VSS AA 20 VSS T 14 VSS
V 24 VSS J 20 VSS P 14 VSS
T 24 VSS F 20 VSS J 14 VSS
P 24 VSS AE 19 VSS AE 13 VSS
M 24 VSS AB 19 VSS AB 13 VSS
K 24 VSS H 19 VSS U 13 VSS
H 24 VSS D 19 VSS R 13 VSS
F 24 VSS A 19 VSS N 13 VSS
B 24 VSS AJ 18 VSS H 13 VSS
AJ 23 VSS AG 18 VSS F 13 VSS
AC 23 VSS AA 18 VSS D 13 VSS
AA 23 VSS J 18 VSS A 13 VSS
D 23 VSS F 18 VSS AJ 12 VSS
A 23 VSS AC 17 VSS AG 12 VSS
AE 22 VSS AB 17 VSS AA 12 VSS
W 22 VSS U 17 VSS J 12 VSS
Datasheet 209
AJ 11 VSS M 7 VSS B 11 VSSALVDS
AC 11 VSS J 7 VSS J 9 VSYNC
AB 11 VSS G 7 VSS V 29 VTTHF
H 11 VSS E 7 VSS M 29 VTTHF
F 11 VSS C 7 VSS H 29 VTTHF
D 11 VSS AG 6 VSS A 24 VTTHF
AJ 10 VSS Y 6 VSS A 22 VTTHF
AE 10 VSS L 6 VSS AB 29 VTTLF
AA 10 VSS Y 5 VSS Y 29 VTTLF
J 10 VSS U 5 VSS K 29 VTTLF
C 10 VSS B 5 VSS F 29 VTTLF
AG 9 VSS AE 4 VSS A 26 VTTLF
AB 9 VSS AC 4 VSS V 22 VTTLF
W 9 VSS AA 4 VSS T 22 VTTLF
U 9 VSS W 4 VSS P 22 VTTLF
T 9 VSS T 4 VSS M 22 VTTLF
R 9 VSS N 4 VSS H 22 VTTLF
N 9 VSS K 4 VSS U 21 VTTLF
L 9 VSS G 4 VSS R 21 VTTLF
E 9 VSS D 4 VSS N 21 VTTLF
AC 8 VSS AJ 3 VSS L 21 VTTLF
Y 8 VSS AG 3 VSS H 20 VTTLF
V 8 VSS R 2 VSS A 20 VTTLF
T 8 VSS AJ 1 VSS J 19 VTTLF
P 8 VSS AE 1 VSS H 18 VTTLF
K 8 VSS AA 1 VSS A 18 VTTLF
H 8 VSS U 1 VSS H 16 VTTLF
AJ 7 VSS L 1 VSS G 15 VTTLF
AE 7 VSS G 1 VSS
AA 7 VSS C 1 VSS
R 7 VSS B 8 VSSADAC
210 Datasheet
11.1 Package Mechanical Information

Figure 14 through Figure 16 provide detail on the package information and dimensions of the
Intel 855GM/855GME GMCH. The Intel 855GM/855GME GMCH comes in a Micro-FCBGA
package, which is similar to the mobile processors. The package consists of a silicon die mounted
face down on an organic substrate populated with solder balls on the bottom side. Capacitors may
be placed in the area surrounding the die. Because the die-side capacitors are electrically
conductive, and only slightly shorter than the die height, care should be taken to avoid contacting
the capacitors with electrically conductive materials. Doing so may short the capacitors and
possibly damage the device or render it inactive.
The use of an insulating material between the capacitors and any thermal solution should be
considered to prevent capacitor shorting. An exclusion, or keepout area, surrounds the die and
capacitors, and identifies the contact area for the package. Care should be taken to avoid contact
with the package inside this area.
Figure 14. Intel® 855GM/855GME GMCH Micro-FCBGA Package Dimensions (Top View)
Datasheet 211
Figure 15. Intel® 855GM/855GME GMCH Micro-FCBGA Package Dimensions (Side View)
212 Datasheet
Figure 16. Intel® 855GM/855GME GMCH Micro-FCBGA Package Dimensions (Bottom View)
Datasheet 213

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Intel® 855GM/855GME Chipset

Document Number: 252615-005

4.1 Conceptual Overview of the Platform Configuration Structure ............................ 51

4.9.2 DID – Device Identification Register..................................................... 87

6.4.2.8 Scan Converter.................................................................. 143

6.5.2.7.1 Panel Power Sequence States.......................... 156

Table 26. PAM Registers and Associated System Memory Segments............................ 71

Revision Description Date

001 Initial release July 2003

002 Updates include: September

• Updated Reference Documents list

003 Updates include: January 2004

• Added Intel Celeron M processor support

004 Updates include: May 2004

• Added Intel Pentium M processor on 90 nm process with 2-MB L2

Revision Description Date

005 Updates include: April 2005

• Added new Chapter 8 Electrical Characteristics

⎯ Absolute Maximum Ratings

• Testability moved to Chapter 9

• Intel 855GM/GME GMCH Strap Pins is now Chapter 10

Ballout and Package Information is now Chapter 11

Intel® 855GM Chipset GMCH Features

⎯ DVO (DVOB and DVOC) support • Ten programmable and predefined

• Twelve level of detail MIP map sizes • Z Bias support

Figure 1. Intel® 855GM GMCH Chipset System Block Diagram

Intel® 855GME Chipset GMCH

 Processor/Host Bus Support ⎯ Graphics Power Management

Figure 2. Intel® 855GME GMCH Chipset System Block Diagram

400 MHz FSB

AGTL+ Advanced Gunning Transceiver Logic + (AGTL+) bus

DDC Display Data Channel (standard created by VESA)

DPMS Display Power Management Signaling (standard created by VESA)

I2C Inter-IC (a two wire serial bus created by Philips)

CRT Cathode Ray Tube

LCD Liquid Crystal Display

BLI Backlight Inverter

Core The internal base logic in the Intel 855GM/GME GMCH

CPU Central Processing Unit

DBI Dynamic Bus inversion

DBL Display Brightness Link

DVO Digital Video Out

DVMT Dynamic Video Memory Technology

EDID Extended Display Identification Data

GMCH Graphics and Memory Controller Hub

Host This term is used synonymously with processor

IGD Integrated Graphics Device

IPI Inter Processor Interrupt

LFP Local Flat Panel

PWM Pulse Width Modulation

SSC Spread Spectrum Clocking

VDL Video Data Link

1.2 Reference Documents

Intel® 852GM/855GM/855GME Chipset Mobile Note 1

PCI Local Bus Specification 2.2 http://www.pcisig.com

Advanced Configuration and Power http://www.acpi.info/

Processor/Host Bus Support ⎯ Graphics Power Management