MODERN DIGITAL

ELECTRONICS
Fourth Edition

R PJain
Director
BM Institute ofEngineering and Technology
Sonepat

Tata McGraw Hill Education Private Limited

NEW DELHI
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CONTENTS
Preface to the Fourth Edition xi
Preface to the First Edition xv
Acknowledgements xvii

1. FUNDAMENTAL CONCEPTS 1
1. 1 Introduction 1
1.2 Digital Signals 2
1.3 Basic Digital Circuits 3
1.4 NANO and NOR Operations 8
1.5 Exclusive-OR and Exclusive-NOR Operations 12
1.6 Boolean Algebra 15
1. 7 Examples ofIC Gates 18
Summary 19
Glossary 21
Review questions 23
Problems 23

2. NUMBER SYSTEMS AND CODES 28

2.1 Introduction 28
2.2 Number Systems 28
2.3 Binary Number System 29
2.4 Signed Binary Numbers 34
2.5 Binary Arithmetic 38
2.6 2's Complement Arithmetic 41
2.7 Octal Number System 43
2.8 Hexadecimal Number System 48
2.9 Codes 53
2.10 Error Detecting and Correcting Codes 60
Summary 69
Glossary 70
Review Questions 71
Problems 72
 vi Modern Digital Electronics

3. SEMICONDUCTOR DEVICES-SWITCHING MODE OPERATION 74

3.1 Introduction 74
3.2 Semiconductors 75
3.3 p-n Junction Diode 76
3.4 Schottky Diode 83
3.5 Bipolar Junction Transistor 83
3.6 Schottky Transistor 91
3.7 Field-Effect Transistor 91
Summary 99
Glossary 99
Review Questions 99
Problems 99

4. DIGITAL LOGIC FAMILIES 105

4.1 Introduction 105
4.2 Characteristics of Digital ICs 106
4.3 Resistor-Transistor Logic (RTL) 109
4.4 Direct-Coupled Transistor Logic (DCTL) 112
4.5 Integrated-Injection Logic (FL) 112
4.6 Diode-Transistor Logic (DTL) 116
4.7 High-Threshold Logic (HTL) 119
4.8 Transistor-Transistor Logic (TTL) 120
4.9 Schottky TTL 125
4.10 5400/7400 TTL Series 125
4.11 Emitter-Coupled Logic (ECL) 128
4.12 Interfacing ECL and TTL 132
4.13 MOS Logic 133
4.14 CMOS Logic 137
4.15 CMOS Logic Families 145
4.16 Low-Voltage CMOS Logic 147
4.17 BiCMOS Logic Family 148
4.18 Interfacing CMOS and TTL 149
4.19 Interfacing CMOS and ECL 151
4.20 Tri-State Logic 151
Summary 155
Glossary 158
Review Questions 160
Problems 160

5. COMBINATIONAL LOGIC DESIGN 165

5.1 Introduction 165
5.2 Standard Representations for Logic Functions 166
 Contents vii

5.3 Karnaugh Map Representation of Logic Functions 173

5.4 Simplification of Logic Functions Using K-Map 178
5.5 Minimisation of Logic Functions Specified
in Minterms/Maxterms or Truth Table 184
5.6 Minimisation of Logic Functions not Specified in
Minterms/Maxterms 188
5.7 Don't-Care Conditions 190
5.8 Design Examples 192
5.9 EX-OR and EX-NOR Simplification ofK-Maps 201
5.10 Five- and Six-Variable K-Maps 208
5.11 Quine-McCluskey Minimisation Technique 210
5.12 Hazards in Combinational Circuits 218
Summary 225
Glossary 225
Review Questions 227
Problems 228

6. COMBINATIONAL LOGIC DESIGN USING MSI CIRCUITS 231

6.1 Introduction 231
6.2 Multiplexers and their use in Combinational Logic Design 231
6.3 Demultiplexers/Decoders and their use in Combinational Logic Design 238
6.4 Adders and their use as Subtractors 242
6.5 BCD Arithmetic 246
6.6 Arithmetic Logic Unit (ALU) 250
6.7 Digital Comparators 252
6.8 Parity Generators/Checkers 256
6.9 Code Converters 258
6.10 Priority Encoders 268
6.11 Decoder/Drivers for Display Devices 271
Summary 275
Glossary 275
Review Questions 276
Problems 276

7. FLIP-FLOPs 279
7.1 Introduction 279
7.2 A 1-Bit Memory Cell 280
7.3 Clocked S-R FLIP-FLOP 282
7.4 J-K FLIP-FLOP 284
7.5 D-TYPE FLIP-FLOP 288
7.6 T-TYPE FLIP-FLOP 289
7.7 Excitation Table of FLIP-FLOP 290
7.8 Clocked FLIP-FLOP Design 290
 viii Modern Digital Electronics

7.9 Edge-Triggered FLIP-FLOPs 294

7.10 Applications of FLIP-FLOPS 299
Summary 303
Glossary 304
Review Questions 305
Problems 306

8. SEQUENTIAL LOGIC DESIGN 312

8.1 Introduction 312
8.2 Registers 312
8.3 Applications of Shift Registers 316
8.4 Ripple or Asynchronous Counters 321
8.5 Synchronous Counters 332
8.6 Synchronous Sequential Circuits Design 348
8.7 Asynchronous Sequential Circuits 369
8.8 Hazards in Sequential Circuits 390
Summary 392
Glossary 392
Review Questions 394
Problems 395

9. TIMING CIRCUITS 400

9.1 Introduction 400
9.2 Applications of Logic Gates in Timing Circuits 401
9.3 OP AMP and its Applications in Timing Circuits 403
9.4 Schmitt Trigger ICs 413
9.5 Monostable Multivibrator ICs 414
9.6 555 Timer 421
Summary 425
Glossary 425
Review Questions 426
Problems 427

10. AID AND DIA CONVERTERS 429

10.1 Introduction 429
10.2 Digital-to-Analog Converters 430
10.3 An Example ofD/A Converter IC 441
10.4 Sample-and-Hold 445
10.5 Analog-to-Digital Converters 446
10.6 An Example of ND Converter IC 457
Summary 459
Glossary 460
Review Questions 461
Problems 461
 Contents ix

11. SEMICONDUCTOR MEMORIES 463

11.1 Introduction 463
11.2 Memory Organisation and Operation 463
11.3 Expanding Memory Size 469
11.4 Classification and Characteristics of Memories 472
11.5 Read-only Memory 475
11.6 Read and Write Memory 485
11.7 Flash Memory 496
11. 8 Content Addressable Memory 4 98
11.9 First-in, first-out Memory (FIFO) 504
11.10 Charge Coupled Device Memory 511
Summary 515
Glossary 516
Review Questions 518
Problems 518

12. PROGRAMMABLE LOGIC DEVICES 522

12.1 Introduction 522
12.2 ROM as a PLD 523
12.3 Programmable Logic Array 524
12.4 Programmable Array Logic 537
12.5 Complex Programmable Logic Devices (CPLDs) 554
12.6 Field-Programmable Gate Array (FPGA) 564
Summary 572
Glossary 572
Review Questions 574
Problems 575

13. FUNDAMENTALS OF MICROPROCESSORS 577

13.1 Introduction 577
13.2 An Ideal Microprocessor 578
13.3 The Data Bus 580
13.4 The Address Bus 582
13.5 The Control Bus 583
13.6 Microprocessor Based System-Basic Operation 584
13.7 Microprocessor Operation 587
13.8 Microprocessor Architecture 588
13.9 Instruction Set 590
13.lOThe 8085AMicroprocessor 592
13.11 The 8086 Microprocessor 617
13 .12 Programming Languages 620
Summary 621
Glossary 622
Review Questions 624
Problems 625
 X Modern Digital Electronics

14. COMPUTER AIDED DESIGN OF DIGITAL SYSTEMS 627

14.1 Introduction 627
14.2 Computer Aided Design (CAD) Concepts 628
14.3 CAD Tools 629
14.4 Introduction to VHDL 633
14.5 Describing Combinational Circuits using VHDL 649
14.6 Describing Sequential Circuits using VHDL 659
Summary 666
Glossary 666
Review Questions 669
Problems 670

Appendix Al-Reserved Words in VHDL 672

Appendix A2-Symbols Defined in VHDL 673

Appendix B-Bibliography 674

Appendix C-Answers to Review Questions 676

Appendix D-Answers to Selected Problems 681

Index 703
 Preface to The Fourth Edition xiii

• Added a large number of Solved Examples, Review Questions with Answers, and Problems to help
students understand and apply the topics discussed successfully.
Chapter 1 introduces the fundamental concepts of digital electronics, advantages of digital systems,
and the basic digital circuits. Various number systems and commonly used codes in digitial systems and
microprocessors have been discussed in Chapter 2. Error-detecting and error-correcting codes have also been
discussed in detail. Chapter 3 reviews semiconductor devices from the point of view of their applications
in digital circuits. Based on these devices, various digital circuits, referred to as logic families, have been
discussed in Chapter 4.
CMOS logic has now almost replaced the earlier most commonly used TTL logic. However, because
of its higher speed of operation and driving capabilities TTL logic is still preferred in many designs. Even
a number of CMOS devices are available which are TTL compatible. The latest 74F (Fast TTL) series has
also been included in this chapter. The CMOS logic has been discussed in detail and the advanced high
speed CMOS logic family series 74AHC/74AHCT/74FCT, and low-voltage CMOS (LVCMOS) logic have
also been included in this edition. The logic family using bipolar and unipolar logic BiCMOS has also been
introduced in this edition. This chapter also deals in detail the interfacing problems between ICs of the same
logic family and between those of different logic families to obtain maximum benefits in the design of digital
systems.
Chapter 5 deals with the conventional methods of combinational circuits design such as algebraic method,
K-map simplification and Quine-Mcluskey method. Hazards in combinational digital circuits and design of
hazard-free circuits have also been included in this edition.
Combinational logic design using MSI circuits is covered in Chapter 6, which is important for the design
of digital systems considering the simplicity in design, cost, space, power requirement, speed and other
factors.
Chapter 7 introduces the basic building block of a sequential circuit-the FLIP-FLOP. All types of
FLIP-FLOPs with their excitation tables and triggering methods have been discussed in detail. Sequential
logic design has been discussed in Chapter 8. Here again, both the approaches, namely conventional design
using FLIP-FLOPs and the modem approach using available MSI circuits, have been discussed. Design of
synchronous sequential as well as asynchronous sequential circuits have been discussed in detail. Synchronous
counters design using D-type FLIP-FLOPs have been added since D-type FLIP-FLOPs are most commonly
used in modem programmable logic devices. Hazards in sequential circuits have also been dealt with in this
chapter.
Chapter 9 deals with timing circuits and their applications which are essential to a digital system.
The analog-to-digital (AID) and digital-to-analog (D/A) converters form an important part of many digital
systems and the commonly used techniques for such conversions have been discussed in Chapter 10.
Chapter 11 deals with semiconductor memories which have assumed an important role in present-day
digital systems. This chapter has thoroughly been revised to include various semiconductor memory devices
which are being used currently. Serial and parallel EEPROMs, serial and parallel flash memories, first-in,
first-out (FIFO) memories, bidirectional FIFO (BiFIFO) memory, asynchronous and synchronous SRAMs,
asynchronous and synchronous DRAMs have been discussed in detail.
Programming techniques used for programmable ROMs and erasing techniques used for erasable
programmable ROMs have also been discussed.
Chapter 12 presents various programmable logic devices (PLDs), such as programmable logic array
(PLA), programmable array logic (PAL), electrically erasable PLD (EEPLD), generic array logic (GAL),
complex programmable logic devices (CPLDs), and field programmable gate array (FPGA) devices. Xilinx
Cool Runner-II CPLD family, Virtex FPGA family, and Altera Stratix FPGA family devices have been
discussed in detail.
 xiv Modern Digital Electronics

The microprocessors have been introduced in Chapter 13. The fundamentals of microprocessors have
been presented in a manner that even a novice would understand this highly sophisticated device. The most
widely used Intel's 8085A 8-bit microprocessor has been chosen for discussion. Its organisation, operation
and programming have been discussed in detail, which will help the students learn the use of microprocessors.
The Intel's 16-bit microprocessor 8086 has also been introduced briefly.
Chapter 14 introduces computer aided design (CAD) approach to digital system design. CAD tools needed
for this purpose have been discussed. The VHDL, a hardware description language has been introduced,
which is the basic requirement of designing using CAD tools.
Combinational logic circuits: truth table, arithmetic circuits, decoders, multiplexers, priority encoder,
digital comparators, BCD-to-7-segment decoder, tristate buffer, and Sequential logic circuits: FLIP-FLOPs,
latches, shift registers, registers, and counters have been described using VHDL.
Glossary of the important terms used in the book and Review Questions with answers for each chapter
have been included to enhance the understanding of the users.
Online Leaming Centre
This book is accompanied by an exhaustive online learning centre http://www.mhhe.com/jain/mde4e which
provides useful resources for students and instructors. Students can access simulation software, sample
chapters, additional MCQs, web links and university questions along with answers. Instructors can avail
PowerPoint Slides (chapter-wise), solution manual, university questions along with answers and class tests.
Suggestions for further improvement of the book can be sent at the following email id-tmh.cse feedback@
gtnail.com (kindly mention the title and author name in the subject line).

RP Jain
 xvi Modern Digital Electronics

Chapter 1 introduces the fundamental concepts of digital electronics, advantages of digital systems and
basic digital circuits. Chapter 2 reviews semiconductor devices from the point of view of their applications
in digital circuits. Based on these devices, various digital circuits, referred to as logic families, have been
discussed in Chapter 3. This also deals with the interfacing problems between ICs of same logic families and
between those of different logic families. Necessary number systems and commonly used codes in digital
systems and microprocessors have been discussed in Chapter 4.
Chapter 5 deals with the conventional methods of combinational system design. The importance of the
methods, such as the Kamaugh map technique, has gone down because of simpler methods required to
design the same systems using other functions such as multiplexers, demultiplexers and PLAs which are
easily available in ICs. Combinational logic design using MSI circuits is covered in Chapter 6 which assumes
greater importance for the design of digital systems due to considerations of simplicity in design, cost, space,
power requirement, speed, etc.
Chapter 7 introduces the basic building block of a sequential circuit-the FLIP-FLOP. All types ofFLIP-
FLOPs with their excitation tables and triggering methods have been discussed in detail. Sequential logic
design has been discussed in Chapter 8. Here again, both the approaches, namely conventional design using
FLIP-FLOPs and the modem method using available MSI circuits, have been discussed.
Chapter 9 deals with timing circuits which are an essential part of a digital system. Timing circuits using
various ICs, such as gates, OP AMP, Schmitt trigger, monostable multivibrator, and 555 Timer, have been
discussed.
The analog-to-digital (AID) and digital-to-analog (D/A) converters form an important part of many digital
systems and the commonly used techniques have been discussed in Chapter 10.
Chapter 11 deals with semiconductor memories which have assumed an important role in present-day
digital systems. Various semiconductor memories, such as static and dynamic shift register memories,
static and dynamic RAMs, ROM, PROM, EPROM, EAROM, CAM, and CCD, have been discussed in
detail. Programming techniques used for programmable ROMs and erasing techniques used for erasable
programmable ROMs have also been discussed thoroughly. The LSI device PLA which is very useful for
digital system design has been introduced in a very simple and systematic way which will help the reader to
understand the operation and usefulness of this device for digital system design.
The microprocessor has been introduced in Chapter 12. The fundamentals of microprocessors have been
presented in a manner which will help a novice understand this highly sophisticated device. The most widely
used Intel's 8085A 8-bit microprocessor has been chosen for discussion. Its organisation, operation and
programming have been discussed in detail, which will help the reader learn the use of microprocessors.

RP Jain
 Combinational Logic Design Using MS! Circuits 263

Table 6.15 Numbero/74184 /Cs Required

Number of
BCD decades 74184 ICs required
2 2
3 6
4 II
5 19
6 28

A read-only-memory (ROM) may be a convenient alternative, which will be discussed later.

Example 6.9
Verify the operation of a 2-decade BCD-to-binary converter of Fig. 6.31 for ar input of 29 .

Solution
The input is
D , C, B , A , D 0 C0 B 0 A 0 = 00101001
The binary output B0 = A 0 = I
The inputs of IC I are E = B, = I
D = A, = 0
C = D0 = I
B = C0 = 0
A = B0 = 0
The outputs ofICI are Y5 = 0
Y4 = I
y3 = I
y2 = I
Y, = 0
The binary outputs B, and B 2 are
B, = Y , = 0
B2 = yl = 0
The inputs ofIC2 are E = D, = 0
D = C, = 0
C= Y5 ofICI = 0
B = Y4 ofICI = 0
A = Y3 ofIC I = I
The outputs of IC2 are Y5 = 0
Y4 = 0
y3 = 0
Y,= 1
Y, = I
 264 Modern Digital Electronics

The binary outputs B,, B4 , B 5 , and B 6 are

B3 = Y, = 1
s. = y2 = 1
BS= Y, = O
B 6 = Y4 = 0
Therefore the full binary output is 0011101.

6.9.2 Binary-to-BCD Converter

The block diagram of binary-to-BCD converter IC 74185A is given in Fig. 6.32 and Table 6.16 gives its truth
table. It has the same pin out as the 74184. The binary inputs are applied at terminals A through E and the
BCD outputs are available at terminals Y, through Y6 ( Y7 and Y8 are not used and these are always at logic 1).
Similar to the BCD-to-binary converter, the least-significant bit bypass the circuit as shown in Fig. 6.32.

Table 6.16 Truth Table of 74185A Binary-to-BCD Converter

Binary Inputs Outputs

Words E D C B A G y• Y, y• Y, Y, Y,
0- 1 0 0 0 0 0 0 0 0 0 0 0 0
2- 3 0 0 0 0 1 0 0 0 0 0 0 1
4- 5 0 0 0 1 0 0 0 0 0 0 1 0
6- 7 0 0 0 1 1 0 0 0 0 0 1 1
8- 9 0 0 1 0 0 0 0 0 0 1 0 0
10 - 11 0 0 1 0 1 0 0 0 1 0 0 0
12 - 13 0 0 1 1 0 0 0 0 1 0 0 1
14 - 15 0 0 1 1 1 0 0 0 1 0 1 0
16 - 17 0 1 0 0 0 0 0 0 1 0 1 1
18 - 19 0 1 0 0 1 0 0 0 1 1 0 0
20 - 21 0 1 0 1 0 0 0 1 0 0 0 0
22 - 23 0 1 0 1 1 0 0 1 0 0 0 1
24 - 25 0 1 1 0 0 0 0 1 0 0 1 0
26 - 27 0 1 1 0 1 0 0 1 0 0 1 1
28 - 29 0 1 1 1 0 0 0 1 0 1 0 0
30 - 31 0 1 1 1 1 0 0 1 1 0 0 0
32 - 33 1 0 0 0 0 0 0 1 1 0 0 1
34 - 35 1 0 0 0 1 0 0 1 1 0 1 0
( Continued)
 Combinational Logic Design Using MS! Circuits 265

Table 6.16 (Continued)

Binary Inputs Outputs

words E D C B A G y• Y, Y, Y, yl Y,
36 - 37 I 0 0 I 0 0 0 I I 0 I I
38 - 39 I 0 0 I I 0 0 I I I 0 0
40 - 41 I 0 I 0 0 0 I 0 0 0 0 0
42 - 43 I 0 I 0 I 0 I 0 0 0 0 I
44 - 45 I 0 I I 0 0 I 0 0 0 I 0
46 - 47 I 0 I I I 0 I 0 0 0 I I
48 - 49 I I 0 0 0 0 I 0 0 I 0 0
50 - 51 I I 0 0 I 0 I 0 I 0 0 0
52 - 53 I I 0 I 0 0 I 0 I 0 0 I
54 - 55 1 1 0 I I 0 I 0 I 0 I 0
56 - 57 I 1 I 0 0 0 I 0 I 0 I I
58 - 59 I I I 0 I 0 I 0 I I 0 0
60 - 61 I I I I 0 0 I I 0 0 0 0
62 - 63 I I I I I 0 I I 0 0 0 I
All X X X X X I I I I I I I

Bo
B,
o----------oAo}
(LSB)
A Y, ~
LSD
~~~cy ~ B Y2 : ~
inputs B3 - C Y3 - Do 2-decade
74185A BCD outputs
B4 D Y4
Bs E Ys
MSB ~
Enable input - ~ G y6 -
(active-low)

Fig. 6.32 A 6-Bit Binary-to-BCD Converter

The method of expansion to accommodate larger number of binary inputs is quite complicated. The circuit
for conversion of 8-bit binary number to BCD is given in Fig. 6.33. This requires three ICs. Table 6.17 gives
the number of ICs required for a given number of input binary bits. Similar to the BCD-to-binary converters
we may have to resort to ROM for conversion of longer binary words.
266 Modern Digital Electronics

8-bit binary inputs

B7 B6 Bs B4 B3 B2 B1 Bo

E D C B A
IC !
y6 Ys Y4 Y3 Y2 Y1

E D C B A
IC2
Ys Y4 Y3 Y2 Y1

- E D C B A
IC3
Ys Y4 Y3 Y2 Yi

B2 A2 D1 Ci Bi Ai Do Co Bo Ao
'-v----' ~ - - - . - - - - ~
MSD LSD
3-decade BCD outputs

Fig. 6.33 An 8-bit Binary-to-BCD Converter

Table 6.17 Number of 74185A /Cs Required

Number of
Binary bits 74185 /Cs required
4- 6 I
7, 8 3
9 4
10 6
11 7
12 8
13 10
14 12
15 14
16 16
 Combinational Logic Design Using MSI Circuits 267

Example 6.10
Verify the operation of 8-bit binary-to BCD converter of Fig. 6.33 for the binary input of 11010011.

Solution
The inputs ofICl are E=B7 = 1
D=B6 = 1
C=B 5 =0
B=B4 = 1
A=B3 =0
The outputs ofICl are Y6 = 1
Y5 =0
y4 = 1
Y3 =0
Y2 =0
YI= 1
The inputs ofIC2 are E= Y3 ofICl = 0
D = Y2 ofICl = 0
C= Y1 ofICl = 1
B=B2 =0
A=BI = 1
The outputs ofIC2 are Y6 =0
Y5 =0
y4 = 1
Y3 =0
Y2 =0
Yl=0
The inputs ofIC3 are E=0
D= Y6 ofICl = 1
C= Y5 ofICl = 0
B= Y4 ofICl = 1
A = Y5 ofIC2 = 0
The outputs ofIC3 are Y6 =0
Y5 = 1
Y4 =0
Y3 =0
Y2 =0
Yl=0
The BCD outputs are B 2 = Y5 ofIC3 = 1
A 2 = Y4 ofIC3 = 0
D 1 = Y3 ofIC3 = 0
cl = y2 ofIC3 = 0
B 1 = Y1 ofIC3 = 0
A 1 = Y4 ofIC2 = 1
D 0 =Y3 ofIC2=0
C0 = Y2 ofIC2 = 0
 268 Modern Digital Electronics

B 0 = Y1 ofIC2 = 0
A 0 =B0 = 1
Therefore, the BCD output is 10 0001 0001 = 211.

6.10 PRIORITY ENCODERS

The encoder was introduced in Section 5.8.3 and a decimal-to-BCD encoder was designed using gates. The
process of encoding is reverse of that of decoding. A number of priority encoder MSI ICs are available.

6.10.1 Decimal-to-BCD Encoder

One of the most commonly used input device for a digital system is a set of ten switches, one for each
numeral between O and 9. These switches generate
1 or O logic levels in response to turning them OFF
2 A or ON. When a particular number is to be fed to the
3 digital circuit in BCD code, the switch corresponding
4 B "' to that number is pressed. There is an IC available for
Q -s
74147 u B- performing this function (7 414 7) which is a priority
C al ::l
0 encoder. The block diagram of 74147 IC is given in
Fig. 6. 34 and Table 6.18 gives its truth table. It has
7 D
(MSB) active-low inputs and outputs. The meaning of the
8
word priority can be seen from the truth table, for
9 example, if inputs 2 and 5 are LOW, the output will
be corresponding to 5 which has a higher priority than
Fig. 6.34 Block Diagram of 74147 2, i.e. the highest numbered input has priority over
Decimal-to-BCD Priority Encoder
lower numbered inputs.

Table 6.18 Truth Table o/74147

Active-low decimal inputs Active-low BCD outputs

1 2 3 4 5 6 7 8 9 D C B A
1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 0
X 0 1 1 1 1 1 1 1 1 1 0 1
X X 0 1 1 1 1 1 1 1 1 0 0
X X X 0 1 1 1 1 1 1 0 1 1
X X X X 0 1 1 1 1 1 0 1 0
X X X X X 0 1 1 1 1 0 0 1
X X X X X X 0 1 1 1 0 0 0
X X X X X X X 0 1 0 1 1 1
X X X X X X X X 0 0 1 1 0
 Combinational Logic Design Using MS! Circuits 269

6.10.2 Octal-to-Binary Encoder

The octal code is often used at the inputs of digital circuits that require manual entering of long binary words.
Priority encoder 74148 IC has been designed to achieve this operation. Its block diagram is given in Fig. 6.35
and Table 6.19 gives its truth table. This circuit also has active-low inputs and active-low outputs. The enable
input and carry outputs, which are also active-low, are used to cascade circuits to handle more inputs. A
hexadecimal-to-binary encoder, which is also a very useful circuit because of widespread use of hexadecimal
code in computers, microprocessors, etc. can be designed using this facility.
The priority encoders can conveniently be used for handling priority interrupts in computers,
microprocessors, etc.

0
I

:}
Binary outputs
2 (active-low)

Octal intputs 3
(active-low) 4 74148 (MSB)
5
6
7 GS} Carry outputs
Enable intput
EO (active-low)
(active-low)

Fig. 6.35 Block Diagram of 74148 Octal-to-Binary Priority Encoder

Table 6.19 Truth Table of 74148

Inputs Outputs
EI 0 1 2 3 4 5 6 7 C B A GS EO
I X X X X X X X X I I I I I
0 0 I I I I I I I I I I 0 I
0 X 0 I I I I I I I I 0 0 I
0 X X 0 I I I I I I 0 I 0 I
0 X X X 0 I I I I I 0 0 0 I
0 X X X X 0 I I I 0 I I 0 I
0 X X X X X 0 I I 0 I 0 0 I
0 X X X X X X 0 I 0 0 I 0 I
( Continued)
 270 Modern Digital Electronics

Table 6.19 ( Continued)

-------
Inputs Outputs
El 0 1 2 3 4 5 6 7 I C B A GS EO
0 X X X X X X X 0 0 0 0 0 I
0 I 0

Example 6.11
Design a hexadecimal-to-binary encoder using 74148 encoders and 74157 multiplexer.

Solution
Since there are sixteen symbols (0-F) in hexadecimal number system, two 74148 encoders are required. Hexadecimal
inputs O through 7 are applied to IC 1 input lines and inputs 8 through F to IC2 input lines. Whenever one of the
inputs of IC2 is active (LOW), IC 1 must be disabled, on the other hand, if all the inputs of IC2 are HIGH then IC 1
must be enabled. This is achieved by connecting the EO line ofIC2 to the EI line ofICl. A quad 2:1 multiplexer is
required to get the proper 4-bit binary outputs. The complete circuit is shown in Fig. 6.36. The GS output of74148
goes LOW whenever one of its inputs is active. Therefore, GS ofIC2 is connected to select input of 74157, which
selects A inputs if it is LOW, otherwise B inputs are selected. The outputs of the multiplexer are the required binary
outputs and are active-low. This circuit is also a priority encoder.

0
A Bo
2 B B1
3 C B2
4 IC ! B3
5 74148
Logic I
6 GS
s 7
·-t~
EO Yo "'
s
a-~
-
. -~
e
0
b Ii"
IC3 Yi 5 ~
·u., .::: 741 57 ~]
. tl
"0

~
::i::
..
~
8
9
El

A Ao
Y2

Y3
-:s~-
i:: · -

~
~

A B A1
B IC2 C A2
C 74148 A3
D -
E GS
F Select Strobe

-
exadecimal-to-Binary PriorityEncoder
------
 Combinational Logic Design Using MS! Circuits 271

6.11 DECODER/DRIVERS FOR DISPLAY DEVICES

6.11.1 BCD-to-Decimal Decoder/Driver

In many digital systems, we prefer to see the output in a decimal format. The outputs can either be displayed
using display devices like LEDs, Nixie tubes, etc. or can be used to actuate some indicators or relays. Table
6.20 gives the available BCD-to-decimal decoder/driver ICs. All these ICs have active-high inputs and active-
low outputs.

Table 6.20 Available BCD-to-decimal decoder/driver /Cs

IC No. Output circuit Application

7441 Open-collector Nixie tube driver
7442 Totem-pole LED driver
7445 Open-collector Indicator/relay driver
74141 Open-collector Nixie tube driver
74145 Open-collector Indicator/relay driver
74445 Open-collector Indicator/relay driver

6.11.2 BCD-to-7-Segment Decoder/Driver

Seven segment display is the most popular display device used in digital systems. For displaying data using
this device, the data have to be converted from BCD to 7-segment code. A number of MSI ICs are available
(Table 6.21) for performing this function. The decoder/driver circuit has 4 input lines for BCD data and 7
output lines to drive a 7-segment display. Output terminals a through g of the decoder are to be connected
to a through g terminals of the display respectively. If the outputs are active-low, then the 7-segment LED
must be of the common anode type, whereas if the outputs are active-high then the 7-segment LED must be
of the common cathode type. The function of LT, RBI, RBO and BI are given in Table 6.22 and are explained
below.

Table 6.21 Available BCD-to-7-Segment Decoder/Driver /Cs

Facilities available
Rating Lamp Ripple blanking Ripple blanking Blanking
(Max voltage, Test Input Output Input
IC No. Output Sink current) LT RBI RBO BI
7446, 74246 Active-low; 30 V, 40 mA Yes Yes Yes Yes
Open-collector
7447, 74247 Active-low; 15 V, 40 mA Yes Yes Yes Yes
Open-collector

(Continued)
 272 Modern Digital Electronics

Table 6.21 (Continued)

Facilities available
Rating Lamp Ripple blanking Ripple blanking Blanking
(Max voltage, Test Input Output Input
IC No. Output Sink current) LT RBI RBO BI
7448, 74248 Active-high; 5.5 V, 6.4 mA Yes Yes Yes Yes
Pull-up resis-
tor=2kf!
7449, 74249 Active-high; 5.5 V, 8 mA No No No Yes
Open-collector

Table 6.22 Summary of BCD-to-7-Segment Decoder Functions

LT RBI BI/RBO BCD inputs Display mode

0 X I output X Lamp test
X X 0 input X Display blank
I I I output Any number Normal decoding
I 0 Normally at Any number Normal decoding with zero blanking
logic I output.
Goes to logic
0 during zero
blanking interval

LT This is used to check the segments of LED. If it is connected to logic O level, all the segments of the
display connected to the decoder will be ON. For normal decoding operation, this terminal is to be connected
to logic 1 level.
RBI It is to be connected to logic 1 for normal decoding operation. If it is connected to O level, the segment
outputs will generate data for normal 7-segment decoding for all BCD inputs except zero. Whenever the
BCD inputs correspond to zero, the 7-segment display switches off This is used for blanking out leading
zeros in multi-digit displays.
BI If it is connected to logic O level, the display is switched off irrespective of BCD inputs. This is used for
conserving power in multiplexed displays.
RBO This output, which is normally at logic 1 goes to logic Oduring zero blanking interval. This is used for
cascading purposes and is connected to RBI of the succeeding stage.

Example 6.12
(a) Set up a single 7-segment LED display using 744 7 BCD-to-7-segment decoder/driver.
(b) Design a 4-digit 7-segment LED display system with leading zero blanking.
(c) Design a 4-digit multiplexed 7-segment LED display system with leading-zero blanking.
 Combinational Logic Design Using MS! Circuits 273

Solution
(a) The set up is given in Fig. 6.37.
(b) A 4-digit display system can display numbers from 0000 to 9999. If the number to be displayed is smaller than
a 4-digit number then there is a problem of leading zeros. It is very often desirable to design a display system
so that any number less than 1000 will not show leading zeros. For example, the number 0203 should appear as
203. The block diagram of a 4-digit display system with leading zero blanking is shown in Fig. 6.38. The reader
should verify the operation of this circuit.
(c) When a multi-digit, 7-segment LED display system is used, it requires power which is n-times the power
required for a single 7-segment LED, where n is the number of such LEDs in the system. Typically, the current
requirement of one segment is 20 mA at full brightness which makes the maximum current requirement for a
single 7-segment LED to be 140 mA (corresponding to zero). If there are four such LEDs in the display system,
then the maximum current required would be 560 mA. It is possible to reduce the overall current drain of the
display system by using the concept of multiplexing the display, i.e. to energize the output digits one at a time.
If this is done in rapid succession, the display would appear to be continuous to the human eyes and the overall
current drain is equal to that of a single 7-segment display. Figure 6.39 gives the block diagram of a 4-digit
multiplexed 7-segment LED display system. Here, a counter (to be discussed later) drives the BCD-to-decimal
decoder 7442 and the output of the decoder through an inverter pulls up the common anode terminal to HIGH.
Each anode is excited in sequence at the rate determined by the clock frequency. Multi-digit 7-segment display
assemblies which can be used only in the multiplexed mode are also commercially available.

Current limiting Common

resistor anode

Vee

BCD { ~o--
: _ __,
=
inputs Co--------t
7447
Du-----_,
(MSB)
LT

----- RBI
GND

FND 507

-
Fig. 6.37 A 7447 Driving a 7-Segment LED Display
274 Modern Digital Electronics

Vee

R R R R

1-
_1 1-
_1 1-
_1 1-
_1
!_I !_I !_I !_I

!CI IC2 IC3 IC4

RBI RBO RB I RBO RBI RBO RBI RBO
7447 7447 7447 7447

MSD LSD
BCD inputs

Fig. 6.38 A 4-digit LED Display System with Leading Zero Blanking

Counter
Clock ----a
A B C D

A B C D
7442

0 2

R R R

1-
_1 1-
_1 1-
_1 1-
_1
!_I !_I !_I !_I

!CI IC2 IC3 IC4

RBI RBO RB I RBO RBI RBO RBI RBO
7447 7447 7447 7447

Vee
MSD LSD
BCD inputs

Fig. 6.39 A 4-digit Multiplexed Display System with Leading Zero Blanking
 Combinational Logic Design Using MS! Circuits 275

SUMMARY

The most popular and commonly available MSI ICs and their applications have been discussed in this
chapter. Since the logic equations for these circuits are very complex, therefore, their applicability
must be recognised at the system level. Quite often, the system specifications are affected by the initial
knowledge of available standard circuits. Each technique discussed can be thought of as a tool and each
tool has its place. The designer has to make a proper choice of the tool for the job. Though more than
one tool may work for a given job, the key is to select the right one. Although system design has been
oriented around making use of higher levels of integration, a lot of little jobs of interfacing the MSI
devices are still best done with discrete gates.
Active-low inputs and outputs have been indicated by small circles throughout. Recently, many
authors have started using an alternative symbol (small right triangle) to represent the active-low input/
output to avoid confusion (of inversion) associated with the small circle. Figure 6.35 is redrawn in Fig.
6.40 to indicate this new system.

2
A}
B
C
Binary
outputs
Octal 3
inputs 4 74148
5
6
GS} Carry
7
EO outputs
EI

Fig. 6.40 An Alternative Representation ofActive-Low Input/Output

GLOSSARY
Arithmetic-logic unit (ALU) A logic circuit that performs arithmetic and logical operations.
Comparator A logic circuit that compares two binary numbers and produces an output indicating whether
they are equal or which is greater if they are unequal.
Demultiplexer A logic circuit that connects a single input line to one of the several output lines.
Dot matrix display A display device consisting of elements in the form of dots arranged in a matrix form.
It is used to display alphanumeric and special characters.
Driver A circuit capable of supplying high load current.
Hardware The physical parts forming a system.
Look-ahead carry A method of generating carry for fast addition.
Multiplexed display A display system used in multiplexed mode.
Priorly encoder An encoder that responds to the highest number when two or more numbers are applied
simultaneously.
 276 Modern Digital Electronics

Strobe An input signal to a digital circuit that can enable or disable the circuit.
Subtractor A logic circuit used for subtraction.
Ten's complement It is 9's complement of a decimal number plus one.

REVIEW QUESTIONS

6.1 A logic circuit that gates one out of several inputs to single output is known as a _ _ _ _ __
6.2 A _ _ _ _ _ is a logic circuit that accepts one data input and distributes it over several
outputs.
6.3 The minimum number of selection inputs required for selecting one out of 32 inputs is _ _ __
6.4 A logic circuit required for converting BCD code to 7-segment code is known as _ _ _ _ __
6.5 In a BCD adder _ _ _ _ _ _ is added in case the sum is not valid BCD number.
6.6 A logic circuit used to compare binary numbers is _ _ _ _ _ __
6.7 _ _ _ _ _ _ _ is used in display systems to save_ _ _ _ _ __
6.8 A 4-variable logic expression can be realised using single _ _ _ _ _ _ multiplexer.
6.9 A decoder with 64 output lines has _ _ _ _ _ _ _ data inputs.
6.10 ALU stands for
-----------
6.11 A bubble at the output of a multiplexer indicates _ _ _ _ _ _ _ output.
6.12 Chip select input of a digital IC has L':,. symbol. This indicates _ _ _ _ __
6.13 A 4-digit display system with leading zero blanking displays 47 as _ _ _ _ _ __
6.14 _ _ _ _ _ _ _ _ complementation is used for performing BCD subtraction.
6.15 Subtractors are designed using _ _ _ _ _ _ _ I Cs.

PROBLEMS
6.1 Realise the logic function of table 6.3 using
(a) A 16:1 multiplexer IC 74150, and
(b) An 8:1 multiplexer IC 74152.
6.2 Design a 32: 1 multiplexer using two 16: 1 multiplexer I Cs
6.3 Design a full adder using 8:1 multiplexer ICs. Compare the IC package count with the NAND-NAND
realisation.
6.4 Design a 4-bit ADDER/SUBTRACTOR circuit with ADD/SUB control line.
6.5 Design a Gray-to-BCD code converter using
(a) Two dual 4:1 multiplexer ICs (74153) and some gates, and
(b) One 1:16 demultiplexer IC 74154 and NAND gates.
 Combinational Logic Design Using MSI Circuits 277

6.6 Design a BCD-to-7-segment decoder with active-low outputs using

(a) Dual 4:1 multiplexers and some gates,
(b) 1:16 demultiplexer and some gates, and
(c) A BCD-to-decimal decoder and NAND gates.
(d) Compare the IC package count.
6.7 Design a BCD-to-Gray code converter using
(a) 8:1 multiplexers,
(b) Dual 4: 1 multiplexers and some gates,
(c) Quad 2: 1 multiplexers and some gates,
(d) A BCD-to-decimal decoder and NAND gates, and
(e) NAND gates only.
(f) Compare package count for the various approaches.
6.8 Realise the following functions of four variables using
(a) 8:1 multiplexers,
(b) 16: 1 multiplexers, and
(c) 4-to-16-line decoder with active-low outputs.
(i) f. = Dn(0, 3, 5, 6, 9, 10, 12, 15)
(ii) Ji= Im(0, 1, 2, 3, 11, 12, 14, 15)
(iii) /2 = TIM(0, 1, 3, 7, 9, 10, 11, 13, 14, 15)
6.9 Design a 40:1 multiplexer using 8:1 multiplexers.
6.10 Design a 1:40 demultiplexer using BCD-to-decimal decoders.
6.11 In the n-bit binary adder shown in Fig. 6.12a, determine the time required for the final carry Cn-i to
reach steady state. Assume each full-adder to be consisting of half-adder circuits (Prob. 5.19(b)) and
propagation delays of gates as given in Prob. 5.20.
6.12 Design a 4-digit BCD adder using 7483 adders.
6.13 Design a 2-bit comparator using gates.
6.14 Design an 8-bit comparator using only two 7485s.
6.15 Verify the operation of the 24-bit comparator of Fig. 6.24 for the following numbers:
A= 100110000111011001010010
B = 101110000111011000100011
6.16 Design a one digit-BCD-to-binary converter using 74184.
6.17 Show that the hexadecimal-to-binary encoder of Fig. 6.36 is a priority encoder.
6.18 Design a 6-bit odd/even parity checker using 74180.
6.19 Design a parity generator circuit using 74180 to add an odd parity bit to a 7-bit word.
6.20 Design a parity generator circuit to add an even parity bit to a 14-bit word. Use two 74180
packages.
6.21 Design a 10-bit parity checker using one 74180 and an EX-OR gate (7486).
6.22 Design a two level parity checker tree using ten packages of7 4180 to check the parity of 81 bits.
6.23 Design a two level parity checker tree using three packages of 74180 to check the parity of 25 bits.
6.24 Design the following circuits:
(a) 7442 BCD-to-decimal decoder driving ten LEDs.
(b) 74141 BCD-to-decimal decoder driving a Nixie tube
6.25 Suggest a suitable alternative circuit for Fig. 6.11 which does not require an OR gate.
6.26 Consider the four digit 7-segment display system shown in Fig. 6.41. Modify the circuit of Fig. 6.39
if this display system is to be used.
 278 Modern Digital Electronics

a
a a a a
b
C f 1-:-1 f 1-;-1 f 1-:-1
1--:-1 b f b b b
Cathodes d
e e/-1
- -
c eI-le
- d
e/-/c
- e-I-le
d d
f d
g

Anodes
Fig. 6.41 A 4-digit 7-Segment Display System

6.27 A commonly used display system known as 7 x 5 dot matrix is shown in Fig. 6.42a. This is used to
display alphanumeric characters and some special symbols. It is desired to display R using this display
system whose pattern of glowing of the dots is shown in Fig. 6.42b. Design a suitable circuit for this .

• • • • • • • • •
2 • • • • • • •
3 • • • • • • •
ROWS
(Cathodes)
4 • • • • • •• • •
5 • • • • • • •
6 • • • • • • •
7.
DP •l 2• •3 4• •5 • •

COLUMNS
(Anodes)
(a) (b)
Fig. 6.42 A 7 x 5 Dot Matrix Display
 CHAPTER 7

FLIP-FLOPS

7.1 INTRODUCTION
So far we have directed our studies towards the analysis and design of combinational digital circuits. Though
very important, it constitutes only a part of digital systems. The other major aspect of digital systems is
analysis and design of sequential circuits. However, sequential circuit design depends, to a large extent, on
the combinational circuit design discussed earlier.
There are many applications in which digital outputs are required to be generated in accordance with the
sequence in which the input signals are received. This requirement can not be satisfied using a combinational
logic system. These applications require outputs to be generated that are not only dependent on the present
input conditions but they also depend upon the past history of these inputs. The past history is provided by
feedback from the output back to the input.
A block diagram of a sequential circuit is shown in Fig. 7.1. It consists of combinational circuits which
accept digital signals from external inputs and from outputs of memory elements and generates signals for
external outputs and for inputs to memory elements referred to as excitation.
A memory element is some medium in which one bit of information ( 1 or 0) can be stored or retained until
necessary, and thereafter its contents can be replaced by a new value. The contents of memory elements in
Fig. 7.1 can be changed by the outputs of the combinational circuit which are connected to its input.

Ex
Nx

Fig. 7.1 Block Diagram of a Sequential Circuit

 280 Modern Digital Electronics

The combinational circuit performs certain operations, some of which are used to determine the digital
signals to be stored in memory elements. The other operations are performed on external inputs and memory
outputs to generate the external outputs.
The above process demonstrates the dependence of the external outputs of a sequential circuit on the
external inputs and the present contents of the memory elements (referred to as the present state of memory
elements). The new contents of the memory elements, referred to as the next state; depend on the external
inputs and the present state. Hence, the output of a sequential circuit is a function of the time sequence of
inputs and the internal states.
Sequential circuits are classified in two main categories, known as asynchronous and synchronous
sequential circuits depending on timing of their signals.
A sequential circuit whose behaviour depends upon the sequence in which the input signals change is
referred to as an asynchronous sequential circuit. The outputs will be affected whenever the inputs change.
The commonly used memory elements in these circuits are time delay devices. These can be regarded as
combinational circuits with feedback.
A sequential circuit whose behaviour can be defined from the knowledge of its signal at discrete instants
of time is referred to as a synchronous sequential circuit. In these systems, the memory elements are affected
only at discrete instants of time. The synchronization is achieved by a timing device known as a system clock
which generates a periodic train of clock pulses as shown in Fig. 7.2. The outputs are affected only with the
application of a clock pulse.

Bit-time Bit-time
n n+l

ftJLl_ __ _
0 T 2T (n -1) T nT (n + 1) T
••• t

Fig. 7.2 A Train ofPulses

Since the design of asynchronous circuits is more-tedious and difficult, therefore their uses are rather
limited.
Synchronous circuits have gained considerable domination and wide popularity and are also known as
clocked-sequential circuits. The memory elements used are FLIP-FLOPS which are capable of storing
binary information.

7.2 A 1-BIT MEMORY CELL

The basic digital memory circuit is known as FLIP- FLOP. It has two stable states which are known as the 1
state and the Ostate. It can be obtained by using NAND or NOR gates. We shall be systematically developing
a FLIP-FLOP circuit starting from the fundamental circuit shown in Fig. 7.3. It consists of two inverters G1
and G2 (NAND gates used as inverters). The output of G 1 is connected to the input of G2 (A 2) and the output of
G2 is connected to the input of G 1 (Ai).
Let us assume the output of G1 to be Q = 1, which is also the input of GiCA 2 = 1). Therefore, the output of
G2 will be Q = 0, which makes A 1 = 0 and consequently Q = 1 which confirms our assumption.
In a similar manner, it can be demonstrated that if Q = 0, then Q = 1 and this is also consistent with the
circuit connections.
 Flip-Flops 281

From the above discussion we note the following:

✓ The outputs Q and Q are always complementary.

;;/ The circuit has two stable states; in one of the stable state
Q = 1 which is referred to as the 1 state (or set state) whereas
in the other stable state Q = 0 which is referred to as the 0
state (or reset state).
V- If the circuit is in 1 state, it continues to remain in this state
and similarly if it is in 0 state, it continues to remain in this
state. This property of the circuit is referred to as memory,
i.e. it can store 1-bit of digital information.
Fig. 7.3 Cross-coupled Inverters as a
Memory Element Since this information is locked or latched in this circuit,
therefore, this circuit is also referred to as a latch.
In the latch of Fig. 7.3, there is no way of entering the desired digital information to be stored in it. In
fact, when the power is switched on, the circuit switches to one of the stable states (Q = 1 or 0) and it is not
possible to predict the state. Ifwe replace the inverters G 1 and G2 with 2-input NANO gates, the other input
terminals of the NANO gates can be used to enter the desired digital information. The modified circuit is
shown in Fig. 7.4. Two additional inverters G3 and G4 have been added for reasons which will become clear
from the following discussion.

s 0-------;
(Set)

Ro------;
(Reset)

Fig. 7.4 The Memory Cell with Provision for Entering Data

If S = R = 0, the circuit is exactly the same as that of Fig. 7.3 (Prob. 7.1). If S = 1 and R = 0, the output of
G3 will be 0 and the output of G4 will be 1. Since one of the inputs of G I is 0, its output will certainly be 1.
Consequently, both the inputs of G2 will be 1 giving an output Q = 0. Hence, for this input condition, Q = 1
and Q= 0. Similarly, if S = 0 and R = 1 then the outputs will be Q = 0 and Q = 1. The first of these two input
conditions (S = 1, R = 0) makes Q = 1 which is referred to as the set state, whereas the second input condition
(S = 0, R = 1) makes Q = 0 which is referred to as the reset state or clear state. This gives us the means for
entering the desired bit in the latch.
Now we see what happens if the input conditions are changed from S = 1, R = 0 to S = R = 0 or from
S = 0, R = 1 to S = R = 0. The output remains unaltered (Prob. 7.2). This shows the basic difference
between a combinational circuit and a sequential circuit, even though the sequential circuit is made up of
combinational circuits.
The two input terminals are designated as set (S) and reset (R) because S = 1 brings the circuit in set state
and R = 1 brings it to reset or clear state.
 282 Modern Digital Electronics

If S = R = 1, both the outputs Q and Q will try to become 1 which is not allowed and therefore, this input
condition is prohibited.

7.3 CLOCKED S-R FLIP-FLOP

It is often required to set or reset the memory cell (Fig. 7.4) in synchronism with a train of pulses (Fig. 7.2)
known as clock (abbreviated as CK). Such a circuit is shown in Fig. 7.5, and is referred to as a clocked set-
reset (S-R) FLIP-FLOP.
In this circuit, if a clock pulse is present ( CK = 1), its operation is exactly the same as that of Fig. 7.4.
On the other hand, when the clock pulse is not present (CK= 0), the gates G3 and G4 are inhibited, i.e. their
outputs are 1 irrespective of the values of Sor R. In other words, the circuit responds to the inputs S and R
only when the clock is present.

Fig. 7 .5 A Clocked S-R FLIP-FLOP

Assuming that the inputs do not change during the presence of the clock pulse, we can express the operation
of a FLIP-FLOP in the form of the truth table in Table 7.1 for the S-R FLIP-FLOP. Here Sn and Rn denote
the inputs and Qn the output during the bit time n (Fig. 7.2). Qn+t denotes the output Q after the pulse passes,
i.e. in the bit time n + 1.

Table 7. 1 Truth Tableo/S-R FLIP-FLOP

Inputs
Output
s R Qn+l
" "
0 0 Q,,
l 0 l
0 l 0
l l ?

If Sn= Rn= 0, and the clock pulse is applied, the output at the end of the clock pulse is same as the output
before the clock pulse, i.e. Qn+t = Qn. This is indicated in the first row of the truth table.
If Sn= 1 and Rn= 0, the output at the end of the clock pulse will be 1, whereas if Sn= 0 and Rn= 1, then
Qn+t = 0. These are indicated in the second and third rows of the truth table respectively.
 Flip-Flops 283

In the circuit of Fig. 7.4, it was mentioned that S = R = 1 is not allowed. Let us see what happens in the
S-R FLIP-FLOP of Fig. 7.5 if Sn= Rn= 1. When the clock is present the outputs of gates G 3 and G 4 are
both 0, making one of the inputs of G I and G 2 NANO gates 0. Consequently, Q and Q both will attain logic 1
which is inconsistent with our assumption of complementary
outputs. Now, when the clock pulse has passed away (CK=
0), the outputs of G 3 and G 4 will rise from Oto 1. Depending
s- - Q upon the propagation delays of the gates, either the stable state
S-R Qn+t = 1 (Qn+i = 0) or Qn+t = 0 (Qn+i = 1) will result. That means
CK - the state of the circuit is undefined, indeterminate or ambiguous
FLIP-FLOP
and therefore is indicated by a question mark (fourth row of the
R Q
truth table).
The condition S n = R n = 1 is forbidden and it must not be
allowed to occur.
Fig. 7.6 Logic Symbol of Clocked S-R The logic symbol of clocked S-R FLIP-FLOP is given
FLIP-FLOP
in Fig. 7.6.

7.3.1 Preset and Clear

In the FLIP-FLOP of Fig. 7.5, when the power is switched on, the state of the circuit is uncertain. It may come
to set (Q = 1) or reset (Q = 0) state. In many applications it is desired to initially set or reset the FLIP-FLOP, i.e.
the initial state of the FLIP-FLOP is to be assigned. This is accomplished by using the direct, or asynchronous
inputs, referred to as preset (Pr) and clear (Cr) inputs. These inputs may be applied at any time between clock
pulses and are not in synchronism with the clock. An S -R FLIP- FLOP with preset and clear is shown in Fig. 7. 7.
If Pr= Cr= 1 the circuit operates in accordance with the truth table of S-R FLIP-FLOP given in Table 7.1.
If Pr= 0 and Cr= 1, the output of G 1(Q) will certainly be 1. Consequently, all the three inputs to G 2 will
be 1 which will make Q = 0. Hence, making Pr= 0 sets the FLIP-FLOP.
Similarly, if Pr= 1 and Cr= 0, the FLIP-FLOP is reset. Once the state of the FLIP-FLOP is established
asynchronously, the asynchronous inputs Pr and Cr must be connected to logic 1 before the next clock is applied.

Prest (Pr)

Clear (Cr)
(a)
Fig. 7.7 (a) An S-R FLIP- FLOP with Preset and Clear,
(b) Its Logic Symbol
 284 Modern Digital Electronics

Pr

s 0---------, Q
S-R
CK o---------,
FLIP - FLOP

Ro---------, Q

Cr
( )
Fig. 7.7 (Continued)

The condition Pr = Cr = 0 must not be used, since this leads to an uncertain state.
In the logic symbol of Fig. 7.7b, bubbles are used for Pr and Cr inputs, which means these are active-low,
i.e. the intended function is performed when the signal applied to Pr or Cr is LOW The operation of Fig. 7.7
is summarised in Table 7.2.
The circuit can be designed such that the asynchronous inputs override the clock, i.e. the circuit can be set
or reset even in the presence of the clock pulse (Prob. 7.4).

Table 7.2 Summary of Operation o/S-R FLIP-FLOP

Inputs Output Operation performed

CK Cr Pr Q
I
l l l Q,,+,(Table 7. 1) Normal FLIP - FLOP
0 0 l 0 Clear
0 l 0 l Preset

7.4 J-K FLIP-FLOP

The uncertainty in the state of an S-R FLIP-FLOP when Sn= Rn= I (fourth row of the truth table) can b_:
eliminated by converting it into a J-K FLIP-FLOP. The data inputs are J and K which are ANDed with Q
and Q, respectively, to obtain Sand R inputs, i.e.

S=J·Q (7.la)

R=K·Q (7.1 b)

AJ-K FLIP-FLOP thus obtained is shown in Fig. 7.8. Its truth table is given in Table 7.3a which is
reduced to Table 7.3b for convenience. Table 7.3a has been prepared for all the possible combinations of J
 Flip-Flops 285

and K inputs, and for each combination both the states of the output have been considered. The reader can
verify this (Prob. 7.5).

Pr

S= JQ
l-----+---<>------0 Q
Ju-----,
S-R
CK 0------1
FF
l------+---ll------0 Q
R = KQ

Cr

Fig. 7 .8 An S-R FLIP- FLOP Converted into J-K FLIP- FLOP

Table 7.3a Truth Table/or Fig. 7.8

Inputs to
Data inputs Outputs S-RFF Output
I -
I

J,, K,, Q,, Q,, s,, Rn Q,,+l

0 0 0 l 0 0
~l = Q,,
0 0 l 0 0 0
l 0 0 l l 0
:] = l
l 0 l 0 0 0
0 l 0 l 0 0
~] = o
0 l l 0 0 l
l l 0 l l 0
0l l = Q,,
-
l l l 0 0 l
 286 Modern Digital Electronics

Table 7 .3b Truth Table ofJ-K FLIP-FLOP

Inputs I Output
J,, K,, Qn+I
0 0 Q,,
l 0 l
0 l 0
l l Qn

It is not necessary to use the AND gates of Fig. 7.8, since the same function can be performed by adding an
extra input terminal to each NANO gate G3 and G4 of Fig. 7.7 (Prob. 7.6). With this modification incorporated
in Fig. 7.7, we obtain the J-K FLIP-FLOP using NANO gates as shown in Fig. 7.9. The logic symbol of J-K
FLIP-FLOP is given in Fig. 7.10.

Pr

Jo------1 f-------0 Q

CK 0------1
J- K
FF
K o------1 f------OQ

Cr

Fig. 7.10 Logic Symbols ofJ-K

Fig. 7.9 A J-K FLIP-FLOP Using NANO Gates FLIP-FLOP

7.4.1 The Race-Around Condition

The difficulty of both inputs l(S = R = 1) being not allowed in an S-R FLIP-FLOP is eliminated in a J-K
FLIP-FLOP by using the feedback connection from outputs to the inputs of the gates G 3 and G4 (Fig. 7.9).
Table 7.3 assumes that the inputs do not change during the clock pulse (CK= 1), which is not true because of
the feedback connections. Consider, for example, that the inputs are J = K = I and Q = 0, and a pulse as shown
in Fig. 7.11 is applied at the clock input. After a time interval !:lt equal to the propagation delay through two
NANO gates in series, the output will change to Q = 1 (see fourth row of Table 7.3b). Now we have J= K = I
and Q = 1 and after another time interval of !:lt the output will change back to Q = 0. Hence, we conclude that
for the duration tp of the clock pulse, the output will oscillate back and forth between 0 and 1. At the end of
the clock pulse, the value of Q is uncertain. This situation is referred to as the race-around condition.
 Flip-Flops 287

Lea i ( siti e) ----I I--- t

Traili
e
( e ati e)
e

"~•,/1~ 0 T
Fig. 7.11 A Clock Pulse

The race-around condition can be avoided if tp < M < T. However, it may be difficult to satisfy this
inequality because of very small propagation delays in ICs. A more practical method for overcoming this
difficulty is the use of the master- slave (M-S) configuration discussed below.

7.4.2 The Master-Slave J-K FLIP-FLOP

A master- slave J-K FLIP-FLOP is a cascade of two S-R FLI P-FLOPs, with feedback from the outputs
of the second to the inputs of the first as illustrated in Fig. 7.12. Positive clock pulses are applied to the first
FLIP-FLOP and the clock pulses are inverted before these are applied to the second FLIP-FLOP.

Pr

CK

Cr
CK

Fig. 7.12 AMaster-SlaveJ-KFLIP-FLOP

When CK= 1, the first FLIP-FLOP is enabled and the outputs Q Mand QMrespond to the inputsJ and K
according to Table 7.3. At this time, the second FLIP- FLOP is inhibited because its clock is LOW (CK= 0).
When CK goes LOW (CK= 1), the first FLIP-FLOP is inhibited and the second FLIP-FLOP is enabled,
because now its clock is HIGH (CK= 1). Therefore, the outputs Q and Q follow the outputs QM and QM,
respectively (second and third rows of Table 7.3b). Since the second FLIP-FLOP simply follows the first
one, it is referred to as the slave and the first one as the master. Hence, this configuration is referred to as
master-slave (M-S) FLIP-FLOP .
 288 Modern Digital Electronics

Pr In this circuit, the inputs to the gates G3M and G4M

)
do not change during the clock pulse, therefore the
race-around condition does not exist. The state of the
(~ master-slave FLIP-FLOP changes at the negative
transition (trailing edge) of the clock pulse. The logic
J Q symbol of a M-S FLIP-FLOP is given in Fig. 7.13.
M-S
J- K At the clock input terminal, the symbol > is used to
CK > illustrate that the output changes when the clock makes
FF
a transition and the accompanying bubble signifies
K - -Q negative transition (change in CK from 1 to 0).
\J
7.5 D-TYPE FLIP-FLOP
)
If we use only the middle two rows of the truth table of
Cr the S-R (Table 7.1) or J-K (Table 7.3b) FLIP-FLOP, we
Fig. 7.13 AMaster-SlaveJ-K FLIP-FLOP obtain a D-type FLIP-FLOP as shown in Fig. 7.14. It has
Logic Symbol only one input referred to as D-input or data input. Its truth
table is given in Table 7.4 from which it is clear that the
output Qn+i at the end of the clock pulse equals the input D n before the clock pulse.

https://static.javatpoint.com/tutorial/digital-electronics/images/d-flip-flop2.png

Pr Pr

J rS
D J-K Q D Q
r D
CK S-R CK FF
FF
Q Q
K rR

Cr Cr
(a) ( )
Fig. 7.14 (a)A J-K or S-R FLIP-FLOP Converted into a D-type FLIP-FLOP (b) its Logic Symbol

Table 7.4 Truth Table ofa D-type FLIP-FLOP

Input Output
D,, Qn+l
0 0
 Flip-Flops 289

This is equivalent to saying that the input data appears at the output at the end of the clock pulse. Thus,
the transfer of data from the input to the output is delayed and hence the name delay (D) FLIP-FLOP . The
D-type FLIP- FLOP is either used as a delay device or as a latch to store 1-bit of binary information.

7.6 T-TYPE FLIP-FLOP https://static.javatpoint.com/tutorial/digital-electronics/images/t-flip-flop4.png

In aJ-K FLIP-FLOP, if J= K, the resulting FLIP-FLOP is referred to as a T-type FLIP-FLOP and is

shown in Fig. 7.15. It has only one input, referred to as T-input. Its truth table is given in Table 7.5 from which
it is clear that if T = I it acts as a toggle switch. For every clock pulse, the output Q changes.

Pr Pr

J
T Q T Q
J-K T
CK FF CK FF

Q Q
K

Cr Cr
(a) ( )
Fig. 7 . 15 (a) AJ-K FLIP-FLOP Converted into a T-type FLIP-FLOP (b) its Logic Symbol

Table 7.5 Truth Tableo/T-type FLIP-FLOP

Input Output
T,, Qn+I
0
Q,,

An S-R FLIP-FLOP cannot be converted into a T-type FLIP-FLOP since S= R = I is not allowed. However,
the circuit of Fig. 7.16 acts as a toggle switch, i.e. the output Q changes with every clock pulse (Prob. 7.11 ).

S - - Q

S-R
CK - r> FF

R -
Q

Fig. 7 . 16 An S-R FLIP-FLOP as a Toggle Switch

 290 Modern Digital Electronics

7.7 EXCITATION TABLE OF FLIP-FLOP

The truth table of a FLIP-FLOP is also referred to as the characteristic table and specifies the operational
characteristic of the FLIP-FLOP.
In the design of sequential circuits, we usually come across situations in which the present state and the
next state of the circuit are specified, and we have to find the input conditions that must prevail to cause the
desired transition of the state. By the present state and the next state we mean the state of the circuit prior
to and after the clock pulse respectively. For example, the output of an S-R FLIP-FLOP before the clock
pulse is Qn = 0 and it is desired that the output does not change when the clock pulse is applied. What input
conditions (Sn and Rn values) must exist to achieve this?
From the truth table (or the characteristic table) ofan S-R FLIP-FLOP (Table 7.1) we obtain the following
conditions:

1. Sn= Rn = 0 (first row)

2. Sn= 0, Rn= 1 (third-row)

We conclude from the above conditions that the Sn input must be 0, whereas the Rn input may be either
0 or 1 (don't-care). Similarly, input conditions can be found for all possible situations. A tabulation of
these conditions is known as the excitation table. It is a very important and useful design aid for sequential
circuits. Table 7.6 gives the excitation tables of S-R, J-K, T, and D FLIP- FLO Ps. This is derived from the
characteristic table of the FLIP-FLOP.

Table 7.6 Excitation Table o/FLIP-FLOPs

Present Next S-R FF J-K FF T-FF D-FF

State State s R J,, K,, T,, Dn
" "
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1

7.8 CLOCKED FLIP-FLOP DESIGN

In earlier sections, we defined or specified the operation of different FLIP- FLO Ps assuming a circuit without
regard to where the circuit came from or how it was designed. In this section, the design ofa FLIP-FLOP
is given. The design philosophy illustrated is, in fact, a general approach for the design of sequential circuits
and systems.
Consider the general model of the FLIP-FLOP shown in Fig. 7.17. Basically, a clocked FLIP-FLOP
is a sequential circuit which stores the bits O and 1. This operation is accomplished by using a binary cell
 Flip-Flops 291

coupled with some combinational set/reset decoding logic to allow some input control over the set and reset
operations of the cell. The steps for the design of FLIP-FLOP are given below.

Set/Reset Feedback
Decoder

I
I
I
~---------------------------------~
Fig. 7 .17 The General Model of the FLIP- FLOP

Step 1. Examine each row of the given characteristic table, specifying the desired inputs and outputs, and
answer the following questions and make a truth table with Y1 and Y2 as output variables.

1. Does the cell need to be set (Qn+i = 1) for this condition?

2. Does the cell need to be reset (Qn+i = 0) for this condition?
3. Does the cell need to be left as it is?

Step 2. Prepare the K-map for Y1 and Y2 output variables, minimize it and determine the logic for Y1 and Y2,
respectively. Draw the complete circuit using gates.
The above design steps are illustrated in Example 7 .1.

Example 7.1
Using the technique described above, design a clocked S- R FLIP - FLOP whose characteristic table is given in
Table 7.7.

Solution
Step 1. Determine the values of Y, and Y2 for each row. For example, for the first row Q" = 0 and Qn+i = 0. To obtain
Qn+i = 0, Y , must be equal to l , since Q"= l , Y2 can be 0 or l since Q" = 0. In a similar manner, complete
the truth table (Table 7.7).
292 Modern Digital Electronics

Table 7.7 Truth Table

-------
Characteristic table Truth table for decoder

CK s R Q,, Y, Y,

0 0 0 0 0 X

0 0 0 1 1 X

0 0 0 0 X

0 0 1 1 1 X

0 0 0 0 X

0 0 1 1 X

0 0 0
0 1 1 1 1 X :}•
0 0 0 0 X

0 0 1 1 X

0 0 0 X

0 1 0 1 0
0 0 0
0 X

0 X X

X X :}•·
*S = R = I can happen with no clock.
**S = R = I must not happen.

Step 2. The K-maps for Y, and Y2 are given in Fig. 7.18 which give

CKS CKS
RQn 00 01 11 10 RQn 00 01 11 10
~

00 0 00 X X X

01 X X X X 01

11 X X X 11 X 0

10 X 10 X X X X

Y1 Y2
Fig. 7.18 K-maps for Ex. 7.1
------
 Flip-Flops 293

J; = CK +S = CK · S
½= R + CK = CK · R
Thus, we see that the circuit resulting from this design is the same as that shown in Fig. 7.5.

7.8.1 Conversion from One Type of FLIP-FLOP to Another Type

In earlier sections, we have discussed conversion from S-R to J-K, S-R ( or J-K) to D-type, and J-K to T-type
FLIP- FLOPS. Now, we shall effect the conversion from one type of FLIP- FLOP to another type by using a
formal technique which is similar to the one used above and will be useful in the design of clocked sequential
circuits.
Consider the general model for conversion from one type of FLIP- FLOP to another type (Fig. 7.19 ). In
this, we are required to design the combinational logic decoder (conversion logic) for converting new input
definitions into input codes which will cause the given FLIP-FLOP to perform as desired.

f--------t---0 Q

FLIP - FLOP
FLIP-FLOP Given
Data Inputs Conversion
FLIP - FLOP
logic
f-------'-----0 Q

Fig. 7.19 The General Model Used to Convert One Type o/FLIP-FLOP to Another Type

To design the conversion logic we need to combine the excitation tables for both FLIP-FLOPS and make
a truth table with data input(s) and Q as the inputs and the input(s) of the given FLIP-FLOP as the output(s).
The conventional method of combinational logic design then follows as usual. The conversion is illustrated
in Example 7.2.

Example 7.2
Convert an S- R FLIP - FLOP to a J- K FLIP - FLOP.

Solution
The excitation tables of S- R and J- K FLIP - FLOPS are given in Table 7.6 from which we make the truth table
given in Table 7.8.
 294 Modern Digital Electronics

Table 7.8 Truth Table of Conversion Logic

-------
FF data inputs Output S-R FF inputs

Row J K Q s R
0 0 0 0 X

2 0 1 0 0 X

3 0 0 0
4 1 0 1 0
5 0 0
6 1 1 0 1
7 0 0 X 0
8 0 X 0

JK JK
00 01 11 10 Q 00 01 11 10
Q
0 0 0 1 1 I 0 X X 0 0
I

1 X 0 0 X 1 0 I 1 1 I 0

s R
Fig. 7.20 K-mapsfor Ex. 7.2

The K-maps are given in Fig. 7 .20, which give

and R = K-Q

Thus, we see that the circuit resulting from this design is the same as that shown in Fig. 7.8.

7.9 EDGE-TRIGGERED FLIP-FLOPs

All FLI P-FLOPs other than the master- slave type discussed in earlier sections are level triggered, i.e.
the outputs respond to the inputs (according to the truth table) as long as the clock is present. The only ICs
available in this category are latches, for example 7475 and 74100 are transparent latches.
The master- slave FLI P-FLOPs are also referred to as the pulse-triggered FLI P-FLOPs, i.e. the outputs
respond to the inputs when a pulse is applied at the clock input. The master FLIP-FLOP responds when the
 Flip-Flops 295

clock is present ( CK = 1) and the output of the slave will be available at the falling edge of the clock pulse
(CK= 0). As discussed in Section 7 .4, this eliminates the problem of race-around condition. In this the data
is locked-out at the falling edge of the clock pulse, i.e. the changes occurring at the inputs once CK goes to 0
will not affect the operation of the FLIP-FLOP.
The inputs to the FLIP-FLOP may change during the presence of the clock pulse due to certain operations
in the system. This causes uncertainty in the outputs of the FLIP-FLOP which is eliminated by using edge-
triggered FLIP- FLO PS.
In the case ofan edge-triggered FLIP-FLOP, the transfer of information from data input(s) to the output
of the FLIP-FLOP occurs at the positive (or negative) edge of the clock pulse. The only time the outputs can
change state is during the brief interval of time when the clock signal is making a transition from the Oto 1
(j), or in some circuits, from the 1 to OU) states. A FLIP-FLOP which responds only to rising (or falling)
edge is referred to as positive-edge-triggered (or negative-edge-triggered). The data lock-out occurs at the
end of the edge.
The logic symbol used for an edge-triggered FLIP-FLOP is the same as that ofa master-slave FLIP-
FLOP. These are shown in Figs. 7.13, 7.14b, and 7.15b.
The timing specifications ofan edge-triggered FLIP-FLOP are illustrated in Fig. 7.21 and are explained
below.

Set-up Time (t.) It is the time required for the input data to settle in before the triggering edge of the
clock. Its minimum time is usually specified by the manufacturers.

Hold Time (th) It is the time for which the data must remain stable after the triggering edge of the clock.
Minimum value of hold time is specified by the manufacturers.
The t. and th timings are shown in Fig. 7.21a.

Propagation Delays Similar to propagation delay in combinational circuits, there is delay in the
FLIP-FLOP output Q, making a change from HIGH-to-LOW or LOW-to-HIGH when a clock pulse is
applied. These delays are specified between the 50% points on the clock and data input waveforms. The
propagation delay, when the output Q changes from LOW-to-HIGH and HIGH-to-LOW, are specified as tpLH
and tpHL respectively. These are shown in Fig. 7.21b.

Clock Pulse Width The minimum time duration for which the clock pulse must remain HIGH (tCH) and
LOW (tcL) are specified by the manufacturers. Failure to meet these requirements may result in unreliable
triggering. These timings are specified between the 50% points on the clock transitions and are shown in Fig
7.21c.

Preset and Clear Pulse Width The manufacturers also specify the minimum time duration for a
preset input (tpLH) and clear input (tpHL).

Maximum Clock Frequency The maximum clock frequency (/max) is the highest rate at which a
FLIP- FLOP can be reliably triggered. If the clock frequency is higher than this, the FF will be enable to
trigger reliably.
Various timing values for some of the commonly used TTL and CMOS FLIP-FLOPs are given in
Table 7.9.