Dr.

Youssef Iraqi 8 March 2023

§2.5 Representing Instructions in the Computer

Representing Instructions
n Instructions are encoded in binary
n Numeric version of instructions: machine language
n Sequence of such instructions: machine code

n RISC-V instructions
n Encoded as 32-bit instruction words
n Small number of formats encoding operation code
(opcode), register numbers, …
n Regularity!

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Hexadecimal
n Base 16
n Compact representation of bit strings
n 4 bits per hex digit

0hex 0000two 4hex 0100two 8hex 1000two chex 1100two

1hex 0001two 5hex 0101two 9hex 1001two dhex 1101two
2hex 0010two 6hex 0110two ahex 1010two ehex 1110two
3hex 0011two 7hex 0111two bhex 1011two fhex 1111two

n Example: eca8 6420hex

n 1110 1100 1010 1000 0110 0100 0010 0000two

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RISC-V R-format Instructions

funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

n Instruction fields
n opcode: operation code
n rd: destination register number
n funct3: 3-bit function code (additional opcode)
n rs1: the first source register number
n rs2: the second source register number
n funct7: 7-bit function code (additional opcode)

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R-format Example
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

add x9,x20,x21
0 21 20 0 9 51

0000000 10101 10100 000 01001 0110011

0000 0001 0101 1010 0000 0100 1011 0011two =

015A04B316

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RISC-V I-format Instructions

immediate rs1 funct3 rd opcode
12 bits 5 bits 3 bits 5 bits 7 bits

n Immediate arithmetic and load instructions

n rs1: source or base address register number
n immediate: constant operand, or offset added to base address
n 2s-complement, sign extended

n Design Principle 3: Good design demands good

compromises
n Different formats complicate decoding, but allow 32-bit
instructions uniformly
n Keep formats as similar as possible

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RISC-V S-format Instructions

imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

n Different immediate format for store instructions

n rs1: base address register number
n rs2: source operand register number
n immediate: offset added to base address
n Split so that rs1 and rs2 fields always in the same place

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RISC-V Instruction encoding

“reg” means a register number between 0 and 31 and

“address” means a 12-bit address or constant.
The funct3 and funct7 fields act as additional opcode
fields.
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Example
If x10 has the base of the array A and x21
corresponds to h, the assignment statement
A[30] = h + A[30] + 1;
is compiled into …

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Stored Program Computers

The BIG Picture n Instructions represented in
binary, just like data
n Instructions and data stored
in memory
n Programs can operate on
programs
n e.g., compilers, linkers, …
n Binary compatibility allows
compiled programs to work
on different computers
n Standardized ISAs

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Check Yourself
n What RISC-V instruction does this
represent?
funct7 rs2 rs1 funct3 rd opcode
32 9 10 0 11 51

1. sub x9, x10, x11

2. add x11, x9, x10
3. sub x11, x10, x9
4. sub x11, x9, x10
n If a person is age 40ten, what is their age in
hexadecimal?
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§2.6 Logical Operations

Logical Operations
n Instructions for bitwise manipulation

n Useful for extracting and inserting

groups of bits in a word

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Shift Operations
n Shift left logical
n Shift left and fill with 0 bits
n sll by i bits multiplies by 2i
n Shift right logical
n Shift right and fill with 0 bits
n srl by i bits divides by 2i (unsigned only)
n Shift right arithmetic
n Shift right and fill with copies of old sign bit
n sra

n slli, srli, srai

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AND Operations
n Useful to mask bits in a word
n Select some bits, clear others to 0
and x9,x10,x11

x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000

x11 00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000

x9 00000000 00000000 00000000 00000000 00000000 00000000 00001100 00000000

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OR Operations
n Useful to include bits in a word
n Set some bits to 1, leave others unchanged
or x9,x10,x11

x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000

x11 00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000

x9 00000000 00000000 00000000 00000000 00000000 00000000 00111101 11000000

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XOR Operations
n Differencing operation
n Creates a 0 when bits are the same and a 1
otherwise.
xor x9,x10,x12 // NOT operation

x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000

x12 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111

x9 11111111 11111111 11111111 11111111 11111111 11111111 11110010 00111111

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§2.7 Instructions for Making Decisions

Conditional Operations
n Branch to a labeled instruction if a condition is
true
n Otherwise, continue sequentially

n beq rs1, rs2, L1

n if (rs1 == rs2) branch to instruction labeled L1

n bne rs1, rs2, L1

n if (rs1 != rs2) branch to instruction labeled L1

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Compiling If Statements
n C code:
if (i==j) f = g+h;
else f = g-h;
n f, g, … in x19, x20, …
n Compiled RISC-V code:
bne x22, x23, Else
add x19, x20, x21
beq x0,x0,Exit // unconditional
Else: sub x19, x20, x21
Exit: …
Assembler calculates addresses
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Compiling Loop Statements

n C code:
while (save[i] == k) i += 1;
n i in x22, k in x24, address of save in x25
n Compiled RISC-V code:
Loop: slli x10, x22, 2
add x10, x10, x25
lw x9, 0(x10)
bne x9, x24, Exit
addi x22, x22, 1
beq x0, x0, Loop
Exit: …

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Basic Blocks
n A basic block is a sequence of instructions
with
n No embedded branches (except at end)
n No branch targets (except at beginning)

n A compiler identifies basic

blocks for optimization
n An advanced processor
can accelerate execution
of basic blocks

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More Conditional Operations

n blt rs1, rs2, L1
n if (rs1 < rs2) branch to instruction labeled L1
n bge rs1, rs2, L1
n if (rs1 >= rs2) branch to instruction labeled L1
n Example
n if (a > b) a += 1;
n a in x22, b in x23
bge x23, x22, Exit // branch if b >= a
addi x22, x22, 1
Exit:

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Signed vs. Unsigned

n Signed comparison: blt, bge
n Unsigned comparison: bltu, bgeu
n Example
n x22 = 1111 1111 1111 1111 1111 1111 1111 1111
n x23 = 0000 0000 0000 0000 0000 0000 0000 0001
n x22 < x23 // signed
n –1 < +1
n x22 > x23 // unsigned
n +4,294,967,295 > +1

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Bounds Check Shortcut

Treating signed numbers as if they were
unsigned
à low-cost way to check 0 ≤ 𝑥 < 𝑦
Example:
Reduce an index out-of-bounds check:
branch to IndexOutOfBounds if 𝑥20 ≥ 𝑥11
or if 𝑥20 is negative.
Solution:
bgeu x20, x11, IndexOutOfBounds

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