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Sigma-Delta Converters Design and Simulations

This document describes simulations of sigma-delta converters. It includes: 1) Simulation of a 1st order sigma-delta ADC with inputs of 0.7V and 0.2V, showing it only works for 0.2V. 2) Design of a 2nd order sigma-delta modulator and simulation with a 0.3V input, showing it produces the correct average output. 3) Conclusion that 1st and 2nd order sigma-delta circuits were designed and tested with different inputs.

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Muhammad Yousaf
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76 views8 pages

Sigma-Delta Converters Design and Simulations

This document describes simulations of sigma-delta converters. It includes: 1) Simulation of a 1st order sigma-delta ADC with inputs of 0.7V and 0.2V, showing it only works for 0.2V. 2) Design of a 2nd order sigma-delta modulator and simulation with a 0.3V input, showing it produces the correct average output. 3) Conclusion that 1st and 2nd order sigma-delta circuits were designed and tested with different inputs.

Uploaded by

Muhammad Yousaf
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LAB 9

Sigma-Delta Converters Design and


Simulations
Name: Mudassir Ali
Roll No.: 21i-2425
Section: IC Design
Date: June 2,2022
Subject: Mixed Signal IC Design
Submitted to: Google Classroom
Contents
Lab Task:.................................................................................................................................................. 3
Switched-Capacitor Realization of a First Order without delay ADC .................................................. 3
Assignment # 1:....................................................................................................................................... 5
Simulate the same circuit as given above for i) u(n) = 0.7V ii) u(n) = 0.2V ....................................... 5
Assignment # 2:....................................................................................................................................... 7
Design second order sigma-delta modulator as given on Lecture#7 and slide#43. Verify it’s
operation for u(n) = 0.3V .................................................................................................................... 7
Conclusion: .............................................................................................................................................. 8

Table of Figures
Figure 1: Schematic of 1st order without delay ADC 3

Figure 2: Testbench for of 1st order without delay ADC 3

Figure 3: Results of 1st order without delay ADC 4

Figure 4: Testbench for 0.7 V input 5

Figure 5: Results for 0.7 V input 5

Figure 6: Testbench for 0.2 V input 6

Figure 7: Results for 0.2 V input 6

Figure 8: Schematic for 2nd order sigma-delta modulator 7

Figure 9: Testbench for 2nd order sigma-delta modulator 7

Figure 10: Results for 2nd order sigma-delta modulator 8


Lab Task:
Switched-Capacitor Realization of a First Order without delay ADC

Figure 1: Schematic of 1st order without delay ADC

Figure 2: Testbench for of 1st order without delay ADC


Figure 3: Results of 1st order without delay ADC

From Figure 3 we can see the output is {−1,1,1}=(−1+1+1)/3=1/3

The avg is 1/3 which is equal to input, so the design is working fine.
Assignment # 1:
Simulate the same circuit as given above for i) u(n) = 0.7V ii) u(n) = 0.2V
and justify if it’s working properly or not.

i. u(n)= 0.7V

Figure 4: Testbench for 0.7 V input

Figure 5: Results for 0.7 V input

From Figure 5 we can see the output is {−1,-1,1,-1,-1,1,-1,-1,1,-1}=({-1+-1+1+-1+-1+1+-1+-


1+1+-1)/10=-4/10=-0.2 V ≠0.7 V
The 1st order ADC is not working for 0.7 V.

i. u(n)= 0.2V

Figure 6: Testbench for 0.2 V input

Figure 7: Results for 0.2 V input


From Figure 7 we can see the output is {−1,1,1,-1,1}=(−1+1+1,-1,1)/5=1/5=0.2 V

The average is 0.2V which is equal to input, so the design is working fine for 0.2V input.

Assignment # 2:
Design second order sigma-delta modulator as given on Lecture#7 and slide#43.
Verify it’s operation for u(n) = 0.3V

Figure 8: Schematic for 2nd order sigma-delta modulator

Figure 9: Testbench for 2nd order sigma-delta modulator


Figure 10: Results for 2nd order sigma-delta modulator

From Figure 10 we can see the output is {1, -1,1}=(1+(-1)+1)/3=1/3

The average is 1/3 which is equal to input, so the design is working fine.

Conclusion:
In this lab we started with the design of 1st order oversampling sigma delta modulator as lab Task. In
Assignment part 1 we simulated the 1st order Sigma-Delta modulator for input=0.2 and 0.7 V and
verified its functionality. In Assignment 2 we designed 2nd order sigma-delta modulator and verified it
functionality for input of 0.33 mV.

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