1

CHAPTER - 1

BIPOLAR JUNCTION TRANSISTOR

Transistor

1. Principle of Operation A transistor is a three terminal semiconductor device

that acts as either electrically controlled switch or amplifier. In transistor, a small voltage
and/or current applied to its control lead controls a larger current flowing through its
other two leads.

2. Use Transistors are used in almost every electronic circuit. For example, you
find transistors in switching circuits, amplifier circuits, oscillator circuits, current source
circuits, voltage-regulator circuits, power-supply circuits, digital logic ICs, and almost
any circuit that uses small control signals to control larger currents.

3. Types The two major families of transistors include bipolar transistors and
field-effect transistors (FETs). The major difference between these two families is that
bipolar transistors are current controlled device, whereas FETs require voltage.

Bipolar Junction Transistor (BJT)

4. Bipolar transistor is a three-terminal device that acts as electrically controlled

switch or as amplifying device. Bipolar transistor is a current operated device and
requires both positive (holes) and negative (electrons) carriers to operate. Bipolar
transistors are incredibly useful devices. Their ability to control current flow by means of
applied control signals makes them essential elements in electrically controlled
switching circuits, current-regulator circuits, voltage-regulator circuits, amplifier circuits,
oscillator circuits, and memory circuits.
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5. Basically, it consists of two back to back or front to front PN junction diodes.

These two junction gives rise to three regions called Emitter, Base and Collector. The
figure below shows a symbol of transistor considered as two back to back connected
diodes.

6. Construction The bipolar transistor consists of three regions of

semiconductor material which gives rise to two PN junctions. The two junctions are
Emitter- Base (E/B) junction and Collector-Base (C/B) junction. Transistor comes in
either NPN or PNP configurations. One type is called a PNP transistor in which two
regions of P type material sandwich a very thin layer of N type material. A second type
is called NPN transistor, in which two regions of N type sandwich a very thin layer of P
type material.

Both BJTs of PNP and NPN transistors have following constructional features as
shown in figure:-

(a) The emitter lies at the left hand section (one end) of the transistor and
most heavily doped region than any of the other regions in a transistor. Its main
function is to supply majority charge (either electrons or holes) to the base
region.

(b) The base lies in the middle section of the transistor. It is very thin (10 -6 m)
as compared to emitter or collector. It is very lightly doped and is sandwiched
between emitter and collector regions.

(c) The collector lays at the right hand section (other end) of the transistor. It
is moderately doped and is the largest of all three transistor regions. Its main
function is to collect majority charge carriers through the base region.
N P N Collector
Emitter P N P Collector Emitter

Base Base

Fig (a) PNP Transistor Fig (b) NPN Transistor

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7. Symbols Symbols of both types of transistors are shown in figure given

below.
E C E C

B B
Symbol of PNP transistor Symbol of NPN transistor

In both transistor’s symbol, arrow head is always at the emitter and it indicates
the direction of conventional current in transistor. For a PNP transistor, arrow head
points from emitter to base meaning that emitter is positive with respect to base (and
also w.r.t. collector). For NPN transistor, it points from base to emitter meaning that
base (and collector as well) is positive with respect to emitter.

8. Transistor Biasing Rule For proper functioning of a transistor as an

amplifier, proper supply must be given to each terminal (E, B and C) of the transistor.
This is called as biasing of transistor. For biasing a Transistor following two rules must
be followed:-

(a) For proper functioning, transistors emitter-base junction must be forward

biased and collector-base junction must be reverse biased.

(b) For a PNP transistor, both collector and base should be negative with
respect to the emitter (Collector should be more negative than base). Similarly,
for NPN transistor both collector and base are positive with respect to the emitter,
collector is more positive than the base.

Working of NPN Transistor

9. A simple model for working of NPN bipolar transistor is given below. (For a PNP
bipolar transistor, all ingredients, polarities, and currents will be reversed).

C E
N P N
IC IE

IB B VBE

VCE
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10. In the above given figures, NPN transistor is forward biased to emitter-base
junction and reverse biased to collector-base junction. Forward bias causes electrons in
the N-type emitter to flow towards the base. These electrons constitute the emitter
current (IE) as they flow through P-type base and combine with holes. The base is lightly
doped and is very thin, therefore only few electrons combined with the holes to
constitute the base current (I B). The reminders cross over to the collector base junction.
The collector region is moderately doped and most of the current carriers injected into
the base jump into the collector region (due to reverse biased) rather than flowing out
from the base lead. Increasing the base voltage increases this jumping effect and hence
increases the emitter-to collector electron flow. In this way, almost entire emitter
electrons flow towards the collector and the conventional current flows from collector to
emitter. Hence the emitter current is the sum of collector and base current.
i.e. IE = IB + IC. A NPN bipolar transistor uses a small input current and positive voltage
at its base (relative to its emitter) to control a much larger collector-to-emitter current.

11. For an NPN transistor, the voltage at the collector VC must be greater than the
voltage at the emitter VE by at least a few tenths of a volt; otherwise, current will not flow
through the collector-emitter junction, no matter what the applied voltage is at the base.
For PNP transistors, the emitter voltage must be greater than the collector voltage by a
similar amount.

12. For an NPN transistor, there is a voltage drop from the base to the emitter of 0.7
V (0.7 V for silicon and 0.3V for germanium transistor). For a PNP transistor, there is a
0.7 V rise from base to emitter. In terms of operation, this means that the base
voltage VB of an NPN transistor must be at least 0.7 V greater than the emitter voltage
VE; otherwise, the transistor will pass an emitter-to-collector current. For a PNP
transistor, VB must be at least 0.7 V less than VE; otherwise, it will not pass a
collector-to emitter current.

Working of PNP Transistor

E C
P N P
IE IC
VBE VCB
B
IB

13. In the above figure, a PNP transistor is forward biased to emitter base junction
which causes the holes in the P-type emitter to flow towards the base and constitutes
the emitter current (IE).These holes cross into the N-type base and combine with the
electrons. As the base is lightly doped and very thin, therefore only a few holes combine
with the electrons. The reminder holes cross into the collector region. Due to reversed
bias collector base junction holes are pulled towards collector terminal and constitute
the collector current (IC). In this way almost the entire emitter current (I E) flows in the
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collector circuit. The current conduction with PNP transistor is by holes. However, in the
external connecting wire the current conduction is still by electron.

Transistor Currents

14. The three primary currents which flow in a properly biased transistor are I E, IB and
(IC). The direction of current flow is shown in the above figure for both type of
transistors. Base current (IB) is approximately 2% of the emitter current (I E), while
remaining 98% of current flows through the collector called collector current(I C)
This means, IE = IB + IC
Or by applying Kirchhoff’s current law:

IE + (-IB) + (-IC) = 0
IE - IB - IC = 0
IE = IB + IC
Leakage Currents in a Transistor

E C
P N P
IE IC

IB B
ICO

15. In above common-base (CB) transistor circuit, the emitter current (I E) (due to
majority carrier) initiated by the forward bias emitter base junction is split into two
parts:-

(a) IB base current, which is (1- α) IE, flows in emitter base circuit.
(b) IC which is αIE becomes collector current in the external circuit.
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(c) It is also seen that due to reverse biased collector base junction, thermally
generated minority charge carriers also flow through the collector base junction,
called leakage current ICO. Therefore total collector current is actually the sum of
two components:

(i) αIE due to majority carriers.

(ii) ICO due to minority carriers.

16. Characteristics Curve of Transistor Figure below shows a typical

characteristic curve for a bipolar transistor. This characteristic curve describes the
effects of the base current IB and the emitter-to-collector voltage VEC have on the
emitter/collector currents IE and IC.

17. Some important terms used to describe a transistor’s operation includes

saturation region, cutoff region, active mode/region, bias, and quiescent point (Q-point).

(a) Saturation region refers to a region of operation where maximum

collector current flows and the transistor acts much like a closed switch from
collector to emitter.

(b) Cutoff region refers to the region of operation near the voltage axis of the
collector characteristics graph, where the transistor acts like an open switch
and only a very small leakage current flows in this mode of operation.

(c) Active region describes transistor operation in the region to the right of
saturation and above cutoff, where a near-linear relationship exists between
terminal currents (IB, IC, IE).

(d) Bias refers to the specific dc terminal voltages and current of the
transistor to set a desired point of active-mode operation, called the quiescent
point, or Q-point.
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Transistor Circuit Configurations

18. Basically there are three types of circuit connections (called configurations) for
operating a transistor.

(a) Common Emitter

(b) Common Base
(c) Common Collector

The term common is used to denote the electrode that is common to the input
and output circuit. The common electrode is generally grounded.

CE (Common Emitter) Configuration

19. In this type of transistor configuration, input signal is applied between the base
and emitter and the output is taken from collector and emitter circuit. Base current (I B) is
the input current and collector current (I C) is the output current. The ratio of the collector
current to base current is called beta (β) or hFE of the transistor.

β = IC / IB
Or IC = β IB or = hFE IB

20. Input Characteristics The graph given below shows the input characteristic
of transistor in common emitter configuration.
IB
75
mA

50

∆ VBE

∆ IB
25

VBE
0.1 0.2 0.3 0.4
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The graph plotted above shows how I B is varies with changes in input voltage
(VBE) when VCE is held constant at a particular value.

For the CE configuration, base current (I B) is the input current, VBE is the input
voltage. The characteristic resembles that of a forward biased diode The
reciprocal of the slope gives the input resistance R in of the transistor.
Rin = ∆ VBE
∆ IB

21. Output Characteristics The graph given below shows the static output/
collector characteristic of transistor in common emitter configuration.
Break down region

IC
Active Region
8 IB = 60μA

6 IB = 40μA

Saturation region IB = 20μA

4
IB =0
2
Cut off region

0 5 10 15 20 25 VCE

22. The graph plotted above I C versus VCE indicates the way in which I C varies with
changes in VCE when IB is held constant. For obtaining this characteristic, firstly, the
value of IB is suitably set and maintained constant and then V CE is increased from zero in
steps, in this procedure I C is noted at each step. Then V CE is reduced to zero and I B
increased to another convenient value and the whole procedure is repeated. Thus, a
group of curves is obtained. It is seen that as V CE increases from zero, I C rapidly
increases to a near saturation level for fixed value of I B. thus a small amount of current
flows even when IB = 0. It is called cut-off.

If VCE is allowed to increase too far, due to this the C/B junction completely
breaks down, and because of this avalanche breakdown, I C increases rapidly and may
cause damage to the transistor. When the value of V CE is very low (ideally zero), the
transistor is said to be saturated and it operates in the saturation region of the
characteristics. Here, IB does not leave any effect on IC.

This characteristic can be used to find β at a specific value of I B and VCE.

β = ∆ VCE
∆ IB
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CB (Common Base) configuration

23. In this type of transistor configuration, emitter current (I E) is the input current and
collector current (IC) is the output current. The input signal is applied between the
emitter and base whereas (α) output is taken out from the collector and base.The ratio
of dc collector current to the emitter current is called alpha (α) or hFB .
α = - IC
IE

Or IC = - αdc. IE
Or α = - IC
IE
24. The negative sign is taken since the emitter current (I E) flows into the transistor
whereas collector current flows out of it. Hence, emitter current is taken as positive and
collector current(IC) is taken as negative.

25. Input Characteristics The input to common base transistor is the emitter
current IE, and it is varied by changing the base emitter voltage VBE. As VBE is varied,
the current flowing through emitter varies. The graph below shows the Input
characteristic of a NPN transistor. Similar characteristics can be obtained for PNP
transistor, having reverse polarities.

26. Output Characteristic The value of collector current is determined by the

emitter current. For a given value of I E and the collector-base voltage, V CB, can be varied
and has very small effect on the value of I C. If the value of VCB is made slightly negative,
the collector will not attract the majority carriers. Thus, I C falls to zero. Figure below is
the output characteristic curve of NPN transistor in common base configuration. Similar
characteristics can be obtained for PNP transistor, having reverse polarities.
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CC (Common Collector) Configuration

27. Common collector amplifier is also called Emitter follower. In this case of
transistor configuration, input signal is applied between base and collector and output
signal is taken out from emitter-collector circuit. Here, base current (I B) is the input
current and emitter current (IE) is the output current. The current gain of the circuit is;

IE = IE . IC = 1 . β
IB IC IB α

= β = _____β____ = (1+ β)
α β / (1+ β)

Or IE = IB + IC = IB+ β IB = (1+ β) IB

Therefore, output current = (1+ β) x input current.

.
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28. Relation between α and β

We know that β = IC / IB and α = IC / IE

So β/ α = IE/IB

Now, IB = IE - IC

So β= IC____ = IC / IE______
IE - IC IE/IE – IC/IE

Or β= α ____
1–α

By cross multiplying above equation, we get

α _= β (1 – α) Or β = α _(1+ β)

Or α _= β .
(1+ β)

29. Comparison between Common Base, Common Emitter and Common Collector
Configurations

Ser Characteristic Common Common Common Collector

No s Base Emitter
(a) Input resistance Very Low Moderate High (20 to 500K )
(30 to 150 (1 to 2 K )
)
(b) Output Very high up Moderate Low (50  to 1 K)
resistance to 500 K  50 K
(c) Current gain = < 1  is high i.e. (1 + ) is High (50
50 to 300. to 500)
(d) Voltage gain About 1500 Very high Less than 1
i.e.1500 or so.
(e) Power gain Up to 30 db 10 to 40 db 10 to 20 db
(f) Phase reversal No phase 180°phase No phase reversal
reversal reversal

DC Load Line

30. The dc load line is a graph that shows all possible values of I C and VCE for a given
transistor amplifier. It is a straight line joining the saturation and cut-off points of the
transistor. The end points of the dc load line represents the value of I C(sat) (saturation
current) and VCE(off) (cut off voltage) of the transistor. In the dc load line given below A
and B points are the cut off and saturation points respectively, whereas C, D, E etc.,
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lying between cut Saturation off and saturation

B
points on the VCC active region of the
transistor are RL E
Active Region
operating points.

IC D

Cut Off
A
0
VCE VCE

31. Drawing a DC Load Line For drawing the dc load line, cut off and
saturation points of the transistor is required. When a transistor is saturated, V CE is
approximately zero, or we can say collector and emitter terminal are shorted. Then total
resistance in the circuit will be the sum of Collector resistance R C & emitter resistance
RE. Thus the saturation current IC(sat) is:

IC (sat) = VCC .
(RC + RE)

When the transistor is cut-off, the collector and emitter region act like an open
circuit, then VCE (off) = VCC

32. Quiescent point It is the point on dc load line which represents the values of
IC and VCE that exist in a transistor circuit when no input signal is applied. It is also
known as working point or dc operating point. The best position for this point is midway
between cut off and saturation points where V CE = ½ VCC.

IC

Q
Transistor as an Amplifier

33. The transistor raises the strength of a week signal and thus acts as an amplifier.
The week signal is applied between emitter-base junction and output is taken from load
resistance connected in the 0 collector circuit. In order to V
achieve
CE amplification, the input
circuit should always remain forward biased.
To do so, proper biasing voltages should be given to keep the input circuit always
forward biased, regardless of the polarity of the signal.
IC v
RL O/P
v

I/P VCC 0
0 IE
VBB
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34. A Common emitter amplifier is shown above has low input resistance, hence, a
small change in input signal voltage causes an appreciable change in emitter current.
This causes almost the same change in collector current (I C = β IB). Hence, large voltage
develops across load resistor connected across collector circuit. Thus, a week signal
applied in the input circuit appears in the amplified form in the collector circuit.

Example: A CE connected transistor has β = 100 and I B = 50μA. Compute the

values of α, IC and IE.

Solution Given values are β = 100 and IB = 50 μA

By formula IC = β IB
IC = 100 x 50
IC = 5000 μA
IC = 5 mA

Now IE = IB + IC
IE = 50 + 5000
IE = 5050 μA
or IE = 5.5 mA

Now α = __β__
1+β
α = 100 / (1+100)
α = 100/101
α = 0.99

Transistor as a Switch

35. Working of transistor as a switch is explained below as a lamp ON-OFF switch

for simplicity.

36. If the switch is open as in figure (a), the base wire of the transistor will be left
“floating” (not connected to anything) and there will be no current through it. In this
state, the transistor is said to be cutoff. Without a connection to the base wire of the
transistor, base current will be zero, and the transistor cannot turn ON, resulting that
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lamp is off. If the switch is closed as in Figure (b), however, electrons will be able to flow
from the emitter through to the base of the transistor, through the switch and up to the
left side of the lamp, back to the positive side of the battery. This base current will
enable a much larger flow of electrons from the emitter through to the collector, thus
lighting up the lamp. In this state of maximum circuit current, the transistor is said to be
saturated. Of course, it may seem pointless to use a transistor in this capacity to control
the lamp.

Thermal Runaway

37. Self destruction of unstabilized transistor is known as thermal runaway. When

the collector base voltage is too large, the collector base diode breaks down, causing a
large undesired collector current to flow. In this condition minority/ leakage current I CO
also increases. The leakage current is extremely temperature dependent. It almost
doubles for every 60C rise in temperature in Ge and for every 10 0C rise in Si. Even in
slight increase in ICO will increases IC considerably. As IC increases, collector power
dissipation increases which raise the temperature and so I CO. If this succession of
increases is allowed to continue, soon I C will increase beyond the safe operating value
thereby damaging the transistor itself. This condition is known as thermal runaway.
Hence, some form of stabilization is necessary to prevent thermal runaway.

Stability Factor

38. The stability factor is defined as the ratio of increment value of I C and ICO keeping
VBE, and β constant. It is denoted by S.

S = d IC
d ICO

At active condition IC = β IB + (1+ β) ICO

Differentiate the above equation with respect to I C, keeping β constant.

d (IC) = β d IB + (1+ β) d ICO

d IC d IC d IC
1 = β d IB + (1+ β)
d IC S

1- β d (IB) = (1+ β)
d IC S

Therefore S= (1+ β) ____

1- β (dIB/ dIC)
Types of Transistor Biasing

39. Some of the methods used for providing bias for a transistor are as follows:-
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(a) Base bias or fixed current bias.

(b) Base bias with collector feed back.
(c) Base bias with emitter feed back.
(d) Voltage divider bias/self bias.

40. Base Bias or Fixed Current Bias It is not a very satisfactory method
because bias voltages and current do not remain constant during transistor operation.
+VCC

IB IC

RL
RB

IE

In a fixed bias circuit, a resistor R B is connected, as shown in the figure. Circuit is

simple only one resistor is used. Base current is made constant since I C = β IB and,

IB = VCC (here VBE is neglected)

RB
In this bias method, β varies with temperature, hence operating point will drift.
Hence It is thermally unstable. Stability factor S = 1 + β is very large.

41. Base Bias with Emitter Feedback This circuit achieves good stability of dc
operating point against changes in β with the help of emitter resistor which causes
degeneration to take place.
+VCC

IB IC

RL
RB

VCE
VBE
VC
IE

RE
VE
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(a) At saturation, VCE is essentially zero, hence VCC is distributed over RL and
RE.
 IC(sat) = ___VCC____
RE + RL

(b) Collector current, IC = ___VCC____

RE + RB/β

(c) Collector to ground voltage, VB = VCC - ICRL

(d) Emitter to ground voltage, VE = IERE ≈ ICRE

(e) β sensitivity of the circuit is, K β = _____1_____

1 + β R E / RB

42. Base Bias with Collector Feedback

+VCC

IC +IB

RC
RB
IB

IC

IB

VBE
IE
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(a) It is also known as collector to base bias or collector feedback bias. In this
method, feedback voltage is given from collector to base through resistance R B
as shown in figure. It provides better bias stability.

(b) IC(sat) = VCC / RL since VCE = 0

(c) VC = VCC – (IB + IC) RL; = VCC – IC RL

Also, VC = IB RB + VBE

Equating the two expressions for VC, we have

IB RB + VBE + VCC – IC RL

Since, IB = IC / β, we get

IC RB + VBE = VCC – IC RL
β

Therefore IC = VCC – VBE = VCC

RL + RB / β RL + RB / β

This is also the approximate value of IE (again, we could take the help of β-rule).

K β = _____1_______ = 1 - _IC____
1 + β R L / RB IC (sat)

(d) Advantages

(i) It is a simple method as it requires only one resistor R B.

(ii) This cct provides some stabilization of the operating point.

(e) Disadvantages

(i) This cct does not provide good stabilization; it is because operating
point does change to lesser extent, due to temp variation and other
effects.

(ii) This cct provides a negative feedback, which reduces the gain of
the amplifier.

43. Voltage Divider Bias / Self Bias This is the most widely used method of
providing biasing and stabilization to a transistor. It is also called universal bias circuit or
base bias with one supply.
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+VCC

I1 RC

R1
IC

VCE
IB

I2
VBE IE
VC
RE
R2
VE

The emitter resistance RE provides stabilization. The name voltage divider is derived
from the fact that resistors R1 and R2 form a potential divider across VCC. The Voltage
drop across R2 forward biases the base- emitter junction whereas V CC supply reverse
biases the collector.
As per voltage divider theorem,

V2 = (Vcc) x R2
R1+R2
As seen, VE = V2 – VBE

 IE = VE = V2 – VBE = V2
RE RE RE

Also, VC = VCC – ICRL

VCE = VC – VE = VCC – ICRL – IERE

= VCC – IC(RL + RE)  IC = IE

Also before, IC(sat) = VCC_

RL + RE

Kβ = 1_____
1 + β RE/(R1║R2)

It is seen from above calculations that value of β is not used anywhere. The base
voltage is only set by VCC and R1 and R2. The dc bias circuit is independent of the
transistor β. That is why this bias circuit is very popular.
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CHAPTER-2
MULTISTAGE AMPLIFIER

Coupling and its Necessity

1. Linking of one circuit to other is called coupling. Electronic appliances/ Eqpts are
made of Number of small electronic ccts. Hence, it is required to couple one cct with
other to transfer the max power/ signal to next cct. In coupling, matching of output
characteristics of one stage to the input of next stage is carried out to transfer the signal
efficiently. Thus, some form of coupling network is required to couple two stages.

All amplifiers need some coupling network. Even a single stage amplifier has to
be coupled to the input and output devices. In the case of multistage amplifier system,
there will be inter stage coupling.

2. Types of Coupling Coupling schemes are mainly of three types:-

(a) RC coupling
(b) Transformer coupling
(c) Direct coupling

3. Resistance Capacitance (RC) Coupling It is also known as capacitive

coupling. The amplifier using RC network is known as RC coupled amplifier and is
shown in the figure below.

RC1 RB

C
Vo
Vi

Here RC coupling network consists of resistor R C1 and capacitor C. The

connecting link between the two stages is capacitor ‘C’. The function of RC
coupling network is:-

(a) To pass AC signal from one stage to next.

(b) To block the passage of DC voltage from one stage to the next.
 20

4. Transformer Coupling Amplifiers coupled using Transformer coupling is

shown as below.

Vo

Vi

Since the secondary of the coupling transformers conveys the AC component of

the signal directly to the base of the second stage, there is no need for a coupling
capacitor. Moreover, the secondary winding also provides a base return path; hence
there is no need for a base resistance. Amplifiers using this coupling are called
transformer coupled amplifier.

5. Direct Coupling Direct coupled amplifiers is shown in the figure below.

Vo

Vi

This coupling is used where load is required to connect directly in series with the
output terminal of the active circuit element. The examples of such load devices are
head phones, loud speakers, DC meters, DC relays and input cct of a transistor etc.
Direct coupling is permissible only when:

(a) DC component of the output does not disturb the normal operation of the
load device.

(b) Device resistance is so low that it does not appreciably reduce the voltage
at the electrodes.
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6. RC Coupled two Stage Amplifier

Vcc

R2 R3 R4
R1
Vo
C1 C3
C2
Vi R5

Q1 Q2

The above figure shows a two stage RC coupled amplifier which consist of two
single stage common emitter amplifiers. The resistors R 2 and capacitor C2 form the
coupling network. R2 is collector load of Q1 and R4 is that of Q2. Capacitor C1 couples the
input signal whereas C3 couples the output signal. R 1 and R3 provide dc bias. R5 is the
load across Q2.

7. Operation The I/P signal (Vi) is amplified by Q1. Its phase is reversed due to
CE configuration. The O/P of the first stage is coupled to I/P of the second stage at R3
by coupling capacitor C2. This capacitor also blocks passage of DC voltages and
currents. The signal at the base of Q2 is amplified and its phase is further reversed. The
AC O/P of Q2 appears across R4 which is coupled by C3 to load resistor R5. The
output signal V0 is the twice amplified replica of the input signal Vi. It is in phase with Vi
because it has been reversed twice.

8. Frequency Versus Gain Characteristics of RC Coupling

Gain

Flat Response
High frequency roll off
Low frequency roll off

f1 f f2
 22

As seen from the above fig, amplifier gain falls off at very low as well as at very
high frequencies. At low frequency gain falls due to capacitive reactance of the coupling
capacitor between the two stages. At high frequency roll off is due to output capacitance
of the first stage, input capacitance of the second stage and stray capacitance.

9. Advantages of RC Coupling

(a) It requires no bulky components and no adjustments. Hence it is small,

light and inexpensive.

(b) Its overall amplification is higher than that of the other couplings.

(c) It has minimum possible non linear distortion because it does not use coils
or transformers which might pick up undesirable signals.

(d) It has very flat frequency response over a wide range (few Hz to MHz).

10. Disadvantages of RC Coupling The only disadvantage of RC coupling is that

due to large drop across collector load resistors, the collectors work at relatively small
voltages unless higher supply voltage is used to overcome this large drop.

Transformer Coupled two Stage Amplifier

T2
T1 R4
R7

R1 Q2

C1
Vi
Q1
R2

R3 C2 R5 C3 R6 C4
 23

11. The circuit shown above is a cascaded transformer coupled amplifier. T1 is the
coupling transformer where as T2 is the out put transformer. C1 is the input coupling
capacitor, where as C2, C3 & C4 are bypass capacitors. Resistors R1 and R2 as well
as R4 & R5 from voltage divider circuits, where as R3 and R6 are emitter stabilizing
resistors.

12. Operation When input signal is coupled through C1 to the base of Q1, it
appears in an amplified form in the primary of T1. From primary it is passed on to the
secondary by magnetic induction. T1 provides DC isolation between the input and
output circuits. The secondary of T1 applies the signal to the base of Q2 which appear
in an amplified form in the primary of T2. From primary it is passed on to the secondary
by magnetic induction and finally appears across the matched load R7.

13. Frequency versus Gain Characteristics of Transformer Coupling The

characteristics of a coupling transformer are:-
(a) It introduces inductances in both the input and output circuits.
(b) Leakage inductance exists between the primary and secondary winding.
(c) Both windings introduce shunting capacitance especially at high
frequencies.

Resonant Rise

Voltage
Gain

0 f fo
It is seen in the above response curve, there is decrease in gain at low
frequencies and also at high frequencies except for the resonant rise in gain at resonant
frequency of the tuned circuit formed by inductance and winding capacitance in the
circuit. At low frequencies, primary reactance is small, hence the gain is less. At high
frequencies, the distributed capacitance existing between turns of the winding acts as
bypass capacitor and so reduces the output voltage and hence the gain. Freq response
is not same for wide range. However, transformer coupled amplifiers have flat frequency
response curve and excellent fidelity over the entire audio frequency range.
 24

14. Advantages of Transformer Coupling

(a) The operation of a transformer coupled system is basically more efficient

because of low DC resistance of the primary connected in the collector circuit.
(b) It provides higher voltage gain.
(c) It provides impedance matching between stages which is desirable for
maximum power transfer.
(d) This coupling is effective when the final amplifier o/p is fed to a low
impedance load.

15. Disadvantages

(a) The coupling transformer is costly and bulky particularly when operated at
audio frequencies because of heavy iron core.
(b) At radio frequencies, the inductance and winding capacitance present lot
of problems.
(c) It has poor frequency response because the transformer is frequency
sensitive.
(d) It tends to introduce ‘hum’ in the output.

Direct Coupled two Stage Amplifier

VCC

R2
R1
Vo
Vi
1 2

Q1
Q2

16. These amplifiers operate without the use of frequency sensitive components
capacitors, inductors and transformers etc. These are specially suited for amplifying;

(a) AC signals with frequencies as low as a fraction of a hertz.

(b) Changes in DC voltages.

 25

17. Operation In above circuit two amplifiers having similar transistor, each
connected in the CE configuration mode. Coupling of both stages employs direct
coupling scheme. Collector of Q1 is connected directly to the base of Q 2 and load
resistor R2 is connected directly to the collector Q 2. The collector R1 establishes the
forward bias of Q1 and also indirectly that of Q 2. Any signal current at the base of Q 1 is
amplified 1 times and appears at the collector which becomes base signal of Q 2. Signal
current gain of the direct coupled amplifier is:

Ai = 1 x 2 = 2 (if transistors are identical)

Gain

0 f f2
18. Advantages

(a) The circuit arrangement is very simple since it uses minimum number of
components.

(b) It is inexpensive.

(c) It has the ability to amplify direct current and low frequency signals.

(d) It has no coupling or bypass capacitor to cause a drop in gain at low

frequencies as shown in the fig above. The frequency response curve is flat up to
upper cut off frequency determined by stray wiring capacitance and internal
transistor capacitance.

19. Disadvantages

(a) It cannot amplify high frequency signals.

(b) It has poor temperature stability.
20. Applications

(a) Regulator circuits of electronic power supplies.

(b) Pulse amplifiers.
(c) Differential amplifiers.
(d) Computer Circuitry.
(e) Electronic Instruments.
 26

CHAPTER-3

FIELD EFFECT TRANSISTOR

Field Effect Transistor (FET)

1. Field Effect Transistor (FET) is a three-terminal, unipolar, solid-state device in

which current is controlled by an electric field as in vacuum tubes. Broadly there are two
types of FETs:-

(a) JFET (Junction field effect transistor)

(b) MOSFET (Metal-Oxide Semiconductor FET) or IGFET (Insulated Gate

FET)

2. Types of FET

FET

JFET MOSFET/IGFET

N-Channel FET P-Channel FET DE-MOSFET E- only MOSFET

N-Channel FET P-Channel FET

N-Channel FET P-Channel FET

JFET (Junction FET)

3. Principle Junction field-effect transistors (JFETs) are also three-lead
semiconductor devices like bipolar transistors. JFETs are exclusively voltage-controlled
—they do not require a biasing current. Another unique trait of a JFET is that it is
normally ON when there is no voltage difference between its gate and source leads.
However, if a voltage difference forms between these leads, the JFET becomes more
resistive to current flow (less current will flow through the drain-source leads). For this
reason, JFETs are referred to as depletion devices, unlike bipolar transistors, which are
enhancement devices (bipolar transistors become less resistive when a current/voltage
is applied to their base leads).
 27

4. Utility JFET’s are used as electrically controlled switches, amplifier controls, and
voltage-controlled resistors.

Types of JFET packages

4. JFETs are available in either n-channel or p-channel configurations. With an N-

channel JFET, a negative voltage applied to its gate (relative to its source lead) reduces
current flow from its drain to source lead. With a P-channel JFET, a positive voltage
applied to its gate reduces current flow from its source to drain lead. The symbols for
both types of JFETs are shown below.

N- Channel FET P- Channel FET

5. Construction of JFET A FET has P type or N type silicon bar in which two
PN Junction are formed at sides by diffusion of other type of semiconductor as shown in
diagram. Having the bar of N type is called N channel FET and of P type is called P
channel FET. Two junction forming diodes on sides are connected internally and have
common terminal called gate. The other two terminals on either side of the channel are
called source and drain. In N Channel FET, majority carriers are electrons whereas in P
Channel, majority carriers are holes.
 28

D D

G G
P P N N

N P

S S

N- Channel FET P- Channel FET

6. The Important elements in FET can be summarised as under:-

(a) Source. It is the terminal through which majority carriers enter the
silicon bar. Since carriers come from it, it is called the source.
(b) Drain. It is the terminal through which majority carriers leave the silicon
bar. The drain to source voltage VDS drives the drain current ID.
(c) Gate. These are two internally connected heavily doped regions which
form two PN junctions. The gate source voltage V GS reverse biases the gate.
(d) Channel. It is the space between two gates through which majority
carriers pass from source to drain when VDS is applied.
7. Operation of N Channel FET

+ VDS + VDS
VGS=0 VGS= - V

Case I: When Voltage VDS is applied and VGS= 0: When small value
VDS is applied and VGS = 0, the two PN Junctions are reverse biased only by V DS,
which forms thin
CASE- CASE- IIof these layers
I depletion layers at the junctions. The width
 29

determines the width of the channel. Hence, the majority carriers (electrons) will
flow from source to drain through the channel between the depletion layers,
whereas conventional drain current I D flows through the channel from drain to
source. If VDS is increased further, ID increases proportionally as per Ohm’s law.
This ohmic relationship between V DS and ID continues till VDS reaches certain
critical value called Pinch off voltage V PO when drain current becomes constant at
its maximum value called I DSS. The SS in IDSS indicates that the gate is shorted to
source to make sure that VGS=0.

Case II: When reverse bias VGS is applied at Gate: When small value
of VGS is applied, depletion layer increases at both PN junctions. Hence the width
of conducting channel decreases. Drain to source current I D is decreases. If VGS is
decreased, the width of the depletion layer decreases which increase the width of
the conducting channel and so Drain to Source current I D. If VGS is increased
further, a stage comes when the two depletion regions touch each other, the
channel is said to be cut off. The value of the V GS which cut off the drain current
is called VGS(OFF). Hence, it is noticed that the drain current I D is controlled by the
gate voltage, VGS in JFET. Therefore, JFET is also called voltage controlled
device.

8. A P-Channel JFET operates exactly in the same manner as a N- Channel JFET

except that current carriers are holes and polarities of both V DD and VGS are reversed.

JFET Drain Characteristics of JFET with VGS= 0

ID

Break down Region

Ohmic VGS=0 C
Region B
A
Pinch off Region

O
VPO VDSO=VBO VDS

9. The drain characteristics curve of FET is drawn I D versus VDS for the value of V GS
is 0 V. The output characteristics curve of FET can be divided into four following
regions:-
 30

(a) Ohmic Region: This part of the characteristics is linear indicating that
for low value of VDS, current varies directly with voltage following Ohm’s law. It
means JFET behaves like an ordinary resistor till point A (called knee) is
reached.

(b) Curve AB: In this region. ID increases non linearly till point B (called
Pinch off point). This progressive fall is due to increase in depletion region where
the two regions are closest without touching each other.

(c) Pinch Off Region: It is also called saturation region. Here FET operates
as constant current device. In this region I D is relatively independent of V DS. It is
the normal operating region of the JFET when used as an amplifier.
(d) Break Down Region: If the value of V DS is increased beyond the
pinch off region i.e., point C, JFET enters the break down region. The value of
VDS at which break down occurs is called break down voltage V BO. Beyond point
C, ID increases to excessive value due to avalanche break down.

JFET Characteristics with External Bias

10. The figure below shows a family of I D versus VDS curves for different values of VGS.
It is seen that as the negative gate bias voltage is increased:
(a) Pinch off voltage VP is reached at a lower value of VDS than when VGS= 0.
(b) Value of VDS for break down is decreased.

ID

VGS=0V

IDSS -1V

-2V

-3V

-4V

VDS
VBO= VDSO
VP
 31

Small Signal JFET Parameters

11. The various parameters of a JFET can be obtained from its two characteristics.
The main parameters of JFET when connected in common source mode are as under:-

(a) AC Drain Resistance (rd): It is also called dynamic drain resistance. It is

the ac resistance between drain and source terminals when JFET is operating in
the pinch off region. It is given by;

rd = Change in VDS = VDS at constant VGS (measured in ohms)

Change in ID  ID

(b) Transconductance (gm): It is simply the slope of transfer characteristic.

gm = Change in ID = ID at constant VDS (measured in siemens)

Change in VGS VGS
(c) Amplification factor (μ): It is given by;

μ = Change in VDS = VDS at constant ID

Change in VGS VGS

Relation between AC drain resistance, Transconductance and Amplification

factor is, μ = gm x rd

(d) DC Drain Resistance (RDS): It is also called the static or ohmic

resistance of the channel. It is given by;

RDS = VDS
ID

FET as an Amplifier
VDD

v
0

0
 32

12. Above figure shows a simple FET amplifier circuit. The weak signal is applied
between gate and source and amplified output signal is obtained from the drain source
circuit. In FET, gate is always reverse biased. A small change in the reverse bias on the
gate produces large change in drain current. This fact makes FET capable of raising the
strength of a week signal. During the positive half cycle of signal, the reverse bias on
the gate decreases. This increases the channel width and hence the drain current.
During the negative half cycle of signal, the reverse voltage on the gate increases. This
decreases the channel width and hence the drain current. The result is that small
change in voltage at the gate produces a large change in drain current. These large
variations in drain current produce large output across the load R L. In this way FET acts
as an amplifier.

Advantages of FET over Bipolar Transistors

13. In reality, FETs are definitely more popular in circuit design today than bipolar
transistors.

The advantages are :-

(a) FET draw essentially zero input-output current at their control leads.

(b) They are easier to manufacture.

(c) Cheaper to make (require less silicon).

(d) Can be made extremely small, making them useful elements in integrated
circuits.

Drawback of FET are :-

(a) One drawback with FETs is in amplifier circuits, where their

transconductance is much lower than the bipolar transistors at the same current.
This means that the voltage gain will not be as large.

(b) For simple amplifier circuits, FETs are seldom used unless extremely high
input impedances and low input currents are required.
 33

CHAPTER-4

MOSFET’s

DE MOSFET

1. This MOSFET is so called because it can be operated in both depletion mode

and enhancement mode by changing the polarity of gate voltage V GS. The DE MOSFET
(Depletion- enhancement MOSFET) can be N channel or P channel. When negative
gate to source voltage is applied, the N Channel DE MOSFET operates in depletion
mode. However, with the positive gate voltage, it operates in the enhancement mode.
Since a channel exist between drain and source, I D flows even when VGS=0. The
symbols of N channel and P channel DE MOSFET are shown below.

Construction

N CHANNEL P CHANNEL
 34

2. Like JFET, it has source, gate and drain. However as shown in figure, its gate is
insulated from the conducting channel by an ultra thin metal oxide insulating film
(usually of silicon dioxide SiO2). Because of this insulating property, MOSFET is also
known as insulated gate FET. Like FET, in MOSFET gate voltage also controls the
drain current. But in MOSFET, both positive and negative voltages to the gate can
control the drain current because it is insulated from the channel. Moreover, the gate,
insulator and channel form a parallel plate capacitor.

3. Working of DE MOSFET
(a) Depletion Mode of N Channel DE MOSFET When VGS= 0, electrons
can flow freely from source to drain through the conducting channel. When gate
is negative, it depletes the channel of its electrons by inducing positive charge in
it. Greater the negative voltage on the gate, greater is the lesser the number of
electrons in the channel and consequently lesser the conductivity of the channel.
Hence, with negative gate voltage, DEMOSFET behaves like a JFET. For
obvious reasons, negative gate operation of a DE MOSFET is called its depletion
mode operation.

ID
D
N
G
P
VDD

VGS N
S
SiO2
+ - ++
Metal gate
+ - ++
+ -
+ -
Depletion Mode of N Chl DE MOSFET

(b) Enhancement Mode of N Channel DE MOSFET When positive gate

voltage is applied to the gate, the input gate capacitor is able to create free
electrons in the channel which increases drain current. These electrons are
added to the existing electrons in channel. This increased number of electrons
enhances the conductivity of the channel. As positive gate voltage increases, the
number of induced electron is increases. Hence, the conductivity of the channel
is increases. That is why, positive gate operation of DE MOSFET is known as its
enhancement mode of operation.
 35

ID
D
N
G

VDD
N
VGS

SiO2

- + -
Metal - + -
gate - + -
- + -

Enhancement Mode of N Chl DE MOSFET

Enhancement-only N Channel MOSFET

4. The Enhancement-only MOSFET can be NMOS or PMOS. In Enhancement-only

MOSFET channel does not exist between drain and the source. On one side of
substrate gate is formed over insulating Silicon dioxide. It works with large value of
gate-source voltage VGS. NMOS operates only with positive gate voltage where as
PMOS operates on negative gate voltage.

Enhancement-only N Channel MOSFET

5. This N channel MOSFET (also called NMOS) finds wide application in digital
circuitry. As shown in the figure (a) in the NMOS, the P-type substrate extends all the
way to the metal-oxide layer. Structurally, there exists no channel between the source
and the drain. Hence, an NMOS can never operate with a negative gate voltage
because it will induce positive charge in the space between the source and drain and
source which will not allow the passage of electrons between the two (as shown in
figure (b). Therefore, it operates with positive gate voltage only.
 36

ID=0
D D
N N
+
G- + RL
G -
P + P
-
- +
RG - +
N VDD
N
VGS
S S

Figure (a)
Figure (b)

6. The normal biasing polarities of this E-only MOSFET (both N-channel and P
channel) are shown in figure below. With V GS = 0, ID is non-existent even when some
positive VDD is applied. It is found that for getting significant amount of drain current, we
have to apply sufficiently high positive gate voltage. This voltage is found to produce a
thin layer of free electrons very close to the metal-oxide film which provides channel for
electrons (and hence acts like N-type material) is called N-type inversion layer or virtual
N-channel.
ID ID
D D
N P
+ -
- RL + RL
G + G + -
- P N
- + + -
- + + -
RG RG
- VDD VDD
P
VGG - N VGG
- S S

Figure (a) Figure (b)

A Enhancement - only N Ch MOSFET Enhancement - only P Ch MOSFET
 37

Advantages of FET

7. MOS FET has many advantages over BJT. Some of the main advantages are as
follows:-

(a) High input impedance.

(b) High frequency response.
(c) Low noise.
(d) High gain.
(e) Good thermal stability.
(f) Long life.

8. The only disadvantage is small gain-bandwidth product and greater susceptibility

to damage in handling them.

Applications

9. FET can be used in almost every applications in which bipolar transistor can be
used such as amplifier, switch etc. However, they have certain applications which are
exclusive to them:-

(a) As input amplifiers in measuring equipments because their high rin

reduces loading effect to the minimum.

(b) In logic circuits, where it is kept OFF when there is zero input and it is
turned ON with very small power input.

(c) For mixer operation of FM and TV receivers.

(d) As voltage variable register in OP amplifiers.

(e) In large scale integration of ICs and computer memories because of very
small size.
 38

CHAPTER- 5

UNIJUNCTION TRANSISTOR

Unijunction Transistor (UJT)

1. It is basically a three terminal silicon diode having one PN Junction. It differs from
an ordinary diode in that it has three leads and it differs from FET in that it has no ability
to amplify. However, it has the ability to control large ac power with a small signal. It
also exhibits a negative resistance characteristic which makes it useful as an oscillator.
B2

Emitter

B1
2. Construction UJT consists of lightly doped N type silicon bar with a
heavily doped P type material alloyed to its one side (closer to B2) for producing single
P-N junction. It has three terminals, one emitter, ‘E’ and two base terminals, B1 and B2.
Bi and B2 at the top and bottom of the silicon bar. Emitter terminal is taken out from P
type diffused material. The emitter leg is drawn in the symbol at an angle to the vertical
and arrow points in the direction of conventional current when UJT is in the conducting
state.

UJT Parameters

3. Inter base Resistance (RBB) It is the resistance between B 2 and B1 i.e., it is

the total resistance of the silicon bar with emitter terminal open.

From the equivalent circuit of UJT, RBB = RB2+RB1

It should also be noted that RB1>RB2. Usually, RB1= 60% of RBB.

 39

4. Intrinsic Stand-off Ratio It is seen that from figure (a) below, when a supply
voltage of 30V is applied across B 2 and B1, there is a progressive fall of voltage over R BB
provided emitter is open. It is obvious from figure (b) that emitter acts as a voltage
divider tap on fixed resistance RBB.

B2
B2
I2
30V
E E RB2
P 20V VBB
A
N
10V RB1
30V ηVBB
0V
B1 I1
B1

Figure (a) Figure (b)

With emitter open, I1 = I2. The inter-base current is given by Ohm’s Law.

I = I2= VBB/RBB

For example, if VBB = 30V and RBB = 20K, I1 = I2 = 2 mA.

It may be noted that part of V BB is dropped over RB2 and part on RB1. Let us call
the voltage, VA = VBB __RB1_
RB1+RB2
The voltage division factor called intrinsic stand-off ratio is given by a special
symbol (η).
η = __RB1_  VA = η VBB
RB1+RB2
The intrinsic stand-off ratio is the property of the UJT and is always less than
unity (0.5 to 0.85). If VBB = 30 V and η = 0.6, then potential of point A with respect
to point B1 = 0.6 x 30 = 18 V. The remaining 12 V drop across R B2.

Example: A given silicon UJT has an inter-base resistance of 10 K. It has R B1 = 6K

with IE = 0. Find,

(a) UJT current if VBB = 20 V and VE is less than VP,

(b) η and VA, (c) Peak point voltage, VP.

Solution (a) Since VE < VP, IE = 0 because P-N junction is reverse biased.
 40

 I1 = I2 = VBB = 20 = 2mA
RBB 10 K

(b) η = RB1 = 6 = 0.6

RBB 10

VA = ηVBB = 0.6 x 20 = 12 V

(c) VP = ηVBB + VB = 12 + 0.7 = 12.7 V

5. Working of UJT Operation of UJT is explained for two cases as given below:-

(a) Case- I: When emitter is open

(i) When voltage VBB is applied between B 1 and B2 with emitter open,
Voltage gradient is established along the Bar.
(ii) The Voltage V1 between emitter and B1 establishes a reverse bias
on the PN Junction and the emitter current is cutoff.

(iii) A leakage current flows from B1 to B2 to emitter due to minority

carrier.

B2

E V2
P

V1
N VBB

B1

(b) Case-II: When positive voltage is applied at the emitter

(i) PN junction remains reverse bias until the emitter input voltage
does not exceeds V1 (also called triggering voltage V trig). When emitter
voltage exceeds V1, the PN Junction becomes forward bias.

(ii) Holes are injected from P type material to N type bar.

(iii) These holes are repelled by positive B 2 terminal and they are
attracted by B1 terminal of the bar.
 41

(iv) These accumulations of holes in the emitter to B 1 region decreases

resistance of the bar, hence IE increases.

(v) The device is now in ON state. I E can be controlled by emitter

power supply only.

B2

IE E V2
P

V1
N VBB

B1

Characteristics of UJT

6. The figure above shows a typical V E versus IE graph of an UJT and its equivalent
circuit. If B1 is grounded, a voltage applied to emitter will have no effect until it exceeds
a critical voltage, known as the triggering voltage. The triggering voltage is given by the
following expression.

Vtrig = VB2 __RB1_ = η VB2

RB1+RB2
Once the triggering voltage reaches this value, the PN junction becomes forward
biased and UJT conducts. The current flows from emitter into the channel.
 42

UJT as Relaxation Oscillator

7. In UJT based relaxation oscillator circuit, the discharging of a capacitor through

UJT can develop a saw tooth pulse output. V BB voltage is applied between B 1 and B2. R1
variable resistance is connected with emitter. R 2 resistance is connected to B 2.
Capacitor is located between E and B1 terminal.

VBB

VC
R1 R2
B2
Charging of C
E

O/P Discharging of C
B1
C t
Sawtooth wave Output

8. Working When voltage VBB is switched on, the capacitor C is charged

through resistor R1. When the capacitor is charges to its peak voltage V P, UJT fires and
rapidly discharges through B 1. At this instant of time the UJT offers low resistance and
the capacitor is discharged between emitter and base B 1. When the capacitor
discharged, the UJT is switched off. After discharging capacitor C starts to charge
again. This cycle is repeated continuously generating Saw tooth wave form. The
frequency of the saw tooth wave O/P can be varied by changing the value of capacitor.
Output can be taken from any terminal of the UJT.
 43

CHAPTER- 6

SILICON CONTROLLED RECTIFIER

1. It is one of the prominent members of thyrister family. It is a four layer or PNPN

device. Basically it is a rectifier with control element. In fact, it consists of three diodes
connected back to back with a gate connection. It is widely used as a switching device
in power control applications. It can control load by switching current OFF and ON with
high speed. A

C
Symbol
2. Construction of SCR As shown in a figure, it is a three junction three
terminal four layer device. The layers are of P type and N type silicon alternatively. The
layers are marked as J1, J2 and J3 whereas the three terminals are anode (A), cathode
(C) and gate (G). The gate is connected to the inner P type layer near the cathode as
shown in figure.
+ Anode
ANODE
P
J1
N
Gate J2
P
J3
N

- CATHODE

3. Biasing of SCR With the polarity of supply voltage (V) as shown in figure (a),
the junctions, J1 and J3 become forward-biased whereas J 2 is reverse-biased. Hence, no
current (except leakage current) can flow through the SCR. In Figure (b) polarity of V
has been reversed. It is seen that, now, junctions J 1 and J3 become reverse-biased and
only J2 is forward-biased. Again, there is no flow of current though the SCR

A A
P P AN
J1 J1
N V NOD V
J2 G E J2
G P P
J3 J3
N N
C C

Figure (a) Figure (b)

 44

4. Operation In figure (a) current flow is blocked due to reverse-biased junction

J2. However, when anode voltage is increased, a certain critical value called forward
break over voltage VBO is reached when J2 breaks down and SCR switches suddenly to
highly conducting state. Under this condition, SCR offers very little forward resistance
(0.01Ω - 1.0 Ω) so that voltage across it drops to a low value (about 1V) and current is
limited only by the power supply and the load resistance. Current keeps flowing
indefinitely until the circuit is opened.

5. With supply connections as in figure (b) the current through the SCR is blocked
by the two reverse-biased junctions, J 1 and J3. When V is increased, a stage comes
when Zener breakdown occurs which may destroy the SCR. Hence it is seen that SCR
is a unidirectional device.

Equivalent Circuit of SCR (Two Transistor Analogy)

6. The basic operation of SCR can be described by using two transistor analogies.
For this purpose, SCR is split into two interconnected transistors as shown in fig.
Transistor Q1 is a PNP transistor and Q2 is an NPN device interconnected together. It is
also noted that the collector current of Q1 is also the base current of Q2, and base
current of Q1 is also the collector current of Q2.

+ A

IE1 Q1

IB1 IC2
G
IC1

IB2 Q2 IE2

7. Operation When anode (A) and cathode (C) terminals are given positive _ C and
negative supply is such that the junction J 2 starts breaking down. Then the collector
current IC1 of Q1 transistor increases. Hence, I B2 also increases. When I B2 increases,
collector current IC2 of Q2 also increases, hence, I B1 also increases. Consequently both
Ic1 and IE1 increase. As seen, a regenerative action takes place whereby an initial
increase in current produces further increase in the same current. Soon maximum
current is reached. The two transistors are turned ON. And the voltage across the two
transistors falls to a very low value permitting maximum current to flow between anode
A and cathode C.

V / I characteristics of SCR

8. The Volt-Amp characteristic of SCR is explained under two conditions when:

(a) Gate is open.

(b) Gate is triggered positive.
 45

+I I
ON STATE

IH OFF
Gate open

-V 0 V
IG1 IG0
IG2

-I VH VBO

(a) Gate open (b) When Gate is triggered positive

(a) When Gate is open For small increase in anode voltage below V BO
(forward break over voltage), Junction J1 and J3 are forward biased but J2 is
reverse biased. Only leakage current will flow and SCR remains at OFF state.
If anode voltage increases to forward break over voltage, junction J2 breaks
down. SCR now switches to high conducting state.

(b) When Gate is triggered positive The junction J2 becomes forward

biased. VBO is reduced and SCR turns to ON state. SCR will remain ON even
when gate current is removed. SCR will remain ON till anode voltage is reduced
below holding voltage (VH ) of the device. The Volt-Amp characteristic of SCR for
different values of Gate Current is shown in the figure.

9. Advantages of SCR

(a) It permits control over large currents (30-100A) to the load by means of
small gate current
(b) Power dissipation is very low.
(c) Operating frequency is up to 50 KHz.

10. Applications of SCR

(a) For power control.

(b) In motor controls.
(c) In relay controls.
(d) In power supply regulators.
(e) In Inverters.
(f) In phase control.
(g) Battery chargers.