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CS40023 Advanced Computer Architecture MA 2011

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28 views

CS40023 Advanced Computer Architecture MA 2011

Uploaded by

Gaurav Yadav
Copyright
© © All Rights Reserved
Available Formats
Download as PDF or read online on Scribd
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TH campus scence and Ensnerng Deparen, Kharagpur Subject: Advanced Computer Architecture Subject No. CS40023 Midsem Exam September, 2011 Time: 2 Hours Full Marks: 60 Instruction: Answer all questions Q1. State whether the following statements are TRUE [T] or FALSE [F} and write few lines to justify your answer. [(1+2) x 6 = 18] (a) Performance of pipelined processors keeps on increasing with increase in the number of stages (b) Single cycle implementation of a processor requires more hardware than multi-cycle implementation of the same processor. (c) Forwarding can eliminate ali possible stalls arising out of data dependences. (d) Miss rate keeps on decreasing as the block size of a cache memory is increased (e) Write back policy is commonly used in virtual memory organization. (f) In superscalar processors, compilers are used to identify instructions which can be executed in parallel 2. (a) Explain with example the various types of data dependences which are responsible for hazard in a pipelined processor [8] (b) Consider the following code sequence. Identify different types of hazards present and find out its execution time on a 7-stage pipeline with 2-cycie latency for non-branch instructions and S-cycle latency for branch instructions. Assume that branch is not taken. BNE r4, #0, 5 DIV 2,c1,17 ADD 18,19, r10 SUB 15, 12,19 MUL 110, 15, 18 6) Q3. (a) Distinguish between static with dynamic instruction scheduling used to reduce the number of stalls in a pipelined processor. (4) (b) Show the schematic diagram of the scoreboard for the MIPS processor. Explain the type hazards it can avoid [10] Q4. A direct-mapped 32-bit cache memory is assumed to have the following fields dex | Offset_| 11-05 _| 4-0 (a) What is the cache fine size? (b) How many entries does the cache have? (c) What is the overhead in percentage of the total cache memory size? (d) Starting from power on following addresses are generated in sequence 0, 4, 16, 132, 232, 160, 1024, 30, 140, 3100, 180, 2150 (i) How many blocks are replaced? (ii) What is the hit ratio? (10) QS, (a) What is TLB? Explain how it improves the performance of a memory system? (©) A system has 48-bit virtual addresses and 128 MB of main memory. The page size is 4B (i) How many virtual and physical pages can address space support? (ii) How many page frames of main memory are there? 4]

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