College of Computing and Informatics

Computer Organization
IT233

Assignment 2
Deadline: Wednesday 1/2/2023 @ 23:59
[Total Marks for this Assignment are 8]

Student Details:
Name: ID:

CRN:

Instructions:

You must submit two separate copies (one Word file and one PDF file)using the Assignment Template on
Blackboard via the allocated folder. These files must not be in compressed format.
It is your responsibility to check and make sure that you have uploaded both the correct files.
Zero mark will be given if you try to bypass the SafeAssign (e.g. misspell words, remove spaces between words,
hide characters, use different character sets or languages other than English or any kind of manipulation).
Email submission will not be accepted.
You are advised to make your work clear and well-presented. This includes filling your information on the cover
page.
You must use this template, failing which will result in zero mark.
You MUST show all your work, and text must not be converted into an image, unless specified otherwise by the
question.
Late submission will result in ZERO mark.
The work should be your own, copying from students or other resources will result in ZERO mark.
Use Times New Roman font for all your answers.
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Learning 2 Mark
Outcome(s): Question One
Describe the Explain how Pipelining is used to enhance the performance in fetch-execute
structure of cycle?
computer
systems Answer :

The CPU runs instructions in a continuous loop, one after the other, in a process called

a fetch execute cycle. The RISC processor executes data using a mechanism called

pipelining. The RISC pipeline consists of memory access, write back, execution,

instruction fetch, and instruction decoding. Additionally, it is where the execution of

several instructions overlaps . Pipelining provides a huge range of flexibility. By

reducing the size of RAM needed to complete the analysis, pipelining enhances

performance. If the utility would be used over and over again, performance is

improved by sharing RAM-loaded code.

By accelerating execution by obtaining the subsequent instructions while decoding,

pipelines improve the fetch-execute cycle's performance.

2 Mark
Learning
Outcome(s): Question Two
What is the use of Buffer in memory management discuss with example?

Analyze the
relationship Answer :

between When moving data from one location to another, the data buffer, which is a component
computer system
of physical memory storage, temporarily holds the data. Buffer management in
structure and
performance. computer science provides managers with flexibility when unanticipated occurrences

happen . Whenever both inbound and outbound packets of data are buffered in

memory, buffer makes sure that there is memory for packets of data available.

Therefore, performance that is less than ideal can result from poor buffer management.

Even with limited memory, buffer management plays a crucial role in maintaining the

protocol stack's functionality . When complexity varies, buffer management in

conventional IP stacks offers good throughput. For instance, in order to keep up with

the increasing amount of data entering from networks, buffers need to be allocated and

deallocated. The UlP buffer management approach is typically straightforward. UlP

limits the capacity of the packet's memory and the complexity of its codes in an only

one memory buffer.For instance, when the communication driver receives an incoming

packet, it copies it in this buffer, and while sending a packet, it creates it right there.

Buffer management uses a single memory buffer and doesn't need any elaborate buffer

management procedures to be implemented.

2 Mark
Learning
Outcome(s): Question Three
Analyze the What is memory interleaving? How it’s used for performance enhancements?
relationship
between Answer :
computer system
structure and Memory interleaving is a phrase used in computing to describe the concept of

performance. segmenting the memory into several modules. A processor that each module

communicates with is separate from the others. Each module has its own memory

address register and data register. The bandwidth possible for any program is increased

by CPUs . High order & low order interleaving are two varieties of interleaved

memory. Comparatively speaking, a system with interleaved memory is faster and

more responsive. Utilizing interleaved memory in vector and pipelining operations has

many benefits. Additionally, it enables simultaneous access to many memory modules.

By respecting each storage request that is made regardless of the condition of other

modules, memory interleaving improves performance .

The memory is divided into many modules, with interleaved memory addressing

sequential memory. The system may simultaneously access n instructions from each of

the n banks in main memory, which is partitioned into n-banks. This type of memory

access can assist in lowering the time factor of the memory access that is close to the

quantity of memory banks. The system is quicker and more responsive thanks to
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interleaved memory, which improves performance. Because of this, simultaneous

memory access shortens CPU processing time and boosts throughput.

2 Marks

Learning Question Four

Analyze the Answer :

networks in order to either start or complete the polling.

Polling has drawbacks, like the CPU using needless time to check devices that haven't

looked for data transfer and some devices' standby times being shorter than their

response times, necessitating the use of a different transmission mechanism.

Other disadvantages include

 Polling is a waste of time.

 Since each station has an equal chance of winning in each round, link sharing is

unfair.

 Only a few stations might run out of data to send.

Refernces :

1. Cai, Q., Guo, W., Zhang, H., Agrawal, D., Chen, G., Ooi, B. C., & Wang,

S. (2018). Efficient distributed memory management with RDMA and

caching. Proceedings of the VLDB Endowment, 11(11), 1604-1617.

2. Foster, N. L., Mueller, M. L., Was, C., Rawson, K. A., & Dunlosky, J.

(2019). Why does interleaving improve math learning? The contributions of

discriminative contrast and distributed practice. Memory & Cognition,

47(6), 1088-1101.