Freescale Semiconductor Document Number: MC9S08QE8

Data Sheet: Technical Data Rev. 8, 4/2011

An Energy Efficient Solution by Freescale

MC9S08QE8
32-Pin QFN
MC9S08QE8 Series Case 2078-01
20-Pin SOIC
751D-07
Covers: MC9S08QE8 and 32-Pin LQFP
Case 873A
MC9S08QE4 16-Pin PDIP
648
28-Pin SOIC
Features 751F-05 16-Pin TSSOP
• 8-Bit HCS08 Central Processor Unit (CPU) 948F
– Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of
–40 °C to 85 °C
– On-chip in-circuit emulator (ICE) debug module containing two
– HC08 instruction set with added BGND instruction
comparators and nine trigger modes; eight deep FIFO for storing
– Support for up to 32 interrupt/reset sources
change-of-flow addresses and event-only data; debug module
• On-Chip Memory
supports both tag and force breakpoints
– Flash read/program/erase over full operating voltage and
• Peripherals
temperature
– ADC — 10-channel, 12-bit resolution; 2.5 s conversion time;
– Random-access memory (RAM)
automatic compare function; 1.7 mV/C temperature sensor;
– Security circuitry to prevent unauthorized access to RAM and
internal bandgap reference channel; operation in stop3; fully
flash contents
functional from 3.6 V to 1.8 V
• Power-Saving Modes
– ACMPx — Two analog comparators with selectable interrupt on
– Two low power stop modes
rising, falling, or either edge of comparator output; compare
– Reduced power wait mode
option to fixed internal bandgap reference voltage; outputs can be
– Low power run and wait modes allow peripherals to run while
optionally routed to TPM module; operation in stop3
voltage regulator is in standby
– SCI — Full-duplex non-return to zero (NRZ); LIN master
– Peripheral clock gating register can disable clocks to unused
extended break generation; LIN slave extended break detection;
modules, thereby reducing currents
wake-up on active edge
– Very low power external oscillator that can be used in stop2 or
– SPI — Full-duplex or single-wire bidirectional; double-buffered
stop3 modes to provide accurate clock source to real time counter
transmit and receive; master or slave mode; MSB-first or
– 6 s typical wake-up time from stop3 mode
LSB-first shifting
• Clock Source Options
– IIC — Up to 100 kbps with maximum bus loading; multi-master
– Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or
operation; programmable slave address; interrupt driven
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to
byte-by-byte data transfer; supporting broadcast mode and 10-bit
16 MHz
addressing
– Internal Clock Source (ICS) — Internal clock source module
– TPMx — Two 3-channel (TPM1 and TPM2); selectable input
containing a frequency-locked-loop (FLL) controlled by internal
capture, output compare, or buffered edge- or center-aligned
or external reference; precision trimming of internal reference
PWM on each channel
allows 0.2% resolution and 2% deviation over temperature and
– RTC — (Real-time counter) 8-bit modulus counter with binary or
voltage; supporting bus frequencies from 1 MHz to 10 MHz
decimal based prescaler; external clock source for precise time
• System Protection
base, time-of-day, calendar or task scheduling functions; free
– Watchdog computer operating properly (COP) reset with option to
running on-chip low power oscillator (1 kHz) for cyclic wakeup
run from dedicated 1 kHz internal clock source or bus clock
without external components; runs in all MCU modes
– Low-voltage warning with interrupt
• Input/Output
– Low-voltage detection with reset or interrupt
– 26 GPIOs, one output-only pin and one input-only pin
– Illegal opcode detection with reset
– Eight KBI interrupts with selectable polarity
– Illegal address detection with reset
– Hysteresis and configurable pullup device on all input pins;
– Flash block protection
configurable slew rate and drive strength on all output pins.
• Development Support
• Package Options
– Single-wire background debug interface
– 32-pin LQFP, 32-pin QFN, 28-pin SOIC, 20-pin SOIC,
– Breakpoint capability to allow single breakpoint setting during
16-pin PDIP, 16-pin TSSOP
in-circuit debugging (plus two more breakpoints in on-chip debug
module)

This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007-2011. All rights reserved.
Table of Contents
1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 20
2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 20
3 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 7 3.10.2TPM Module Timing. . . . . . . . . . . . . . . . . 21
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . 7 3.11 Analog Comparator (ACMP) Electricals. . . . . . . 24
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 8 3.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . 25
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 8 3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . 29
3.5 ESD Protection and Latch-Up Immunity. . . . . . . 10 3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 29
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 11 3.14.1Conducted Transient Susceptibility . . . . . 30
3.7 Supply Current Characteristics. . . . . . . . . . . . . . 14 4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 External Oscillator (XOSCVLP) Characteristics . 17 5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9 Internal Clock Source (ICS) Characteristics . . . . 18 5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . 31

Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.

Rev Date Description of Changes

2 Nov 7 2007 Initial preliminary product preview release.
3 Jan 22 2008 Initial public release.
4 March 13 2008 Added Figure 11.
5 October 8 2008 Updated the Stop2 and Stop3 mode supply current in the Table 8.
Replaced the stop mode adders section from Table 8 with an individual Table 9 with new
specifications.
Added a footnote to the Min. of the suppply voltage in Table 7.
Changed the typical value of |IIn| and |IOZ| to — (no typical value) in Table 7.
Added tVRR to Table 12.
Updated “How to reach us” information.
6 Nov. 4 2008 Updated the operating voltage in Table 7.
7 April 29 2009 Changed VDDAD to VDDA, IDDAD to IDDA, and VSSAD to VSSA.
In Table 7, added |IOZTOT|.
In Table 11, updated the DCO output frequency range-trimmed, and changed some symbols.
Updated typicals and Max. for tIRST.
Updated Table 17.
8 April 12, 2011 Added 32-pin QFN package.

Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08QE8RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.

MC9S08QE8 Series Data Sheet, Rev. 8

2 Freescale Semiconductor
 MCU Block Diagram

1 MCU Block Diagram

The block diagram, Figure 1, shows the structure of MC9S08QE8 series MCU.

BKGD/MS
HCS08 CORE
DEBUG MODULE (DBG)

CPU BDC
REAL-TIME COUNTER
(RTC) PTA7/TPM2CH2/ADP9
HCS08 SYSTEM CONTROL PTA6/TPM1CH2/ADP8
SCL
PTA5/IRQ/TCLK/RESET
RESETS AND INTERRUPTS IIC MODULE (IIC) SDA

PORT A
MODES OF OPERATION PTA4/ACMP1O/BKGD/MS
POWER MANAGEMENT IRQ PTA3/KBIP3/SCL/ADP3
RxD
SERIAL COMMUNICATIONS PTA2/KBIP2/SDA/ADP2
COP IRQ LVD TxD
INTERFACE MODULE (SCI) PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+
SS
USER FLASH MISO
(MC9S08QE8 = 8192 BYTES) SERIAL PERIPHERAL PTB7/SCL/EXTAL
MOSI
(MC9S08QE4 = 4096 BYTES) INTERFACE MODULE (SPI) PTB6/SDA/XTAL
SPSCK
PTB5/TPM1CH1/SS
TCLK PTB4/TPM2CH1/MISO

PORT B
USER RAM
(MC9S08QE8 = 512 BYTES) TPM1CH0 PTB3/KBIP7/MOSI/ADP7
16-BIT TIMER PWM
(MC9S08QE4 = 256 BYTES) TPM1CH1 PTB2/KBIP6/SPSCK/ADP6
MODULE (TPM1)
TPM1CH2 PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
20 MHz INTERNAL CLOCK TCLK
SOURCE (ICS) TPM2CH0
16-BIT TIMER PWM PTC7/ACMP2–
LOW-POWER OSCILLATOR MODULE (TPM2) TPM2CH1 PTC6/ACMP2+
EXTAL
31.25 kHz to 38.4 kHz TPM2CH2 PTC5/ACMP2O
1 MHz to 16 MHz XTAL
PORT C

(XOSCVLP) ACMP1O PTC4

VSSA
ANALOG COMPARATOR ACMP1– PTC3
VSS VDDA
(ACMP1) ACMP1+ PTC2
VOLTAGE REGULATOR ACMP2O PTC1/TPM2CH2
VDD VSSA
ANALOG COMPARATOR ACMP2– PTC0/TPM1CH2
VDDA
(ACMP2) ACMP2+
VSSA/VREFL PTD3
VDDA/VREFH
PORT D

12-BIT ADP9–ADP0 PTD2

VREFL ANALOG-TO-DIGITAL PTD1
VREFH CONVERTER (ADC12)
PTD0

KEYBOARD INTERRUPT KBIP7–KBIP0

MODULE (KBI)

pins not available on 16-pin packages

pins not available on 16-pin or 20-pin packages
pins not available on 16-pin, 20-pin or 28-pin packages
Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device.
When PTA4 is configured as BKGD, pin becomes bi-directional.
For the 16-pin and 20-pin packages, VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively.

Figure 1. MC9S08QE8 Series Block Diagram

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 3
Pin Assignments

2 Pin Assignments
This section shows the pin assignments for the MC9S08QE8 series devices.

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA1/KBIP1/TPM2CH0ADP1/ACMP1–
PTA4/ACMP1O/BKGD/MS

PTA5/IRQ/TCLK/RESET

PTC5/ACMP2O

PTC6/ACMP2+

PTC7/ACMP2–
PTC4
32 31 30 29 28 27 26 25
PTD1 1 24 PTA2/KBIP2/SDA/ADP2

PTD0 2 23 PTA3/KBIP3/SCL/ADP3

VDD 3 22 PTD2

VDDA/VREFH 4 21 PTD3

VSSA/VREFL 5 20 PTA6/TPM1CH2/ADP8

VSS 6 19 PTA7/TPM2CH2/ADP9

PTB7/SCL/EXTAL 7 18 PTB0/KBIP4/RxD/ADP4

PTB6/SDA/XTAL 8 17 PTB1/KBIP5/TxD/ADP5

9 10 11 12 13 14 15 16
PTB3/KBIP7/MOSI/ADP7
PTC3
PTB4/TPM2CH1/MISO
PTB5/TPM1CH1/SS

PTC2

PTC1/TPM2CH2

PTB2/KBIP6/SPSCK/ADP6
PTC0/TPM1CH2

Pins shown in bold type are lost in the next lower pin count package.

Figure 2. MC9S08QE8 Series in 32-Pin LQFP/QFN Package

MC9S08QE8 Series Data Sheet, Rev. 8

4 Freescale Semiconductor
 Pin Assignments

PTC5/ACMP2O 1 28 PTC6/ACMP2+

PTC4 2 27 PTC7/ACMP2–

PTA5/IRQ/TCLK/RESET 3 26 PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA4/ACMP1O/BKGD/MS 4 25 PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–

VDD 5 24 PTA2/KBIP2/SDA/ADP2

VDDA/VREFH 6 23 PTA3/KBIP3/SCL/ADP3

VSSA/VREFL 7 22 PTA6/TPM1CH2/ADP8

VSS 8 21 PTA7/TPM2CH2/ADP9

PTB7/SCL/EXTAL 9 20 PTB0/KBIP4/RxD/ADP4

PTB6/SDA/XTAL 10 19 PTB1/KBIP5/TxD/ADP5
PTB5/TPM1CH1/SS 11 18 PTB2/KBIP6/SPSCK/ADP6

PTB4/TPM2CH1/MISO 12 17 PTB3/KBIP7/MOSI/ADP7

PTC3 13 16 PTC0/TPM1CH2

PTC2 14 15 PTC1/TPM2CH2

Pins shown in bold type are lost in the next lower pin count package.

Figure 3. MC9S08QE8 Series in 28-pin SOIC Package

PTA5/IRQ/TCLK/RESET 1 20 PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA4/ACMP1O/BKGD/MS 2 19 PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–

VDD 3 18 PTA2/KBIP2/SDA/ADP2

VSS 4 17 PTA3/KBIP3/SCL/ADP3

PTB7/SCL/EXTAL 5 16 PTB0/KBIP4/RxD/ADP4

PTB6/SDA/XTAL 6 15 PTB1/KBIP5/TxD/ADP5

PTB5/TPM1CH1/SS 7 14 PTB2/KBIP6/SPSCK/ADP6

PTB4/TPM2CH1/MISO 8 13 PTB3/KBIP7/MOSI/ADP7

PTC3 9 12 PTC0/TPM1CH2

PTC2 10 11 PTC1/TPM2CH2

Pins shown in bold type are lost in the next lower pin count package.

Figure 4. MC9S08QE8 Series in 20-pin SOIC Package

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 5
Pin Assignments

PTA5/IRQ/TCLK/RESET 1 16 PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA4/ACMP1O/BKGD/MS 2 15 PTA1/KBIP1/TPM2CH0ADP1/ACMP1–

VDD 3 14 PTA2/KBIP2/SDA/ADP2

VSS 4 13 PTA3/KBIP3/SCL/ADP3

PTB7/SCL/EXTAL 5 12 PTB0/KBIP4/RxD/ADP4

PTB6/SDA/XTAL 6 11 PTB1/KBIP5/TxD/ADP5

PTB5/TPM1CH1/SS 7 10 PTB2/KBIP6/SPSCK/ADP6

PTB4/TPM2CH1/MISO 8 9 PTB3/KBIP7/MOSI/ADP7

Figure 5. MC9S08QE8 Series in 16-pin PDIP and TSSOP Packages

Table 1. Pin Availability by Package Pin-Count

Pin Number <-- Lowest Priority --> Highest

32 28 20 16 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

1 — — — PTD1
2 — — — PTD0
3 5 3 3 VDD
4 6 — — VDDA/VREFH
5 7 — — VSSA/VREFL
6 8 4 4 VSS
7 9 5 5 PTB7 SCL1 EXTAL
1
8 10 6 6 PTB6 SDA XTAL
9 11 7 7 PTB5 TPM1CH1 SS
10 12 8 8 PTB4 TPM2CH1 MISO
11 13 9 — PTC3
12 14 10 — PTC2
13 15 11 — PTC1 TPM2CH22
14 16 12 — PTC0 TPM1CH23
15 17 13 9 PTB3 KBIP7 MOSI ADP7
16 18 14 10 PTB2 KBIP6 SPSCK ADP6
17 19 15 11 PTB1 KBIP5 TxD ADP5
18 20 16 12 PTB0 KBIP4 RxD ADP4
2
19 21 — — PTA7 TPM2CH2 ADP9
3
20 22 — — PTA6 TPM1CH2 ADP8
21 — — — PTD3
22 — — — PTD2
23 23 17 13 PTA3 KBIP3 SCL1 ADP3
1
24 24 18 14 PTA2 KBIP2 SDA ADP2
25 25 19 15 PTA1 KBIP1 TPM2CH0 ADP14 ACMP1–4

MC9S08QE8 Series Data Sheet, Rev. 8

6 Freescale Semiconductor
 Electrical Characteristics

Table 1. Pin Availability by Package Pin-Count (continued)

Pin Number <-- Lowest Priority --> Highest

32 28 20 16 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

26 26 20 16 PTA0 KBIP0 TPM1CH0 ADP04 ACMP1+4
27 27 — — PTC7 ACMP2–
28 28 — — PTC6 ACMP2+
29 1 — — PTC5 ACMP2O
30 2 — — PTC4
31 3 1 1 PTA5 IRQ TCLK RESET
32 4 2 2 PTA4 ACMP1O BKGD MS
1
IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2, default reset locations
are PTA3 and PTA2.
2 TPM2CH2 pin can be repositioned using TPM2CH2PS in SOPT2, default reset location is

PTA7.
3 TPM1CH2 pin can be repositioned using TPM1CH2PS in SOPT2, default reset location is

PTA6.
4 If ADC and ACMP1 are enabled, both modules will have access to the pin.

3 Electrical Characteristics
3.1 Introduction
This section contains electrical and timing specifications for the MC9S08QE8 series of microcontrollers
available at the time of publication.

3.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 2. Parameter Classifications

P Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically relevant
C
sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices
T under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.

D Those parameters are derived mainly from simulations.

NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 7
Electrical Characteristics

3.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pullup resistor associated with the pin is enabled.

Table 3. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage VDD –0.3 to 3.8 V

Maximum current into VDD IDD 120 mA
Digital input voltage VIn –0.3 to VDD + 0.3 V
Instantaneous maximum current
ID 25 mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range Tstg –55 to 150 C
1 Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins, except for PTA5 are internally clamped to V
SS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).

3.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.

MC9S08QE8 Series Data Sheet, Rev. 8

8 Freescale Semiconductor
 Electrical Characteristics

Table 4. Thermal Characteristics

Rating Symbol Value Unit

Operating temperature range TL to TH

TA C
(packaged) –40 to 85
Maximum junction temperature TJM 95 C
Thermal resistance
Single-layer board
32-pin QFN 110
32-pin LQFP 66
28-pin SOIC 57
JA C/W
20-pin SOIC 71
16-pin PDIP 64
16-pin TSSOP 108
Thermal resistance
Four-layer board
32-pin QFN 42
32-pin LQFP 47
28-pin SOIC 42
JA C/W
20-pin SOIC 52
16-pin PDIP 47
16-pin TSSOP 78

The average chip-junction temperature (TJ) in C can be obtained from:

TJ = TA + (PD  JA) Eqn. 1

where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD  VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O  Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:

PD = K  (TJ + 273 C) Eqn. 2

Solving Equation 1 and Equation 2 for K gives:

K = PD  (TA + 273 C) + JA  (PD)2 Eqn. 3

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 9
Electrical Characteristics

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 5. ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Series resistance R1 1500 
Human
Body Storage capacitance C 100 pF
Number of pulses per pin — 3 —

Series resistance R1 0 
Machine Storage capacitance C 200 pF
Number of pulses per pin — 3 —
Minimum input voltage limit — –2.5 V
Latch-up
Maximum input voltage limit — 7.5 V

Table 6. ESD and Latch-Up Protection Characteristics

No. Rating1 Symbol Min Max Unit

1 Human body model (HBM) VHBM 2000 — V

2 Machine model (MM) VMM 200 — V

3 Charge device model (CDM) VCDM 500 — V

4 Latch-up current at TA = 85 C ILAT 100 — mA

1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.

MC9S08QE8 Series Data Sheet, Rev. 8

10 Freescale Semiconductor
 Electrical Characteristics

3.6 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics

Num C Characteristic Symbol Condition Min. Typical1 Max. Unit

Operating voltage
1 VDD rising 2.02 3.6 V
VDD falling 1.8
All I/O pins, VDD > 1.8 V,
C VDD – 0.5 — —
low-drive strength ILoad = –2 mA
Output high VDD > 2.7 V,
2 P VOH VDD – 0.5 — — V
voltage All I/O pins, ILoad = –10 mA
high-drive strength VDD > 1.8V,
C VDD – 0.5 — —
ILoad = –2 mA
Output high
D Max total IOH for all ports IOHT — — — 100 mA
3 current
All I/O pins, VDD > 1.8 V,
C — — 0.5
low-drive strength ILoad = 0.6 mA
Output low VDD > 2.7 V,
4 P VOL — — 0.5 V
voltage All I/O pins, ILoad = 10 mA
high-drive strength VDD > 1.8 V,
C — — 0.5
ILoad = 3 mA
Output low
5 D Max total IOL for all ports IOLT — — — 100 mA
current
P Input high VDD  2.7 V 0.70  VDD — —
6 All digital inputs VIH
C voltage VDD 1.8 V 0.85  VDD — —
V
P Input low VDD  2.7 V — — 0.35  VDD
7 All digital inputs VIL
C voltage VDD 1.8 V — — 0.30  VDD
Input
8 C All digital inputs Vhys — 0.06 x VDD — — mV
hysteresis
Input
All input only pins
9 P leakage |IIn| VIn = VDD or VSS — — 1 A
(per pin)
current
Hi-Z
(off-state) All input/output
10 P |IOZ| VIn = VDD or VSS — — 1 A
leakage (per pin)
current
Total
leakage
combined
11 P All input only and I/O |IOZTOT| VIn = VDD or VSS — — 2 A
for all inputs
and Hi-Z
pins
All digital inputs, when
Pullup,
enabled (all I/O pins other RPU,
12a P pulldown 17.5 — 52.5 k
than RPD —
resistors
PTA5/IRQ/TCLK/RESET

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 11
Electrical Characteristics

Table 7. DC Characteristics (continued)

Num C Characteristic Symbol Condition Min. Typical1 Max. Unit

RPU,
Pullup,
RPD
12b C pulldown (PTA5/IRQ/TCLK/RESET) 17.5 — 52.5 k
resistors —
3
(Note )
DC injection Single pin limit –0.2 — 0.2 mA
13 C current 4, 5, Total MCU limit, includes IIC VIN < VSS, VIN > VDD
6 –5 — 5 mA
sum of all stressed pins
14 C Input capacitance, all pins CIn — — — 8 pF
15 C RAM retention voltage VRAM — — 0.6 1.0 V
7
16 C POR re-arm voltage VPOR — 0.9 1.4 2.0 V
17 D POR re-arm time tPOR — 10 — — s
VDD falling 1.80 1.84 1.88
18 P Low-voltage detection threshold VLVD V
VDD rising 1.88 1.92 1.96
VDD falling
19 P Low-voltage warning threshold VLVW 2.08 2.14 2.24 V
VDD rising
Low-voltage inhibit reset/recover
20 P Vhys — — 80 — mV
hysteresis
21 P Bandgap voltage reference8 VBG — 1.15 1.17 1.18 V
1 Typical values are measured at 25 C. Characterized, not tested
2
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL.
3
The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when
measured externally on the pin.
4
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
5 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
6 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
7 Maximum is highest voltage that POR is guaranteed.
8
Factory trimmed at VDD = 3.0 V, Temp = 25 C

MC9S08QE8 Series Data Sheet, Rev. 8

12 Freescale Semiconductor
 Electrical Characteristics

PULLUP RESISTOR TYPICALS

40 PULLDOWN RESISTOR TYPICALS
85C 40
25C 85C

PULLDOWN RESISTANCE (k)

–40C 25C
PULL-UP RESISTOR (k)

35 –40C
35

30
30

25
25

20
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 20
VDD (V) 1.8 2.3 2.8 3.3 3.6
VDD (V)

Figure 6. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)

TYPICAL VOL VS IOL AT VDD = 3.0 V TYPICAL VOL VS VDD

1.2 0.2
85C
1 25C
–40C 0.15
0.8
0.6 VOL (V) 0.1
VOL (V)

0.4
0.05 85C, IOL = 2 mA
0.2 25C, IOL = 2 mA
–40C, IOL = 2 mA
0 0
0 5 10 15 20 1 2 3 4
IOL (mA) VDD (V)

Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)

TYPICAL VOL VS IOL AT VDD = 3.0 V TYPICAL VOL VS VDD

1 0.4
85C 85C
25C 25C
0.8 –40C –40C
0.3
0.6
VOL (V)

0.2
VOL (V)

IOL = 10 mA
0.4
IOL = 6 mA
0.2 0.1
IOL = 3 mA
0 0
0 10 20 30 1 2 3 4
VDD (V)
IOL (mA)

Figure 8. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 13
 Electrical Characteristics

TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V TYPICAL VDD – VOH VS VDD AT SPEC IOH
1.2 0.25
85C 85C, IOH = 2 mA
1 25C 25C, IOH = 2 mA
–40C 0.2 –40C, IOH = 2 mA
VDD – VOH (V)

VDD – VOH (V)

0.8
0.15
0.6
0.1
0.4
0.2 0.05

0 0
0 –5 –10 –15 –20 1 2 3 4
IOH (mA)) VDD (V)

Figure 9. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)

TYPICAL VDD – VOH VS VDD AT SPEC IOH

0.4
85C
25C
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 0.3 –40C
0.8
85C
25C

VDD – VOH (V)

0.6
VDD – VOH (V)

–40C 0.2 IOH = –10 mA

0.4 IOH = –6 mA
0.1
0.2 IOH = –3 mA
0 0
0 –5 –10 –15 –20 –25 –30
1 2 3 4
IOH (mA) VDD (V)
Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)

3.7 Supply Current Characteristics

This section includes information about power supply current in various operating modes.
Table 8. Supply Current Characteristics
Parameter Bus VDD Temp
Num C Symbol Freq (V) Typical1 Max Unit (C)
P Run supply current 10 MHz 5.60 8.2 mA
1 RIDD –40 to 85 C
T FEI mode, all modules on 1 MHz 3 0.80 —
T Run supply current 10 MHz 3.60 —
2 RIDD mA –40 to 85 C
T FEI mode, all modules off 1 MHz 3 0.51 —
16 kHz
T 165 —
Run supply current FBILP
3 RIDD 3 A –40 to 85 C
LPRS = 0, all modules off 16 kHz
T 105 —
FBELP
16 kHz
T Run supply current 77 —
FBILP
4 LPRS = 1, all modules off; running RIDD 3 A –40 to 85 C
from flash 16 kHz
T 21 —
FBELP

MC9S08QE8 Series Data Sheet, Rev. 8

14 Freescale Semiconductor
 Electrical Characteristics

Table 8. Supply Current Characteristics (continued)

Parameter Bus VDD Temp
Num C Symbol Freq (V) Typical1 Max Unit (C)
16 kHz
T Run supply current 77 —
FBILP
5 LPRS = 1, all modules off; running RIDD 3 A –40 to 85 C
from RAM 16 kHz
T 7.3 —
FBELP
T Wait mode supply current 10 MHz 570 —
6 WIDD 3 A –40 to 85 C
T FEI mode, all modules off 1 MHz 290 —
Wait mode supply current 16 kHz
7 T WIDD 3 1 — A –40 to 85 C
LPRS = 1, all modules off FBELP
P — 0.3 0.65 –40 to 25 C
C — 3 0.5 0.8 70 C
P — 1 2.5 85 C
8 Stop2 mode supply current S2IDD A
C — 0.25 0.50 –40 to 25 C
C — 2 0.3 0.6 70 C
C — 0.7 2.0 85 C
P — 0.4 0.8 –40 to 25 C
C — 3 1.0 1.8 70 C
P Stop3 mode supply current — 3 6 85 C
9 S3IDD A
C no clocks active — 0.35 0.60 –40 to 25 C
C — 2 0.8 1.5 70 C
C — 2.5 5.5 85 C
1
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.

Table 9. Stop Mode Adders

Temperature
Num C Parameter Condition Units
–40C 25C 70C 85C

1 T LPO — 50 75 100 150 nA

2 T ERREFSTEN RANGE = HGO = 0 1000 1000 1100 1500 nA
3 T IREFSTEN 1 — 63 70 77 81 A
4 T RTC Does not include clock source 50 75 100 150 nA
current
5 T LVD1 LVDSE = 1 90 100 110 115 A
6 T ACMP1 Not using the bandgap (BGBE = 0) 18 20 22 23 A
7 T ADC1 ADLPC = ADLSMP = 1 95 106 114 120 A
Not using the bandgap (BGBE = 0)
1
Not available in stop2 mode.

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 15
Electrical Characteristics

5.000

4.500

4.000

3.500 TBD
3.000 FEI: 10 MHz
FBELP: 10 MHz
IDD (mA)

FEI: 5 MHz
2.500
FBELP: 5 MHz
FEI: 1 MHz
2.000 FBELP: 1 MHz

1.500

1.000

0.500

0.000
1.8 2 2.2 2.4 2.6 2.8 3
VDD (V)

Figure 11. Typical Run IDD for FBE and FEI, IDD vs. VDD
(ADC off, All Other Modules Enabled)

MC9S08QE8 Series Data Sheet, Rev. 8

16 Freescale Semiconductor
 Electrical Characteristics

3.8 External Oscillator (XOSCVLP) Characteristics

Refer to Figure 12 and Figure 13 for crystal or resonator circuits.
Table 10. XOSCVLP Specifications (Temperature Range = –40 to 85C Ambient)

Num C Characteristic Symbol Min. Typical1 Max. Unit

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

Low range (RANGE = 0) flo 32 — 38.4 kHz
1 C
High range (RANGE = 1), high gain (HGO = 1), FBELP mode fhi 1 — 16 MHz
High range (RANGE = 1), low power (HGO = 0), FBELP mode fhi 1 — 8 MHz

Load capacitors
See Note 2
2 D Low range (RANGE=0), low power (HGO = 0) C1,C2
Other oscillator settings See Note 3

Feedback resistor
Low range, low power (RANGE = 0, HGO = 0)2 — — —
3 D RF M
Low range, high gain (RANGE = 0, HGO = 1) — 10 —
High range (RANGE = 1, HGO = X) — 1 —

Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2 — — —
Low range, high gain (RANGE = 0, HGO = 1) — 100 —
High range, low power (RANGE = 1, HGO = 0) — 0 —
4 D RS k
High range, high gain (RANGE = 1, HGO = 1)
 8 MHz — 0 0
4 MHz — 0 10
1 MHz — 0 20
Crystal start-up time4
t
Low range, low power CSTL — 600 —
5 C Low range, high gain — 400 —
t ms
High range, low power CSTH — 5 —
High range, high gain — 15 —

Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)

6 D FEE mode fextal 0.03125 — 20 MHz
FBE or FBELP mode 0 — 20 MHz
1 Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.
2
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0.
3 See crystal or resonator manufacturer’s recommendation.
4
Proper PC board layout procedures must be followed to achieve specifications.

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 17
Electrical Characteristics

XOSCVLP
EXTAL XTAL

RS
RF

Crystal or Resonator
C1
C2

Figure 12. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain

XOSCVLP
EXTAL XTAL

Crystal or Resonator

Figure 13. Typical Crystal or Resonator Circuit: Low Range/Low Power

3.9 Internal Clock Source (ICS) Characteristics

Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient)

Num C Characteristic Symbol Min. Typical1 Max. Unit

Average internal reference frequency — factory trimmed

1 P fint_t — 32.768 — kHz
at VDD = 3.6 V and temperature = 25 C
2 P Internal reference frequency — user trimmed fint_ut 31.25 — 39.06 kHz

3 T Internal reference start-up time tIRST — 5 10 s

DCO output frequency range — Low range
4 P fdco_t 16 — 20 MHz
trimmed2 (DRS = 00)

5 P DCO output frequency2 fdco_DMX32 — 19.92 — MHz

Reference = 32768 Hz and DMX32 = 1
Resolution of trimmed DCO output frequency at fixed
6 C fdco_res_t — 0.1 0.2 %fdco
voltage and temperature (using FTRIM)

MC9S08QE8 Series Data Sheet, Rev. 8

18 Freescale Semiconductor
 Electrical Characteristics

Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) (continued)

Num C Characteristic Symbol Min. Typical1 Max. Unit

Resolution of trimmed DCO output frequency at fixed

7 C fdco_res_t — 0.2 0.4 %fdco
voltage and temperature (not using FTRIM)

Total deviation of DCO output from trimmed frequency3

8 C Over full voltage and temperature range fdco_t — –1.0 to 0.5 2 %fdco
Over fixed voltage and temperature range of 0 to 70 C 0.5 1

10 C FLL acquisition time4 tAcquire — — 1 ms

Long term jitter of DCO output clock (averaged over 2-ms

11 C CJitter — 0.02 0.2 %fdco
interval)5
1 Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.
2 The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3 This parameter is characterized and not tested on each device.
4
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used
as the reference, this specification assumes it is already running.
5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.

1.00%

0.50%

0.00%
-60 -40 -20 0 20 40 60 80 100 120
Deviation (%)

-0.50%

-1.00% TBD
-1.50%

-2.00%
Temperature

Figure 14. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 19
Electrical Characteristics

3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.

3.10.1 Control Timing

Table 12. Control Timing

Num C Rating Symbol Min Typical1 Max Unit

1 D Bus frequency (tcyc = 1/fBus) fBus dc — 10 MHz

2 D Internal low power oscillator period tLPO 700 — 1300 s

3 D External reset pulse width2 textrst 100 — — ns

4 D Reset low drive trstdrv 34  tcyc — — ns

BKGD/MS setup time after issuing background debug
5 D tMSSU 500 — — ns
force reset to enter user or BDM modes
BKGD/MS hold time after issuing background debug
6 D tMSH 100 — — s
force reset to enter user or BDM modes 3
IRQ pulse width
7 D Asynchronous path2 tILIH, tIHIL 100 — — ns
Synchronous path4 1.5  tcyc — —
8 D Keyboard interrupt pulse width
Asynchronous path2 tILIH, tIHIL 100 — — ns
Synchronous path4 1.5  tcyc — —
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5 tRise, tFall ns
Slew rate control disabled (PTxSE = 0) — 16 —
Slew rate control enabled (PTxSE = 1) — 23 —
9 C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5 tRise, tFall ns
Slew rate control disabled (PTxSE = 0) — 5 —
Slew rate control enabled (PTxSE = 1) — 9 —

10 C Voltage regulator recovery time tVRR — 4 — s

1
Typical values are based on characterization data at VDD = 3.0 V, 25 C unless otherwise stated.
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 85C.

textrst

RESET PIN

Figure 15. Reset Timing

MC9S08QE8 Series Data Sheet, Rev. 8

20 Freescale Semiconductor
 Electrical Characteristics

tIHIL

KBIPx

IRQ/KBIPx

tILIH

Figure 16. IRQ/KBIPx Timing

3.10.2 TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 13. TPM Input Timing

No. C Function Symbol Min Max Unit

1 D External clock frequency fTCLK 0 fBus/4 Hz

2 D External clock period tTCLK 4 — tcyc
3 D External clock high time tclkh 1.5 — tcyc
4 D External clock low time tclkl 1.5 — tcyc
5 D Input capture pulse width tICPW 1.5 — tcyc

tTCLK
tclkh

TCLK

tclkl

Figure 17. Timer External Clock

tICPW

TPMCHn

TPMCHn

tICPW

Figure 18. Timer Input Capture Pulse

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 21
Electrical Characteristics

3.10.3 SPI Timing

Table 14 and Figure 19 through Figure 22 describe the timing requirements for the SPI system.
Table 14. SPI Timing

No. C Function Symbol Min Max Unit

Operating frequency
— D Master fop fBus/2048 fBus/2 Hz
Slave 0 fBus/4
SPSCK period
1 D Master tSPSCK 2 2048 tcyc
Slave 4 — tcyc
Enable lead time
2 D Master tLead 12 — tSPSCK
Slave 1 — tcyc
Enable lag time
3 D Master tLag 12 — tSPSCK
Slave 1 — tcyc
Clock (SPSCK) high or low time
4 D Master tWSPSCK tcyc –30 1024 tcyc ns
Slave tcyc – 30 — ns
Data setup time (inputs)
5 D Master tSU 15 — ns
Slave 15 — ns
Data hold time (inputs)
6 D Master tHI 0 — ns
Slave 25 — ns
7 D Slave access time ta — 1 tcyc
8 D Slave MISO disable time tdis — 1 tcyc
Data valid (after SPSCK edge)
9 D Master tv — 25 ns
Slave — 25 ns
Data hold time (outputs)
10 D Master tHO 0 — ns
Slave 0 — ns
Rise time
11 D Input tRI — tcyc – 25 ns
Output tRO — 25 ns
Fall time
12 D Input tFI — tcyc – 25 ns
Output tFO — 25 ns

MC9S08QE8 Series Data Sheet, Rev. 8

22 Freescale Semiconductor
 Electrical Characteristics

SS1
(OUTPUT)

2 1 11 3
SPSCK 4
(CPOL = 0)
(OUTPUT) 4

12
SPSCK
(CPOL = 1)
(OUTPUT)

5 6

MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN

9 9 10

MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT

NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. SPI Master Timing (CPHA = 0)

SS(1)
(OUTPUT)

1
2 12 11 3
SPSCK
(CPOL = 0)
(OUTPUT)
4 4 11 12
SPSCK
(CPOL = 1)
(OUTPUT)
5 6
MISO
(INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN

9 10
MOSI
(OUTPUT) PORT DATA MASTER MSB OUT(2) BIT 6 . . . 1 MASTER LSB OUT PORT DATA

NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 20. SPI Master Timing (CPHA =1)

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 23
Electrical Characteristics

SS
(INPUT)

1 12 11 3
SPSCK
(CPOL = 0)
(INPUT)
2 4 4
11 12
SPSCK
(CPOL = 1)
(INPUT) 8
7 9 10 10

MISO SEE
(OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE

5 6

MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

NOTE:
1. Not defined but normally MSB of character just received
Figure 21. SPI Slave Timing (CPHA = 0)

SS
(INPUT)

1 3
2 12 11
SPSCK
(CPOL = 0)
(INPUT)
4 4 11 12
SPSCK
(CPOL = 1)
(INPUT)
9 10 8
MISO SEE
(OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT

7 5 6
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

NOTE:
1. Not defined but normally LSB of character just received
Figure 22. SPI Slave Timing (CPHA = 1)

3.11 Analog Comparator (ACMP) Electricals

Table 15. Analog Comparator Electrical Specifications

C Characteristic Symbol Min Typical Max Unit

D Supply voltage VDD 1.8 — 3.6 V

P Supply current (active) IDDAC — 20 35 A

MC9S08QE8 Series Data Sheet, Rev. 8

24 Freescale Semiconductor
 Electrical Characteristics

Table 15. Analog Comparator Electrical Specifications (continued)

C Characteristic Symbol Min Typical Max Unit

D Analog input voltage VAIN VSS – 0.3 — VDD V

P Analog input offset voltage VAIO — 20 40 mV
C Analog comparator hysteresis VH 3.0 9.0 15.0 mV

P Analog input leakage current IALKG — — 1.0 A

C Analog comparator initialization delay tAINIT — — 1.0 s

3.12 ADC Characteristics

Table 16. 12-Bit ADC Operating Conditions

Characteristic Conditions Symb Min Typical1 Max Unit Comment

Supply voltage Absolute VDDA 1.8 — 3.6 V —

Delta to VDD (VDD – VDDA)2 VDDA –100 0 100 mV —

Ground voltage Delta to VSS (VSS – VSSA)2 VSSA –100 0 100 mV —

Input voltage — VADIN VREFL — VREFH V —

Input
— CADIN — 4.5 5.5 pF —
capacitance

Input
— RADIN — 5 7 k —
resistance

Analog source 12-bit mode

resistance fADCK > 4 MHz — — 2
fADCK < 4 MHz — — 5

10-bit mode RAS k External to MCU

fADCK > 4 MHz — — 5
fADCK < 4 MHz — — 10

8-bit mode (all valid fADCK) — — 10

ADC High speed (ADLPC = 0) 0.4 — 8.0

conversion fADCK MHz —
clock freq. Low power (ADLPC = 1) 0.4 — 4.0
1 Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 25
Electrical Characteristics

SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT ZADIN
SIMPLIFIED
Pad
ZAS leakage CHANNEL SELECT
due to CIRCUIT
ADC SAR
input ENGINE
RAS RADIN
protection
+
VADIN
–
CAS
VAS +
–

RADIN

INPUT PIN
RADIN

INPUT PIN
RADIN

INPUT PIN CADIN

Figure 23. ADC Input Impedance Equivalency Diagram

Table 17. ADC Characteristics (VREFH = VDDA, VREFL = VSSA)

C Characteristic Conditions Symbol Min Typ1 Max Unit Comment

Supply current
ADLPC = 1
T IDDA — 120 — A
ADLSMP = 1
ADCO = 1

Supply current
ADLPC = 1
T IDDA — 202 — A
ADLSMP = 0
ADCO = 1

Supply current
ADLPC = 0
T IDDA — 288 — A
ADLSMP = 1
ADCO = 1

Supply current
ADLPC = 0
P IDDA — 0.532 1 mA
ADLSMP = 0
ADCO = 1

ADC High speed (ADLPC = 0) 2 3.3 5

tADACK =
P asynchronous fADACK MHz
Low power (ADLPC = 1) 1.25 2 3.3 1/fADACK
clock source

MC9S08QE8 Series Data Sheet, Rev. 8

26 Freescale Semiconductor
 Electrical Characteristics

Table 17. ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)

C Characteristic Conditions Symbol Min Typ1 Max Unit Comment

Conversion Short sample (ADLSMP = 0) — 20 — See QE8

ADCK
P time (including tADC reference
Long sample (ADLSMP = 1) — 40 — cycles
sample time) manual for
conversion
Short sample (ADLSMP = 0) — 3.5 — ADCK
P Sample time tADS time
Long sample (ADLSMP = 1) — 23.5 — cycles variances

Temp sensor –40 C– 25 C — 1.646 —

D m mV/C
slope 25 C– 85 C — 1.769 —

Temp sensor
D 25 C VTEMP25 — 701.2 — mV
voltage

Characteristics for devices with dedicated analog supply (28- and 32-pin packages only)

T 12-bit mode, 3.6> VDDA > 2.7 — –1 to 3 –2.5 to 5.5

T Total 12-bit mode, 2.7> VDDA > 1.8V — –1 to 3 –3.0 to 6.5 Includes
unadjusted ETUE LSB2
P 10-bit mode — 1 2.5 quantization
error
P 8-bit mode — 0.5 1.0

T 12-bit mode — 1.0 –1.5 to 2.0

Differential
P 10-bit mode3 DNL — 0.5 1.0 LSB2
non-linearity
P 8-bit mode3 — 0.3 0.5

–2.5 to
T 12-bit mode — 1.5
2.75
Integral
INL LSB2
T non-linearity 10-bit mode — 0.5 1.0

T 8-bit mode — 0.3 0.5

T 12-bit mode — 1.5 2.5

Zero-scale VADIN =
P 10-bit mode EZS — 0.5 1.5 LSB2
error VSSA
P 8-bit mode — 0.5 0.5

T 12-bit mode — 1.0 –3.5 to 1.0

VADIN =
P Full-scale error 10-bit mode EFS — 0.5 1 LSB2
VDDA
P 8-bit mode — 0.5 0.5

12-bit mode — –1 to 0 —
Quantization
D 10-bit mode EQ — — 0.5 LSB2
error
8-bit mode — — 0.5

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 27
Electrical Characteristics

Table 17. ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)

C Characteristic Conditions Symbol Min Typ1 Max Unit Comment

12-bit mode — 2 —
Pad
Input leakage
D 10-bit mode EIL — 0.2 4 LSB2 leakage4 *
error
RAS
8-bit mode — 0.1 1.2

Characteristics for devices with shared supply (16- and 20-pin packages only)

T 12-bit mode Not recommended usage

Total
Includes
P unadjusted 10-bit mode ETUE — 1.5 3.5 LSB2
quantization
error
P 8-bit mode — 0.7 1.5

T 12-bit mode Not recommended usage

Differential
P 10-bit mode3 DNL — 0.5 1.0 LSB2
non-linearity
P 8-bit mode3 — 0.3 0.5

T 12-bit mode Not recommended usage

Integral
T 10-bit mode INL — 0.5 1.0 LSB2
non-linearity
T 8-bit mode — 0.3 0.5

T 12-bit mode Not recommended usage

Zero-scale VADIN =
P 10-bit mode EZS — 1.5 2.1 LSB2
error VSSA
P 8-bit mode — 0.5 0.7

T 12-bit mode Not recommended usage

VADIN =
P Full-scale error 10-bit mode EFS — 1 1.5 LSB2
VDDA
P 8-bit mode — 0.5 0.5

12-bit mode Not recommended usage

Quantization
D 10-bit mode EQ — — 0.5 LSB2
error
8-bit mode — — 0.5

12-bit mode Not recommended usage

Pad
Input leakage
D 10-bit mode EIL — 0.2 4 LSB2 leakage4 *
error
RAS
8-bit mode — 0.1 1.2
1
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
1 LSB = (VREFH – VREFL)/2N
3
Monotonicity and No-missing-codes guaranteed in 10-bit and 8-bit modes
4 Based on input pad leakage current. Refer to pad electricals.

MC9S08QE8 Series Data Sheet, Rev. 8

28 Freescale Semiconductor
 Electrical Characteristics

3.13 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
Table 18. Flash Characteristics

C Characteristic Symbol Min Typical Max Unit

Supply voltage for program/erase

D —
–40 C to 85 C Vprog/erase 1.8 3.6 V
D Supply voltage for read operation VRead 1.8 — 3.6 V
D Internal FCLK frequency1 fFCLK 150 — 200 kHz
D Internal FCLK period (1/FCLK) tFcyc 5 — 6.67 s
P Byte program time (random location)2 tprog 9 tFcyc
P Byte program time (burst mode)2 tBurst 4 tFcyc
P Page erase time2 tPage 4000 tFcyc
P Mass erase time2 tMass 20,000 tFcyc
Byte program current3 RIDDBP — 4 — mA
Page erase current3 RIDDPE — 6 — mA
Program/erase endurance4
C TL to TH = –40C to 85 C 10,000 — — cycles
T = 25 C 100,000 —
C Data retention5 tD_ret 15 100 — years
1
The frequency of this clock is controlled by a software setting.
2 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how

Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and

de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

3.14 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 29
Ordering Information

3.14.1 Conducted Transient Susceptibility

Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale
test method. The measurement is performed with the microcontroller installed on a custom EMC
evaluation board and running specialized EMC test software designed in compliance with the test method.
The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of
the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4
(EFT/B). The transient voltage required to cause performance degradation on any pin in the tested
configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below
Table 19.

Table 19. Conducted Susceptibility, EFT/B

Parameter Symbol Conditions fOSC/fBUS Result Amplitude1 Unit

(Min)
A 2.3
VDD = 3.3 V
8 MHz B 4.0
Conducted susceptibility, electrical TA = 25 oC
VCS_EFT crystal kV
fast transient/burst (EFT/B) package type
8 MHz bus C >4.0
32-pin LQFP
D >4.0
1 Data based on qualification test results. Not tested in production.

The susceptibility performance classification is described in Table 20.

Table 20. Susceptibility Performance Classification

Result Performance Criteria

A No failure The MCU performs as designed during and after exposure.

Self-recovering The MCU does not perform as designed during exposure. The MCU returns
B
failure automatically to normal operation after exposure is removed.

The MCU does not perform as designed during exposure. The MCU does not return to
C Soft failure
normal operation until exposure is removed and the RESET pin is asserted.

The MCU does not perform as designed during exposure. The MCU does not return to
D Hard failure
normal operation until exposure is removed and the power to the MCU is cycled.

The MCU does not perform as designed during and after exposure. The MCU cannot
E Damage be returned to proper operation due to physical damage or other permanent
performance degradation.

4 Ordering Information
This section contains ordering information for the device numbering system.
Example of the device numbering system:

MC9S08QE8 Series Data Sheet, Rev. 8

30 Freescale Semiconductor
 Package Information

MC 9 S08 QE 8 C XX

Status
(MC = Fully qualified) Package designator (see Table 21)

Memory Temperature range

(9 = Flash-based) (C = –40 C to 85 C)
Core
Family Approximate flash size in Kbytes

5 Package Information
Table 21. Package Descriptions

Pin Count Package Type Abbreviation Designator Case No. Document No.
32 Quad Flat No-Leads QFN FM 2078 98ASA00071D
32 Low Quad Flat Package LQFP LC 873A 98ASH70029A
28 Small Outline Integrated Circuit SOIC WL 751F 98ASB42345B
20 Small Outline Integrated Circuit SOIC WJ 751D 98ASB42343B
16 Plastic Dual In-line Package PDIP PG 648 98ASB42431B
16 Thin Shrink Small Outline Package TSSOP TG 948F 98ASH70247A

5.1 Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 21.

MC9S08QE8 Series Data Sheet, Rev. 8

Freescale Semiconductor 31
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MC9S08QE8
Rev. 8
4/2011