a Serial Input 16-Bit

4 mA–20 mA, 0 mA–20 mA DAC

AD420
FEATURES FUNCTIONAL BLOCK DIAGRAM
4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA Current Output
16-Bit Resolution and Monotonicity VCC

ⴞ0.012% Max Integral Nonlinearity

VLL REFERENCE
ⴞ0.05% Max Offset (Trimmable) 4kV 40V
ⴞ0.15% Max Total Output Error (Trimmable) REF OUT
BOOST
AD420
Flexible Serial Digital Interface (3.3 MBPS)
REF IN
On-Chip Loop Fault Detection
DATA OUT CLOCK
On-Chip 5 V Reference (25 ppm/ⴗC Max) CLEAR IOUT
DATA I/P
Asynchronous CLEAR Function LATCH REGISTER SWITCHED
VOUT
16-BIT
Maximum Power Supply Range of 32 V CLOCK DAC CURRENT 1.25kV
DATA IN SOURCES
Output Loop Compliance of 0 V to VCC – 2.5 V FAULT
RANGE AND
24-Lead SOIC and PDIP Packages SELECT 1 FILTERING DETECT
RANGE
SELECT 2
PRODUCT DESCRIPTION
The AD420 is a complete digital to current loop output con- OFFSET CAP 1 CAP 2 GND
TRIM
verter, designed to meet the needs of the industrial control
market. It provides a high precision, fully integrated, low cost
single-chip solution for generating current loop signals in a
The AD420 is available in a 24-lead SOIC and PDIP over the
compact 24-lead SOIC or PDIP package.
industrial temperature range of –40°C to +85°C.
The output current range can be programmed to 4 mA–20 mA,
0 mA–20 mA or an overrange function of 0 mA–24 mA. The PRODUCT HIGHLIGHTS
AD420 can alternatively provide a voltage output from a sepa- 1. The AD420 is a single chip solution for generating 4 mA–
rate pin that can be configured to provide 0 V–5 V, 0 V–10 V, 20 mA or 0 mA–20 mA signals at the “controller end” of the
± 5 V or ± 10 V with the addition of a single external buffer current loop.
amplifier.
2. The AD420 is specified with a power supply range
The 3.3M Baud serial input logic design minimizes the cost of from 12 V to 32 V. Output loop compliance is 0 V to
galvanic isolation and allows for simple connection to com- VCC – 2.5 V.
monly used microprocessors. It can be used in three-wire or
3. The flexible serial input can be used in three-wire mode
asynchronous mode and a serial-out pin is provided to allow
with SPI® or MICROWIRE® microcontrollers, or in asyn-
daisy chaining of multiple DACs on the current loop side of the
chronous mode which minimizes the number of control
isolation barrier.
signals required.
The AD420 uses sigma-delta (Σ∆) DAC technology to achieve
4. The serial data out pin can be used to daisy chain any num-
16-bit monotonicity at very low cost. Full-scale settling to 0.1%
ber of AD420s together in three-wire mode.
occurs within 3 ms. The only external components that are re-
quired (in addition to normal transient protection circuitry) are 5. At power-up the AD420 initializes its output to the low end
two low cost capacitors which are used in the DAC output filter. of the selected range.
If the AD420 is going to be used at extreme temperatures and 6. The AD420 has an asynchronous CLEAR pin which sends
supply voltages, an external output transistor can be used to the output to the low end of the selected range (0 mA,
minimize power dissipation on the chip via the “BOOST” pin. 4 mA, or 0 V).
The FAULT DETECT pin signals when an open circuit occurs 7. The AD420 BOOST pin accommodates an external transis-
in the loop. The on-chip voltage reference can be used to supply tor to off-load power dissipation from the chip.
a precision +5 V to external components in addition to the 8. The offset of ± 0.05% and total output error of ± 0.15% can
AD420 or, if the user desires temperature stability exceeding be trimmed if desired, using two external potentiometers.
25 ppm/°C, an external precision reference such as the AD586
can be used as the reference.
SPI is a registered trademark of Motorola.
MICROWIRE is a registered trademark of National Semiconductor.

REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD420–SPECIFICATIONS (T = T A MIN –TMAX, VCC = +24 V, unless otherwise noted)
AX-32 Version1
Parameter Min Typ Max Units Comments
RESOLUTION 16 Bits
IOUT CHARACTERISTICS RL = 500 Ω
Operating Current Ranges 4 20 mA
0 20 mA
0 24 mA
Current Loop Voltage Compliance 0 VCC – 2.5 V V
Settling Time (to 0.1% of FS)2 2.5 3 ms
Output Impedance (Current Mode) 25 MΩ
Accuracy 3
Monotonicity 16 Bits
Integral Nonlinearity ± 0.002 ± 0.012 %
Offset (0 mA or 4 mA) (TA = +25°C) ± 0.05 %
Offset Drift 20 50 ppm/°C
Total Output Error (20 mA or 24 mA) (TA = +25°C) ± 0.15 %
Total Output Error Drift 20 50 ppm/°C
PSRR4 5 10 µA/V
VOUT CHARACTERISTICS
FS Output Voltage Range (Pin 17) 0 5 V
VOLTAGE REFERENCE
REF OUT
Output Voltage (T A = +25°C) 4.995 5.0 5.005 V
Drift ± 25 ppm/°C
Externally Available Current 5 mA
Short Circuit Current 7 mA
REF IN
Resistance 30 kΩ
VLL
Output Voltage 4.5 V
Externally Available Current 5 mA
Short Circuit Current 20 mA
DIGITAL INPUTS
VIH (Logic 1) 2.4 V
VIL (Logic 0) 0.8 V
IIH (V IN = 5.0 V) ± 10 µA
IIL (V IN = 0 V) ± 10 µA
Data Input Rate (“3-Wire” Mode) No Minimum 3.3 MBPS
Data Input Rate (“Asynchronous” Mode) No Minimum 150 kBPS
DIGITAL OUTPUTS
FAULT DEFECT
VOH (10 kΩ Pull-Up Resistor to V LL) 3.6 4.5 V
VOL (10 kΩ Pull-Up Resistor to V LL) 0.2 0.4 V
VOL @ 2.5 mA 0.6 V
DATA OUT
VOH (IOH = –0.8 mA) 3.6 4.3 V
VOL (IOL = 1.6 mA) 0.3 0.4 V
POWER SUPPLY
Operating Range V CC 12 32 V
Quiescent Current 4.2 5.5 mA
Quiescent Current (External VLL ) 3 mA
TEMPERATURE RANGE
Specified Performance –40 +85 °C
NOTES
1
X refers to package designator, R or N.
2
External capacitor selection must be as described in Figure 5.
3
Total Output Error includes Offset and Gain Error. Total Output Error and Offset Error are with respect to the Full-Scale Output and are measured with an ideal
+5 V reference. If the internal reference is used, the reference errors must be added to the Offset and Total Output Errors.
4
PSRR is measured by varying VCC from 12 V to its maximum 32 V.
Specifications subject to change without notice.

–2– REV. F
 AD420
ABSOLUTE MAXIMUM RATINGS* VCC
23
VCC to GND
VLL 2 REFERENCE
AD420AR/AN-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 V
4kV 40V
IOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC REF OUT 14
19 BOOST
AD420
Digital Inputs to GND . . . . . . . . . . . . . . . . . . . –0.5 V to +7 V
REF IN 15
Digital Output to GND . . . . . . . . . . . . . –0.5 V to VLL + 0.3 V
DATA OUT 10 CLOCK
VLL and REF OUT: Outputs Safe for Indefinite Short to Ground 18 IOUT
CLEAR 6
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C DATA I/P 17 VOUT
LATCH 7 REGISTER 16-BIT
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C DAC
SWITCHED
1.25kV
CLOCK 8 CURRENT
Thermal Impedance: DATA IN 9 SOURCES
SOIC (R) Package . . . . . . . . . . . . . . . . . . . . . . θJA = 75°C/W 3
FAULT
AND DETECT
RANGE 5
PDIP (N) Package . . . . . . . . . . . . . . . . . . . . . . θJA = 50°C/W SELECT 1 FILTERING
RANGE 4
*Stresses above those listed under Absolute Maximum Ratings may cause perma- SELECT 2
16 20 21 11
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational OFFSET CAP 1 CAP 2 GND
TRIM
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Figure 1. Functional Block Diagram

ORDERING GUIDE Table I. Truth Table

Temperature Max Operating Package Inputs
Model Range Voltage Options*
Range Range
AD420AN-32 – 40°C to +85°C 32 V N-24 CLEAR Select 2 Select 1 Operation
AD420AR-32 – 40°C to +85°C 32 V R-24
0 X X Normal Operation
*N = Plastic DIP, R = Plastic SOIC.
1 X X Output at Bottom of Span
PIN DESIGNATIONS X 0 0 0 V–5 V Range
X 0 1 4 mA–20 mA Range
X 1 0 0 mA–20 mA Range
NC NC
X 1 1 0 mA–24 mA Range
VL L VCC
FAULT DETECT NC
RANGE SELECT 2 CAP2
RANGE SELECT 1 CAP1
AD420
CLEAR TOP VIEW BOOST
LATCH (Not to Scale)
IOUT
CLOCK VOUT
DATA IN OFFSET TRIM
DATA OUT REF IN
GND REF OUT
NC NC

NC = NO CONNECT

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD420 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. F –3–
AD420
Timing Requirements (T = –40ⴗC to +85ⴗC, V A CC = +12 V to +32 V)
THREE-WIRE INTERFACE
CLOCK
CLOCK

WORD "N" WORD "N + 1" DATA IN 0 1 0 0 1

BIT 15
1 0

START
BIT

BIT 14

BITs
13-1

STOP
BIT
1 1 0 0 1

BIT 0

NEXT
START
BIT
DATA IN 0 0 111 0 0 1 1 1 0 0 1
(MSB)

B13
B12
B11
B10

B15
B14
B13
B12
B9
B8
B7
B6
B5
B4

B3
B2
B1
B0
B15
B14

(LSB)
(INTERNALLY GENERATED LATCH)
LATCH
EXPANDED TIME VIEW BELOW
WORD "N – 1" WORD "N"
CLOCK COUNTER STARTS HERE
DATA OUT 1 0 1 1 CONFIRM START BIT SAMPLE BIT 15

B14
B13
B12
tCK B15
CLOCK
tCL
CLOCK 0 1 2 8 16 24
tCH
tDH DATA IN START BIT DATA BIT 15 BIT 14
tDS

DATA IN
EXPANDED TIME VIEW BELOW
tDW tACK
tACL
tLD
tLL CLOCK
LATCH tACH
tLH
tADS tADH
tSD tADW
DATA OUT DATA IN

Figure 2. Timing Diagram for Three-Wire Interface Figure 3. Timing Diagram for Asynchronous Interface

Table II. Timing Specification for Three-Wire Interface Table III. Timing Specifications for Asynchronous Interface

Parameter Label Limit Units Parameter Label Limit Units

Data Clock Period tCK 300 ns min Asynchronous Clock Period tACK 400 ns min
Data Clock Low Time tCL 80 ns min Asynchronous Clock Low Time tACL 50 ns min
Data Clock High Time tCH 80 ns min Asynchronous Clock High Time tACH 150 ns min
Data Stable Width tDW 125 ns min Data Stable Width (Critical Clock Edge) tADW 300 ns min
Data Setup Time tDS 40 ns min Data Setup Time (Critical Clock Edge) tADS 50 ns min
Data Hold Time tDH 5 ns min Data Hold Time (Critical Clock Edge) tADH 20 ns min
Latch Delay Time tLD 80 ns min Clear Pulsewidth tCLR 50 ns min
Latch Low Time tLL 80 ns min
Latch High Time tLH 80 ns min
ASYNCHRONOUS INTERFACE
Serial Output Delay Time tSD 225 ns max
Note in the timing diagram for asynchronous mode operation
Clear Pulsewidth tCLR 50 ns min
each data word is “framed” by a START (0) bit and a STOP
Three-Wire Interface Fast Edges on Digital Input (1) bit. The data timing is with respect to the rising edge of the
With a fast rising edge (<10 ns) on one of the serial inputs CLOCK at the center of each bit cell. Bit cells are 16 clocks
(CLOCK, DATA IN, LATCH) while another input is logic long, and the first cell (the START bit) begins at the first clock
high, the part may be triggered into a test mode and the con- following the leading (falling) edge of the START bit. Thus the
tents of the data register may become corrupted, which may MSB (D15) is sampled 24 clock cycles after the beginning of
result in the output being loaded with an incorrect value. If fast the START bit, D14 is sampled at clock number 40, and so on.
edges are expected on the digital input lines, it is recommended During any “dead time” before writing the next word the
that the latch line remain at Logic 0 during serial loading of the DATA IN pin must remain at Logic 1.
DAC. Similarly, the clock line should remain low during updates The DAC output updates when the STOP bit is received. In
of the DAC via the latch pin. Alternatively, the addition of the case of a “framing error” (the STOP bit sampled as a 0) the
small value capacitors on the digital lines will slow down the AD420 will output a pulse at the DATA OUT pin one clock
edge. period wide during the clock period subsequent to sampling the
STOP bit. The DAC output will not update if a “framing error”
is detected.

–4– REV. F
 AD420
PIN DESCRIPTION

Pin # Symbol Function

1, 12, 13, 24 NC No Connection. No internal connections inside device.
2 VLL Auxiliary buffered +4.5 V digital logic voltage. This pin is the internal supply voltage
for the digital circuitry and can be used as a termination for pull-up resistors. An
external +5 V power supply can be connected to VLL. It will override this buffered
voltage, thus reducing the internal power dissipation. The VLL pin should be decoupled
to GND with a 0.1 µF capacitor. See Power Supplies and Decoupling section.
3 FAULT DETECT FAULT DETECT, connected to a pull-up resistor, is asserted low when the
output current does not match the DAC’s programmed value, for example, in
case the current loop is broken.
4 RANGE SELECT 2 Selects the converter’s output operating range. One output voltage range and three
5 RANGE SELECT 1 output current ranges are available.
6 CLEAR Valid VIH will unconditionally force the output to go to the minimum of its
programmed range. After CLEAR is removed the DAC output will remain at this
value. The data in the input register is unaffected.
7 LATCH In the three-wire interface mode a rising edge parallel loads the serial input register
data into the DAC. To use the asynchronous mode connect LATCH through a
current limiting resistor to VCC.
8 CLOCK Data Clock Input. The clock period is equal to the input data bit rate in the three-
wire interface mode and is 16 times the bit rate in asynchronous mode.
9 DATA IN Serial Data Input.
10 DATA OUT Serial Data Output. In the three-wire interface mode, this output can be used for
daisy-chaining multiple AD420s. In the asynchronous mode a positive pulse will
indicate a framing error after the stop-bit is received.
11 GND Ground (Common).
14 REF OUT +5 V Reference Output.
15 REF IN Reference Input.
16 OFFSET TRIM Offset Adjust.
17 VOUT Voltage Output.
18 IOUT Current Output.
19 BOOST Connect to an external transistor to reduce the power dissipated in the AD420
output transistor, if desired.
20 CAP 1 These pins are used for internal filtering. Connect capacitors between each of these
21 CAP 2 pins and VCC. Refer to the description of current output operation.
22 NC No Connection. Do not connect anything to this pin.
23 VCC Power Supply Input. The VCC pin should always be decoupled to GND with a
0.1 µF capacitor. See Power Supplies and Decoupling section.

DEFINITIONS OF SPECIFICATIONS GAIN ERROR: Gain error is a measure of the output error
RESOLUTION: For 16-bit resolution, 1 LSB = 0.0015% of the between an ideal DAC and the actual device output with all 1s
FSR. In the 4 mA–20 mA range 1 LSB = 244 nA. loaded after offset error has been adjusted out.
INTEGRAL NONLINEARITY: Analog Devices defines inte- OFFSET ERROR: Offset error is the deviation of the output
gral nonlinearity as the maximum deviation of the actual, ad- current from its ideal value expressed as a percentage of the full-
justed DAC output from the ideal analog output (a straight line scale output with all 0s loaded in the DAC.
drawn from 0 to FS – 1 LSB) for any bit combination. This is DRIFT: Drift is the change in a parameter (such as gain and
also referred to as relative accuracy. offset) over a specified temperature range. The drift temperature
DIFFERENTIAL NONLINEARITY: Differential nonlinearity coefficient, specified in ppm/°C, is calculated by measuring the
is the measure of the change in the analog output, normalized to parameter at TMIN, 25°C, and T MAX and dividing the change in
full scale, associated with an LSB change in the digital input code. the parameter by the corresponding temperature change.
Monotonic behavior requires that the differential linearity error be CURRENT LOOP VOLTAGE COMPLIANCE: The voltage
greater than –1 LSB over the temperature range of interest. compliance is the maximum voltage at the IOUT pin for which
MONOTONICITY: A DAC is monotonic if the output either the output current will be equal to the programmed value.
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.

REV. F –5–
AD420
THEORY OF OPERATION one volt remaining of drive capability (when the gate of the
The AD420 uses a sigma-delta (Σ∆) architecture to carry out output PMOS transistor nearly reaches ground). Thus the
the digital-to-analog conversion. This architecture is particularly FAULT DETECT output activates slightly before the compli-
well suited for the relatively low bandwidth requirements of the ance limit is reached. Since the comparison is made within the
industrial control environment because of its inherent monoto- feedback loop of the output amplifier, the output accuracy is
nicity at high resolution. maintained by its open-loop gain, and no output error occurs
before the fault detect output becomes active.
In the AD420 a second order modulator is used to keep com-
plexity and die size to a minimum. The single bit stream from The three-wire digital interface, comprising DATA IN, CLOCK,
the modulator controls a switched current source that is then and LATCH, interfaces to all commonly used serial micropro-
filtered by two, continuous time resistor-capacitor sections. The cessors without the addition of any external glue logic. Data is
capacitors are the only external components that have to be loaded into an input register under control of CLOCK and is
added for standard current-out operation. The filtered current is loaded to the DAC when LATCH is strobed. If a user wants to
amplified and mirrored to the supply rail so that the application minimize the number of galvanic isolators in an intrinsically safe
simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA application, the AD420 can be configured to run in “asynchro-
current source output with respect to ground. The AD420 is nous” mode. This mode is selected by connecting the LATCH
manufactured on a BiCMOS process that is well suited to imple- pin to VCC through a current limiting resistor. The data must
menting low voltage digital logic with high performance and then be combined with a start and stop bit to “frame” the infor-
high voltage analog circuitry. mation and trigger the internal LATCH signal.
The AD420 can also provide a voltage output instead of a cur- VCC
rent loop output if desired. The addition of a single external 23
amplifier allows the user to obtain 0 V–5 V, 0 V–10 V, ±5 V, or VLL 2 REFERENCE
± 10 V. 4kV 40V
REF OUT 14
AD420 19 BOOST
The AD420 has a loop fault detection circuit that warns if the
voltage at IOUT attempts to rise above the compliance range, due REF IN 15

to an open-loop circuit or insufficient power supply voltage. The DATA OUT 10 CLOCK
CLEAR 6
18 IOUT
FAULT DETECT is an active low open drain signal so that one DATA I/P 17 VOUT
LATCH 7
can connect several AD420s together to one pull-up resistor for REGISTER 16-BIT SWITCHED
1.25kV
CLOCK 8 DAC CURRENT
global error detection. The pull-up resistor can be tied to the SOURCES
DATA IN 9 FAULT
VLL pin, or an external +5 V logic supply. RANGE 5
AND 3
DETECT
SELECT 1 FILTERING
The I OUT current is controlled by a PMOS transistor and RANGE 4
internal amplifier as shown in the functional block diagram. The SELECT 2
16 20 21 11
internal circuitry that develops the fault output avoids using a OFFSET CAP 1 CAP 2 GND
comparator with “window limits” since this would require an TRIM
actual output error before the FAULT DETECT output becomes
Figure 4. Functional Block Diagram
active. Instead, the signal is generated when the internal ampli-
fier in the output stage of the AD420 has less than approximately

–6– REV. F
 AD420
APPLICATIONS Table IV. Buffer Amplifier Configuration
CURRENT OUTPUT
The AD420 can provide 4 mA–20 mA, 0 mA–20 mA, or 0 mA– R1 R2 R3 VOUT
24 mA output without any active external components. Filter Open Open 0 0 V–5 V
capacitors C1 and C2 can be any type of low cost ceramic ca- Open R R 0 V–10 V
pacitors. To meet the specified full-scale settling time of 3 ms, R Open R ±5 V
low dielectric absorption capacitors (NPO) are required. Suit- R 2R 2R ± 10 V
able values are C1 = 0.01 µF and C2 = 0.01 µF.
Suitable R = 5 kΩ.
VCC
0.1mF 0.1mF OPTIONAL SPAN AND ZERO TRIM
VLL
C1 C2 For those users who would like lower than specified values of
offset and gain error, Figure 7 shows a simple way to trim these
2 20 21 23
RANGE
5
parameters. Care should be taken to select low drift resistors
SELECT 1
because they will affect the temperature drift performance of the
RANGE 4
SELECT 2 IOUT (4mA–20mA) DAC.
CLEAR 6 18
AD420 The adjustment algorithm is iterative. The procedure for trim-
LATCH 7 RLOAD
ming the AD420 in the 4 mA–20 mA mode can be accom-
CLOCK 8
plished as follows:
DATA IN 9
14 15 11 STEP I . . . OFFSET ADJUST
REF REF GND
OUT IN Load all zeros. Adjust RZERO for 4.00000 mA of output
current.
Figure 5. Standard Configuration STEP II . . . GAIN ADJUST
Load all ones. Adjust RSPAN for 19.99976 mA (FS – 1 LSB) of
DRIVING INDUCTIVE LOADS output current.
When driving inductive or poorly defined loads connect a
0.01 µF capacitor between IOUT (Pin 18) and GND (Pin 11). Return to STEP I and iterate until convergence is obtained.
This will ensure stability of the AD420 with loads beyond
VCC
50 mH. There is no maximum capacitance limit. The capacitive
VLL
component of the load may cause slower settling, though this C1 C2
0.1mF 0.1mF
may be masked by the settling time of the AD420. A pro-
20 21 23 5kV
grammed change in the current may cause a back EMF voltage RANGE
2
RSPAN2
5
on the output that may exceed the compliance of the AD420. SELECT1
19 BOOST
RANGE 4
To prevent this voltage from exceeding the supply rails connect SELECT2
protective diodes between IOUT and each of VCC and GND. CLEAR 6 IOUT (4mA–20mA)
AD420 18
LATCH 7
RLOAD
VOLTAGE-MODE OUTPUT CLOCK 8
Since the AD420 is a single supply device, it is necessary to add DATA IN 9
an external buffer amplifier to the VOUT pin to obtain a selec- 14 15 16 11
tion of bipolar output voltage ranges as shown in Figure 6. VREF
500V
RSPAN
VCC
VLL 10kV GND
RZERO
0.1mF C1 C2 0.1mF

2 20 21 23 Figure 7. Offset and Gain Adjust

RANGE
5
SELECT 1
VOUT Variation of RZERO between REF OUT (5 V) and GND leads
RANGE 4 17 to an offset adjust range from –1.5 mA to 6 mA, (1.5 mA/V
SELECT 2 VOUT
CLEAR 6
AD420
centered at 1 V).
R3
LATCH 7 The 5 kΩ RSPAN2 resistor is connected in parallel with the
CLOCK 8 R1 R2 internal 40 Ω sense resistor, which leads to a gain increase of
DATA IN 9 +0.8%.
15 11
As RSPAN is changed to 500 Ω, the voltage on REF IN is
14
REF REF GND
OUT IN
attenuated by the combination of RSPAN and the 30 kΩ
REF IN input resistance. When added together with RSPAN2
Figure 6. this results in an adjustment range of –0.8% to +0.8%.

REV. F –7–
AD420
THREE-WIRE INTERFACE ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS
Figure 8 shows the AD420 connected in the three-wire interface The AD420 connected in ASYNCHRONOUS INTERFACE
mode. The AD420 data input block contains a serial input shift mode with optocouplers is shown in Figure 9. Asynchronous
register and a parallel latch. The contents of the shift register are operation minimizes the number of control signals required for
controlled by the DATA IN signal and the rising edges of the isolation of the digital system from the control loop. The resistor
CLOCK. Upon request of the LATCH pin the DAC and inter- connected between the LATCH pin and VCC is required to
nal latch are updated from the shift register parallel outputs. activate this mode. For operation with VCC below 18 V use a
The CLOCK should remain inactive while the DAC is updated. 50 kΩ pull-up resistor, from 18 V–32 V use 100 kΩ. Asynchro-
Refer to the timing requirements for three-wire interface. nous mode requires that the clock run at 16 times the data bit
rate, therefore to operate at the maximum input data rate of
FAULT DETECT 150 kBPS an input clock of 2.4 MHz is required. The actual
VCC VCC data rate achieved may be limited by the type of optocouplers
VLL chosen. The number of control signals can further be reduced
VCC 10kV VCC
FAULT FAULT
by creating the appropriate clock signal on the current loop side
DETECT DETECT of the isolation barrier. If optocouplers with relatively slow rise
LATCH
LATCH
AD420
LATCH
AD420 and fall times are used, Schmitt triggers may be required on the
CLOCK digital inputs to prevent erroneous data being presented to the
CLOCK DAC1 CLOCK DAC2
DATA IN DATA DATA DATA DATA
DAC.
IN OUT IN OUT
GND IOUT GND IOUT +24V
RLOAD RLOAD 23 VCC
100kV
7 LATCH
Figure 8. Three-Wire Interface Using Multiple DACs with 2 VLL
+5V
Joint Fault Detect
8 CLOCK
USING MULTIPLE DACS WITH FAULT DETECT CLOCK
AD420
The three-wire interface mode can utilize the serial DATA
OUT for easy interface to multiple DACs. To program the two 9 DATA IN
AD420s in Figure 8, 32 data bits are required. The first 16 bits DATA
11 GND
are clocked into the input shift register of DAC1. The next 16
bits transmitted pass the first 16 bits from the DATA OUT pin GALVANIC ISOLATION
of DAC1 to the input register of DAC2. The input shift regis- BARRIER

ters of the two DACs operate as a single 32-bit shift register, Figure 9. Asynchronous Interface Using Optocouplers
with the leading 16 bits representing information for DAC2 and
the trailing 16 bits serving for DAC1. Each DAC is then up-
dated upon request of the LATCH pin. The daisy-chain can be
extended to as many DACs as required.

–8– REV. F
 AD420
MICROPROCESSOR INTERFACE SECTION
SO DATA IN
AD420-TO-MC68HC11 (SPI BUS) INTERFACE MICROWIRE
The AD420 interface to the Motorola SPI (Serial Peripheral SK CLOCK AD420
Interface) is shown in Figure 10. The MOSI, SCK, and SS pins G1 LATCH
of the HC11 are respectively connected to the DATA IN,
CLOCK, and LATCH pins of the AD420. The majority of the Figure 11. AD420-to-MICROWIRE Interface
interfacing issues are done in the software initialization. A typi-
cal routine such as the one shown below begins by initializing EXTERNAL BOOST FUNCTION
the state of the various SPI data and control registers. The external boost transistor reduces the power dissipated in
INIT LDAA #$2F ;SS = 1; SCK = 0; MOSI = 1 the AD420 by reducing the current flowing in the on-chip
STAA PORTD ;SEND TO SPI OUTPUTS output transistor (dividing it by the current gain of the external
LDAA #$38 ;SS, SCK, MOSI = OUTPUTS circuit). A discrete NPN transistor with a breakdown voltage,
STAA DDRD ;SEND DATA DIRECTION INFO BVCEO, greater than 32 V can be used as shown in Figure 12.
LDAA #$50 ;DABL INTRPTS, SPI IS MASTER & ON
STAA SPCR ;CPOL = 0, CPHA = 0, 1MHZ BAUDRATE MJD31C
NEXTPT LDAA MSBY ;LOAD ACCUM W/UPPER 8 BITS OR
BOOST 19 2N3053
BSR SENDAT ;JUMP TO DAC OUTPUT ROUTINE
JMP NEXTPT ;INFINITE LOOP AD420
SENDAT LDY #$1000 ;POINT AT ON-CHIP REGISTERS IOUT 18
BCLR $08,Y,$20 ;DRIVE SS (LATCH) LOW
STAA SPDR ;SEND MS-BYTE TO SPI DATA REG 1kV RLOAD
WAIT1 LDAA SPSR ;CHECK STATUS OF SPIE 0.022mF
BPL WAIT1 ;POLL FOR END OF X-MISSION
LDAA LSBY ;GET LOW 8 BITS FROM MEMORY
STAA SPDR ;SEND LS-BYTE TO SPI DATA REG Figure 12. External Boost Configuration
WAIT2 LDAA SPSR ;CHECK STATUS OF SPIE
The external boost capability has been developed for those users
BPL WAIT2; ;POLL FOR END OF X-MISSION
BSET $08,Y,$20 ;DRIVE SS HIGH TO LATCH DATA who may wish to use the AD420, in the SOIC package, at the
RTS extremes of the supply voltage, load current, and temperature
range. The PDIP package (because of its lower thermal resis-
The SPI data port is configured to process data in 8-bit bytes. tance) will operate safely over the entire specified voltage, tem-
The most significant data byte (MSBY) is retrieved from perature, and load current ranges without the boost transistor.
memory and processed by the SENDAT routine. The SS pin is The plot in Figure 13 shows the safe operating region for both
driven low by indexing into the PORTD data register and clear package types. The boost transistor can also be used to reduce
Bit 5. The MSBY is then sent to the SPI data register where it is the amount of temperature induced drift in the part. This will
automatically transferred to the AD420 internal shift resister. minimize the temperature induced drift of the on-chip voltage
The HC11 generates the requisite eight clock pulses with data reference, which improves drift and linearity.
valid on the rising edges. After the MSBY is transmitted, the
least significant byte (LSBY) is loaded from memory and trans- WHEN USING SOIC PACKAGED DEVICES, AN
VCC EXTERNAL BOOST TRANSISTOR IS REQUIRED
mitted in a similar fashion. To complete the transfer, the FOR OPERATION IN THIS AREA
LATCH pin is driven high when loading the complete 16-bit
word into the AD420.
32V

28V
MOSI DATA IN
68HC11 25V
SCK CLOCK AD420
SS LATCH 20V

AD420 OR AD420-32
Figure 10. AD420-to-68HC11 (SPI) Interface
12V

AD420-TO-MICROWIRE INTERFACE
The flexible serial interface of the AD420 is also compatible 4V
with the National Semiconductor MICROWIRE interface. The
MICROWIRE interface is used in microcontrollers such as the –60 –40 –20 0 20 40 60 80 100
COP400 and COP800 series of processors. A generic interface TEMPERATURE – 8C

to use the MICROWIRE interface is shown in Figure 11. The Figure 13. Safe Operating Region
G1, SK, and SO pins of the MICROWIRE interface are respec-
tively connected to the LATCH, CLOCK, and DATA IN pins
of the AD420.

REV. F –9–
AD420
AD420 PROTECTION BOARD LAYOUT AND GROUNDING
TRANSIENT VOLTAGE PROTECTION The AD420 ground pin, designated GND, is the “high quality”
The AD420 contains ESD protection diodes which prevent ground reference point for the device. Any external loads on the
damage from normal handling. The industrial control environ- REF OUT and VOUT pins of the AD420 should be returned to
ment can, however, subject I/O circuits to much higher tran- this reference point. Analog and digital ground currents should
sients. In order to protect the AD420 from excessively high not share a common path. Each signal should have an appropri-
voltage transients such as those specified in IEC 801, external ate analog or digital signal return routed close to it. Using this
power diodes and a surge current limiting resistor may be re- approach, signal loops enclose a small area, minimizing the
quired, as shown in Figure 14. The constraint on the resistor is inductive coupling of noise. Wide PC tracks, large gauge wire,
that during normal operation the output voltage level at IOUT and ground planes are highly recommended to provide low
must remain within its voltage compliance limit impedance signal paths.
(IOUT × (Rp + RLOAD) ≤ VCC – 2.5 V)
POWER SUPPLIES AND DECOUPLING
and the two protection diodes and resistor must have appropri- The AD420 supply pins, VCC (Pin 23) and VLL (Pin 2), should
ate power ratings. be decoupled to GND with 0.1 µF capacitors to eliminate high
frequency noise that may otherwise get coupled into the analog
VCC
system. High frequency ceramic capacitors are recommended.
The decoupling capacitors should be located in close proximity
VCC to the pins and the ground line to have maximum effect. Further
RP reductions in noise, and improvements in performance, may be
AD420 IOUT
achieved by using a larger value capacitor on the VLL pin.
GND RLOAD

Figure 14. Output Transient Voltage Protection

–10– REV. F
 AD420
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

24-Lead Plastic DIP

(N-24)

C1870e–0–9/99
1.275 (32.30)
1.125 (28.60)

24 13
0.280 (7.11)
1 12 0.240 (6.10)
0.325 (8.25)
0.060 (1.52) 0.300 (7.62) 0.195 (4.95)
PIN 1 0.015 (0.38) 0.115 (2.93)
0.210
(5.33)
MAX 0.150
(3.81)
MIN
0.015 (0.381)
0.200 (5.05) 0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204)
0.125 (3.18) 0.014 (0.356) (2.54) PLANE
0.045 (1.15)
BSC

24-Lead Small Outline (SOIC)

(R-24)

0.6141 (15.60)
0.5985 (15.20)

24 13
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)

1 12

PIN 1 0.1043 (2.65) 0.0291 (0.74)

x 45°
0.0926 (2.35) 0.0098 (0.25)

8° 0.0500 (1.27)
0.0500 0.0192 (0.49)
0.0118 (0.30)
(1.27) SEATING 0.0125 (0.32) 0° 0.0157 (0.40)
0.0040 (0.10) 0.0138 (0.35) PLANE
BSC 0.0091 (0.23)

PRINTED IN U.S.A.

REV. F –11–