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Lecture 8: Verilog Code: EE533: Network Processor Design and Programming

This document provides an overview of Verilog code, including: 1) A brief history of Verilog and its development as a hardware descriptive language. 2) An introduction to different modeling approaches in Verilog like behavioral, dataflow, and structural. 3) Descriptions of key Verilog concepts such as modules, ports, data types, always blocks, non-blocking assignments, and memory instantiation. 4) Examples of combinational and sequential logic coding styles and the use of clocks, resets, and enable signals.

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Ahmed Hamouda
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160 views28 pages

Lecture 8: Verilog Code: EE533: Network Processor Design and Programming

This document provides an overview of Verilog code, including: 1) A brief history of Verilog and its development as a hardware descriptive language. 2) An introduction to different modeling approaches in Verilog like behavioral, dataflow, and structural. 3) Descriptions of key Verilog concepts such as modules, ports, data types, always blocks, non-blocking assignments, and memory instantiation. 4) Examples of combinational and sequential logic coding styles and the use of clocks, resets, and enable signals.

Uploaded by

Ahmed Hamouda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lecture 8: Verilog Code

EE533: Network Processor Design and Programming

Instructor: Young Cho


History

• Need: a simple, intuitive and effective


way of describing digital circuits for
modeling, simulation and analysis.
• Developed in 1984-85 by Philip Moorby
• In 1990 Cadence opened the language
to the public
• Standardization of language by IEEE in
1995
Design Approach
Hardware Descriptive Language
• There are many different systems for modeling and
simulating hardware.
– Verilog
– VHDL
– L-language, M-language (Mentor)
– DECSIM (DEC)
– Aida (IBM / HaL)
• Two most popular languages are Verilog and VHDL.
– For this class we will be using Verilog
– Have both a simulator and synthesis tools that work with Verilog
Syntax
• Module Definition
– module name (port1, port2, port3, port4, ...);
• Port Definition
– output port1;
– input port2, port3;
– inout port4;
– reg port1; // output ports are usually defined as registers
– reg variable1, variable2; // definitions of local registered variables
– wire variable3; // without register
• Behavioral Statements
– initial
– always
– assign
– continuous-assign-statements // required for nets
• Module Instantiation
– mod1 mod1Instance (variable1, variable2, ...) // instantiating lower level
Data Types
• NETS –
– Represent the physical connection between entities.
– They hold the value of their drivers which changes continuously
by the driving circuit.
– ”wire” is the most frequently used type.
– declared as an input or in-out port.
• Registers
– The register variables are used in procedural blocks which store
values from one assignment to the next.
– Some register data types are: reg, integer, time and real

When the reg or wire size is more than one bit


then register and wire are declared as vectors.
Behavioral

Behavioral
• Implementation in terms of the desired design algorithm
without concern for the hardware implementation details.
module Mux_4to1(
input [3:0] i,
input [1:0] s,
output reg o
);

always @(s or i)
begin
case (s)
2'b00 : o = i[0];
2'b01 : o = i[1];
2'b10 : o = i[2];
2'b11 : o = i[3];
default : o = 1'bx;
endcase
end
endmodule
Dataflow

• The module is designed by specifying the data flow.

module Mux_4to1_df(
input [3:0] i,
input [1:0] s,
output o
);

assign o = (~s[1] & ~s[0] & i[0]) | (~s[1] & s[0] & i[1]) | (s[1] & ~s[0] & i[2]) | (s[1] & s[0] & i[3]);
endmodule
Structural

• The module is implemented in terms of logic gates and


interconnections between these gates.
module Mux_4to1_gate(
input [3:0] i,
input [1:0] s,
output o
);

wire NS0, NS1;


wire Y0, Y1, Y2, Y3;
not N1(NS0, s[0]);
not N2(NS1, s[1]);
and A1(Y0, i[0], NS1, NS0);
and A2(Y1, i[1], NS1, s[0]);
and A3(Y2, i[2], s[1], NS0);
and A4(Y3, i[3], s[1], s[0]);
or O1(o, Y0, Y1, Y2, Y3);
endmodule
Assignments – Continuous and Procedural

Continuous assignments Procedural assignments


• Models combinational logic • Models combinational and sequential logic
• Assigns values to data-types net • Assigns values to data-types reg
module and(a, b, out); module and(a, b, out);
input a, b; input a, b;
output out; output out;
wire out; reg out;
assign out = #1 a & b; always @(a or b)
endmodule begin
• Is evaluated as soon as one of the RHS Out <= #1 a&b;
operand changes and value is assigned end
to LHS endmodule
• Out is continuously driven • Out will remain unchanged until the always
block is executed again
Examples - Modeling and testbench

module nand2(in1, in2, Out); module top;


input in1, in2; reg a, b;
output Out; wire out;
reg Out;
nand2 i1(a,b, out);
always @(in1 or in2)
initial
begin
begin
Out = ~(in1 & in2); a = 0; b = 0;
end #5
a = 0; b = 1;
endmodule #5
end
endmodule
Always/Initial

• Initial
– Starts at time 0
– Executes only once
– Is typically used for initialization in behavioral code (e.g., testbenches)
– Syntax
initial
begin
a = 1’b1;
b = 1’b0;
end
• Always
– Starts at time 0
– Executes as an infinite loop similar to a infinite loop in C
– Syntax
always
begin
#5 clock = ~clock;
end
Always

When is an always block executed?


• always
 Starts at time 0
• always @(a or b or c)
 Whenever there is a change on a, b, or c
• always @(posedge clk)
 Whenever clk goes from low to high
• always @(negedge bar)
 Whenever bar goes from high to low
Blocking assignments

• Statements are executed in order like Von-Neuman.


• Example
always
begin
X = 0;
Y = #10 1;
Z = #20 1;
End
• X = 0 will happen at time t = 0
• Y = 1 will happen at time t = 10
• Z = 1 will happen at time t = 30
Non Blocking assignments

• Statements are executed without blocking execution of following


statements - more like the hardware
• Example
always
begin
X <= 0;
Y <= #10 1;
Z <= #20 1;
End
• X = 0 will happen at time t = 0
• Y = 1 will happen at time t = 10
• Z = 1 will happen at time t = 20
NEVER MIX BLOCKING AND NON-BLOCKING !
begin/end and fork/join statements

• begin/end
– Event happens in sequence
– Example
Begin
#10 a=1; At time = 10, a is set to 1
#20 b=1; At time = 30, b is set to1
End
– control passes out of the block after the last statement executes
• fork/join
– Event happens in parallel
– Example
fork
#10 a=1; At time = 10, a is set to 1
#20 b=1; At time = 20, b is set to1
Join
– control passes out of the block after time 20
Combinational Circuit Example I

• Include all input signals to sensitivity list.


// Poor coding for AND gate.
always @(a) // missing “b” signal
begin
if ((a == 1’b1) and (b == 1’b1)) // if “a” and “b”
is 1
c = 1’b1; // set “c” to 1
else
c = 1’b0; // set “c” to 0
end
Combinational Circuit Example I
• Recommended coding for AND gate.

always @(a or b) // include both “a” and


“b”
begin // in sensitivity list.
if ((a == 1’b1) and (b == 1’b1)) // if “a” and
“b” is 1
c = 1’b1; // set “c” to 1
else
c = 1’b0; // otherwise, set “c” to 0
Combinational Circuit Example II

• Poor coding style: missing “else


statement”.

always @(a or b)
begin
if (a == 1’b1)
q = b;
// missing “else statement” infers latch.
end
end
Combinational Circuit Example II

• Recommended coding style.

always @(a or b)
begin
if (a == 1’b1)
q = b;
else // include “else statement”
q = 1’b0;
end
Combinational Circuit Example III

• Missing assignments and condition.

always @(d)
begin
case (d)
2’b00: z = 1’b1; // missing “s” assignment
2’b01: z = 1’b0; // missing “s” assignment
2’b10: z = 1’b1; s = 1’b1;
// missing condition “2’b11”.
endcase
end
Sequential process assignment
• Use non-blocking assign. in always @(posedge clk) block
// Poor coding style
always @(posedge clk)
b = a; // assignment of values depends on which
always @(posedge clk) // always block scheduler chooses
a = b; // first

// Recommended coding style


always @(posedge clk) begin
b <= a; // both signals are assigned at the clk edge
a <= b;
end
Sequential circuit with sync reset
• Process with synchronous reset.

always @(posedge clk)


begin
if (rst == 1’b1) // synchronous when “rst” is 1
begin
… // reset condition
end
else
begin
...
end
end
Sequential circuit w/ async reset

• Process with asynchronous reset

always @(posedge clk or posedge rst)


begin
if (rst == 1’b1) // async. reset when “rst” is 1
begin
… // reset condition
end
else
begin
…
end
end
Example of D-FF w/ asynch reset
module ASYNC_FF (d, clk, rst, q);
input d;
input clk;
input rst;
output q;
req q;

always @posedge clk or negedge RST)


if (!RST) // reset when “RST” is 0
q <= 0; // set “q” to 0
else // at the positive clk edge
q <= d; // set “q” to input “d”
Enable pos edge flip-flop

module pos_ff(clk, in, en, out)


input clk, en;
input [7:0] in;
output [7:0] out;
reg[7:0] out;

always @(posedge clk) begin


if (en == 1’b1)
in = out;
end
endmodule
Memory Instantiation
• 2D Register Array
• Earlier FPGAs
– FPGA LUT
– In the order of KB
– More slices for support circuit
• Modern FPGAs
– Embedded SRAM Modules
– In the order of MB
Memory Instantiation .. Continued
• There is no FOR loop in VERILOG to initialize or load
multiple data into memory.

always @(posedge clk)


begin
if (reset) begin
Counter <= 0;
…..
end
else begin
Counter <= Counter + 1
case (counter)
memory [16] <= 32’hCAFE_BEEF;
….
end case
end
…..
end

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