Module 3
Module 3
Kirchhoff’s current law (KCL) states that the algebraic sum of currents entering a node (or a
closed boundary) is zero.
Mathematically, KCL implies that ∑𝑁 𝑛=1 𝑖𝑛 = 0 where N is the number of branches connected to
the node and in is the nth current entering (or leaving) the node. By this law, currents entering a
node may be regarded as positive, while currents leaving the node may be taken as negative or
vice versa.
Since currents 𝑖 1, 𝑖 3, and 𝑖 4 are entering the node, while the currents 𝑖 2 and 𝑖 5 are leaving it. By
rearranging the terms, we get
𝑖1 + 𝑖 3 + 𝑖 4 = 𝑖 2 + 𝑖 5
The sum of the currents entering a node is equal to the sum of the currents leaving the node.
Note that KCL also applies to a closed boundary. This may be regarded as a generalized case,
because a node may be regarded as a closed surface shrunk to a point. In two dimensions, a closed
boundary is the same as a closed path. As typically illustrated in the circuit of Figure 3.2, the total
current entering the closed surface is equal to the total current leaving the surface.
COLLEGE OF ENGINEERING
EE 419- BASIC ELECTRICAL ENGINEERING
ENGR. ERICKA RULLODA – GUEST LECTURER
BATANGAS STATE UNIVERSITY
Figure 3.3 Current sources in parallel: (a) original circuit, (b) equivalent circuit.
A circuit cannot contain two different currents, I1 and I2, in series, unless I1= I2; otherwise KCL
will be violated.
Kirchoff’s voltage law (KVL) states that the algebraic sum of all voltages around a closed path
(or loop) is zero.
Expressed mathematically, KVL states that ∑𝑀 𝑚=1 𝑣𝑚 = 0 where M is the number of voltages in
the loop (or the number of branches in the loop) and vm is the mth voltage.
To illustrate KVL, consider the circuit in Figure 3.4. The sign on each voltage is the polarity of
the terminal encountered first as we travel around the loop. We can start with any branch and go
around the loop. We can start with any branch and go around the loop either clockwise or
counterclockwise. Suppose we start with the voltage source and go clockwise.
Suppose we start with the voltage source and go clockwise around the loop as shown; then voltages
would be –v1 , + v2 + v3 , -v4 and v5, in that order. For example, as we teach branch 3, the positive
terminal is met first; hence, we have +v3. For branch 4, we reach the negative terminal first; hence,
-v4. Thus KVL yields
–v1 + v2 + v3 -v4 + v5 = 0 eqn.3
COLLEGE OF ENGINEERING
EE 419- BASIC ELECTRICAL ENGINEERING
ENGR. ERICKA RULLODA – GUEST LECTURER
BATANGAS STATE UNIVERSITY
When the voltage sources are connected in series, KVL can be applied to obtain the total voltage.
The combined voltage is the algebraic sum of the voltage. The combined voltage is the algebraic
sum of the voltages of the individual sources. For example, for the voltage sources shown in Fig
3.5(a), the combined or equivalent voltage source in figure 3.5(b) is obtained by applying KVL.
To avoid violating KVL, a circuit cannot contain two different voltages V1 and V2 in parallel unless
V1 = V2.
Figure 3.5 Voltage sources in series: (a) original circuit, (b) equivalent circuit
COLLEGE OF ENGINEERING
EE 419- BASIC ELECTRICAL ENGINEERING
ENGR. ERICKA RULLODA – GUEST LECTURER
BATANGAS STATE UNIVERSITY
1. For the circuit in figure below (a), find voltages v1 and v2.
COLLEGE OF ENGINEERING
EE 419- BASIC ELECTRICAL ENGINEERING
ENGR. ERICKA RULLODA – GUEST LECTURER
BATANGAS STATE UNIVERSITY
COLLEGE OF ENGINEERING
EE 419- BASIC ELECTRICAL ENGINEERING
ENGR. ERICKA RULLODA – GUEST LECTURER