High Performance, 3.

2 GHz, 14-Output
Jitter Attenuator with JESD204B
Data Sheet HMC7044
FEATURES APPLICATIONS
Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at JESD204B clock generation
2457.6 MHz Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
Noise floor: −156 dBc/Hz at 2457.6 MHz Data converter clocking
Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output Microwave baseband cards
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) Phase array reference distribution
from PLL2
GENERAL DESCRIPTION
Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx
frequency up to 3200 MHz The HMC7044 is a high performance, dual-loop, integer-N
JESD204B-compatible system reference (SYSREF) pulses jitter attenuator capable of performing reference selection and
25 ps analog, and ½ VCO cycle digital delay independently generation of ultralow phase noise frequencies for high speed data
programmable on each of 14 clock output channels converters with either parallel or serial (JESD204B type) interfaces.
SPI-programmable phase noise vs. power consumption The HMC7044 features two integer mode PLLs and overlapping
SYSREF valid interrupt to simplify JESD204B synchronization on-chip VCOs that are SPI-selectable with wide tuning ranges
Narrow-band, dual core VCOs around 2.5 GHz and 3 GHz, respectively. The device is designed to
Up to 2 buffered voltage controlled oscillator (VCXO) outputs meet the requirements of GSM and LTE base station designs and
Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes offers a wide range of clock management and distribution
Frequency holdover mode to maintain output frequency features to simplify baseband and radio card clock tree designs.
Loss of signal (LOS) detection and hitless reference switching The HMC7044 provides 14 low noise and configurable outputs
4× GPIOs alarms/status indicators to determine the health of to offer flexibility in interfacing with many different components
the system including data converters, field-programmable gate arrays
External VCO input to support up to 6000 MHz (FPGAs), and mixer local oscillators (LOs).
On-board regulators for excellent PSRR The DCLK and SYSREF clock outputs of the HMC7044 can be
68-lead, 10 mm × 10 mm LFCSP_VQ configured to support signaling standards, such as CML, LVDS,
LVPECL, and LVCMOS, and different bias settings to offset
varying board insertion losses.

FUNCTIONAL BLOCK DIAGRAM

OSCIN
CPOUT1 OSCIN CPOUT2 OSCOUT1 OSCOUT1

CLKOUT0
CLKOUT0
CLKIN0/RFSYNCIN
SCLKOUT1
CLKIN0/RFSYNCIN SCLKOUT1
CLKIN1/FIN ÷
CLKOUT2
CLKIN1/FIN PLL1 PLL2 CLKOUT2
CLKIN2/OSCOUT0 SCLKOUT3
CLKIN2/OSCOUT0 SCLKOUT3
CLKIN3
CLKIN3
CLKOUT12
CLKOUT12
÷
SCLKOUT13
SYSREF SCLKOUT13
SYNC CONTROL
SPI 14-CLOCK
CONTROL DISTRIBUTION
SDATA
INTERFACE
13033-001

SLEN SCLK

Figure 1.

Rev. C Document Feedback

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HMC7044 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1  Theory of Operation ...................................................................... 23 
Applications ...................................................................................... 1  Detailed Block Diagram ............................................................ 24 
General Description ......................................................................... 1  Dual PLL Overview .................................................................... 25 
Functional Block Diagram .............................................................. 1  Component Blocks—Input PLL (PLL1) ................................. 25 
Table of Contents ............................................................................. 2  Component Blocks—Output PLL (PLL2) .............................. 30 
Revision History ............................................................................... 2  Clock Output Network .............................................................. 31 
Specifications .................................................................................... 3  Reference Buffer Details ............................................................ 38 
Conditions ..................................................................................... 3  Typical Programming Sequence .............................................. 38 
Supply Current ............................................................................. 3  Power Supply Considerations .................................................. 39 
Digital Input/Output (I/O) Electrical Specifications .............. 4  SeriaL Control Port ........................................................................ 42 
PLL1 Characteristics .................................................................... 5  Serial Port Interface (SPI) Control .......................................... 42 
PLL2 Characteristics .................................................................... 7  Applications Information ............................................................. 43 
VCO Characteristics .................................................................... 8  PLL1 Noise Calculations ........................................................... 43 
Clock Output Distribution Characteristics .............................. 9  PLL2 Noise Calculations ........................................................... 43 
Spur Characteristics ................................................................... 10  Phase Noise Floor and Jitter ..................................................... 43 
Noise and Jitter Characteristics ................................................ 10  Control Registers ............................................................................ 44 
Clock Output Driver Characteristics....................................... 11  Control Register Map ................................................................ 44 
Absolute Maximum Ratings ......................................................... 13  Control Register Map Bit Descriptions................................... 52 
ESD Caution................................................................................ 13  Evaluation PCB Schematic............................................................ 69 
Pin Configuration and Function Descriptions .......................... 14  Evaluation PCB........................................................................... 69 
Typical Performance Characteristics ........................................... 17  Outline Dimensions ....................................................................... 71 
Typical Application Circuits ......................................................... 21  Ordering Guide .......................................................................... 71 
Terminology .................................................................................... 22 

REVISION HISTORY
9/2021—Rev. B to Rev. C Changes to Table 49 ....................................................................... 57
Change to Bit 5, Register 0x0001, Table 25................................. 44 Change to Table 75 ........................................................................ 68
Change to Bit 5, Register 0x0001, Table 27................................. 52
5/2016—Rev. 0 to Rev. A
11/2016—Rev. A to Rev. B Changes to Table 3 ............................................................................4
Changes to Table 1 and Endnote 4, Table 2 ................................. 3 Changes to Current Range (ICP2) Parameter, Table 5 ...................8
Changes to Reliable Signal Swing Parameter, Table 4 ................ 5 Changes to Table 9 ......................................................................... 11
Change to PLL2 VCXO Input Parameter, Table 5 ...................... 7 Changes to Table 10 ....................................................................... 13
Changes to Table 7 ........................................................................... 9 Changes to LDOBYP5 Pin Description ...................................... 15
Added Figure 13; Renumbered Sequentially .............................. 18 Changes to Figure 13 ..................................................................... 19
Added Figure 20 ............................................................................. 19 Changes to Figure 30 ..................................................................... 25
Added Figure 21, Figure 22, and Figure 23 ................................ 20 Changes to Evaluation PCB Section ............................................ 69
Changes to Figure 34 ..................................................................... 21 Added Figure 46; Renumbered Sequentially .............................. 69
Changes to Table 15 and Table 17 ............................................... 34 Added Figure 50 ............................................................................. 71
Changes to Figure 47 ..................................................................... 37 Updated Outline Dimensions ...................................................... 71
Changes to Table 23 ....................................................................... 41
Changes to Table 25 ....................................................................... 46 9/2015—Revision 0: Initial Version

Rev. C | Page 2 of 71
Data Sheet HMC7044

SPECIFICATIONS
Unless otherwise noted, fVCXO = 122.88 MHz single-ended; CLKIN0/CLKIN0, CLKIN1/CLKIN1, CLKIN2/CLKIN2, and CLKIN3/CLKIN3
differential at 122.88 MHz; fVCO = 2949.12 MHz; doubler is on; typical value is given for VCC = 3.3 V; and TA = 25°C. Minimum and maximum
values are given over the full VCC and TA (−40°C to +85°C) variation, as listed in Table 1. Note that multifunction pins, such as CLKIN0/
RFSYNCIN, are referred to either by the entire pin name or by a single function of the pin, for example, CLKIN0, when only that
function is relevant.
CONDITIONS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE, VCC
VCC1_VCO 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for VCO and VCO distribution
VCC2_OUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for Output Channel 2 and
Output Channel 3
VCC3_SYSREF 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for common SYSREF divider
VCC4_OUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for Output Channel 4,
Output Channel 5, Output Channel 6, Output Channel 7
VCC5_PLL1 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for the LDO used in PLL1
VCC6_OSCOUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for oscillator output path
VCC7_PLL2 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for the LDO used in PLL2
VCC8_OUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for Output Channel 8, Output Channel 9,
Output Channel 10, and Output Channel 11
VCC9_OUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for Output Channel 0, Output Channel 1,
Output Channel 12, and Output Channel 13
TEMPERATURE
Ambient Temperature Range, TA −40 +25 +85 °C

SUPPLY CURRENT
For detailed test conditions, see Table 22 and Table 23.

Table 2.
Parameter 1, 2 Min Typ Max Unit Test Conditions/Comments
CURRENT CONSUMPTION 3
VCC1_VCO 157 225 mA
VCC2_OUT 4 65 250 mA Typical value is given at TA = 25°C with two LVDS clocks at divide by 8
VCC3_SYSREF 12 37 mA
VCC4_OUT4 78 500 mA Typical value is given at 25°C with two LVPECL high performance clocks,
fundamental frequency of internal VCO (fO), 2 SYSREF clocks (off)
VCC5_PLL1 39 125 mA
VCC6_OSCOUT 0 80 mA
VCC7_PLL2 46 80 mA
VCC8_OUT4 124 500 mA Typical value is given at 25°C with two LVPECL high performance clocks at
divide by 2, 2 SYSREF clocks (off)
VCC9_OUT4 65 500 mA Typical value is given at 25°C with two LVDS clocks at divide by 8, 2 SYSREF
clocks (off)
Total Current 586 mA
1
Maximum values are guaranteed by design and characterization.
2
Currents include LVPECL termination currents.
3
Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary
synchronization events.
4
Typical specification applies to a normal usage profile (Profile 1 in Table 23), where PLL1 and PLL2 are locked, but very low duty cycle currents (sync events) and some
optional features are disabled. This specification assumes output configurations as described in the test conditions/comments column.

Rev. C | Page 3 of 71
HMC7044 Data Sheet
DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUT SIGNALS (RESET, SYNC, SLEN, SCLK)
Safe Input Voltage Range 1 −0.1 +3.6 V
Input Load 0.3 pF
Input Voltage
Input Logic High (VIH) 1.2 VCC V
Input Logic Low (VIL) 0 0.5 V
SPI Bus Frequency 10 MHz
DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS
INPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)
Safe Input Voltage Range1 −0.1 +3.6 V
Input Capacitance 0.4 pF
Input Resistance 50G Ω
Input Voltage
Input Logic High (VIH) 1.22 VCC V
Input Logic Low (VIL) 0 0.24 V
Input Hysteresis 0.2 V Occurs around 0.85 V
GPIO1 TO GPIO4 ALARM MUXING/DELAY
Delay from Internal Alarm/Signal to General-Purpose 2 ns Does not include tDGPO
Output (GPO) Driver
DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS
OUTPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)
CMOS MODE
Logic 1 Level 1.6 1.9 2.2 V
Logic 0 Level 0 0.1 V
Output Drive Resistance (RDRIVE) 50 Ω
Output Driver Delay (tDGPO) 1.5 + 42 × ns Approximately 1.5 ns + 0.69 × RDRIVE × CLOAD
CLOAD (CLOAD in nF)
Maximum Supported DC Current1 0.6 mA
OPEN-DRAIN MODE1 External 1 kΩ pull-up resistor
Logic 1 Level 3.6 V 3.6 V maximum permitted; specifications
set by external supply
Logic 0 Level 0.13 0.28 V Against a 1 kΩ external pull-up resistor to
3.3 V
Pull-Down Impedance 60 Ω
Maximum Supported Sink Current 5 mA
1
Guaranteed by design and characterization.

Rev. C | Page 4 of 71
Data Sheet HMC7044
PLL1 CHARACTERISTICS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
PLL1 REFERENCE INPUTS
(CLKIN0/CLKIN0, CLKIN1/CLKIN1,
CLKIN2/CLKIN2, CLKIN3/CLKIN3)
Reliable Signal Swing
Differential 0.375 1.4 V p-p Differential, keep signal at reference input pin
<2.8 V, measured at 800 MHz
Single-Ended 1 0.375 1.4 V p-p <250 MHz; keep signal at reference input pin
<2.8 V
Common-Mode Range 0.4 2.4 V If user supplied, on-chip VCM is approximately
2.1 V
Input Impedance 100 to 2000 Ω User selectable; differential
Return Loss −12 dB When terminated with 100 Ω differentially
PLL1 REFERENCE DIVIDER
8-Bit Lowest Common Multiple 1 255
(LCM) Dividers
16-Bit R Divider (R1) 1 65,535
PLL1 FEEDBACK DIVIDER
16-Bit N Divider (N1) 1 65,535
PLL1 FREQUENCY LIMITATIONS
PLL1 REF Input Frequency (fREF) 0.00015 800 MHz Minimum specification set by Phase Detector 1
(PD1) low limit
Digital LOS/LCM Frequency (fLCM) 0.00015 123 MHz Typically run at about 38.4 MHz
PD1 Frequency (fPD1) 0.00015 50 MHz Minimum specification = VCXO minimum
frequency ÷ 65,535; 9.76 MHz typical
PLL1 CHARGE PUMP
Charge Pump Current Range (ICP1) 120 to 1920 μA ICP1 from 0 to 15, VCXO control voltage (VTUNE) =
1.4 V
ICP1 Variation over Process Voltage ±15 % VTUNE = 1.4 V
Temperature (PVT)
Source/Sink Current Mismatch 2 % Source/sink mismatch at 1.4 V
Charge Pump Current Step Size 120 μA
Charge Pump Compliance Range1 0.4 to 2.5 V ICP variation less than 10%
0.1 to 2.7 V Maintain lock in test environment
PLL1 NOISE PROFILE1
Floor Figure of Merit (FOM) −222 dBc/Hz Normalized to 1 Hz
Flicker FOM −252 dBc/Hz Normalized to 1 Hz
Flicker Noise Determined by formula 2 dBc/Hz At fOUT, fOFFSET
Noise Floor Determined by formula 3 dBc/Hz At fOUT, fPD1
Total Phase Noise (Unfiltered) Determined by formula 4 dBc/Hz
PLL1 BANDWIDTH AND
ACQUISITION TIMES1
Supported Loop Bandwidths fLCM/225 fPD1/10 Hz Typically, PLL1 low BW is set by the application
(PLL1_BW) 5 and ranges between 5 Hz and 2 kHz
PLL1 Slew Time 6 N1/ sec N1 = 10 (typical) and fDELTA_VCXO = 10 kHz
fDELTA_VCXO (typical) results in 1 ms of slew time
PLL1 Linear Acquisition Time 5/PLL1_BW sec When VCXO has stopped slewing to steady
state (within 5°)
PLL1 Phase Error at PD1 ±2.9 ns
Invalidates Lock
PLL1 Lock Detect Timer Period 4 to 226 tLCM User-selectable low phase error counts to
(tLKD)7 declare lock

Rev. C | Page 5 of 71
HMC7044 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
PLL1 BEHAVIOR ON REFERENCE
FAILURE1
LOS Assertion Delay7 2 + tDGPO 3 + tDGPO tLCM From missing signal edge to alarm on GPO
Erroneously Active ICP1 Time on 0 8 ns
Reference Failure 8
Temporary Frequency Glitch Due 0.03 ppm ICP1 = 1 mA, C12 = 4.6 nF, Crystek CVPD-952
to Reference Failure VCXO
Integrated Frequency Error Due 0.016 ppm ICP1 = 1 mA, C13 = 1 μF, Crystek CVPD-952 VCXO
to Reference Failure
Signal Valid Time to Clear LOS 9 2 3 tLOSVAL
PLL1 VTUNE LEAKAGE SOURCES
Charge Pump Tristate Leakage 0.2 nA
Current
Board Level XTAL Tune Input Port 0.5 nA Crystek CVPD-952 VCXO
Board Level Loop Filter 2 nA C12 = 4.6 nF, C13 = 1 μF, R9 = 11 kΩ, C15 =
Components unpopulated
HOLDOVER CHARACTERISTICS
VTUNE Drift Over 1 sec in Tristate 2 mV C12 = 4.6 nF, C13 = 1 μF, R9 = 11 kΩ,
Mode CVPD-950 VCXO
Holdover
Analog-to-Digital Converter 19 mV 7-bit, monotonic, no missing code
(ADC)/Digital-to-Analog
Converter (DAC) Resolution
ADC/DAC Code 0 Voltage 0.28 V
ADC/DAC Code 127 Voltage 2.71 V
DAC Temperature Stability 0.07 mV/°C At maximum code
ADC/DAC Integral Nonlinearity −0.11 LSBs Worst case across codes
(INL)
Holdoff Timer Period1, 10 1 226 tLCM
HOLDOVER EXIT—INITIAL PHASE
OFFSETS1
Exit Criteria = Wait for Low Phase The phase offset to make up after a transition
Error from holdover to acquisition when using this
feature
Exit Action = None ±4 ns
Exit Criteria = Any 11
Exit Action = Reset Dividers 1 2 tVCXO Assumes N2 > 3 and dividers are reset upon
exit; note that VCXO lags at start; value applies
as the starting phase error if DAC assisted
release is used
Exit Action = None ±N1 tVCXO Dividers are not reset upon exit
HOLDOVER EXIT CHARACTERISTICS1, 12
DAC Assisted Release Period per 1/2 1/16 tLKD Based on lock detect timer setpoint
Step (tDACASSIST)
DAC Assisted Release Time 9 tDACASSIST Time from decision to leave holdover until in
fully natural acquisition; assumes no
interruption by LOS or user
Delay of Exit Criteria13 = Wait for N1/fERR_VCXO sec
Low Phase Error 14

Rev. C | Page 6 of 71
Data Sheet HMC7044
Parameter Min Typ Max Unit Test Conditions/Comments
HOLDOVER EXIT—FREQUENCY
TRANSIENTS vs. MODE
Peak Frequency Transient
DAC Assisted Release 2 ppm Only available if using DAC-based holdover
1
Guaranteed by design and characterization.
2
See the PLL1 Noise Calculations section for more information on how to calculate the flicker noise for PLL1.
3
See the PLL1 Noise Calculations section for more information on how to calculate the noise floor for PLL1.
4
See the PLL1 Noise Calculations section for more information on how to calculate the total phase noise (unfiltered) for PLL1.
5
Set by external components. Set the lock detect thresholds (PLL1 Lock Detect Timer[4:0] in Register 0x0028) appropriately in the SPI.
6
Depends on initial phase offset (worst case is proportional to N1) and VCXO excess tuning range available over the target (fDELTA_VCXO). For PFD rates typical of PLL1,
cycle slipping is normally insignificant.
7
tLCM is the least common multiple (LCM) of PLL1 clock input frequencies. The specification is given in multiples of tLCM.
8
If LOS triggers before the PFD edge is normally detected (more likely with high R1 values), the charge pump is more likely to disable before the next invalid
comparison occurs. Otherwise, the fast tristate circuit disables the charge pump after about 4 ns (8 ns worst case) of phase error.
9
tLOSVAL is a register value that is programmable from 1, 2, 4, …, 64 tLCM.
10
If the holdoff timer is used, the finite state machine (FSM) stays in holdover after LOS of the active reference before switching clocks, giving the original clock a chance
to return.
11
tVCXO is the VCXO clock period.
12
See the PLL1 Holdover Exit section.
13
The time required for the phases to intersect is inversely proportional to the holdover frequency error. Note that the frequency error during holdover is expected to
be much smaller than is available from the tuning range of the VCXO.
14
fERR_VCXO is the error frequency of the VCXO.

PLL2 CHARACTERISTICS
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
PLL2 VCXO INPUT
Recommended Swing
Differential 0.2 1.4 V p-p Differential, keep signal at OSCIN and OSCIN pins < 2.8 V
Single-Ended (<250 MHz)1 0.2 1.4 V p-p Keep signal at OSCIN and OSCIN pins < 2.8 V
Common-Mode Range 1.6 2.1 2.4 V If user supplied, on-chip VCM is approximately 2.1 V
VCXO Input Slew Rate 300 mV/ns Slew rates as low as 100 mV/ns are functional, but can
degrade the phase noise plateau by about 3 dB
Input Capacitance 1.5 pF Per side; 3 pF differential
Differential Input Resistance 100 to 1000 Ω User selectable
Return Loss −12 dB When terminated with 100 Ω differential
PLL2 EXTERNAL VCO INPUT
Recommended Input
Power, AC-Coupled
Differential −6 6 dBm
Single-Ended1 −6 6 dBm
Return Loss −12 dB When terminated with 100 Ω differential
External VCO Frequency1 400 3200 MHz Fundamental mode; if < 1 GHz, set the low frequency
external VCO path bit (Register 0x0064, Bit 0)
400 6000 MHz Using external VCO ÷ 2
Common-Mode Range1 1.6 2.1 2.2 V
PLL2 DIVIDERS
12-Bit Reference Divider 1 4095
Range (R2)
16-Bit Feedback Divider 8 65,535
Range (N2)
PLL2 FREQUENCY LIMITATIONS
VCXO Frequency (fVCXO) 10 500 MHz 122.88 MHz or 155 MHz are typical
VCXO Duty Cycle
Using Doubler1 40 60 % Distortion can lead to a spur at fPD/2 offset, note that
minimum pulse width > 3 ns

Rev. C | Page 7 of 71
HMC7044 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
Reference Doubler Input 10 175 MHz
Frequency
R2 Input Frequency 10 500 MHz
PD2 Frequency (fPD2) 0.00015 250 MHz Recommended at high end of the range for best phase
noise; typically, 122.88 MHz × 2
PLL2 CHARGE PUMP
Current Range (ICP2) 160 to 2560 μA ICP2 setting from 0 to 15 with 160 μA step size, VTUNE = 1.4 V
ICP2 Variation over PVT ±25 % VTUNE = 1.4 V
Source/Sink Current 2 % Source/sink mismatch at 1.4 V
Mismatch
Current Step Size 160 μA
Compliance Range 0.3 to 2.45 V ICP variation less than 10%
PLL2 NOISE PROFILE
Floor FOM −232 dBc/Hz Normalized to 1 Hz
Flicker FOM −266 dBc/Hz Normalized to 1 Hz
FOM Variation vs. PVT ±3 dB
FOM Degradation 3 dB At minimum VCXO slew rate
PLL2 Flicker Noise Determined by formula2 dBc/Hz At fOUT, fOFFSET
PLL2 Noise Floor Determined by formula 3 dBc/Hz At fOUT, fPD2
PLL2 Total Phase Noise Determined by formula 4 dBc/Hz
(Unfiltered)
PLL2 BANDWIDTH AND
ACQUISITION TIMES
Supported Loop 10 to 700 kHz Set by external components
Bandwidths (PLL2_BW)
VCO Automatic Gain 10 20 ms Time from power-up of VCO before initiating calibration;
Control (AGC) Settling this applies to the 100 nF/1 μF configuration of external
Time1 decoupling capacitors on the VCO supply network
VCO Calibration Time 5 2694 tPD2 N2 from 8 to 31
779 tPD2 N2 from 32 to 256
214 tPD2 N2 from 256 to 4095
139 tPD2 N2 > 4095
Temperature Range −40 +85 °C Maintains lock from any temperature to any
Postcalibration1 temperature
PLL2 Linear Acquisition 5/PLL2_BW sec After VCXO has stopped slewing to steady state
Time
PLL2 Lock Detect Timer 512 tPD2 Low phase error counts to declare lock
Period5
1
Guaranteed by design and characterization.
2
See the PLL2 Noise Calculations section for more information on how to calculate the flicker noise for PLL2.
3
See the PLL2 Noise Calculations section for more information on how to calculate the noise floor for PLL2.
4
See the PLL2 Noise Calculations section for more information on how to calculate the total phase noise (unfiltered) for PLL2.
5
tPD2 is the period of Phase Detector 2.

VCO CHARACTERISTICS
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
VOLTAGE CONTROLLED OSCILLATOR (VCO)
Frequency Tuning Range, On-Board VCOs1 2150 2880 MHz Low VCO typical coverage
2650 3550 MHz High VCO typical coverage
2400 3200 MHz Guaranteed frequency coverage 2
Tuning Sensitivity 38 to 44 MHz/V Low frequency VCO at 2457.6 MHz
35 to 40 MHz/V High frequency VCO at 2949.12 MHz

Rev. C | Page 8 of 71
Data Sheet HMC7044
Parameter Min Typ Max Unit Test Conditions/Comments
OPEN-LOOP VCO PHASE NOISE
fOUT = 2457.6 MHz
fOFFSET = 100 kHz −109 dBc/Hz High performance mode, does not include
floor contribution due to output network
fOFFSET = 800 kHz −134 dBc/Hz
fOFFSET = 1 MHz −136 dBc/Hz
fOFFSET = 10 MHz −156 dBc/Hz
Normalized Phase Noise Variation vs. ±2 dB Sweep across both VCOs, all bands;
Frequency normalize to 2457.6 MHz
Phase Noise Variation vs. Temperature ±2 dB
Phase Noise Degradation in Low 2 dB
Performance Mode
1
Guaranteed by design and characterization.
2
Although the device covers this range without any gaps, for frequencies between ~2700 Hz and 2900 Hz, using a different VCO core to synthesize the frequency can
be required as process parameters shift. Features are built into the HMC7044 to determine which core is selected for a given frequency that can fall in this range, but it
can require software to configure these circuits appropriately.

CLOCK OUTPUT DISTRIBUTION CHARACTERISTICS

Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
CLOCK OUTPUT SKEW
CLKOUTx/CLKOUTx to 15 |ps| Same pair, same type termination and
SCLKOUTx/SCLKOUTx Skew within One configuration
Clock Output Pair
Any CLKOUTx/CLKOUTx to Any 30 |ps| Any pair, same type termination and configuration
SCLKOUTx/SCLKOUTx
CLOCK OUTPUT DIVIDER
12-Bit Divider Range 1 4094 1, 3, 5, and all even numbers up to 4094
SYSREF CLOCK OUTPUT DIVIDER
12-Bit Divider Range 1 4094 1, 3, 5 and all even numbers up to 4094; pulse
generator behavior is only supported for divide
ratios ≥ 32
CLOCK OUTPUT ANALOG FINE DELAY
Analog Fine Delay
Adjustment Range 1 135 670 ps 24 delay steps, fCLKOUT = 983.04 MHz
Resolution 25 ps fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Maximum Analog Fine Delay Frequency1 3200 MHz
CLOCK OUTPUT COARSE DELAY (FLIP FLOP
BASED)
Coarse Delay Adjustment Range 0 17 ½ VCO 17 delay steps in ½ VCO period
period
Coarse Delay Resolution 169.54 ps fVCO = 2949.12 MHz
Maximum Frequency Coarse Delay1 3200 MHz
CLOCK OUTPUT COARSE DELAY (SLIP
BASED)
Coarse Delay
Adjustment Range 1 to ∞ VCO period
Resolution 339.08 ps fVCO = 2949.12 MHz
Maximum Frequency Coarse Delay 1600 MHz
1
Guaranteed by design and characterization.

Rev. C | Page 9 of 71
HMC7044 Data Sheet
SPUR CHARACTERISTICS
Table 8.
Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE SPUR PERFORMANCE
At 122.88 MHz and Its Harmonics −70 dBc

NOISE AND JITTER CHARACTERISTICS

Table 9.
Parameter Min Typ Max Unit Test Conditions/Comments
CLOSED-LOOP PHASE NOISE—WIDE LOOP FILTER For best integrated noise
SSB Phase Noise
At 2457.6 MHz 1
−98.0 dBc/Hz Offset = 100 Hz
−111.1 dBc/Hz Offset = 1 kHz
−119.8 dBc/Hz Offset = 10 kHz
−125.2 dBc/Hz Offset = 100 kHz
−126.9 dBc/Hz Offset = 300 kHz
−131.3 dBc/Hz Offset = 1 MHz
−150.0 dBc/Hz Offset = 5 MHz
−154.0 dBc/Hz Offset = 10 MHz
−156.3 dBc/Hz Offset = 100 MHz
44.0 fs Integrated jitter = 12 kHz to 20 MHz
At 614.4 MHz1
−110.4 dBc/Hz Offset = 100 Hz
−122.8 dBc/Hz Offset = 1 kHz
−131.3 dBc/Hz Offset = 10 kHz
−136.6 dBc/Hz Offset = 100 kHz
−138.3 dBc/Hz Offset = 300 kHz
−142.7 dBc/Hz Offset = 1 MHz
−157.6 dBc/Hz Offset = 5 MHz
−158.8 dBc/Hz Offset = 10 MHz
−159.2 dBc/Hz Offset = 100 MHz
50.0 fs Integrated jitter = 12 kHz to 20 MHz
CLOSED-LOOP PHASE NOISE—NARROW LOOP FILTER For best 800 kHz offset
SSB Phase Noise
At 2949.12 MHz 2
−100.9 dBc/Hz Offset = 100 Hz
−103.8 dBc/Hz Offset = 1 kHz
−106.9 dBc/Hz Offset = 10 kHz
−109.9 dBc/Hz Offset = 100 kHz
−132.3 dBc/Hz Offset = 800 kHz
−134.5 dBc/Hz Offset = 1 MHz
−152 dBc/Hz Offset = 10 MHz
−155.3 dBc/Hz Offset = 100 MHz
108 fs Integrated jitter = 12 kHz to 20 MHz

Rev. C | Page 10 of 71
Data Sheet HMC7044
Parameter Min Typ Max Unit Test Conditions/Comments
At 983.04 MHz2
−110.4 dBc/Hz Offset = 100 Hz
−113.3 dBc/Hz Offset = 1 kHz
−116.4 dBc/Hz Offset = 10 kHz
−119.4 dBc/Hz Offset = 100 kHz
−141.7 dBc/Hz Offset = 800 kHz
−143.7 dBc/Hz Offset = 1 MHz
−157.1 dBc/Hz Offset = 10 MHz
−157.1 dBc/Hz Offset = 100 MHz
102 fs Integrated jitter 12 kHz to 20 MHz
OUTPUT NETWORK FLOOR FOM
CML with 100 Ω Internal Termination (CML100)
Fundamental Mode −250 dBc/Hz High performance
Divide by 1 to Divide by N −248 dBc/Hz High performance
Divide by 1 to Divide by N −247 dBc/Hz Low power (4 dB less power)
LVPECL
Fundamental Mode −250 dBc/Hz
Divide by 1 to Divide by N −247 dBc/Hz
LVDS
Divide by 1 to Divide by N −244 dBc/Hz High performance
Divide by 1 to Divide by N −243 dBc/Hz Low power (4 dB less power)
PHASE NOISE DEGREDATION DUE TO HARMONICS3
Fundamental Only 0.00 dB
Third Harmonic 0.25 dB
Third and Fifth Harmonics 0.40 dB
Third, Fifth, and Seventh Harmonics 0.50 dB
Third, Fifth, Seventh, and Ninth Harmonics 0.53 dB
Third Through 61st Harmonics 0.64 dB
PHASE NOISE FLOOR AND JITTER
Phase Noise Floor at fOUT Determined by formula 4 dBc/Hz
Jitter Density of Floor at fOUT Determined by formula 5 sec/√Hz
RMS Additive Jitter Due to Floor Determined by formula 6 sec From fOUT and output channel FOM
1
PLL2 locked at 122.88 MHz × 2 × 10, wide (600 kHz) loop filter for best 12 kHz to 20 MHz jitter, CML100 high performance output buffer.
2
PLL2 locked at 122.88 MHz × 2 × 12, narrow loop for best 800 Hz offset, CML100 high performance output buffer.
3
When the harmonics of the signal are captured in the measurement bandwidth of the receiving instrument/circuit, the noise power of those harmonics can fold and
influence the overall noise. Their presence causes a decibel for decibel influence. For example, if the third harmonic is at −10 dBc, there is an additional noise contributor of 10 dB
lower than the fundamental at all offsets that folds in-band and causes a 0.2 dB hit overall. The influence of the harmonics factoring into the degradation is primarily a
function of the frequency of the buffer bandwidth relative to the third, fifth, and seventh harmonics. As the output frequency reduces, more harmonics fall into the observation
bandwidth, and the degradation worsens, but only slightly. This effect produces a penalty of 0.65 dB maximum if harmonics up to the 61st harmonic is included.
4
See the Phase Noise Floor and Jitter section for more information on how to calculate the phase noise floor.
5
See the Phase Noise Floor and Jitter section for more information on how to calculate the jitter density of floor.
6
See the Phase Noise Floor and Jitter section for more information on how to calculate the rms additive jitter due to floor.

CLOCK OUTPUT DRIVER CHARACTERISTICS

Table 10.
Parameter Min Typ Max Unit Test Conditions/Comments
CML MODE (LOW POWER) RL = 100 Ω, 9.6 mA
−3 dB Bandwidth 1950 MHz Differential output voltage = 980 mV p-p diff
Output Rise Time 175 ps fCLKOUT = 245.76 MHz, 20% to 80%
145 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 185 ps fCLKOUT = 245.76 MHz, 20% to 80%
145 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle 1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 1390 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1360 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Common-Mode Output Voltage VCC − 1.05 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
Rev. C | Page 11 of 71
HMC7044 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
CML MODE (HIGH POWER) RL = 100 Ω, 14.5 mA
3 dB Bandwidth 1400 MHz Differential output voltage = 1410 mV p-p diff
Output Rise Time 250 ps fCLKOUT = 245.76 MHz, 20% to 80%
165 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 255 ps fCLKOUT = 245.76 MHz, 20% to 80%
170 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 2000 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1800 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Common-Mode Output Voltage VCC − 1.6 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
LVPECL MODE RL = 150 Ω, 4.8 mA
3 dB Bandwidth 2400 MHz Differential output voltage = 1240 mV p-p diff
Output Rise Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
130 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
130 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 1760 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1850 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Common-Mode Output Voltage VCC − 1.3 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
LVDS MODE (LOW POWER) 1.75 mA
Maximum Operating Frequency 600 MHz Differential output voltage = 400 mV p-p diff
Output Rise Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
100 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 135 ps fCLKOUT = 245.76 MHz, 20% to 80%
95 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 390 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
Common-Mode Output Voltage 1.1 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
LVDS MODE (HIGH POWER) 3.5 mA
Maximum Operating Frequency 1700 MHz Differential output voltage = 650 mV p-p diff
Output Rise Time 145 ps fCLKOUT = 245.76 MHz, 20% to 80%
105 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Fall Time 145 ps fCLKOUT = 245.76 MHz, 20% to 80%
100 ps fCLKOUT = 983.04 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Differential Output Voltage Magnitude 750 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
730 mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
Common-Mode Output Voltage 1.1 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
CMOS MODE
Maximum Operating Frequency 600 MHz Single-ended output voltage = 940 mV p-p diff
Output Rise Time 425 ps fCLKOUT = 245.76 MHz, 20% to 80%
Output Fall Time 420 ps fCLKOUT = 245.76 MHz, 20% to 80%
Output Duty Cycle1 47.5 50 52.5 % fCLKOUT = 1075 MHz (2150 MHz/2)
Output Voltage
High VCC − 0.07 V Load current = 1 mA
VCC − 0.5 V Load current = 10 mA
Output 0.07 V Load current = 1 mA
0.5 V Load current = 10 mA
1
Guaranteed by design and characterization.

Rev. C | Page 12 of 71
Data Sheet HMC7044

ABSOLUTE MAXIMUM RATINGS

Table 11. Stresses at or above those listed under Absolute Maximum
Parameter Rating Ratings may cause permanent damage to the product. This is a
VCC1_VCO, VCC2_OUT, VCC3_SYSREF, −0.3 V to +3.6 V stress rating only; functional operation of the product at these
VCC4_OUT, VCC5_PLL1, VCC6_OSCOUT, or any other conditions above those indicated in the operational
VCC7_PLL2, VCC8_OUT, VCC9_OUT section of this specification is not implied. Operation beyond
Maximum Junction Temperature (TJ) 125°C the maximum operating conditions for extended periods may
Maximum Peak Reflow Temperature 260°C affect product reliability.
Thermal Resistance (Channel to Ground 7°C/W
Paddle) ESD CAUTION
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
ESD Sensitivity Level
Human Body Model Class 1C
Charged Device Model1 Class 3
1
Per JESD22-C101-F (CDM) standard.

Rev. C | Page 13 of 71
HMC7044 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

65 SCLKOUT13
64 SCLKOUT13

61 SCLKOUT11
60 SCLKOUT11

54 SCLKOUT9
53 SCLKOUT9
68 VCC9_OUT

57 VCC8_OUT
67 CLKOUT12
66 CLKOUT12

59 CLKOUT10
58 CLKOUT10

56 CLKOUT8
55 CLKOUT8
63 GPIO4
62 GPIO3

52 GPIO2
CLKOUT0 1 51 VCC7_PLL2
CLKOUT0 2 50 CPOUT2
SCLKOUT1 3 49 LDOBYP7
SCLKOUT1 4 48 OSCIN
RESET 5 47 OSCIN
SYNC 6 46 LDOBYP6
BGABYP1 7 45 OSCOUT1
LDOBYP2 8 HMC7044 44 OSCOUT1
LDOBYP3 9 TOP VIEW 43 CLKIN2/OSCOUT0
(Not to Scale)
VCC1_VCO 10 42 CLKIN2/OSCOUT0
LDOBYP4 11 41 VCC6_OSCOUT
LDOBYP5 12 40 CLKIN0/RFSYNCIN
SCLKOUT3 13 39 CLKIN0/RFSYNCIN
SCLKOUT3 14 38 VCC5_PLL1
CLKOUT2 15 37 CLKIN1/FIN
CLKOUT2 16 36 CLKIN1/FIN
VCC2_OUT 17 35 RSV
SLEN 18
SCLK 19
SDATA 20
VCC3_SYSREF 21
SCLKOUT5 22
SCLKOUT5 23
CLKOUT4 24
CLKOUT4 25
VCC4_OUT 26
CLKOUT6 27
CLKOUT6 28
SCLKOUT7 29
SCLKOUT7 30
GPIO1 31
CPOUT1 32
CLKIN3 33
CLKIN3 34

13033-002
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A HIGH QUALITY RF/DC GROUND.

Figure 2. Pin Configuration

Table 12. Pin Function Descriptions

Pin No. Mnemonic Type1 Description
1 CLKOUT0 O True Clock Output Channel 0. Default DCLK profile.
2 CLKOUT0 O Complementary Clock Output Channel 0. Default DCLK profile.
3 SCLKOUT1 O True Clock Output Channel 1. Default SYSREF profile.
4 SCLKOUT1 O Complementary Clock Output Channel 1. Default SYSREF profile.
5 RESET I Device Reset Input. Active high. For normal operation, set RESET to 0.
6 SYNC I Synchronization Input. This pin is used for multichip synchronization. If not used, set SYNC to 0.
7 BGABYP1 Band Gap Bypass Capacitor Connection. Connect a 4.7 µF capacitor to ground. This pin affects all
internally regulated supplies.
8 LDOBYP2 LDO Bypass 2. Connect a 4.7 µF capacitor to ground. The internal digital supply is 1.8 V. This pin is
the LDO bypass for the PLL1, PLL2, and SYSREF sections.
9 LDOBYP3 LDO Bypass 3. Connect a 4.7 µF capacitor to ground. This pin is the 2.8 V supply to PLL1, Phase
Frequency Detector 1 (PFD1), Charge Pump 1 (CP1), RF synchronization (RFSYNC), and Pin 36
buffers.
10 VCC1_VCO P 3.3 V Supply for VCO and VCO Distribution.
11 LDOBYP4 LDO Bypass 4. Connect a 1 µF capacitor to ground. This pin is the first stage regulator for the VCO
supply.
12 LDOBYP5 LDO Bypass 5. Connect a 100 nF capacitor to LDOBYP4. This pin is the VCO core supply voltage.
13 SCLKOUT3 O True Clock Output Channel 3. Default SYSREF profile.
14 SCLKOUT3 O Complementary Clock Output Channel 3. Default SYSREF profile.
15 CLKOUT2 O True Clock Output Channel 2. Default DCLK profile.
16 CLKOUT2 O Complementary Clock Output Channel 2. Default DCLK profile.
17 VCC2_OUT P Power Supply for Clock Group 1 (Southwest)—Channel 2 and Channel 3. See the Clock Grouping,
Skew, and Crosstalk section.
18 SLEN I SPI Latch Enable.
Rev. C | Page 14 of 71
Data Sheet HMC7044
Pin No. Mnemonic Type1 Description
19 SCLK I SPI Clock.
20 SDATA I/O SPI Data.
21 VCC3_SYSREF P Power Supply for Common SYSREF Divider.
22 SCLKOUT5 O True Clock Output Channel 5. Default SYSREF profile.
23 SCLKOUT5 O Complementary Clock Output Channel 5. Default SYSREF profile.
24 CLKOUT4 O True Clock Output Channel 4. Default DCLK profile.
25 CLKOUT4 O Complementary Clock Output Channel 4. Default DCLK profile.
26 VCC4_OUT P Power Supply for Clock Group 2 (South)—Channel 4, Channel 5, Channel 6, and Channel 7. See the
Clock Grouping, Skew, and Crosstalk section.
27 CLKOUT6 O True Clock Output Channel 6. Default DCLK profile.
28 CLKOUT6 O Complementary Clock Output Channel 6. Default DCLK profile.
29 SCLKOUT7 O True Clock Output Channel 7. Default SYSREF profile.
30 SCLKOUT7 O Complementary Clock Output Channel 7. Default SYSREF profile.
31 GPIO1 I/O Programmable General-Purpose Input/Output 1.
32 CPOUT1 O PLL1 Charge Pump Output.
33 CLKIN3 I True Reference Clock Input 3 of PLL1.
34 CLKIN3 I Complementary Reference Clock Input 3 of PLL1.
35 RSV R Reserved Pin. This pin must be tied to ground.
36 CLKIN1/FIN I True Reference Clock Input 1 of PLL1/External VCO Input for External VCO Mode.
37 CLKIN1/FIN I Complementary Reference Clock Input 1 of PLL1/Complementary External VCO Input for External
VCO Mode.
38 VCC5_PLL1 P Power Supply for LDO, Used for PLL1.
39 CLKIN0/RFSYNCIN I True Reference Clock Input 0 of PLL1/RF Synchronization Input with Deterministic Delay.
40 CLKIN0/RFSYNCIN I Complementary Reference Clock Input 0 of PLL1/Complementary RF Synchronization Input with
Deterministic Delay.
41 VCC6_OSCOUT P Power Supply for Oscillator Output Path.
42 CLKIN2/OSCOUT0 I/O True Reference Clock Input 2 (Bidirectional Pin) of PLL1/Buffered Output 0 of Oscillator Input.
43 CLKIN2/OSCOUT0 I/O Complementary Reference Clock Input 2 (Bidirectional Pin) of PLL1/Complementary Buffered
Output 0 of Oscillator Input.
44 OSCOUT1 O True Buffered Output 1 of Oscillator Input.
45 OSCOUT1 O Complementary Buffered Output 1 of Oscillator Input.
46 LDOBYP6 LDO Bypass, Connect a 4.7 µF capacitor to ground. This pin is the LDO bypass for R2, N2, Phase
Frequency Detector 2 (PFD2), Charge Pump 2 (CP2), and the PLL2 loop filter.
47 OSCIN I True Feedback Input to PLL1. This pin is a reference input to PLL2.
48 OSCIN I Complementary Feedback Input to PLL1. This pin is a reference input to PLL2.
49 LDOBYP7 LDO Bypass. Connect a 4.7 µF capacitor to ground. This pin is the LDO bypass for the VCXO buffer
and frequency doubler oscillator output divider.
50 CPOUT2 I/O PLL2 Charge Pump Output.
51 VCC7_PLL2 P Power Supply for LDO for PLL2.
52 GPIO2 I/O Programmable General-Purpose Input/Output 2.
53 SCLKOUT9 O True Clock Output Channel 9. Default SYSREF profile.
54 SCLKOUT9 O Complementary Clock Output Channel 9. Default SYSREF profile.
55 CLKOUT8 O True Clock Output Channel 8. Default DCLK profile.
56 CLKOUT8 O Complementary Clock Output Channel 8. Default DCLK profile.
57 VCC8_OUT P Power Supply for Clock Group 3 (North)—Channel 8, Channel 9, Channel 10, and Channel 11. See
the Clock Grouping, Skew, and Crosstalk section.
58 CLKOUT10 O True Clock Output Channel 10. Default DCLK profile.
59 CLKOUT10 O Complementary Clock Output Channel 10. Default DCLK profile.
60 SCLKOUT11 O True Clock Output Channel 11. Default SYSREF profile.
61 SCLKOUT11 O Complementary Clock Output Channel 11. Default SYSREF profile.
62 GPIO3 I/O Programmable General-Purpose Input/Output 3. Sleep input by default.
63 GPIO4 I/O Programmable General-Purpose Input/Output 4. Pulse generator request by default.
64 SCLKOUT13 O True Clock Output Channel 13. Default SYSREF profile.

Rev. C | Page 15 of 71
HMC7044 Data Sheet
Pin No. Mnemonic Type1 Description
65 SCLKOUT13 O Complementary Clock Output Channel 13. Default SYSREF profile.
66 CLKOUT12 O True Clock Output Channel 12. Default DCLK profile.
67 CLKOUT12 O Complementary Clock Output Channel 12. Default DCLK profile.
68 VCC9_OUT P Power Supply for Clock Group 0 (Northwest)—Channel 0, Channel 1, Channel 12, and Channel 13.
See the Clock Grouping, Skew, and Crosstalk section.
EP Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.
1
O is output, I is input, P is power, and I/O is input/output.

Rev. C | Page 16 of 71
Data Sheet HMC7044

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, PFD PLL1 = 7.68 MHz, PFD PLL2 = 122.88 MHz × 2; ICP1 = 1.92 mA, ICP2 = 2.56 mA (wide loop), ICP2 = 1.12 mA
(narrow loop), PLL1 loop BW ~ 70 Hz, PLL2 wide loop BW ≈ 650 kHz, PLL2 narrow loop BW ≈ 215 kHz, PLL2 narrow loop filter =
1.1 nF | 160 Ω × 33 nF; PLL2 wide loop filter = 150 pF | 430 Ω × 4.7 nF; PLL1 loop filter = 4.7 nF | 10 µF × 1.2 kΩ.
–40 –60
1: 1kHz, –107.8dBc/Hz
–50 2: 10kHz, –119.5dBc/Hz
3: 100kHz, –124.7dBc/Hz –70
–60 4: 1MHz, –131.5Bc/Hz TOTAL PLL1 NOISE (SIMULATED)
5: 10MHz, –153.1dBc/Hz
–70 6: 20MHz, –154.4dBc/Hz –80 PFD/CP NOISE (SIMULATED)
7: 20MHz, –154.4dBc/Hz WENZEL REF (SIMULATED)
x: START 12kHz

PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

–80 STOP 20MHz –90 VCXO (SIMULATED)

–90 CENTER 10MHz TOTAL PLL1 NOISE (MEASURED)
SPAN 20MHz
–100
–100 1

–110 2
–110
PLL1 3
–120 CASCADED PLL1 + PLL2
4 –120
–130
–140 –130
NOISE:
ANALYSIS RANGE X: BAND MARKER 6
–150 ANALYSIS RANGE Y: BAND MARKER –140
INTG NOISE: –66dBc/20MHz 5
–160 RMS NOISE: 696µrad 7

13033-008
13033-003
0.004° –150
–170 RMS JITTER: 45fs
RESIDUAL FM: 1.6kHz
–180 –160
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 3. Cascaded Phase Noise at 2457.6 MHz, PLL2 Wide Loop Bandwidth Figure 6. Closed-Loop Phase Noise at 122.88 MHz, PLL1 Measurement vs.
Simulated, Clean Reference Source, ~70 Hz Loop Bandwidth 80° Phase Margin

–70 –60
1: 1kHz, –105.3dBc/Hz TOTAL PLL1 OUTPUT (SIMULATED)
2: 10kHz, –108.5dBc/Hz PFD/CP NOISE (SIMULATED)
–80 3: 100kHz, –111.4dBc/Hz –70 NOISY SOURCE (SIMULATED)
4: 800kHz, –134.2dBc/Hz VCXO (SIMULATED)
5: 1MHz, –136.5dBc/Hz NOISY SOURCE, OPEN LOOP (MEASURED)
–90 6: 10MHz, –153.3dBc/Hz –80
7: 20MHz, –154.6dBc/Hz
TOTAL PLL1 NOISE (MEASURED)
PHASE NOISE (dBc/Hz)

x: START 12kHz
PHASE NOISE (dBc/Hz)

–100 1
STOP 20MHz –90
2 CENTER 10MHz
SPAN 20MHz –100
–110
3
–120 –110

WIDE LOOP –120

–130 NARROW LOOP
4
–140 5 –130
NOISE:
ANALYSIS RANGE X: BAND MARKER
–150 ANALYSIS RANGE Y: BAND MARKER –140
INTG NOISE: –56.9dBc/20MHz
RMS NOISE: 2.0µrad 6

13033-009
13033-005

7 –150
–160 .116°
RMS JITTER: 131fs
RESIDUAL FM: 1.5kHz
–170 –160
1k 10k 100k 1M 10M 1 10 100 1k 10k 100k
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 4. Phase Noise at 2457.6 MHz, Narrow vs. PLL2 Wide Loop Figure 7. Closed-Loop Phase Noise at 122.88 MHz, PLL1 Measurement vs.
Bandwidth Simulated, Noisy Reference Source, ~70 Hz Loop Bandwidth, 80° Phase Margin

–70 –120
1: 1kHz, –110.4dBc/Hz
2: 10kHz, –120.0dBc/Hz
–80 3: 100kHz, –124.9dBc/Hz –125
4: 1MHz, –131.2dBc/Hz
5: 10MHz, –153.2dBc/Hz
–90 6: 20MHz, –154.5dBc/Hz –130
7: 20MHz, –154.5dBc/Hz
PHASE NOISE (dBc/Hz)

x: START 12kHz
PHASE NOISE (dBc/Hz)

–100 STOP 20MHz –135

1 CENTER 10MHz
SPAN 20MHz –140
–110
2
20×LOG (800kHz WIDE LOOP)
–120 3 –145 20×LOG (800kHz NARROW LOOP)
4 800kHz WIDE LOOP
CRYSTEK VCXO –150
–130 WENZEL VCXO 800kHz NARROW LOOP

–140 –155
NOISE:
ANALYSIS RANGE X: BAND MARKER
–150 ANALYSIS RANGE Y: BAND MARKER 6 –160
INTG NOISE: –66.1dBc/20.0MHz
RMS NOISE: 702µrad 5
13033-006
13033-004

7 –165
–160 .040°
RMS JITTER: 45fs
RESIDUAL FM: 1.6kHz
–170 –170
100 1k 10k 100k 1M 10M 100 600 1100 1600 2100 2600 3100 3600
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 5. PLL2 Phase Noise vs. Frequency, VCXO Quality at 2457.6 MHz, Figure 8. Phase Noise vs. Frequency at Common Output Frequencies
Wide Loop Bandwidth

Rev. C | Page 17 of 71
HMC7044 Data Sheet
160 3.0

JITTER WIDE LOOP

140 LOW VCO –40°C HIGH VCO –40°C
JITTER NARROW LOOP 2.5 LOW VCO +25°C HIGH VCO +25°C
LOW VCO +85°C HIGH VCO +85°C
120

2.0

VCO VTUNE (V)

100
JITETR (fs)

80 1.5

60
1.0
40

0.5
20

13033-007

13033-011
0 0
100 600 1100 1600 2100 2600 3100 3600

2050

2250

2450

2650

2850

3050

3250

3450

3650
FREQUENCY (MHz)
FREQUENCY (MHz)

Figure 9. 12 kHz to 20 MHz Jitter vs. Frequency, Wide Loop and Narrow Figure 12. VCO VTUNE vs. Frequency
Loop at Common Output Frequencies

–90 3.5
8: 100Hz, –99.8dBc/Hz

DIFFERENTIAL OUTPUT VOLTAGE (V p-p DIFF)

–95 1: 1kHz, –111.1dBc/Hz
2: 10kHz, –119.8dBc/Hz LVPECL
–100 3: 100kHz, –125.2dBc/Hz 3.0 CML100 HIGH
8
7: 300kHz, –126.9dBc/Hz CML100 LOW
–105 4: 1MHz, –131.3Bc/Hz LVDS HIGH
5: 10MHz, –153.1dBc/Hz
6: 32.8MHz, –156.3dBc/Hz CMOS (NOT IN
PHASE NOISE (dBc/Hz)

–110 x: START 12kHz 2.5 DIFFERENTIAL MODE)

1 STOP 20MHz
–115 CENTER 10MHz
SPAN 20MHz
–120 2.0
2
–125
3
–130 7 1.5
–135 4

–140 NOISE: 1.0

ANALYSIS RANGE X: BAND MARKER
–145 ANALYSIS RANGE Y: BAND MARKER
INTG NOISE: –66.4dBc/20MHz
–150 RMS NOISE: 678µrad 0.5
13033-021

13033-112
.039° 6
–155 RMS JITTER: 44fs 5
RESIDUAL FM: 1.5kHz
–160 0
100 1k 10k 100k 1M 10M 100M 1G 3G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 10. Phase Noise, CLKOUTx/CLKOUTx = 2457.6 MHz, Optimized for Best Figure 13. Differential Output Voltage vs. Frequency at Different Modes
Integrated Jitter (12 kHz to 20 MHz)

100 2.25
DIFFERENTIAL OUTPUT VOLTAGE (V p-p DIFF)

2.10
90
1.95 LVPECL
CML100 HIGH
80 1.80 CML100 LOW
2865.72MHz 1.65 LVDS HIGH
70
3511.86MHz 1.50
KVCO (MHz/V)

60 1.35
1.20
50
1.05
40 0.90
2115.38MHz
2627.755 MHz 0.75
30
0.60
20 0.45
CAP = 0 LOW VCO CAP = 31 LOW VCO 0.30
13033-012
13033-010

10
CAP = 0 HIGH VCO CAP = 31 HIGH VCO 0.15
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 1.0 1.5 2.0 2.5 3.0 3.5
VCO VTUNE (V) FREQUENCY (GHz)

Figure 11. VCO Gain (KVCO) vs. VCO VTUNE Figure 14. Differential Output Voltage vs. Frequency at Different Modes

Rev. C | Page 18 of 71
Data Sheet HMC7044
2.5 30
DIFFERENTIAL OUTPUT POWER (V p-p DIFF)

–40°C
+25°C
2.0 +85°C
25

DELAY STEP SIZE (ps)

1.5

20

1.0 –40°C
+25°C
+85°C
15
0.5

13033-013

13033-020
0 10

1
2
3
4
5
6
7
8
9

11
10

12
13
14
15
16
17
18
19
20
21
22
23
24
100M 1G 3G
FREQUENCY (Hz) DELAY STEP

Figure 15. LVPECL Differential Output Voltage vs. Frequency at Different Figure 18. Analog Delay Step Size vs. Delay Step over Temperature, LVPECL
Temperatures at 1474.56 MHz
0.4 800

700
0.3
CLKOUT0/CLKOUT0 VOLTAGE (V)

600
0.2
500

ANALOG DELAY (ps)

0.1 –40°C
400 +25°C
+85°C
0 300

–0.1 200

100
–0.2
0
–0.3
13033-017

13033-019
–100 FUND: FUNDAMENTAL MODE AT 2949MHz
DIS: ANALOG DELAY IS DISABLED AT 1474MHz
–0.4 –200
0 0.4 0.8 1.2 1.6 2.0
DIS
0
1
2
3
4
5
6
7
8
9
11
FUND

10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
TIME (ns)

DELAY SETTING

Figure 16. Differential CLKOUT0/CLKOUT0 at 2457 MHz, LVPECL Figure 19. Analog Delay vs. Delay Setting over Temperature, LVPECL
at 1474.56 MHz

1.0 30

0.8
25
CLKOUT0/CLKOUT0 VOLTAGE (V)

0.6
DELAY STEP SIZE (ps)

0.4
20
0.2

0 15

–0.2
10
–0.4
–40°C
–0.6 +25°C
5 +85°C
13033-018

–0.8

–1.0 0
13033-119

0 1 2 3 4 5 6 7 8 9 10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

TIME (ns) DELAY STEP

Figure 17. Differential CLKOUT0/CLKOUT0 Voltage at 614.4 MHz, LVPECL Figure 20. Analog Delay Step Size vs Delay Step over Temperature,
LVPECL at 3072 MHz with Digital Delay = 0

Rev. C | Page 19 of 71
HMC7044 Data Sheet

CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)

700 0.6 2.5
CLKOUT0
CLKOUT2
VALID PHASE ALARM
600
0.4 2.0

CLOCK OUPUT VOLTAGE (V)

500
ANALOG DELAY (ps)

0.2 1.5

400
0 1.0
–40°C
300 +25°C
+85°C
–0.2 0.5
200

–0.4 0
100

0 –0.6 –0.5

13033-014
13033-120
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
0 200 400 600 800 1000

DELAY SETTING TIME (ns)

Figure 21. Analog Delay vs. Delay Setting over Temperature, LVPECL at Figure 24. Output Channel Synchronization Before and After Rephase
3072 MHz with Digital Delay = 0

30

CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)

0.6 2.5
–40°C
+25°C
+85°C 0.4 2.0

CLOCK OUTPUT VOLTAGE (V)

CLKOUT0
25 CLKOUT2
DELAY STEP SIZE (ps)

VALID PHASE ALARM

0.2 1.5

20 0 1.0

–0.2 0.5
15

–0.4 0

10 –0.6 –0.5

13033-015
13033-121
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

330 335 340 345 350

DELAY STEP TIME (ns)

Figure 22. Analog Delay Step Size vs Delay Step over Temperature, LVPECL Figure 25. Output Channel Synchronization Before Rephase
at 3072 MHz with Digital Delay = 1

CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)

800 0.6 2.5

700
0.4 2.0
CLOCK OUTPUT VOLTAGE (V)

600
ANALOG DELAY (ps)

0.2 1.5
500

400 0 1.0
–40°C
+25°C
300 +85°C
–0.2 0.5
200

–0.4 0
100
CLKOUT0 VALID PHASE ALARM
CLKOUT2
0 –0.6 –0.5
13033-016

695 700 705 710 715

13033-122
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DELAY SETTING TIME (ns)

Figure 23. Analog Delay vs. Delay Setting over Temperature, LVPECL at Figure 26. Output Channel Synchronization After Rephase
3072 MHz with Digital Delay = 1

Rev. C | Page 20 of 71
Data Sheet HMC7044

TYPICAL APPLICATION CIRCUITS

HMC7044 0.1µF HMC7044

HIGH HIGH
LVDS LVDS
100Ω IMPEDANCE DOWNSTREAM 100Ω IMPEDANCE DOWNSTREAM
OUTPUT DEVICE OUTPUT DEVICE
INPUT INPUT

13033-023
13033-022
0.1µF

Figure 27. AC-Coupled LVDS Output Driver Figure 31. DC-Coupled LVDS Output Driver

VCC
HMC7044
100Ω 100Ω
LVPECL- DOWNSTREAM
HMC7044 0.1µF COMPATIBLE DEVICE
OUTPUT (LVPECL)
HIGH
100Ω IMPEDANCE DOWNSTREAM
INPUT DEVICE 50Ω 50Ω

13033-028
CML 0.1µF
OUTPUT 50Ω

13033-025
GND

Figure 28. AC-Coupled CML (Configured High-Z) Output Driver Figure 32. DC-Coupled LVPECL Output Driver

HMC7044 0.1µF HMC7044 DOWNSTREAM

DEVICE
100Ω 100Ω (CML)
HIGH
VCCx_OUT 100Ω IMPEDANCE DOWNSTREAM VCCx_OUT
INPUT DEVICE
100Ω 100Ω

13033-027
13033-026

CML 0.1µF CML

OUTPUT OUTPUT

Figure 29. AC-Coupled CML (Internal) Output Driver Figure 33. DC-Coupled CML (Internal) Output Driver

0.1µF HMC7044 HMC7044

3.3V
DRIVER
47Ω

SELF BIASED
13033-030

REF, VCXO

13033-031
0.1µF INPUTS
0.1µF

Figure 30. CLKIN0/CLKIN0, CLKIN1/CLKIN1, CLKIN2/CLKIN2, CLKIN3/CLKIN3, Figure 34. CLKIN0, CLKIN1, CLKIN2, CLKIN3, and OSCIN Input,
and OSCIN/OSCIN Input, Differential Mode Single-Ended Mode

Rev. C | Page 21 of 71
HMC7044 Data Sheet

TERMINOLOGY
Phase Jitter wave, the time jitter is a displacement of the edges from their
An ideal sine wave can be thought of as having a continuous ideal (regular) times of occurrence. In both cases, the variations in
and even progression of phase with time from 0° to 360° for timing from the ideal are the time jitter. Because these variations
each cycle. Actual signals, however, display a certain amount are random in nature, the time jitter is specified in seconds root
of variation from ideal phase progression over time. This mean square (rms) or 1 sigma of the Gaussian distribution.
phenomenon is phase jitter. Although many causes can Time jitter that occurs on a sampling clock for a DAC or an
contribute to phase jitter, one major cause is random noise, ADC decreases the signal-to-noise ratio (SNR) and dynamic
which is characterized statistically as being Gaussian (normal) range of the converter. A sampling clock with the lowest possible
in distribution. jitter provides the highest performance from a given converter.
This phase jitter leads to the energy of the sine wave in the Additive Phase Noise
frequency domain spreading out, producing a continuous Additive phase noise is the amount of phase noise that is
power spectrum. This power spectrum is usually reported as attributable to the device or subsystem being measured.
a series of values whose units are dBc/Hz at a given offset in The phase noise of any external oscillators or clock sources is
frequency from the sine wave (carrier). The value is a ratio subtracted, which makes it possible to predict the degree to
(expressed in decibels) of the power contained within a 1 Hz which the device impacts the total system phase noise when
bandwidth with respect to the power at the carrier frequency. used in conjunction with the various oscillators and clock
For each measurement, the offset from the carrier frequency is sources, each of which contributes its own phase noise to the
also given. total. In many cases, the phase noise of one element dominates
Phase Noise the system phase noise. When there are multiple contributors
It is meaningful to integrate the total power contained within to phase noise, the total is the square root of the sum of squares
some interval of offset frequencies (for example, 10 kHz to of the individual contributors.
10 MHz). This is the integrated phase noise over that frequency Additive Time Jitter
offset interval and can be readily related to the time jitter due to Additive time jitter is the amount of time jitter that is attributable
the phase noise within that offset frequency interval. to the device or subsystem being measured. The time jitter of
Phase noise has a detrimental effect on the performance of ADCs, any external oscillators or clock sources is subtracted, which
DACs, and RF mixers. It lowers the achievable dynamic range makes it possible to predict the degree to which the device
of the converters and mixers, although they are affected in impacts the total system time jitter when used in conjunction with
somewhat different ways. the various oscillators and clock sources, each of which contributes
Time Jitter its own time jitter to the total. In many cases, the time jitter of the
Phase noise is a frequency domain phenomenon. In the time external oscillators and clock sources dominates the system
domain, the same effect is exhibited as time jitter. When observing time jitter.
a sine wave, the time of successive zero crossings varies. In a square

Rev. C | Page 22 of 71
Data Sheet HMC7044

THEORY OF OPERATION
The HMC7044 is a high performance, dual-loop, integer N programmed to have a different phase offset. The phase
jitter attenuator capable of performing frequency translation, adjustment capability allows the designer to offset board flight
reference selection, and generation of ultralow phase noise time delay variations, data converter sample window matching,
references for high speed data converters with either parallel or and meet JESD204B synchronization challenges. The output
serial (JESD204B type) interfaces. The device is designed to signal path design of the HMC7044 is implemented to ensure
meet the requirements of demanding base station designs and both linear phase adjustment steps and minimal noise perturbation
offers a wide range of clock management and distribution when phase adjustment circuits are turned on.
features to simplify baseband and radio card clock tree designs. One of the key challenges in JESD204B system design is ensuring
The HMC7044 uses a dual-loop architecture, where two integer the synchronization of data converter frame alignment across
mode PLLs are connected in series to form a jitter attenuating the system, from the FPGA or DFE to ADCs and DACs
clock multiplier unit. The high performance dual-loop topology through a large clock tree that can comprise multiple clock
of the HMC7044 enables the wireless/RF system designer to generation and distribution ICs. The HMC7044 is specifically
attenuate the incoming jitter of a primary system reference designed to offer features to address this challenge. Using the
clock (for example, Common Public Radio Interface™ (CPRI) SYSREF valid interrupt feature, the wait time latency can be
source) and generate low phase noise, high frequency clocks to reduced in the FPGAs. The HMC7044 raises this flag through
drive data converter sample clock inputs. The HMC7044 provides its GPO port when all counters are set and outputs are at the
14 low noise and configurable outputs to offer flexibility in desired phases. Additionally, an external reference-based
interfacing with many different components in an RF trans- synchronization feature (SYNC via PLL2 or RF SYNC only in
ceiver system, such as data converters, local oscillators, fanout mode) synchronizes multiple devices, that is, it ensures
transmit/receive modules, FPGAs, and digital front-end (DFE) that all clock outputs start with same rising edge. This operation is
ASICs. achieved by rephasing the SYSREF control unit deterministi-
The first PLL in the HMC7044 is designed for low bandwidth cally, and then restarting the output dividers with this new
configuration using appropriately selected external loop filter desired phase.
components, and internal charge pump bias settings to achieve Offering excellent crosstalk, frequency isolation, and spurious
less than a few hundred Hz bandwidth, typically. The exact performance, the device generates independent frequencies in
bandwidth roll-off points depend on the frequency spectrum of both single-ended and differential formats. The four input
noise that must be attenuated in the system. The first PLL locks reference options allows up to three backup frequency sources,
an external VCXO and provides the clock holdover functions with hitless switching and holdover capabilities, supporting
and the reference frequency to the high performance second system redundancy and uninterrupted operation on reference
PLL loop. The combination of the loops provides an excellent data and clock failures. The device also features dedicated oscillator
clock generation unit with the capability to attenuate incoming fanout mode for best clock isolation, which generates multiple
reference clock jitter. The second PLL loop features two copies of the VCXO clock to be distributed across the board
overlapping on-chip VCOs that are SPI selectable with center with excellent frequency isolation.
frequencies at 2.5 GHz and 3 GHz, respectively. Both VCOs are Both the DCLK and SYSREF clock outputs can be configured
designed to have wide tuning ranges for broad output frequency to support different signaling standards, including CML, LVDS,
coverage. The desired output frequency is set by the chosen LVPECL, and LVCMOS, and different bias conditions to offset
VCXO frequency, VCO core (higher or lower frequency core), varying board insertion losses. The outputs can also be
and the programmed second PLL feedback divider and output programmed for ac or dc coupling and 50 Ω or 100 Ω internal
channel divider values. and external termination options.
The HMC7044 generates up to seven DCLK and SYSREF clock The HMC7044 is programmed via a 3-wire serial port interface
pairs per the JESD204B interface requirements. The system (SPI) and powers up with a default configuration that generates
designer can generate a lower number of DCLK and SYSREF valid output frequencies within the VCO tuning ranges regardless
pairs, and configure the remaining output signal paths as of whether a reference clock exists.
desired, either as DCLKs or additional SYSREFs or other
reference clocks with independent phase and frequency The HMC7044 is offered in a 68-lead, 10 mm ×10 mm,
adjustment. Frequency adjustment can be accomplished by LFCSP_VQ with the exposed pad to ground.
selecting the appropriate output divider values. One of the Note that, throughout this data sheet, multifunction pins, such
unique features of the HMC7044 is the independent flexible as CLKIN0/RFSYNCIN, are referred to either by the entire pin
phase management of each of the 14 channels. Using a name or by a single function of the pin, for example, CLKIN0,
combination of divider slip-based, digital/coarse and when only that function is relevant.
analog/fine delay adjustments, each channel can be

Rev. C | Page 23 of 71
Data Sheet HMC7044
DETAILED BLOCK DIAGRAM
RFSYNCIN/
RFSYNCIN

CLKIN0/RFSYNCIN IN0 PRESCALER

CLKIN0/RFSYNCIN (1 TO 255)
FIN/
FIN LOS
DETECT HOLDOVER
CLKIN1/FIN IN1 PRESCALER
CLKIN1/FIN (1 TO 255)

CLKIN3 IN3 PRESCALER R1 DIVIDER

REF
CLKIN3 (1 TO 255) MUX (1 TO 65535)
PHASE DETECTOR
CHARGE PUMP CPOUT1 VCO1 ~ 2500MHz
CLKIN2/OSCOUT0 IN2 PRESCALER VCO2 ~ 3000MHz
N1 DIVIDER PLL1
CLKIN2/OSCOUT0 SPI (1 TO 255) CPOUT2
(1 TO 65535)

VCXO PRESCALER PARTIALLY

(1 TO 255) INTEGRATED INTERNAL
2× 2× R2 DIVIDER LOOP VCO
MUX FILTER ×2
(1 TO 4095)
OSCOUT1 PHASE DETECTOR
OSC DIVIDER
CHARGE PUMP
OSCOUT1 ÷1, ÷2, ÷4, ÷8
N2 DIVIDER PLL2
(8 TO 4095)

OSCIN
OSCINBUF
OSCIN
CLK DISTRIBUTION PATH
VCO
MUX DIVIDER EXT VCO
FIN/FIN
COARSE CYCLE ÷1, ÷2
DIVIDER
DIGITAL SLIP/
DELAY (1 TO 4094)
CLKOUT0 SYNC FSM SYNC
ANALOG
MUX DELAY SYSREF TIMER
CLKOUT0 FUNDAMENTAL MODE RFSYNCIN/
RFSYNCIN
COARSE CYCLE SYNC/PULSOR GPI
DIVIDER SPI
DIGITAL SLIP/ CONTROL
SCLKOUT1 DELAY (1 TO 4094)
SYNC
MUX ANALOG
SCLKOUT1 DELAY
FUNDAMENTAL MODE TO LEAF DIVIDERS OSCINBUF
COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE
DIGITAL SLIP/ SLIP/ DIGITAL
(1 TO 4094) (1 TO 4094) DELAY
DELAY SYNC SYNC
CLKOUT2 ANALOG ANALOG CLKOUT8
MUX DELAY DELAY MUX
CLKOUT2 FUNDAMENTAL MODE FUNDAMENTAL MODE CLKOUT8

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ DIGITAL
SCLKOUT3 (1 TO 4094) (1 TO 4094) DELAY SCLKOUT9
DELAY SYNC SYNC
MUX ANALOG ANALOG MUX
SCLKOUT3 DELAY DELAY SCLKOUT9
FUNDAMENTAL MODE FUNDAMENTAL MODE

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ DIGITAL
(1 TO 4094) (1 TO 4094)
DELAY SYNC SYNC DELAY
CLKOUT4 ANALOG ANALOG CLKOUT10
MUX DELAY DELAY MUX
CLKOUT4 FUNDAMENTAL MODE FUNDAMENTAL MODE CLKOUT10

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ DIGITAL
SCLKOUT5 (1 TO 4094) (1 TO 4094) DELAY SCLKOUT11
DELAY SYNC SYNC
MUX ANALOG ANALOG MUX
SCLKOUT5 DELAY DELAY SCLKOUT11
FUNDAMENTAL MODE FUNDAMENTAL MODE

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ DIGITAL
(1 TO 4094) (1 TO 4094) DELAY
DELAY SYNC SYNC
CLKOUT6 ANALOG ANALOG CLKOUT12
MUX DELAY DELAY MUX
CLKOUT6 FUNDAMENTAL MODE FUNDAMENTAL MODE CLKOUT12

COARSE DIVIDER CYCLE CYCLE DIVIDER COARSE

DIGITAL SLIP/ SLIP/ DIGITAL
SCLKOUT7 (1 TO 4094) (1 TO 4094) DELAY SCLKOUT13
DELAY SYNC SYNC
MUX ANALOG ANALOG MUX
SCLKOUT7 DELAY DELAY SCLKOUT13
FUNDAMENTAL MODE FUNDAMENTAL MODE

DEVICE
LDOs SPI ALARM GENERATION CONTROL
13033-032

BGA LDO LDO LDO LDO LDO LDO SDATA SCLK SLEN GPIO1 GPIO2 GPIO3 GPIO4 SYNC RESET
BYP1 BYP2 BYP3 BYP4 BYP5 BYP6 BYP7

Figure 35. Top Level Diagram

Rev. C | Page 24 of 71
Data Sheet HMC7044
DUAL PLL OVERVIEW In addition, PLL1 monitors its active reference for failure and
The HMC7044 uses a cascade of two PLLs, referred to as a dual smoothly takes appropriate action, switching to a redundant
loop topology. The term dual loop sometimes refers to other reference or going into holdover as appropriate. Figure 36
architectures as well; therefore, always refer to the block diagram shows the architecture of PLL1 with a typical frequency
shown in Figure 35 to remove any ambiguity. In this architecture, configuration.
the first PLL (PLL1) normally operates as a jitter attenuator. PLL1 Jitter Attenuation
locks a clean local VCXO to a relatively noisy reference using a For jitter attenuation, PLL1 consists of all the usual
very narrow loop bandwidth. The loop bandwidth preserves the components in a PLL: a phase/frequency detector (PFD1),
average frequency of the reference signal (which is normally charge pump (CP1), reference divider (R1), and feedback
correct), while rejecting most of its noise. The second PLL takes divider (N1). The loop filter is external to provide maximum
this low noise VCXO and multiplies it up to the VCO frequency flexibility, and the loop bandwidth (BW) is normally
(in the 2 GHz to 3 GHz range) with very little additive noise. The configured very narrow (20 Hz to 500 Hz) to filter any jitter
architecture provides the benefits of an output frequency locked to and spurious tones coming in from relatively poor references.
an input reference signal, while being insensitive to its noise
The noise profile of PLL1 is typically dependent on the loop
profile.
bandwidth, input reference noise, and the VCXO characteristic.
In ICs such as the HMC7044, the VCO is then connected to an The inherent noise sources of PLL1 (the PFD, dividers, and
array of output channels, each with an optional RF divider and charge pump) are not normally observable in an application
phase control. The key feature that distinguishes an IC with and are significantly more relaxed compared with PLL2.
JESD204B support is the ability to ensure that all outputs with
Note that the loop filter components on the board are typically
their associated dividers have a user defined phase relationship
configured to produce a certain loop bandwidth, given a fixed
every time, regardless of process, voltage, or temperature. This
PFD rate, charge pump current, and VCXO characteristic.
ability is necessary to support the JESD204B SERDES standard
Adjusting any of these parameters from their nominal positions
for data converters, but it is also an immensely useful feature in
affects the loop dynamics, which can be to the advantage of the
other applications as well, in all forms of arrayed systems and in
user (for example, to scale loop BW with charge pump current),
many test and measurement scenarios.
but it must not be performed without an analysis of the stability
COMPONENT BLOCKS—INPUT PLL (PLL1) of the loop. Analog Devices, Inc., provides a variety of software
PLL1 General Description (Jitter Attenuator) tools to design the loop filter and model the effects of any
A variety of local clocks, particularly in synchronous networks, change in parameters. Contact Analog Devices for the latest
derive their timing from a remote node in the network. These recommendation.
reference signals can arrive via a GPS or clock data recovery The lock time of PLL1 typically takes the longest duration in
(CDR) receiver, or from a variety of other sources. Often, these the clock network, and, aside from any nonlinear slewing, takes
derived references are relatively poor quality, in terms of spurious approximately 5/PLL1_BW (for example, 5 ms for a 1 kHz loop
content, noise, and reliability. BW). Fortunately, there are no requirements that PLL1 must be
The function of PLL1 is to lock a clean VCXO to the average locked before proceeding with PLL2, output calibration, and
frequency of one of these references and feed it to PLL2 to phasing, which normally allows system configuration to
generate a high quality clock for local use. continue in parallel while PLL1 is settling.

Rev. C | Page 25 of 71
HMC7044 Data Sheet
FORCE
VTUNE
LOCKDET
CYCLESLIP PLL1 DAC
FORCE VTUNE ADC/DAC
FSM
LOS CONTROL
MAINTAIN_HOLDOVER

61.44MHz RESET
COMPARATOR
122.88MHz
61.44MHz 9.76MHz
38.4MHz ÷R1 UP TO FSMI LOCKDET
RST

PHASE TRISTATE
SET PFD1 ERROR CP1
>~4ns?
0 D Q LOCKDET
LCM RST MAINTAIN LOOP
DIVIDERS DOWN HOLDOVER FILTER
÷N1

CYCLE SLIP
DETECTED
(TO PLL1 FSM)
VCXO

13033-033
TO PLL2 122.88MHz

Figure 36. PLL1 Architecture with a Typical Frequency Configuration

Lock Detect PLL1 can operate in manual or automode (via the automode
The lock detect circuit in both PLL1 and PLL2 function the reference switching bit). In manual mode, the user selects the
same way. They count the number of consecutive clock cycles active reference using Manual Mode Reference Switching[1:0]
in which the phase error at the PFD is below a threshold. Any in Register 0x0029 and determines whether to go into holdover
phase error above this threshold resets the counter, and the (via the force holdover bit). In automode, the PLL1 FSM uses
count is restarted. When the count reaches its programmed the loss of signal (LOS) information, phase error data, lock
limit, the lock detect signal is issued and the clock of the detect, and configuration data from the SPI to determine how
counter is gated off to reduce power/coupling until a large to handle reference interruptions. In either mode, all status
phase error restarts the process. indicators are available, but PLL1 only takes evasive action in
automode. Figure 37 shows a simplified state diagram of the
Although the PLL2 loop BW is relatively well defined, the PLL1
PLL1 FSM.
loop BW can vary widely in any given application. The SPI word,
PLL1 Lock Detect Timer[4:0] in Register 0x0028, configures the During reset, PLL1 is held in the initialization (INIT) state. When
PLL1 lock detect timer and looks for 2PLL1 Lock Detect Timer[4:0] reset is deasserted, during the preload state, the enabled reference
consecutive LCM clock cycles with a phase-error <~4 ns to paths, the reference priority table, and LOS indicators are
issue the lock detect. Because the loop BW of PLL1 can vary examined to select the best reference, and, on the next cycle, it
drastically depending on the application, the user must set up attempts to lock. After the requisite number of counts has
the threshold such that 2PLL1 Lock Detect Timer[4:0] LCM periods is on elapsed with low phase error, lock detect is asserted and PLL1
the order of 2× to 4× the loop time constant. For example, for transitions to the locked state. When PLL1 is locked, a loss of lock,
fLCM = 61.44 MHz, and a loop BW of 200 Hz, set PLL1 Lock Detect LOS on the active reference, or a reference switch event initiated
Timer[4:0] = 19 or 20. If the value is set much higher, the lock by a priority clash transitions the FSM to enter holdover, where it
detect circuit takes an unnecessary length of time to indicate tristates the CP and potentially forces VTUNE with the holdover
lock after the phases stabilize. If the value is set much lower (for DAC. When a stable clock is available and other optional
example, much less than a loop time constant), it can improperly conditions are met, the FSM exits holdover. Exiting holdover is
indicate lock during acquisition, which can cause the PLL1 handled in one of a few different ways, designed to minimize
finite state machine (FSM) to improperly fall in and out of phase/frequency hits during the transition. Figure 37 shows a
holdover mode. simplification of the PLL1 FSM. In the actual implementation,
the holdover state is broken into a number of subsections
Holdover/Reference Switching Overview corresponding to holdover entry, stable holdover conditions,
When switching between redundant references, or when all and holdover exit. The state of the PLL1 FSM is always available
references are gone and the PLL1 is left open loop, there are for a read via the SPI (PLL1 FSM State[2:0] bits in
often requirements to prevent frequency deviations that can Register 0x0082).
cause downstream circuits and traffic links to overrun FIFOs
and/or lose lock themselves.

Rev. C | Page 26 of 71
Data Sheet HMC7044
RESET
PLL1 LOS Detection
The HMC7044 checks the validity of a reference by comparing
INIT
its approximate frequency vs. the VCXO. The HMC7044 supports
references at different frequencies. The first step is to divide the
available references and the VCXO to the lowest common multiple
PRELOAD
frequency (fLCM). These divider settings are available via the SPI
control bits (CLKINx/CLKINx Input Prescaler[7:0] and OSCIN/
LOCKING OSCIN Input Prescaler[7:0]). In the example shown in Figure 36,
fLCM = 61.44 MHz. The VCXO derived clock at fLCM is the main
LOCKDET clock to the PLL1 FSM controlling the FSM, lock detect timer,
and ADC/DAC filtering and holdover circuits. Although not
LOCKED
required, using the VCXO clock allows the LOS detection and
REVERTIVE
PLL1 FSM to operate at a higher rate than the PFD, allowing it to
NOT LOCKDET AND HIGHER PRIORITY LOS ACTIVE REF recognize a reference failure early and enter holdover, sometimes
CLOCK IS AVAILABLE
before a failing reference that has started to drift in either phase
or frequency (or both) can influence the PFD or CP.
HOLDOVER
The dividers in the LOS block, and to some extent, R1, pose a
AT LEAST ONE REFERENCE OK AND BEST few challenges. The input frequencies are up to 800 MHz, with
AVAILABLE REFERENCE IS SELECTED
[AND PHASES CROSSED ZERO (OPTIONAL)]
a wide divider range. Furthermore, they are designed to tolerate
[AND DAC ASSISTED RELEASE COMPLETE (OPTIONAL)] glitchy clocks without catastrophic results, because a reset
OR
JUST ENTERED HOLDOVER (<HOLDOFF TIMER[7:0]) phase is not always available after an issue is detected.
13033-034

AND PREVIOUS CLOCK RECOVERS

[AND DAC ASSISTED RELEASE COMPLETE (OPTIONAL)] When all the references are divided to the same frequency, they
Figure 37. PLL1 FSM Simplified State Diagram— are compared relative to the VCXO derived path, and thus each
Autorevertive Reference Switching = 1
other. This comparison is performed by a circuit that looks for
PLL1 Reference Inputs three edges of a clock within one period of the other. If it appears
PLL1 accepts up to four candidate references on that a reference signal is too slow, its LOS flag is asserted and, in
CLKIN3/CLKIN3 to CLKIN0/CLKIN0. If all references appear automode, PLL1 uses this information to disqualify and/or
valid, according to the LOS, PLL1 uses a reference priority table abandon a reference. Conversely, if it appears that the VCXO is
to select the best candidate. Using the PLL1 reference priority too slow according to any of the active references, a warning is
generated (available as one of the configurable options for the
control bits, program the highest priority clock (CLKIN0/CLKIN0
GPO, or readable on the SPI) but no automated action occurs.
, CLKIN1/CLKIN2, CLKIN2/CLKIN2, or CLKIN3/CLKIN3),
and then second priority clock, and so on. It is not necessary to The HMC7044 monitors reference signals for three edges of a
include unused reference inputs in the reference priority table. clock within one period of the other, instead of the more intuitive
Instead, specify the same useful clock in multiple positions. In two edges, to avoid false LOS flags as clocks that are slightly out
automode, reference switching occurs in the preload state (see of frequency cross each other in phase in the presence of
Figure 37) as PLL1 exits reset, or while PLL1 is in the holdover interference, noise, and circuit offsets. The result is that the LOS
state. triggers when the failing reference clock frequency is
approximately an octave from the intended frequency.
The reference clock input pins (Pin 36, Pin 37, Pin 39, Pin 40,
Pin 42, and Pin 43) have dual functions; therefore, SPI configura- After a reference signal returns and its frequency is within an
tion is important for proper functionality. See the PLL1 octave of the VCXO, two to three cycles of the LOS validation
Programming Considerations section for more information timer must expire before the LOS flag is deasserted and the
about the relevant control bits, and the Reference Buffer Details reference is considered for potential use. The LOS validation
section for interface recommendations. timer is programmable between 0 LCM cycles (no hysteresis),
and 64 LCM cycles via LOS Validation Timer[2:0] in
When a reference fails, the sourcing circuit recognizes a fault
Register 0x0015, Bits[2:0].
and disables either the clock or the buffer driving the signal to
the HMC7044. For this reason, hysteresis in the input buffers
prevents internal toggling for signal swings <~75 mV p-p
differential, which allows further elements in the PLL1 architecture
to cleanly recognize the interruption and prevent unwanted
transients in the frequency.

Rev. C | Page 27 of 71
HMC7044 Data Sheet
PLL1 Holdover Entry Shortcut The recommended methods are as follows:
When a reference fails, the LOS circuit takes a number of LCM • Wait for zero phase error (no divider reset): wait for LOS =
clock cycles to recognize the problem and to request the PLL1 0 and low phase error at PFD (Holdover Exit Criteria[1:0] = 1,
FSM enter holdover and tristate the CP. By that time, if one of Holdover Exit Action[1:0] = 1)
the missing edges is needed to trigger the R divider output, the • Resetting the dividers: wait for LOS = 0 and reset the
PFD and CP have already saturated, pulling current out of the R1/N2 dividers (Holdover Exit Criteria[1:0] = 0, Holdover
loop filter for these cycles, and disturbing the holdover frequency. Exit Action[1:0] = 0)
The probability of this happening decreases as the PFD rate • DAC assisted release: wait for LOS = 0, reset R1/N2, and
decreases relative to fLCM, but it is not eliminated. The HMC7044 configure for DAC assisted release (Holdover Exit
includes a unique feature to prevent this type of frequency Criteria[1:0] = 0, Holdover Exit Action[1:0] = 3)
runaway.
Wait for Zero Phase Error
A sensor watches the up/down pulses from the PFD (see
Figure 35). When locked, the pulse width is small, based on any While the CP is still in tristate, the FSM monitors the PDF for a
small signal error, PFD/CP offset, and the reset delay of the PFD. If cycle slip indication as the candidate reference and VCXO signal
the device is in the locked state and has a phase error that is larger cross each other. The crossing of the reference and VCXO phases
than expected (~4 ns), it is a sign that the reference has failed, and eventually occurs but can take a long time, as determined by the
the device immediately tristates the pump, reducing the inherent frequency error due to an imperfect holdover. Just after a
amount of time charge can be extracted from the loop from cycle slip event, the phase error at the PFD is at its minimum
about five LCM cycles (162 ns at 30.72 MHz) to <4 ns. This error value, and there is minimal glitch as the PLL reacquires. Figure 38
indication also invalidates the lock detect. When the FSM shows an example where the reference is removed and PLL1
acknowledges the issue, it holds the CP in tristate. When using goes into tristate-based holdover. After approximately 7 sec, the
the optional DAC-based holdover, the FSM instructs the reference is restored and, about a second later, the phases cross
ADC/DAC that is tracking the VTUNE voltage to switch from and the PLL reacquires, all with less than 0.15 ppm of deviation
sense mode to force mode, holding it steady to within 1 LSB from the original frequency value.
(about 20 mV or 0.4 ppm) until the HMC7044 senses a stable 1.0
FREQUENCY DEVIATION FROM NOMINAL (ppm)

reference and transitions out of holdover. 0.8

PLL1 Holdover Steady State 0.6

When in the holdover state, the user has the following two 0.4
TRISTATE HOLDOVER MODE ≈ 8 SECONDS
options: 0.2

• Tristate the CP 0

• Tristate the CP and engage the holdover DAC –0.2

ENABLE REFERENCE AND LOCK
–0.4
When in tristate mode, the HMC7044 has a very high
impedance charge pump output (~10 GΩ). This output is –0.6

normally an insignificant contributor to PLL1 VTUNE leakage,

13033-035
–0.8

which is determined primarily by the on-board loop filter –1.0

0 1 2 3 4 5 6 7 8 9 10
components and the VCXO tuning port. This mode allows the TIME (Seconds)
tuning voltage to maintain itself for significant periods while in
Figure 38. Frequency Deviation from Nominal vs. Time of Tristate Holdover
holdover. Entry and Exit When the Phases Cross Zero
To accommodate indefinite periods in holdover, or to ensure This first method of uncontrolled release suffers from an
VTUNE is driven and not susceptible to drift, the second option indeterminate amount of time for the phases to cross and exit
(set via the holdover uses DAC bit in Register 0x0029, Bit 2) holdover. However, if it takes 1 sec for the phases to cross, the
forces the VTUNE voltage to its time averaged value, obtained by frequencies are off by only 1 Hz. If it takes 10 sec to cross, the
low-pass filtering the ADC value while the PLL is reporting error is 0.1 Hz. If the error is so low that it takes a long time to
lock. The holdover sensing ADC and the driving DAC are exit holdover, the device is effectively frequency locked. In
seven bits each and have an LSB of approximately 19 mV. some applications, being open-loop for this long of a duration
PLL1 Holdover Exit can be acceptable, considering the very small frequency errors.
The transition out of holdover can happen in three ways and Although this method of holdover exit is very smooth, it can
is controlled by the Holdover Exit Criteria[1:0] bits and the take a very long time to occur.
Holdover Exit Action[1:0] bits in Register 0x0016 (see the Control
Register Map Bit Descriptions section for details), which
describes the steps that the FSM takes as the HMC7044 exits
holdover and acquires lock.
Rev. C | Page 28 of 71
Data Sheet HMC7044
Resetting the Dividers 20

FREQUENCY DEVIATION FROM NOMINAL (ppm)

16
If using tristate-based holdover, the second holdover exit
method is recommended. When a reference appears available 12
DAC RELEASE
(LOS = 0), the FSM resets the R and N dividers and allows them 8

to restart immediately. This approach limits the maximum phase 4

error coming out of holdover to two VCXO cycles (about 8 ns 0
for typical VCXO frequencies). There is no need to wait an
–4
undetermined amount of time (as in the first method of
uncontrolled release) to initiate the switch. –8

–12
DAC Assisted Release

13033-136
–16
If using DAC-based holdover, the DAC and CP can set VTUNE
–20
concurrently as the devices exits holdover. With the DAC output –10 0 10 20 30 40 50 60 70 80 90

impedance at a relatively low setting (for example, 5 Ω), the device TIME (ms)

resets the dividers as in the second method, and then the CP Figure 40. DAC Assisted Release
attempts to influence VTUNE. The CP fails, with the DAC sinking 20

FREQUENCY DEVIATION FROM NOMINAL (ppm)

the current it is trying to inject into the VTUNE node. Gradually, 16
the device increases the output impedance of the DAC, and the 12
CP gains more influence to manipulate VTUNE, pulling the phases 8
DO NOTHING

into alignment. Using this DAC assisted CP release method

4
limits the holdover exit transients to within ~1 ppm.
0
Figure 39 to Figure 41 compare the holdover release methods:
–4
resetting the dividers vs. DAC assisted release, and
uncontrolled release (which starts with a phase error of up to –8

one PFD period) as the device exits holdover and reacquires to –12

a reference signal.

13033-236
–16
20
–20
FREQUENCY DEVIATION FROM NOMINAL (ppm)

–10 0 10 20 30 40 50 60 70 80 90
16
TIME (ms)
12 Figure 41. Wait for Zero Phase Error (No Divider Reset)
RESET DIVS
8
PLL1 Programming Considerations
4
Configuring Reference Inputs for PLL1 vs. Other Uses
0
To use the four reference clocks for PLL1, the input buffer must
–4
be enabled and selected as a relevant path for PLL1.
–8

–12
Table 13. Input Buffer and Reference Path Settings
Bit Name Description
13033-036

–16
Buffer Enable Enable the input buffer (where x = 0,
–20
–10 0 10 20 30 40 50 60 70 80 90 1, 2, 3, or V for VCXO) via
TIME (ms) Register 0x000A to Register 0x000E
Figure 39. Resetting the Dividers PLL1 Reference Path Select one of four available reference
Enable[3:0] paths for PLL1
Because the CLKIN0/RFSYNCIN, CLKIN0/RFSYNCIN,
CLKIN1/FIN, and CLKIN1/FIN pins can be configured for
output network purposes, and the CLKIN2/OSCOUT0 and
CLKIN2/OSCOUT0 pins can function as oscillator outputs, the
SPI bits in Table 14 must be configured accordingly.

Rev. C | Page 29 of 71
HMC7044 Data Sheet
Table 14. Reference Clock Input Bit Settings PLL2 has the following features:
Bit Name Description • Lock detect
CLKIN0/CLKIN0 In RF SYNC 0 = CLKIN0/CLKIN0 does not • Frequency doubler
Input Mode function as an RF sync input
• Partially integrated loop filter
CLKIN1/CLKIN1 in External 0 = CLKIN1/CLKIN1 does not
VCO Input Mode
• VCO selection, external VCO use
function as external VCO (FIN//FIN)
• VCO calibration
OSCOUT0/OSCOUT0 1 = OSCOUT0/OSCOUT0 buffer
Driver Enable does not drive CLKIN2/CLKIN2 pins • Multichip synchronization via PLL2
Lock Detect
Choosing fPD1 The lock detect function of PLL2 behaves the same way as in
Although PLL1 supports a wide range of PFD frequencies, PLL1. It counts the number of consecutive PFD clock cycles
there are trade-offs with setting the frequency too high or too that occur with a low phase error. When it reaches a count of
low. A few megahertz is high enough to allow the comparison 512, it declares lock. The threshold of 512 is adjustable, but
frequency to stay at an offset outside of the PLL2 loop BW and because the PLL2 loop BW does not vary as much as PLL1, it is
thus suppress any coupling that manages to bypass the PLL1 expected that the user never needs to change this threshold.
loop filter. Frequency Doubler
Choosing fLCM The user can engage a frequency doubler after the VCXO buffer
At a minimum, fLCM must be a common submultiple of all and before the reference divider (see Figure 35). The frequency
available references. Typical frequencies include 122.88 MHz, doubler assumes an approximate 50% input duty cycle, where
61.44 MHz, 38.4 MHz, 30.72 MHz, 3.84 MHz, and 1.92 MHz. any duty cycle distortion can result in a spur, at fPD2/2, sup-
This fLCM clock is the main clock for the PLL1 digital logic. This pressed by the PLL2 loop filter. Use of the frequency doubler is
clock rate also scales the PLL1 lock detect timer speeds/thresholds, highly recommended to achieve the best spectral performance,
holdover ADC averaging times, and LOS assertion and provided the PFD is kept under its 250 MHz frequency limit.
revalidation delays. Higher frequencies slightly improve the Partially Integrated Loop Filter
response times to reference interruptions, whereas lower
Although the large components for the PLL2 loop filter are off
frequencies can slightly reduce current consumption of the
chip, there is a small on-chip resister/capacitor (RC) section
device by up to ~10 mA. Values in the 30 MHz to 70 MHz
formed with R = 80 Ω and C = 4.7 pF in series. This RC section
range are recommended.
forms a higher order pole at ~420 MHz. For practical condi-
Program the PLL1 lock detect timer threshold based on the tions, this filter segment does not affect the stability of the loop.
PLL1 loop BW and fLCM of the user. OFF-CHIP
80Ω
There are reserved registers, as described in the Control Register CP VCO

Map Bit Descriptions section, that must be reprogrammed from 4.7pF

their default values. For example, Register 0x00A5 must be set 13033-037
from 0x00 to 0x06.
Figure 42. On-Chip RC Circuit
COMPONENT BLOCKS—OUTPUT PLL (PLL2)
PLL2 Overview Figure 43 shows the VCO input network. Depending on the
frequency band of interest (2.5 GHz or 3.0 GHz), the user must
PLL2 is a very low noise integer PLL designed to multiply the specify which VCO to enable via the VCO Selection[1:0] SPI
frequency from the VCXO to the VCO. It typically operates
word. To use the CLKIN1/FIN pin as an external VCO signal,
with a loop BW of 10 kHz to 700 kHz. Use bandwidths on the
program this word to 0, and set the CLKIN1/CLKIN1 in external
lower end of the range to preserve the inherent VCO phase
VCO input mode bit.
noise at 800 kHz offset (useful in GSM-based systems), where
bandwidths on the upper end can provide the best integrated
phase noise/jitter values.
Internally, PLL2 has a number of features that allow it to
efficiently achieve a Banerjee floor FOM of −232 dBc and a
flicker FOM of −266 dBc. The combination of the on-board
VCO, an internal VCXO doubler, a low N2 minimum divide
ratio, and the ability to clock the PFD at up to 250 MHz results
in an integrated jitter (at 12 kHz to 20 MHz) of 44.0 fs typical.

Rev. C | Page 30 of 71
Data Sheet HMC7044
VCO Selection, External VCO Use Apply the SYNC input rising edge only once. After sensing the
rising edge on the VCXO domain, the SYNC input is ignored
~2.5GHz for the next 16 × 6 tPD2 periods as the FSM processes the event.
VCO
VCO ENABLE[1:0] = 10 After this period expires, the FSM becomes sensitive again to
the SYNC pin. If the SYNC is applied periodically, the first edge
TO PLL2
initializes the synchronization process, and then the subsequent
AUTOCAL ~3.0GHz N2 DIVIDER edges may or may not be recognized depending on their
VCO
VCO ENABLE[1:0] = 01 width/repetition rate with respect to 16 × 6 tPD2.
TO
OUTPUT
NETWORK
Note that the SYNC rising edge must be provided cleanly with
CLKIN1/CLKIN1 respect to the HMC7044 VCXO input pin (OSCIN/OSCIN).
IN EXTERNAL VCO
INPUT MODE = 1
The user normally has access to the CLKINx/CLKINx pins of
PLL1, and not to the VCXO signal directly. When PLL1 is locked,
however, the VCXO rising edge is roughly aligned to the PLL1
÷2 active reference, and, therefore, the user has indirect knowledge
of the phase of the VCXO. The VCXO is also available as an

13033-038
DIVIDE BY 2 ON
output of the HMC7044, if the user wants to retime the SYNC
EXTERNAL VCO ENABLE signal more directly.
Figure 43. VCO Input Network The phase offset of the PLL1 active reference with respect to the
VCO Calibration VCXO is a function of the internal delay of each path. This base
The on-board VCOs contain an AGC loop that regulates the delay offset is a function of deterministic conditions (LCM, R1,
core voltage of the oscillator to achieve the desired swing and N1 divider setpoints, termination setups, and slew rates), but is also
thus the trade-off between phase-noise and power consump- subject to PVT variations that compress or exaggerate this offset.
tion. This AGC loop uses large external bypass capacitors to For most practical purposes, the multichip synchronization
eliminate the noise impact of the AGC loop, and therefore takes feature is limited to PLL1 reference rates <200 MHz.
time to settle after power-up, sleep, or after changing the VCO CLOCK OUTPUT NETWORK
Selection[1:0] setting. With the 100 nF/1 μF configuration,
settling time takes approximately 10 ms (typical). In the HMC7044, PLL1 is responsible for frequency cleanup,
redundancy, and hitless switching. PLL2 and the VCOs handle
Each of the VCOs in the HMC7044 has 32 frequency bands. integrated jitter and performance at an 800 kHz offset. Although
Normally, three or more subbands can synthesize any particular the PLL1/PLL2 and VCXO components are important, much of
frequency, and an on-board autotune algorithm selects the the uniqueness of a JESD204B clock generation chip relates to
solution that provides tuning margin for temperature fluctuations. its array of output channels.
Temperature compensation is applied inside to ensure the device
can be calibrated at any frequency and maintain lock as the In a device such as the HMC7044, some of the output network
frequency is carried to any other frequency in the operating requirements include the following:
range. • Very good phase noise floor of the DCLK channels that
The autotune is triggered by toggling the restart dividers/FSMs can be connected to critical data converter sample clock
bit in Register 0x0001, Bit 1, after R2 and N2 are programmed, inputs
the VCXO is applied, and the VCO peak detector loop has settled. • A large number of DCLK and SYSREF channels
• Deterministic phase alignment between all output
When the VCXO is applied to the system and the R2 and N2
channels relative to one another
divide ratios are programmed, the autotune algorithm has the
• Fine phase control of synchronization channels with
information needed to find the appropriate band of the VCO.
respect to the DCLK channel
Multichip Synchronization via PLL2 • Frequency coverage to satisfy typical clock rates in
To synchronize multiple HMC7044 devices together, it is recom- expectant systems
mended to use the SYNC input pin. If the SYNC pin transitions • Skew between SYSREF and DCLK channels that is much
from 0 to 1 with sufficient setup/hold margin with respect to the less than a DCLK period
VCXO, this synchronization event is deterministically carried • Spur and crosstalk performance that does not impact
through PLL2, up the timing chain through the N2 divider, and system budgets
then to the master SYSREF timer (see the Clock Output Network
section for more information). This mechanism of deterministic
phase adjustment allows synchronization of the SYSREF timer
and output phases of multiple HMC7044 devices.

Rev. C | Page 31 of 71
HMC7044 Data Sheet
The HMC7044 output network also supports the following Each of the 14 output channels are logically identical. The only
recommended features, which are sometimes critical in user distinction between the SYSREF and DCLK channels is in the
applications: SPI configuration and in how they are used. Each channel
contains independent dividers, phase adjustment, and analog
• Deterministic synchronization of the output channels with
delay circuits. This combination provides the ultimate flexibility,
respect to an external signal, which allows multichip
cleanly accommodating nonJESD204B devices in the system.
synchronization and clean expansion to larger systems
• Pulse generator behavior to temporarily generate a In addition to the 14 output channel dividers, there is an internal
synchronization pulse stream at user request SYSREF timer that continually operates, and the synchronization
• Flexibility to define unused JESD204B SYSREF and DCLK of the output channel dividers occurs deterministically with respect
channels for other purposes to this timer, which can be rephased externally by the user.
• Glitchless phase control of signals relative to each other The pulse generator functionality of the JESD204B standard
• 50% duty cycle clocks with odd division ratios involves temporarily generating SYSREF output pulses, with
• Multimode output buffers with a variety of swings and appropriate phasing, to downstream devices. The centralized
termination options SYSREF timer and its associated SYNC/pulse generator control
• Skew between all channels that is much less than a DCLK manage the process of enabling the intended SYSREF channels,
period phasing them, and then disabling them for signal integrity and
• Adjustable performance vs. power consumption for less power saving advantages.
sensitive clock channels
• Flexibility to use an external VCO for very high
performance application requirements
SYSREF INPUT NETWORK
SYNC FROM PLL2 N DIVIDER
(DUE TO SYNC PIN EVENT)

RF SYNC

D Q RESET

SYSREF
TIMER
VCO PATH
SYNC/ PULSE GENERATOR REQUEST (FROM SPI, GPI, OR SYNC PIN)
PULSE GENERATOR
CONTROL SYNC REQUEST (FROM SPI OR GPI)

SYNC_FSM_STATE
OUTPUT CHANNEL × 14

LEAF
CONTROLLER

CLOCK DIGITAL DELAY

GATING DIVIDER AND RETIME
13033-039

Figure 44. Clock Output Network Simplified Diagram

Rev. C | Page 32 of 71
Data Sheet HMC7044
Basic Output Divider Channel System wide broadcast signals can be triggered from the SPI or
Each of the 14 output channels are logically identical, and support general-purpose input (GPI) port to issue a SYNC command
divide ratios from 1 to 4094. The supported odd divide ratios (to align dividers to the system internal SYSREF timer), issue a
(1, 3, 5) have 50.0% duty cycle. The only distinction between a pulse generator stream, (temporarily exporting SYSREF signals to
SYSREF channel and a DCLK channel is in the SPI configura- receivers), or to cause the dividers to slip a number of VCO
tion and the typical usage of a given channel. cycles to adjust their phases.

For basic functionality and phase control, each output path Individual dividers can be made sensitive to these events by
consists of the following: adjusting their slip enable, SYNC enable, and Start-Up Mode[1:0]
configuration, as described in Table 16.
• Divider—generates the logic signal of the appropriate
frequency and phase When output buffers are configured in CMOS mode and phase
alignment is required among the outputs, additional multislip
• Digital phase adjust—adjusts the phase of each channel in
increments of ½ VCO cycles delays must be issued for Channel 0, Channel 3, Channel 5,
Channel 6, Channel 9, Channel 10, and Channel 13. The value
• Retimer—a low noise flip flop to retime the channel,
of the delay must be as large as half of the selected divider ratio.
removing any accumulated jitter
Note that this requirement of having additional multislip delays
• Analog fine delay—provides a number of ~25 ps delay steps
is not needed when channels are used in LVPECL, CML or
• Selection mux—selects the fundamental, divider, or analog LVDS mode.
delay, or an alternate path
• Multimode output buffer—low noise LVDS, CML, CMOS, If a channel is configured to behave as a pulse generator, to
or LVPECL temporarily power up and power down according to GPI, SPI,
or SYNC pin pulse generator commands, it has additional
The digital phase adjuster and retimer launch on either clock controls to define its behavior outside of the pulse generator
phase of the VCO, depending on the digital phase adjust setpoint chain (see Table 17).
(Coarse Digital Delay[4:0]).
Each divider has an additional phase offset register that adjusts
To support divider synchronization, arbitrary phase slips, and its start phase, or to influence the behavior of slip events sent
pulse generator modes, the following blocks are included: via the SPI (see Table 18).
• A clock gating stage pauses the clock for synchronization Table 19 outlines the typical configuration combinations for a
or slip operations DCLK channel relative to a SYSREF synchronization channel.
• An output channel leaf (×14) controller manages slip, Note that other combinations are possible. Synchronization of
synchronization, and pulse generators with information downstream devices can be managed manually, or by using the
from the SYSREF FSM pulse generator functionality of the HMC7044. See the Typical
Each channel has an array of control signals. Some of the controls Programming Sequence section for more information about the
are described in Table 15. differences between the two methods.

Rev. C | Page 33 of 71
HMC7044 Data Sheet
Table 15. Basic Divider Controls
Bit Name Description
Channel Enable Channel enable. If 0, the channel is disabled. If 1, the channel can be enabled depending on the settings of
Start-Up Mode[1:0], Seven Pairs of 14-Channel Outputs Enable[6:0], and sleep mode.
12-Bit Channel Divider[11:0] Divide ratio.12-bit divide ratio, split across two words (MSB and LSB). Set to 0 if not using the channel divider
(Output Mux Selection[1:0] = 2 or 3).
High Performance Mode High performance mode. Adjusts divider and buffer bias to slightly improve swing/phase noise at the
expense of power. The performance advantage is about 1 dB, and the current penalty depends on whether
the divider is enabled.
Coarse Digital Delay[4:0] Digital delay. Adjusts the phase of the divider signal by up to 17 ½ cycles of the VCO. This circuit is practically
noiseless; however, note that a low amount of additional current is consumed.
Fine Analog Delay[4:0] Analog delay. Adjusts the delay of the divider signal in increments of ~25 ps. Set Output Mux Selection[1:0] =
1 to expose this channel. Causes phase noise degradation of up to 12 dB; therefore, do not use on noise sensitive
DCLK channels.
Output Mux Selection[1:0] Output mux selection. 00 = divider channel, 01 = analog delay, 10 = other channel of pair, 11 = input VCO
clock. Fundamental mode can be generated with the divider (12-Bit Channel Divider[11:0] = 1), or via Output
Mux Selection[1:0] = 10 and 12-Bit Channel Divider[11:0] = 0. Because the divider path consumes power and
degrades phase noise slightly, the fundamental mux path is recommended, but at a cost of a deterministic
skew vs. a path that is divider based. Such skew can be compensated for with delay (digital and analog) on
the divider-based path.

Table 16. Channel Features

Bit Name Description
Slip Enable Slip enable. A channel processes slip requests broadcast from the SPI or GPI (or, if multislip enable = 1, initiated
following a recognized SYNC or pulse generator startup).
SYNC Enable SYNC enable. A channel processes synchronization events broadcast from the SPI or GPI or due to SYNC/RF SYNC (via
the SYSREF FSM) to reset its phase. This signal can be safely toggled on and off to adjust SYNC sensitivity without
risking the state of the divider.
Start-Up Mode[1:0] 00 = asynchronous (normal mode). The divider starts with uncontrolled phase. It is rephased by SYNC events if SYNC
enable = 1.
11 = dynamic (pulse generator mode). The divider monitors pulse generator events broadcast from the SYSREF
controller. It is powered up just before a pulse generator chain, rephased at the start, and powered down after the
pulse generator chain. This is only supported for divide ratios > 31.

Table 17. Pulse Generator Mode Behavior Options

Bit Name Description
Dynamic Driver Enable Dynamic output buffer enable (pulse generator mode only).
0 = the output buffer is simply enabled/disabled with the main channel enable.
1 = the output buffer enable is controlled together with the channel divider, which allows it to dynamically power
down outside pulse generator events.
Force Mute[1:0] Force mute for dynamic mode. If 10, and the channel enable is true (channel enable = 1), the signal just before the
output buffer is asynchronously forced to Logic 0 when not generating pulses. Otherwise, if 00, outputs are forced
to float naturally to VCM. To see the effect of this, the output buffer must be enabled, which is dependent on the
dynamic driver enable and Start-Up Mode[1:0] controls. Logic 0 is supported for CML, LVPECL and CMOS driver modes.

Rev. C | Page 34 of 71
Data Sheet HMC7044
Table 18. Multislip Configuration
Bit Name Description
Multislip Enable Allow multislip. This bit determines whether the 12-Bit Multislip Digital Delay[11:0] parameter is used for multislip
operations. Note that a multislip operation is automatically started following a SYNC or pulse generator initiation if
multislip enable = 1.
12-Bit Multislip Digital Multislip amount. If multislip enable = 1, any slip events (caused by GPI, SPI, SYNC, or pulse generator events) repeat the
Delay[11:0] number of times set by 12-Bit Multislip Digital Delay[11:0] to adjust the phase by the multislip amount × VCO cycles. A
value of 0 is not supported if multislip enable = 1. Note that phase slips are free from a noise and current perspective,
that is, no additional power is needed and with no noise degradation, but they take some time to occur. Each slip
operation takes a number of nanoseconds to complete, and thus the phases do not necessarily stabilize immediately.
An alarm is available for the user to indicate when all phase operations are complete.

Table 19. Typical Configuration Combinations

Pulse Generator
Bit Name DCLK SYSREF Manual SYSREF NonJESD204B
12-Bit Channel Divider[11:0] Small Big Big Any
Start-Up Mode Bit Normal Pulse generator Normal Normal
Fine Analog Delay[4:0] Off Optional Optional Off
Coarse Digital Delay[4:0] Optional Optional Optional Optional
Slip Enable Optional Optional Optional Optional
Multislip Enable Optional Off Optional Optional
High Performance Mode Optional Off Off Optional
Sync Enable On On On Optional
Dynamic Driver Enable Don’t care On Don’t care Don’t care
Force Mute[1:0] Don’t care On Don’t care Don’t care

Synchronization FSM/Pulse Generator Timing Figure 46 shows the start-up behavior of an example divider
The block diagram showing the interface of the SYNC/pulse that is configured as a pulse generator, with a period matching
generator control to the divider channels and the internal the internal SYSREF period.
SYSREF timer is shown in Figure 44. The startup of the pulse stream occurs a fixed number of VCO
The SYSREF timer counts in periods defined by SYSREF cycles after the FSM transitions to the start phase. Disabling the
Timer[11:0], a 12-bit setting from the SPI. It sequences the enable, pulse generator stream where the logic path is forced to zero
reset, and startup, and disables the downstream dividers in the comes from a combinational path, directly from the FSM.
event of SYNC or pulse generator requests. Program the SYSREF Because the divider has the option for nearly arbitrary phase
timer count to a submultiple of the lowest output frequency in adjustment, it provides the opportunity for the stop condition
the clock network, and not faster than 4 MHz. To synchronize to arrive when the pulse stream is a Logic 1 and creates a runt
divider channels, it is recommended, though not required, that pulse.
the SYSREF Timer[11:0] bits be set to a related frequency that For phase offsets of zero to 50% − 8 VCO cycles, and VCO
is either a factor or multiple of other frequencies on the IC. frequencies <3 GHz, this condition is met naturally within the
The pulse generator is defined with respect to the periods of design. For fanout only mode >3 GHz, it is recommended to
this SYSREF timer, not with respect to the output period. This use digital delay or slip offsets to increase the natural phase
leads to timing constraint that must be considered to prevent offset and avoid the stress condition.
any runt pulses from affecting the pulse generator stream.
The situation is avoided by never applying phase offset more
than 50% − 8 VCO cycles to an output channel configured as a
pulse generator.

Rev. C | Page 35 of 71
HMC7044 Data Sheet
RF_SYNC OR PLL2 SYNC

RESET

NOTIFY CHANNEL FSM

PULSE
SYNC GENERATOR WHAT TYPE OF EVENT
SETUP SETUP IS COMING

CLEAR POWER DIVIDERS/SYNC BLOCKS,

PAUSE BLOCKS, RESET LATCHES

WAIT REMOVE LATCH RESET,

PREPARE TO START CLOCKS
SYNC
REQUEST START CLOCKS,
STARTUP WITH CLEAN TIMING,
SMALL PIPELINE DELAY

PULSE WAIT UNTIL THE NUMBER OF

GENERATOR PULSE GENERATOR CYCLES
TIMEOUT?
EXPIRES

DONE REMOVE POWER

13033-041
PULSE
GENERATOR
REQUEST

Figure 45. Synchronization FSM Flowchart

FSM STATE STARTUP PULSE GENERATOR = 2 DONE

DIVIDER CHANNEL

IF MUTE SIGNAL ARRIVES QUICKLY

RELATIVE TO SIGNAL TRAIN,
FIXED NUMBER OF VCO CYCLES NO RUNT PULSE
FROM STATE CHANGE TO STARTUP, AND
ANY INTENTIONAL DIGITAL/ANALOG OFFSET

FSM STATE STARTUP PULSE GENERATOR = 2 DONE

DIVIDER CHANNEL
13033-042

IF CONTROL IS TOO LATE

RELATIVE TO SIGNAL TRAIN,
THERE IS A RUNT PULSE

Figure 46. Start-Up Behavior of an Example Divider Configured as a Pulse Generator

Clock Grouping, Skew, and Crosstalk As the output channels are more tightly coupled (by sharing a
Although the output channels are logically independent, for clock group, or by sharing a supply pin), the skew is minimized.
physical reasons, they are first grouped into pairs called clock However, the isolation between those channels suffers. Table 20
groups. Each clock group shares a reference, an input buffer, shows the clock grouping, and Table 21 show the typical skew
and a sync retime flip flop originating from the VCO and isolation that can be expected and how it scales with distance
distribution network. between output channels.

The second level of grouping is according to the supply pin. Isolation improves as either the aggressor or affected frequencies
Clock Group 1 (Channel 2 and Channel 3) are on an independ- decreases. Nevertheless, for particularly important clock channels
ent supply, and the other supply pins are each responsible for where spurious tones must be minimized, carefully consider
two clock groups. their frequency and channel configurations to isolate continu-
ously running frequencies onto different supply domains.
Channels configured as pulse generators are normally not an
issue, because they are disabled during normal operation.

Rev. C | Page 36 of 71
Data Sheet HMC7044
NORTHWEST NORTH
Table 20. Supply Pin Clock Grouping by Location

SCLKOUT11,
SCLKOUT13,

SCLKOUT11
SCLKOUT13

SCLKOUT9,
CLKOUT12,

CLKOUT10,

SCLKOUT9
VCC9_OUT

VCC8_OUT
CLKOUT12

CLKOUT10

CLKOUT8,
CLKOUT8
Supply Pin Location Clock Group Channel

GPIO3,
GPIO4

GPIO2
VCC2_OUT Southwest 1 2
3 CLKOUT0, VCC7_PLL2
VCC4_OUT South 2 4 CLKOUT0
SCLKOUT1, CPOUT2

5 SCLKOUT1
LDOBYP7
RESET AND SYNC
3 6 OSCIN, OSCIN
BGABYP1
7 LDOBYP6
LDOBYP2
VCC8_OUT North 4 8 OSCOUT1,
LDOBYB3 OSCOUT1
9 CLKIN2/OSCOUT0,
VCC1_VCO CLKIN2/OSCOUT0
5 10 LDOBYP4 VCC6_OSCOUT
11 LDOBYP5 CLKIN0/RFSYNCIN,
CLKIN0/RFSYNCIN
VCC9_OUT Northwest 6 12 SCLKOUT3,
SCLKOUT3 VCC5_PLL1
13 CLKOUT2,
CLKOUT2 CLKIN1/FIN,
0 0 VCC2_OUT CLKIN1/FIN

VCC4_OUT (CH4,
CH5, CH6, CH7
SCLKOUT5,

SCLKOUT7,
SCLKOUT5

SCLKOUT7
CLKOUT4,

CLKOUT6,
CLKOUT4

CLKOUT6

CPOUT1
SYSREF

CLKIN3,
CLKIN3
GPIO1
VCC3
SPI
Table 21. Typical Skew and Isolation vs. Distance

13033-043
Typical 1 GHz Isolation SOUTHWEST SOUTH

Distance Skew (ps) Differential (dB) Figure 47. Clock Grouping

Distant Supply Group ±20 90 to 100
SYSREF Valid Interrupt
Closest Neighbor on ±15 70
Different Supply Group One of the challenges in a JESD204B system is to control and
Shared Supply ±10 60 minimize the latency from the primary system controller IC,
Same Clock Group ±10 45 typically an ASIC or FPGA, to the data converters. To estimate
the correct amount of latency in the system, the designer must
Output Buffer Details know how long it takes for a master clock generator like the
Figure 47 shows the clock groups by supply pin location on the HMC7044 to provide the correct output phases at each output
package. With appropriate supply pin bypassing, spurious noise channel after receiving the synchronization request. Typically, a
of the outputs is improved. Table 20 describes how the supply period of time is required on the device to implement the
pins of each of the 14 clock channels are connected within the change requests on the outputs due to internal state machine
seven clock groups. Clock channels that are closest to each cycles, data transfers, and any propagation delays. The SYSREF
other have the best channel to channel skew performance, but valid interrupt is a function to notify the user that the correct
they also have the lowest isolation from each other. Select output settings and phase relationships are established,
critical signals that require high isolation from each other from allowing the user to identify quickly that the desired SYSREF
groups with distant supply pin locations. An example of the and device clock states are presented at the outputs of the
expected isolation and channel to channel skew performance of HMC7044.
the HMC7044 at 1 GHz is provided in Table 21. The user has the flexibility to assign the SYSREF valid interrupt
to a GPO pin or to use a software flag, set via Register 0x007D,
Bit 2, which the user can poll as necessary. The flag notifies the
user when the system is configured and operating in the desired
state, or conversely when it is not ready.

Rev. C | Page 37 of 71
HMC7044 Data Sheet
REFERENCE BUFFER DETAILS Single-Ended Operation
Input Termination Network—Common for All Input The buffers support single-ended signals with a slightly reduced
Buffers input sensitivity and bandwidth. If driving these buffers single-
The four reference input buffers to PLL1, as well as the VCXO ended, ac couple the unused section of the buffer to ground at
input buffer, share similar architecture and control features. the input of the die.
The input termination network is configurable to 100 Ω, 200 Ω, Maximum Signal Swing Considerations
and 2 kΩ differentially. It is typically ac-coupled on the board, The internal supplies to these buffers are regulated from 3.3 V
and uses the on-chip resistive divider to set the internal to 2.8 V using on-chip regulation. With very high power
common-mode voltage, VCM, to 2.1 V. references, the signal swing can be enough to drive the signal
By closing the 50 Ω termination switch (see Figure 48), the above the 2.8 V rail. The ESD network and parasitic diodes are
network also serves as the termination system for an LVPECL generally able to shunt the excess power and protect the
driver. Although the input termination network for the four internal circuits even above 13 dBm. Nevertheless, to protect
PLL1 reference buffers and the VCXO input buffer is identical, from latch-up concerns, the signals on reference inputs must
the buffer behind the network is different. not exceed the 2.8 V internal supply. For a 2.1 V common-
mode, 50 Ω single-ended source, this 2.8 V limit allows
2.8V
50Ω, ~700 mV of amplitude, or 6 dBm of maximum reference
100Ω,
1kΩ power.
4kΩ
TYPICAL PROGRAMMING SEQUENCE
5kΩ 1pF
50Ω, To initialize the HMC7044 to an operational state, use the
100Ω,
50Ω 1kΩ following programming procedure:
13033-045

1. Connect the HMC7044 to the rated power supplies. No

Figure 48. On-Chip Termination Network for VCXO and Reference Buffers specific power supply sequencing is necessary.
2. Release the hardware reset by switching from Logic 1 to
PLL1 Reference Buffer Stages Logic 0) when all supplies are stable.
The PLL1 reference buffers use a CMOS input stage, are 3. Load the configuration updates (provided by Analog
capable of a wide common-mode input range (0.4 V to 2.4 V) Devices) to specific registers (see Table 74).
and have hysteresis to support reliable LOS detection. These 4. Program PLL2. Select the VCO range (high or low). Then
buffers are designed to be driven reliably with an input swing of program the dividers (R2, N2, and reference doubler).
>375 mV p-p diff (the half swing point of the LVDS standard) and 5. Program PLL1. Set the lock detect timer threshold based
support up to 800 MHz operation. For signal swings that are on the PLL1 BW of the user system. Set the LCM, R1, and
below 375 mV p-p diff, the hysteresis of the buffer can engage N1 divider setpoints. Enable the reference and VCXO
and shut down the signal to the internal reference paths. The input buffer terminations.
exact input hysteresis threshold varies as a function of common- 6. Program the SYSREF timer. Set the divide ratio (a
mode level and input frequency, but generally ranges from submultiple of the lower output channel frequency). Set the
about 75 mV p-p diff to 300 mV p-p diff. pulse generator mode configuration, for example, selecting
VCXO Buffer Stage level sensitive option and the number of pulses desired.
7. Program the output channels. Set the output buffer modes
The VCXO input buffer is implemented with a bipolar input
(for example, LVPECL, CML, and LVDS). Set the divide
stage to meet the stringent noise requirements of PLL2. Its
ratio, channel start-up mode, coarse/analog delays, and
common-mode input range is tighter and, if set externally,
performance modes.
must be kept between 1.6 V and 2.4 V. This buffer does not
8. Wait until the VCO peak detector loop has stabilized
have hysteresis and is functional down to very low signal levels.
(~10 ms after Step 4).
Although the buffer remains functional down to these low
9. Ensure that the references are provided to PLL1 and the
signal levels, for optimal performance, keep the input power
VCXO is powered.
greater than −4 dBm when driven single-ended, or −7 dBm per
10. Issue a software restart to reset the system and initiate
side when driven differentially.
calibration. Toggle the restart dividers/FSMs bit to 1 and
Recommendations for Normal Use then back to 0.
For both styles of buffer, unless there are extenuating circum- 11. PLL1 starts to lock in parallel with PLL2 going through its
stances in the application, use the 100 Ω differential termination calibration and lock procedure. Wait for PLL2 to be locked
to control reflections, use the on-chip dc bias network to set the (takes ~50 μs in typical configurations).
common-mode level, and externally ac couple the input signals. 12. Confirm that PLL2 is locked by checking the PLL2 lock
Do not use receiver side dc termination of the LVPECL signal. detect bit.

Rev. C | Page 38 of 71
Data Sheet HMC7044
13. Send a sync request via the SPI (set the reseed request bit) POWER SUPPLY CONSIDERATIONS
to align the divider phases and send any initial pulse The HMC7044 contains on-board regulators to shield some of
generator stream. the more sensitive supplies from external noise and interference as
14. Wait 6 SYSREF periods (6 × SYSREF Timer[11:0]) to allow much as possible. Nevertheless, the user must still take special
the outputs to phase appropriately (takes ~3 μs in typical care to the supply noise profile of the VCC1_VCO supply to
configurations). achieve the intended performance of the device.
15. Confirm that the outputs have all reached their phases by
checking that the clock outputs phases status bit = 1. In general, a flat input noise of 200 nV/Hz is an equivalent
16. At this time, initialize any other devices in the system. contributor to the VCO noise and causes a 3 dB increase in the
PLL1 may not be locked yet, but the small frequency offset noise profile from about 100 kHz to 10 MHz when the VCO is
that can result on the output of the HMC7044 is not normally the dominant contributor. This increase equates to a roughly
severe enough to cause synchronization or initialization one-to-one conversion from dBV to dBc/Hz at a 1 MHz offset,
failures. Configure slave JESD204B devices in the system and fOUT = 2.457 GHz, that is, 200 nV/Hz = −134 dBV, and the
to operate with the SYSREF signal outputs from the performance of the VCO at 1 MHz offset at 2.4576 GHz is
HMC7044. SYSREF channels from the HMC7044 can ~−134 dBc/Hz. The PSRR of the VCO follows its closed-loop
either be on asynchronously, or dynamically, and can noise profile; therefore, as the offset moves in and the VCO
temporarily turn on for a pulse generator stream. profile becomes higher, the 200 nV/Hz noise stays approximately
17. Wait for PLL1 to lock. This takes ~50 ms for a 100 Hz BW equal to the VCO. To stay suitably below the VCO, a supply
(from Step 11). input with <50 nV/Hz is recommended on the VCC1_VCO pin
18. When all JESD204B slaves are powered and ready, send a across the 100 kHz to 10 MHz frequency range.
pulse generator request to send out a pulse generator chain The output buffers are also susceptible to supply noise, but to a
on any SYSREF channels programmed for pulse generator lesser extent. A noise tone of −60 dBV at a 40 MHz offset
mode. results in a −90 dBc tone at the output of the buffers in CML
mode and −85 dBc in LVPECL mode. This result is a relatively flat
The system is now initialized.
frequency response, and these numbers are measured
For power savings and the reduction of the crosscoupling of differentially. Phase noise/spurs caused by supply noise on the
frequencies on the HMC7044, shut down the SYSREF channels. output buffers do not scale with output frequency, whereas
1. Program each JESD204B slave to ignore the SYSREF input those on the VCO do.
channel. Table 22 lists the supply network of the HMC7044 by pin,
2. On the HMC7044, disable the individual channel enable showing the relevant functional blocks. Six different usage
bits of each SYSREF channel. profiles are defined for the network, not including the output
To resynchronize one or more of the JESD204B slaves, use the channel supplies, which are accounted for separately.
following procedure: The values listed under Profile 0 to Profile 5 in Table 22 and
1. Set the channel enable (and SYNC enable bit) of the Table 23 are the typical currents of that block or feature. If a
SYSREF channel of interest. number is not listed in a profile column, a typical profile does
2. To prevent an output channel from responding to a sync not exist for that block or feature, but the user can mix and
request, disable the SYNC enable mask of each channel so match features outside of the profile list and can determine what
that it continues to run normally without a phase the power consumption is going to be given the current listings
adjustment. per feature.
3. Issue a reseed request to phase the SYSREF channel
properly with respect to the DCLK.
4. Enable the JESD204B slave sensitivity to the SYSREF
channel.
5. If the SYSREF channel is in pulse generator mode, wait at
least 20 SYSREF periods from Step 3, and issue a pulse
generator request.

Rev. C | Page 39 of 71
HMC7044 Data Sheet
Table 22. Supply Network of the HMC7044 by Pin for PLL1, PLL2, VCO, and SYSREF
Typical Current Profile 1
Circuit Block Comment (mA) 0 1 2 3 4 5
VCC5_PLL1
CLKIN1/CLKIN1 Used as a PLL1 reference 2 2 2 2 2
CLKIN1/CLKIN1 Buffer Extra if used as buffer for external VCO 5 5 5
CLKIN0/CLKIN0 Used as a PLL1 reference 2 2
CLKIN0/CLKIN0 Buffer Extra current if used as RF 5
synchronization buffer2
External VCO Path (fOUT) 18 18
External VCO Path Extra current for divide by 2 10
External RF Synchronization Path 3 3
Regulator to 1.8 V, Bypassed on LDOBYP2 N2, digital functions 2 2 2 2 2 2 2
PLL1 Functions LOS, R1, N1, FSMs 10 10 10
PLL2 Functions R2, N2, lock detect 17 17 17 17
SYSREF Timer 1 1
GPO Drivers in High Speed Mode 4
Regulator to 2.8 V, Bypassed on LDOBYP3 2 2 2 2 2 2 2
PLL1 PFD/CP 7 7 7
PLL1 DAC Holdover Circuits 2 2
CLKIN2/CLKIN2 Buffer 2 2
CLKIN3/CLKIN3 Buffer 2 2
Subtotal for VCC5_PLL1 90 4 49 23 21 46 11
VCC7_PLL2
Regulator to 2.8 V, Bypassed on LDOBYP7 2 2 2 2 2 2 2
PLL2 PFD, Doubler, and R2 and N2 21 4 21 21 21
Outputs
PLL2 Charge Pump 8 8 8 8
Regulator to 2.8 V, Bypassed on LDOBYP6 2 2 2 2 2 2 2
VCXO Buffer 16 16 16 16 16
OSCOUTx/OSCOUTx Divider/Mux 5 8
Subtotal for VCC7_PLL2 57 8 49 20 49 49 4
VCC1_VCO
VCO Distribution Network Minimum possible value 71 8 71 0 71 71 71
Sync Retiming Network Minimum possible value 6 8
VCO Regulator, Bypass to LDOBYP4 and 84 84 84
LDOBYP5
VCO Core
Subtotal for VCC1_VCO 163 8 155 0 155 71 71
VCC3_SYSREF
SYSREF Input Network3 11
SYSREF Counter Base 12 12 12
SYSREF Counter, SYNC network 4
Subtotal for VCC3_SYSREF 27 0 12 0 0 0 12
Subtotal (Without Output Paths) 20 265 43 225 166 98
1
Profile 0 = sleep mode; Profile 1 = power-up defaults, PLL1 with four references and PLL2 locked with internal VCO, SYSREF timer running; Profile 2 = PLL1 only, one
reference; Profile 3 = PLL2 + VCO, PLL1 disabled, Profile 4 = PLL2 with external VCO, PLL1 disabled, Profile 5 = fanout mode only, SYSREF running.
2
This is the incremental amount of current for the circuit when put in this mode. For example, the CLKIN0/CLKIN0 buffer used for PLL1 reference path is 2 mA. If it is
used as the external synchronization buffer instead, it is 2 + 5 mA.
3
The transient current in PLL2 synchronization mode can be temporarily enabled when using external synchronization.
4
The current is highly dependent on rate of input/output and load of input/output traces. For heavily loaded traces, it is recommended to use a series resistance of
~100 Ω to minimize the IR drop on the internal regulator during transitions.
5
The function varies from 8 mA to 14 mA depending on divide ratio.
6
A temporary current only.

Rev. C | Page 40 of 71
Data Sheet HMC7044
Table 23. Supply Network of the HMC7044 by Pin for the Clock Output Network
Profile 1
Per Output Channel Comment Typical Current (mA) 0 1 2 3 4
Digital Regulator and Other Sources 2.5 0.5 2.5 2.5 2.5 2.5
Buffer
LVPECL
Including term currents 43 43 43 43
CML100
High Power Including term currents 31
Low Power 24
LVDS
High Power At 307 MHz 10 10
Low Power
CMOS At 100 MHz, both sections 25
Channel Mux Included 2
Digital Delay
Off Included2
Setpoint > 1 3 3 3
Analog Delay
Off Included2 0
Minimum Setting Glitchless mode enabled 9 9
Maximum Setting 9 9
Divider Logic
0 Not using divider path Included2 0 0
÷1 27
÷2 27
÷3 31
÷4 29
÷5 32
÷6 29
÷8 30
÷16 31 31
÷32 32
÷2044 32 32
SYNC Logic 3 4
Slip Logic3 4
Subtotal 2.5 48 89 13 92
1
Profile 0 = sleep mode; Profile 1 = fundamental mode; Profile 2 =SYSREF channel matched to fundamental mode; Profile 3 = LVDS—high power signal source from
other channel; Profile 4 = worst case configuration for power consumption of a channel.
2
The base current consumption of the circuit (for example, mux) is included in the buffer typical current.
3
Currents occur only temporarily during a synchronization event.

Rev. C | Page 41 of 71
HMC7044 Data Sheet

SERIAL CONTROL PORT

SERIAL PORT INTERFACE (SPI) CONTROL 4. The host registers the 8-bit data on the next eight rising
The HMC7044 can be controlled via the SPI using 24-bit edges of SCLK. The HMC7044 places 8-bit data (D7 to D0)
registers and three pins: serial port enable (SLEN) serial data MSB first on the next eight falling edges of SCLK.
input/output (SDATA), and serial clock (SCLK). 5. Deassertion of SLEN completes the register read cycle.

The 24-bit register, shown in Table 24, consists of the Typical Write Cycle
following: A typical write cycle is shown in Figure 49, and occurs as
• 1-bit read/write command follows:
• 2-bit multibyte field (W1, W0) 1. The master (host) asserts both SLEN and SDATA to
• 13-bit address field (A12 to A0) indicate a read, followed by a rising edge SCLK. The slave
• 8-bit data field (D7 to D0) (HMC7044) reads SDIO on the first rising edge of SCLK
after SLEN. Setting SDATA low initiates a write.
Table 24. SPI Bit Map 2. The host places the 2-bit multibyte field to be written to
MSB LSB low (0) on the next two falling edges of SCLK. The
Bit 23 Bit 22 Bit 21 Bits[20:8] Bits[7:0] HMC7044 registers the 2-bit multibyte field on the next
R/W W1 W0 A12 to A0 D7 to D0 two rising edges of SCLK.
3. The host places the13-bit address field (A12 to A0), MSB
Typical Read Cycle first on SDATA on the next 13 falling edges of SCLK. The
A typical read cycle is shown in Figure 48 and occurs as follows: HMC7044 registers the 13-bit address field (MSB first) on
SDIO over the next 13 rising edges of SCLK.
1. The master (host) asserts both SLEN and SDATA to
4. The host places the 8-bit data (D7 to D0) MSB first on the
indicate a read, followed by a rising edge SCLK. The slave
next eight falling edges of SCLK. The HMC7044 register
(HMC7044) reads SDATA on the first rising edge of SCLK
the 8-bit data (D7 to D0) MSB first on the next eight rising
after SLEN. Setting SDATA high initiates a read.
edges of SCLK.
2. The host places the 2-bit multibyte field to be written to
5. The final rising edge of SCLK performs the internal data
low (0) on the next two falling edges of SCLK. The
transfer into the register file, updating the configuration of
HMC7044 registers the 2-bit multibyte field on the next
the device.
two rising edges of SCLK.
6. Deassertion of SLEN completes the register write cycle.
3. The host places the 13-bit address field (A12 to A0) MSB
first on SDATA on the next 13 falling edges of SCLK. The
HMC7044 registers the 13-bit address field (MSB first) on
SDATA over the next 13 rising edges of SCLK.

SCLK 1 2 3 4 5 16 17 18 24

SDATA X READ W1 W0 A12 A11 A0 D7 D6 D0

13033-046

SLEN

Figure 49. SPI Timing Diagram, Read Operation

1 2 3 4 5 16 17 18 24
SCLK

WRITE
SDATA X W1 W0 A12 A11 A0 D7 D6 D0
13033-047

SLEN

Figure 50. SPI Timing Diagram, Write Operation

Rev. C | Page 42 of 71
Data Sheet HMC7044

APPLICATIONS INFORMATION
PLL1 NOISE CALCULATIONS where:
Use the following equations to calculate the flicker noise, noise Floor_FOM is the figure of merit at the floor frequency.
floor, and total unfiltered phase noise specifications for PLL1 fPD2 is the phase detector frequency of PLL2.
(see Table 4). Calculate the total phase noise (unfiltered) as follows:
Calculate the flicker noise using the following equation: PN ( f OUT , f PD2 , f OFFSET ) =
PN(fOUT, fOFFSET) = Flicker_FOM + 20 × log(fOUT) – 10 ×  2 2 
 PN _ Flicker   PN _ Floor 
log(fOFFSET) (1)       (6)
10 × log  10  10  + 10  10  
where:  
 
PN() is the phase noise.
fOUT is the output frequency. where:
fOFFSET is the offset of noise frequency from the output carrier PN_Flicker is the phase noise at the flicker frequency.
frequency. PN_Floor is the phase noise at the floor frequency.
Flicker_FOM is the figure of merit at the flicker frequency. PHASE NOISE FLOOR AND JITTER
Calculate the noise floor as follows: Use the following equations to calculate the phase noise floor,
PN ( f OUT , f PD1 ) = jitter density, and rms additive jitter due to floor specifications
(2) (see Table 9).
 f 
Floor_ FOM + 20 × log  OUT  − 10 × log ( f PD1 ) Calculate the phase noise floor using the following equation:

 f PD1 
PNFLOOR = FOMOCHAN + 10 × log(fOUT) + Harmonic
where:
Degradation + Power Degradation (7)
fPD1 is the phase detector frequency of PLL1.
Floor_FOM is the figure of merit at the floor frequency. where:
PNFLOOR is the phase noise floor at fOUT.
Calculate the total phase noise (unfiltered) as follows:
FOMOCHAN is the figure of merit of the output channel.
PN ( f OUT , f PD1 , f OFFSET ) = Harmonic Degradation is the harmonics of the signal captured
  PN _ Flicker 
2
 PN _ Floor 
2  in the measurement bandwidth of the receiving
      (3) instrument/circuit. The noise power of those harmonics can
10 × log  10  10  + 10  10 

  fold and influence the overall noise.
  Power Degradation results when the noise floor (−174 dBm/Hz)
where: of the measurement system approaches the noise power in the
PN_Flicker is the phase noise at the flicker frequency. phase noise floor of the signal. For example, a phase noise value
PN_Floor is the phase noise at the floor frequency. of−155 dBc/Hz at 0 dBm carrier level is −155 dBm/Hz and is
PLL2 NOISE CALCULATIONS easily measurable. If, however, the carrier level is −20 dBm, the
phase noise of –155 dBc/Hz is −175 dBm/Hz and is not
Use the following equations to calculate the flicker noise, noise
measurable below the other noise sources in the system.
floor, and total unfiltered phase noise specifications for PLL2
(see Table 5). Calculate the jitter density at fOUT as follows:
 PN floor 10 
Calculate the flicker noise using the following equation:  
 f × 2π 
PN(fOUT, fOFFSET) = Flicker_FOM + 20 × log(fOUT) – 10 × JITTER _ DENSITY _ FLOOR = 2 × 10  OUT  (8)
log(fOFFSET) (4) where JITTER_DENSITY_FLOOR is the jitter density of floor at
where: fOUT.
fOUT is the output frequency. Calculate the rms additive jitter due to floor using the following
fOFFSET is the offset of noise frequency from the output carrier equation:
frequency.
JITTER_RMS_FLOOR = JITTER_DENSITY_FLOOR ×
Flicker_FOM is the figure of merit at the flicker frequency.
√Observation Bandwidth (9)
Calculate the noise floor as follows:
where Observation Bandwidth is the desired integration
 f  bandwidth of the noise with a lower and upper bound offset
PN ( f OUT , f PD2 ) = Floor_ FOM + 20 × log  OUT  − 10 ×

 f PD2  from the output carrier frequency.
log ( f PD2 )
(5)

Rev. C | Page 43 of 71
HMC7044 Data Sheet

CONTROL REGISTERS
CONTROL REGISTER MAP
Register addresses that are not listed in Table 25 are not used and writing to those registers has no effect. Do not change the values of
registers that are marked as reserved. When writing to registers with bits that are marked reserved, take care to always write the default
value for the reserved bits, unless listed otherwise in the subsection of other controls in Table 25.

Table 25. Control Register Map

Default
Addr. Register Bit 0 Value
(Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex)
Global Control
0x0000 Global soft Reserved Soft reset 0x00
reset control
0x0001 Global Reseed High Reserved Force Mute Pulse Restart Sleep 0x00
request and request performance holdover output generator dividers/ mode
mode control distribution drivers request FSMs
path
0x0002 Reserved PLL2 Slip Reserved 0x00
autotune request
trigger
0x0003 Global Reserved RF reseeder VCO Selection[1:0] SYSREF PLL2 PLL1 0x37
enable enable timer enable enable
control enable
0x0004 Reserved Seven Pairs of 14-Channel Outputs Enable[6:0] 0x7F
0x0005 Global mode SYNC Pin Mode CLKIN1/ CLKIN0/ PLL1 Reference Path Enable[3:0] 0x4F
and enable Selection[1:0] CLKIN1 in CLKIN0 in RF
control external VCO SYNC input
input mode mode
0x0006 Global clear Reserved Clear 0x00
alarms alarms
0x0007 Global Reserved 0x00
0x0008 miscellaneous Reserved (Scratchpad) 0x00
control
0x0009 Reserved Disable 0x01
SYNC at
lock
PLL1
0x000A CLKIN0/ Reserved Input Buffer Mode[3:0] Buffer 0x07
CLKIN0 input enable
buffer control
0x000B CLKIN1/ Reserved Input Buffer Mode[3:0] Buffer 0x07
CLKIN1 input enable
buffer control
0x000C CLKIN2/ Reserved Input Buffer Mode[3:0] Buffer 0x07
CLKIN2 input enable
buffer control
0x000D CLKIN3/ Reserved Input Buffer Mode[3:0] Buffer 0x07
CLKIN3 input enable
buffer control
0x000E OSCIN/OSCIN Reserved Input Buffer Mode[3:0] Buffer 0x07
input buffer enable
control
0x0014 PLL1 Fourth Priority Third Priority CLKINx/CLKINx Second Priority First Priority 0xE4
reference CLKINx/CLKINx Input[1:0] Input[1:0] CLKINx/CLKINx CLKINx/CLKINx
priority Input[1:0] Input[1:0]
control
0x0015 PLL1 loss of Reserved LOS Validation Timer[2:0] 0x03
signal (LOS)
control
0x0016 PLL1 Reserved Holdover Exit Holdover Exit 0x0C
holdover exit Action[1:0] Criteria[1:0]
control

Rev. C | Page 44 of 71
Data Sheet HMC7044
Default
Addr. Register Bit 0 Value
(Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex)
0x0017 PLL1 Reserved Holdover DAC Value[6:0] 0x00
0x0018 holdover Reserved ADC Force Holdover BW 0x04
DAC/ADC tracking DAC to Reduction[1:0]
control disable holdover
in quick
mode
0x0019 PLL1 LOS Reserved LOS LOS uses 0x00
mode control bypass VCXO
input prescaler
prescaler
0x001A PLL1 charge Reserved PLL1 CP Current[3:0] 0x08
pump control
0x001B PLL1 PFD Reserved PLL1 PFD up PLL1 PFD PLL1 PFD PLL1 PFD PLL1 PFD 0x18
control enable down up force down polarity
enable force
0x001C CLKIN0/ CLKIN0/CLKIN0 Input Prescaler[7:0] 0x04
CLKIN0 input
prescaler
control
0x001D CLKIN1/ CLKIN1/CLKIN1 Input Prescaler[7:0] 0x01
CLKIN1 input
prescaler
control
0x001E CLKIN2/ CLKIN2/CLKIN2 Input Prescaler[7:0] 0x04
CLKIN2 input
prescaler
control
0x001F CLKIN3/ CLKIN3/CLKIN3 Input Prescaler[7:0] 0x01
CLKIN3 input
prescaler
control
0x0020 OSCIN/OSCIN OSCIN/OSCIN Input Prescaler[7:0] 0x04
Input
prescaler
control
0x0021 PLL1 16-Bit R1 Divider[7:0] (LSB) 0x04
0x0022 reference 16-Bit R1 Divider[15:8] (MSB) 0x00
divider
control (R1)
0x0026 PLL1 16-Bit N1 Divider[7:0] (LSB) 0x10
0x0027 feedback 16-Bit N1 Divider[15:8] (MSB) 0x00
divider
control (N1)
0x0028 PLL1 lock Reserved PLL1 lock PLL1 Lock Detect Timer[4:0] 0x0F
detect detect uses
control slip
0x0029 PLL1 Reserved Bypass Manual Mode Reference Holdover Auto- Auto- 0x05
reference debouncer Switching[1:0] uses DAC revertive mode
switching reference reference
control switching switching
0x002A PLL1 holdoff Holdoff Timer[7:0] 0x00
time control
PLL2
0x0031 PLL2 Reserved 0x01
miscellaneou
s control
0x0032 PLL2 Reserved Bypass 0x01
frequency frequency
doubler doubler
control
0x0033 PLL2 12-Bit R2 Divider[7:0] (LSB) 0x02
0x0034 reference Reserved 12-Bit R2 Divider[11:8] (MSB) 0x00
divider
control (R2)

Rev. C | Page 45 of 71
HMC7044 Data Sheet
Default
Addr. Register Bit 0 Value
(Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex)
0x0035 PLL2 16-Bit N2 Divider[7:0] (LSB) 0x20
0x0036 feedback 16-Bit N2 Divider[15:8] (MSB) 0x00
divider
control (N2)
0x0037 PLL2 charge Reserved PLL2 CP Current[3:0] 0x0F
pump control
0x0038 PLL2 PFD Reserved PLL2 PFD up PLL2 PFD PLL2 PFD PLL2 PFD PLL2 PFD 0x18
control enable down up force down polarity
enable force
0x0039 OSCOUTx/ Reserved OSCOUTx/ OSCOUTx/ 0x00
OSCOUTx OSCOUTx Divider[1:0] OSCOUTx
path control path
enable
0x003A OSCOUTx/ Reserved OSCOUT0/OSCOUT0 Driver Reserved OSCOUT0/OSCOUT0 OSCOUT0/ 0x00
OSCOUTx Mode[1:0] Driver Impedance[1:0] OSCOUT0
driver control driver
enable
0x003B Reserved OSCOUT1/OSCOUT1 Driver Reserved OSCOUT1/OSCOUT1 OSCOUT1/ 0x00
Mode[1:0] Driver Impedance[1:0] OSCOUT1
driver
enable
0x003C PLL2 Reserved 0x00
miscellaneous
control
GPIO/SDATA Control
0x0046 GPI1 control Reserved GPI1 Selection[3:0] GPI1 0x00
enable
0x0047 GPI2 control Reserved GPI2 Selection[3:0] GPI2 0x00
enable
0x0048 GPI3 control Reserved GPI3 Selection[3:0] GPI3 0x09
enable
0x0049 GPI4 control Reserved GPI4 Selection[3:0] GPI4 0x11
enable
0x0050 GPO1 control GPO1 Selection[5:0] GPO1 GPO1 0x37
mode enable
0x0051 GPO2 control GPO2 Selection[5:0] GPO2 GPO2 0x33
mode enable
0x0052 GPO3 control GPO3 Selection[5:0] GPO3 GPO3 0x00
mode enable
0x0053 GPO4 control GPO4 Selection[5:0] GPO4 GPO4 0x00
mode enable
0x0054 SDATA Reserved SDATA SDATA 0x03
control mode enable
SYSREF/SYNC Control
0x005A Pulse Reserved Pulse Generator Mode Selection[2:0] 0x00
generator
control
0x005B SYNC control Reserved SYNC SYNC SYNC 0x06
retime through polarity
PLL2
0x005C SYSREF timer SYSREF Timer[7:0] (LSB) 0x00
0x005D control Reserved SYSREF Timer[11:8] (MSB) 0x01
0x005E SYSREF Reserved 0x00
miscellaneous
control

Rev. C | Page 46 of 71
Data Sheet HMC7044
Default
Addr. Register Bit 0 Value
(Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex)
Clock Distribution Network
0x0064 External VCO Reserved Divide by Low 0x00
control 2 on frequency
external external
VCO VCO path
enable
0x0065 Analog delay Reserved Analog 0x00
common delay low
control power
mode
Alarm Masks Registers
0x0070 PLL1 alarm PLL1 near PLL1 lock PLL1 lock PLL1 holdover PLL1 CLKINx/CLKINx LOS Mask[3:0] 0x00
mask control lock mask acquisition detect mask status mask
mask
0x0071 Alarm mask Reserved Sync request PLL1 and Clock SYSREF PLL2 lock 0x10
control mask PLL2 lock outputs sync detect
detect phase status mask
mask status mask
mask
Product ID Registers
0x0078 Product ID Product ID Value[7:0] (LSB) 0x51
0x0079 Product ID Value[15:8] (Mid) 0x16
0x007A Product ID Value[23:16] (MSB) 0x30
Alarm Readback Status Registers
0x007B Readback Reserved Alarm
register signal
0x007C PLL1 alarm PLL1 near PLL1 lock PLL1 lock PLL1 holdover CLKINx/CLKINx LOS[3:0]
readback lock acquisition detect status
0x007D Alarm Reserved Sync request PLL1 and Clock SYSREF PLL2 lock
readback status PLL2 lock outputs sync detect
detect phases status
status
0x007E Latched Reserved PLL2 lock PLL1 lock PLL1 holdover CLKINx/CLKINx LOS Latched[3:0]
alarm acquisition acquisition latched
readback latched latched
0x007F Alarm Reserved
readback
miscellaneous
PLL1 Status Registers
0x0082 PLL1 status Reserved PLL1 Best Clock[1:0] PLL1 Active PLL1 FSM State[2:0]
registers CLKINx/CLKINx[1:0]
0x0083 Reserved PLL1 Holdover DAC Averaged Value[6:0]
0x0084 Holdover PLL1 Holdover DAC Current Value[6:0]
comparator
value
0x0085 Reserved PLL1 PLL1 PLL1 PLL1
active VCXO holdover holdover
CLKINx/ status ADC ADC input
CLKINx status range
LOS status
0x0086 Reserved PLL1 Holdover Exit Reserved
Phase[1:0]
0x0087 Reserved
PLL2 Status Registers
0x008C PLL2 status PLL2 autotune value
0x008D registers PLL2 Autotune Signed Error[7:0] (LSB)
0x008E PLL2 PLL2 PLL2 Autotune Signed Error[13:8] (MSB)
autotune autotune
status error sign
0x008F PLL2 Autotune FSM State[3:0] PLL2 SYNC FSM State[3:0]
0x0090 Reserved

Rev. C | Page 47 of 71
HMC7044 Data Sheet
Default
Addr. Register Bit 0 Value
(Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex)
SYSREF Status Register
0x0091 SYSREF status Reserved Channel SYSREF FSM State[3:0]
register outputs FSM
busy
Other Controls
0x0096 Reserved Reserved 0x00
0x0097 Reserved Reserved 0x00
0x0098 Reserved Reserved 0x00
0x0099 Reserved Reserved 0x00
0x009A Reserved Reserved 0x00
0x009B Reserved Reserved 0xAA
0x009C Reserved Reserved 0xAA
0x009D Reserved Reserved 0xAA
0x009E Reserved Reserved 0xAA
0x009F Reserved Clock output driver low power setting (for optimum performance, set to 0x4D instead of default value) 0x55
0x00A0 Reserved Clock output driver high power setting (for optimum performance, set to 0xDF instead of default value) 0x56
0x00A1 Reserved Reserved 0x97
0x00A2 Reserved Reserved 0x03
0x00A3 Reserved Reserved 0x00
0x00A4 Reserved Reserved 0x00
0x00A5 Reserved PLL1 more delay (PFD1, lock detect) (for optimum performance, set to 0x06 instead of default value) 0x00
0x00A6 Reserved Reserved 0x1C
0x00A7 Reserved Reserved 0x00
0x00A8 Reserved PLL1 holdover DAC gm setting (for optimum performance, set to 0x06 instead of default value) 0x22
0x00A9 Reserved Reserved 0x00
0x00AB Reserved Reserved 0x00
0x00AC Reserved Reserved 0x20
0x00AD Reserved Reserved 0x00
0x00AE Reserved Reserved 0x08
0x00AF Reserved Reserved 0x50
0x00B0 Reserved VTUNE preset setting (for optimum performance, set to 0x04 instead of default value) 0x09
0x00B1 Reserved Reserved 0x0D
0x00B2 Reserved Reserved 0x00
0x00B3 Reserved Reserved 0x00
0x00B5 Reserved Reserved 0x00
0x00B6 Reserved Reserved 0x00
0x00B7 Reserved Reserved 0x00
0x00B8 Reserved Reserved 0x00
Clock Distribution
0x00C8 Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 0 performance enable enable enable
control mode
0x00C9 12-Bit Channel Divider[7:0] (LSB) 0x04
0x00CA Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x00CB Reserved Fine Analog Delay[4:0] 0x00
0x00CC Reserved Coarse Digital Delay[4:0] 0x00
0x00CD 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00CE Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00CF Reserved Output Mux 0x00
Selection[1:0]
0x00D0 Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver enable
0x00D1 Reserved 0x00

Rev. C | Page 48 of 71
Data Sheet HMC7044
Default
Addr. Register Bit 0 Value
(Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex)
0x00D2 Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 1 performance enable enable enable
control mode
0x00D3 12-Bit Channel Divider[7:0] (LSB) 0x00
0x00D4 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x00D5 Reserved Fine Analog Delay[4:0] 0x00
0x00D6 Reserved Coarse Digital Delay[4:0] 0x00
0x00D7 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00D8 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00D9 Reserved Output Mux 0x00
Selection[1:0]
0x00DA Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver enable
0x00DB Reserved 0x00
0x00DC Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 2 performance enable enable enable
control mode
0x00DD 12-Bit Channel Divider[7:0] (LSB) 0x08
0x00DE Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x00DF Reserved Fine Analog Delay[4:0] 0x00
0x00E0 Reserved Coarse Digital Delay[4:0] 0x00
0x00E1 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00E2 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00E3 Reserved Output Mux 0x00
Selection[1:0]
0x00E4 Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver enable
0x00E5 Reserved 0x00
0x00E6 Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 3 performance enable enable enable
control mode
0x00E7 12-Bit Channel Divider[7:0] (LSB) 0x00
0x00E8 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x00E9 Reserved Fine Analog Delay[4:0] 0x00
0x00EA Reserved Coarse Digital Delay[4:0] 0x00
0x00EB 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00EC Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00ED Reserved Output Mux 0x00
Selection[1:0]
0x00EE Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver enable
0x00EF Reserved 0x00
0x00F0 Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 4 performance enable enable enable
control mode
0x00F1 12-Bit Channel Divider[7:0] (LSB) 0x02
0x00F2 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x00F3 Reserved Fine Analog Delay[4:0] 0x00
0x00F4 Reserved Coarse Digital Delay[4:0] 0x00
0x00F5 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x00F6 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x00F7 Reserved Output Mux 0x00
Selection[1:0]
0x00F8 Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver enable
0x00F9 Reserved 0x00

Rev. C | Page 49 of 71
HMC7044 Data Sheet
Default
Addr. Register Bit 0 Value
(Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex)
0x00FA Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 5 performance enable enable enable
control mode
0x00FB 12-Bit Channel Divider[7:0] (LSB) 0x00
0x00FC Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x00FD Reserved Fine Analog Delay[4:0] 0x00
0x00FE Reserved Coarse Digital Delay[4:0] 0x00
0x00FF 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0100 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0101 Reserved Output Mux 0x00
Selection[1:0]
0x0102 Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver enable
0x0103 Reserved 0x00
0x0104 Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 6 performance enable enable enable
control mode
0x0105 12-Bit Channel Divider[7:0] (LSB) 0x02
0x0106 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x0107 Reserved Fine Analog Delay[4:0] 0x00
0x0108 Reserved Coarse Digital Delay[4:0] 0x00
0x0109 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x010A Reserved 12-bit Multislip Digital Delay[11:8] (MSB) 0x00
0x010B Reserved Output Mux 0x00
Selection[1:0]
0x010C Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver enable
0x010D Reserved 0x00
0x010E Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 7 performance enable enable enable
control mode
0x010F 12-Bit Channel Divider[7:0] (LSB) 0x00
0x0110 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x0111 Reserved Fine Analog Delay[4:0] 0x00
0x0112 Reserved Coarse Digital Delay[4:0] 0x00
0x0113 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0114 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0115 Reserved Output Mux 0x00
Selection[1:0]
0x0116 Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver enable
0x0117 Reserved 0x00
0x0118 Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 8 performance enable enable enable
control mode
0x0119 12-Bit Channel Divider[7:0] (LSB) 0x02
0x011A Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x011B Reserved Fine Analog Delay[4:0] 0x00
0x011C Reserved Coarse Digital Delay[4:0] 0x00
0x011D 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x011E Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x011F Reserved Output Mux 0x00
Selection[1:0]
0x0120 Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver enable
0x0121 Reserved 0x00

Rev. C | Page 50 of 71
Data Sheet HMC7044
Default
Addr. Register Bit 0 Value
(Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex)
0x0122 Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 9 performance enable enable enable
control mode
0x0123 12-Bit Channel Divider[7:0] (LSB) 0x00
0x0124 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x0125 Reserved Fine Analog Delay[4:0] 0x00
0x0126 Reserved Coarse Digital Delay[4:0] 0x00
0x0127 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0128 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0129 Reserved Output Mux 0x00
Selection[1:0]
0x012A Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver enable
0x012B Reserved 0x00
0x012C Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 10 performance enable enable enable
control mode
0x012D 12-Bit Channel Divider[7:0] (LSB) 0x02
0x012E Reserved 12-bit channel divider[11:8] (MSB) 0x00
0x012F Reserved Fine Analog Delay[4:0] 0x00
0x0130 Reserved Coarse Digital Delay[4:0] 0x00
0x0131 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0132 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0133 Reserved Output mux 0x00
selection[1:0]
0x0134 Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver enable
0x0135 Reserved 0x00
0x0136 Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 11 performance enable enable enable
control mode
0x0137 12-Bit Channel Divider[7:0] (LSB) 0x00
0x0138 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x0139 Reserved Fine Analog Delay[4:0] 0x00
0x013A Reserved Coarse Digital Delay[4:0] 0x00
0x013B 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x013C Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x013D Reserved Output Mux 0x00
Selection[1:0]
0x013E Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver enable
0x013F Reserved 0x00
0x0140 Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xF3
Output 12 performance enable enable enable
control mode
0x0141 12-Bit Channel Divider[7:0] (LSB) 0x10
0x0142 Reserved 12-Bit Channel Divider[11:8] (MSB) 0x00
0x0143 Reserved Fine Analog Delay[4:0] 0x00
0x0144 Reserved Coarse Digital Delay[4:0] 0x00
0x0145 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0146 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0147 Reserved Output Mux 0x00
Selection[1:0]
0x0148 Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x01
driver enable
0x0149 Reserved 0x00

Rev. C | Page 51 of 71
HMC7044 Data Sheet
Default
Addr. Register Bit 0 Value
(Hex) Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex)
0x014A Channel High SYNC Slip enable Reserved Start-Up Mode[1:0] Multislip Channel 0xFD
Output 13 performance enable enable enable
control mode
0x014B 12-Bit Channel Divider[7:0] (LSB) 0x00
0x014C Reserved 12-Bit Channel Divider[11:8] (MSB) 0x01
0x014D Reserved Fine Analog Delay[4:0] 0x00
0x014E Reserved Coarse Digital Delay[4:0] 0x00
0x014F 12-Bit Multislip Digital Delay[7:0] (LSB) 0x00
0x0150 Reserved 12-Bit Multislip Digital Delay[11:8] (MSB) 0x00
0x0151 Reserved Output Mux 0x00
Selection[1:0]
0x0152 Force Mute[1:0] Dynamic Driver Mode[1:0] Reserved Driver Impedance[1:0] 0x30
driver enable
0x0153 Reserved 0x00

CONTROL REGISTER MAP BIT DESCRIPTIONS

Global Control (Register 0x0000 to Register 0x0009)
Table 26. Global Soft Reset Control
Address Bits Bit Name Settings Description Access
0x0000 [7:1] Reserved Reserved. RW
0 Soft reset Resets all registers, dividers, and FSMs to default values.

Table 27. Global Request and Mode Control

Address Bits Bit Name Settings Description Access
0x0001 7 Reseed request Requests the centralized resync timer and FSM to reseed any of the RW
output dividers that are programmed to pay attention to sync events.
This signal is rising edge sensitive and is only acknowledged if the
resync FSM has completed all events (has finished any previous pulse
generator and/or sync events and is in the done state; SYSREF FSM
State[3:0] = 0010).
6 High performance High performance distribution path select. The VCO clock distribution
distribution path path has two modes.
0 Power priority.
1 Noise priority. Provides the option for better noise floors on the
divided output signals.
5 Reserved Reserved
4 Force holdover Force PLL1 into holdover mode. A holdover request from the GPI or
SPI is debounced inside the device when transferred to the PLL1 FSM
clock domain (which is nominally at the VCXO or LCM rate). With the
debouncer enabled, the delay from force holdover assertion to the
HOLDOVER state is six clock cycles. If the debouncer is bypassed, the
delay is two clock cycles. To asynchronously tristate the charge pump,
the user can disable the up and down signals from the PFD via Bits[4:3]
(PLL1 PFD up enable, PLL1 PFD down enable) in the PLL1 PFD control
register (Register 0x001B).
3 Mute output drivers Mutes the output drivers (dividers still run in the background).
2 Pulse generator request Asks for a pulse stream (see the Typical Programming Sequence
section).
1 Restart dividers/FSMs Resets all dividers and FSMs. Does not affect configuration registers.
0 Sleep mode Forces shutdown. PLL1 and PLL2, output network, and I/O buffers are
disabled.

Rev. C | Page 52 of 71
Data Sheet HMC7044
Address Bits Bit Name Settings Description Access
0x0002 [7:3] Reserved Reserved. RW
2 PLL2 autotune trigger Triggers an autotune if there is an error/issue when the device comes
out of reset.
1 Slip request Requests a slip or multislip event from all divider channels that are
sensitive to slip or multislip commands. The dividers are rising edge
sensitive and take some time to process the request, after which the
phase synchronization alarm is asserted.
0 Reserved Reserved.

Table 28. Global Enable Control

Address Bits Bit Name Settings Description Access
0x0003 [7:6] Reserved Reserved RW
5 RF reseeder enable Enable RF reseed for SYSREF
[4:3] VCO Selection[1:0] 00 Internal disabled/external
01 High
10 Low
2 SYSREF timer enable Enable internal SYSREF time reference
1 PLL2 enable Master analog enable to PLL2
0 PLL1 enable Master analog enable to PLL1
0x0004 7 Reserved Reserved RW
[6:0] Seven Pairs of 14 Bit 0 Enable Channel 0 and Channel 1
Channel Outputs Bit 1 Enable Channel 2 and Channel 3
Enable[6:0] Bit 2 Enable Channel 4 and Channel 5
Bit 3 Enable Channel 6 and Channel 7
Bit 4 Enable Channel 8 and Channel 9
Bit 5 Enable Channel 10 and Channel 11
Bit 6 Enable Channel 12 and Channel 13

Table 29. Global Mode and Enable Control

Address Bits Bit Name Settings Description Access
0x0005 [7:6] SYNC Pin Mode SYNC pin configuration with respect to PLL2. RW
Selection[1:0] 00 Disabled.
01 SYNC. A rising edge is carried through PLL2. Useful for multichip
synchronization.
10 Pulse generator. Request a pulse generator stream from any channels
configured for dynamic startup. This behaves in the same way as a GPI
requested pulse generator.
11 Causes SYNC if alarm exists, otherwise causes pulse generator.
5 CLKIN1/CLKIN1 in CLKIN1/CLKIN1 input is used for external VCO.
external VCO input
mode
4 CLKIN0/CLKIN0 in RF CLKIN0/CLKIN0 input is used for external RF sync.
SYNC input mode
[3:0] PLL1 Reference Path Selects and enables the reference path for PLL1.
Enable[3:0] Bit 0 Enable CLKIN0/CLKIN0 input path.
Bit 1 Enable CLKIN1/CLKIN1 input path.
Bit 2 Enable CLKIN2/CLKIN2 input path.
Bit 3 Enable CLKIN3/CLKIN3 input path.

Rev. C | Page 53 of 71
HMC7044 Data Sheet
Table 30. Global Clear Alarms
Address Bits Bit Name Settings Description Access
0x0006 [7:1] Reserved Reserved RW
0 Clear alarms Clear latched alarms

Table 31. Global Miscellaneous Control

Address Bits Bit Name Settings Description Access
0x0007 [7:0] Reserved Reserved. RW
0x0008 [7:0] Reserved (Scratchpad) Reserved. The user can write/read to this register to confirm I/Os to the RW
HMC7044. This register does not affect device operation.
0x0009 [7:1] Reserved Reserved. RW
0 Disable SYNC at lock 0 PLL2 sends a sync event up N2 when lock is achieved.
1 This feature is disabled, and SYNC is not internally generated on PLL2
lock.

PLL1 (Register 0x000A to Register 0x002A)

Table 32. CLKINx/CLKINx and OSCIN/OSCIN Input Buffer Control
Address Bits Bit Name Settings Description Access
0x000A, 0x000B, 0x000C, 0x000D, 0x000E [7:5] Reserved Reserved RW
[4:1] Input Buffer Mode[3:0] Input buffer control
Bit 0 Enable internal 100 Ω termination
Bit 1 Enable ac coupling input mode
Bit 2 Enable LVPECL input mode
Bit 3 Enable high-Z input mode
0 Buffer enable Enable input buffer

Table 33. PLL1 Reference Priority Control

Address Bits Bit Name Settings Description Access
0x0014 [7:6] Fourth Priority CLKINx/CLKINx Input[1:0] If third choice clock is not available, use the fourth RW
choice clock
[5:4] Third Priority CLKINx/CLKINx Input[1:0] If second choice clock is not available, use the third
choice clock
[3:2] Second Priority CLKINx/CLKINx Input[1:0] If the first choice clock is not available, use the
second choice clock
[1:0] First Priority CLKINx/CLKINx Input[1:0] This is the first choice clock

Table 34. PLL1 Loss of Signal (LOS) Control

Address Bits Bit Name Settings Description Access
0x0015 [7:3] Reserved Reserved. RW
[2:0] LOS Validation LCM cycles of LOS hysteresis. This is the number of LCM cycles to wait before
Timer[2:0] exiting LOS state when the reference input becomes valid again. 1
000 None.
001 2 cycles.
010 4 cycles.
011 8 cycles.
100 16 cycles.
101 32 cycles.
110 64 cycles.
111 128 cycles.
1
The LOS revalidation takes between two and three times this number of cycles. The LOS revalidation ambiguity is dependent on whether another channel is in LOS.

Rev. C | Page 54 of 71
Data Sheet HMC7044
Table 35. PLL1 Holdover Exit Control
Address Bits Bit Name Settings Description Access
0x0016 [7:4] Reserved Reserved RW
[3:2] Holdover Exit Action[1:0] Action the PLL1 FSM takes as it exits holdover mode.
00 Reset dividers.
01 Do nothing.
10 Do nothing.
11 DAC assist.
[1:0] Holdover Exit Criteria[1:0] Criteria the PLL1 FSM uses to exit holdover mode.
X0 1 Exit holdover when LOS is gone.
01 Exit holdover when phase error = 0.
11 Exit holder immediately.
1
X means don’t care.

Table 36. PLL1 Holdover DAC/ADC Control

Address Bits Bit Name Settings Description Access
0x0017 7 Reserved Reserved RW
[6:0] Holdover DAC In holdover mode, if ADC tracking disable is set 1, the holdover DAC control
Value[6:0] value is set to this value (regarded as an unsigned integer value); otherwise,
the holdover average DAC value is summed by this value (regarded as twos
complement coded signed integer value)
0x0018 [7:4] Reserved Reserved RW
3 ADC tracking Disable ADC tracking; use DAC hold word
disable
2 Force DAC to Force DAC control value from DAC current value to computed DAC
holdover in quick holdover value immediately, not gradually
mode
[1:0] Holdover BW Reduce tracking BW
Reduction[1:0]

Table 37. PLL1 LOS Mode Control

Address Bits Bit Name Settings Description Access
0x0019 [7:2] Reserved Reserved RW
1 LOS bypass input Bypass LCM R divider cascade; the R1 input is the selected
prescaler CLKINx/CLKINx input
0 LOS uses VCXO prescaler For very low PFD rates; cascades VCXO LCM divider after N1

Table 38. PLL1 Charge Pump Control

Address Bits Bit Name Settings Description Access
0x001A [7:4] Reserved Reserved RW
[3:0] PLL1 CP Current[3:0] PLL1 charge pump current

Rev. C | Page 55 of 71
HMC7044 Data Sheet
Table 39. PLL1 PFD Control
Address Bits Bit Name Settings Description Access
0x001B [7:5] Reserved Reserved RW
4 PLL1 PFD up enable Enable PLL1 PFD up
3 PLL1 PFD down enable Enable PLL1 PFD down
2 PLL1 PFD up force Force PLL1 charge pump up; do not assert simultaneously with PLL1
PFD down force
1 PLL1 PFD down force Force PLL1 charge pump down; do not assert simultaneously with PLL1
PFD up force
0 PLL1 PFD polarity Select PFD polarity
0 Positive
1 Negative

Table 40. CLKINx/CLKINx and OSCIN/OSCIN Input Prescaler Control

Address Bits Bit Name Settings Description Access
0x001C [7:0] CLKIN0/CLKIN0 Input Prescaler[7:0] CLKIN0/CLKIN0 Prescaler divider setpoint RW
0x001D [7:0] CLKIN1/CLKIN1 Input Prescaler[7:0] CLKIN1/CLKIN1 Prescaler divider setpoint RW
0x001E [7:0] CLKIN2/CLKIN2 Input Prescaler[7:0] CLKIN2/CLKIN2 Prescaler divider setpoint RW
0x001F [7:0] CLKIN3/CLKIN3 Input Prescaler[7:0] CLKIN3/CLKIN3 Prescaler divider setpoint RW
0x0020 [7:0] OSCIN/OSCIN Input Prescaler[7:0] OSCIN/OSCIN Prescaler divider setpoint RW

Table 41. PLL1 Reference Divider Control (R1)

Address Bits Bit Name Settings Description Access
0x0021 [7:0] 16-Bit R1 Divider[7:0] (LSB) 16-bit R1 divider setpoint LSB RW
0x0022 [7:0] 16-Bit R1 Divider[15:8] (MSB) 16-bit R1 divider setpoint MSB RW

Table 42. PLL1 Feedback Divider Control (N1)

Address Bits Bit Name Settings Description Access
0x0026 [7:0] 16-Bit N1 Divider[7:0] (LSB) 16-bit N1 divider setpoint LSB RW
0x0027 [7:0] 16-Bit N1 Divider[15:8] (MSB) 16-bit N1 divider setpoint MSB RW

Table 43. PLL1 Lock Detect Control

Address Bits Bit Name Settings Description Access
0x0028 [7:6] Reserved Reserved RW
5 PLL1 lock detect uses slip Use the slip indicator instead of ~2 ns timer for lock detect
[4:0] PLL1 Lock Detect Timer[4:0] PLL1 lock detect center depth (LCMs); increments of
2PLL1 Lock Detect Timer[4:0] cycles
00000 1 cycle
00001 2 cycles
00010 4 cycles
… …
11110 1,073,741,824 cycles
11111 2,147,483,648 cycles

Rev. C | Page 56 of 71
Data Sheet HMC7044
Table 44. PLL1 Reference Switching Control
Address Bits Bit Name Settings Description Access
0x0029 [7:6] Reserved Reserved RW
5 Bypass debouncer Bypass the debouncer in manual mode and GPI clock/holdover
selection
[4:3] Manual Mode Reference If automode REF switching = 0, manual selection of
Switching[1:0] CLKINx/CLKINx input
2 Holdover uses DAC In holdover, selects whether PLL1 uses the DAC or tristates the
charge pump
0 Tristate the charge pump
1 Use holdover DAC
1 Autorevertive reference Revert to PLL1 best clock option if it becomes available again
switching
0 Automode reference switching Clock switching is automatic based on LOS/PLL1 reference
priority control register (Register 0x0014)

Table 45. PLL1 Holdoff Time Control

Address Bits Bit Name Settings Description Access
0x002A [7:0] Holdoff Timer[7:0] PLL1 waits in holdover for 2Holdoff Timer[7:0] LCM cycles to give the abandoned RW
reference a chance to recover before switching to the next priority clock. If
Holdoff Timer[7:0] equals to 0, holdoff functionality is disabled and switches
directly to the next priority clock.

PLL2 (Register 0x0031 to Register 0x003C)

Table 46. PLL2 Miscellaneous Control
Address Bits Bit Name Settings Description Access
0x0031 [7:0] Reserved Reserved RW
0x003C [7:0] Reserved Reserved RW

Table 47. PLL2 Frequency Doubler Control

Address Bits Bit Name Settings Description Access
0x0032 [7:1] Reserved Reserved RW
0 Bypass frequency doubler Bypass PLL2 frequency doubler
0 Enable frequency doubler before R2 divider
1 Bypass frequency doubler

Table 48. PLL2 Reference Divider Control (R2)

Address Bits Bit Name Settings Description Access
0x0033 [7:0] 12-Bit R2 Divider[7:0] 12-bit R2 divider setpoint LSB. Divide by 1 to divide by 4095. 00000000, RW
(LSB) 00000001 = divide by 1.
0x0034 [7:4] Reserved Reserved. RW
[3:0] 12-Bit R2 Divider[11:8] 12-Bits R2 divider setpoint MSB.
(MSB)

Table 49. PLL2 Feedback Divider Control (N2)

Address Bits Bit Name Settings Description Access
0x0035 [7:0] 16-Bit N2 Divider[7:0] (LSB) 16-bit N2 divider setpoint LSB. RW
0x0036 [7:0] 16-Bit N2 Divider[15:8] (MSB) 16-bit N2 divider setpoint MSB. RW

Rev. C | Page 57 of 71
HMC7044 Data Sheet
Table 50. PLL2 Charge Pump Control
Address Bits Bit Name Settings Description Access
0x0037 [7:4] Reserved Reserved. RW
[3:0] PLL2 CP These 4 bits set the magnitude of PLL2 charge pump current. Granularity is
Current[3:0] ~160 µA with full magnitude of ~2560 µA.

Table 51. PLL2 PFD Control

Address Bits Bit Name Settings Description Access
0x0038 [7:5] Reserved Reserved RW
4 PLL2 PFD up enable Enable PLL2 PFD up
3 PLL2 PFD down Enable PLL2 PFD down
enable
2 PLL2 PFD up force Force PLL2 charge pump up; do not assert simultaneously with PLL2 PFD
down force
1 PLL2 PFD down Force PLL2 charge pump down; do not assert simultaneously with PLL2
force PFD up force
0 PLL2 PFD polarity Select PFD polarity
0 Positive
1 Negative

Table 52. OSCOUTx/OSCOUTx Path Control

Address Bits Bit Name Settings Description Access
0x0039 [7:3] Reserved Reserved RW
[2:1] OSCOUTx/OSCOUTx Oscillator output divider ratio
Divider[1:0] 00 Divided by 1
01 Divided by 2
10 Divided by 4
11 Divided by 8
0 OSCOUTx/OSCOUTx Enable the oscillator output path (divider and the internal path except
path enable driver)

Table 53. OSCOUTx/OSCOUTx Driver Control

Address Bits Bit Name Settings 1 Description Access
0x003A, [7:6] Reserved Reserved RW
0x003B [5:4] OSCOUTx/OSCOUTx Driver Mode[1:0] Oscillator output driver mode selection
00 CML mode
01 LVPECL mode
10 LVDS mode
11 CMOS mode
[3] Reserved Reserved
[2:1] OSCOUTx/OSCOUTx Driver Oscillator output driver impedance selection for
Impedance[1:0] CML mode
00 Internal resistor disable
01 Internal 100 Ω resistor enable per output pin
10 Reserved
11 Internal 50 Ω resistor enable per output pin
0 OSCOUTx/OSCOUTx driver enable Enable oscillator driver
1
X means don’t care.

Rev. C | Page 58 of 71
Data Sheet HMC7044
GPIO/SDATA Control (Register 0x0046 to Register 0x0054)
Table 54. GPIx Control
Address Bits Bit Name Settings Description Access
0x0046, 0x0047, [7:5] Reserved Reserved. RW
0x0048, 0x0049 [4:1] GPIx Selection[3:0] Select the GPIx functionality.
0000 Reserved.
0001 Force PLL1 to holdover.
0010 Select PLL1 reference manually, Bit 1.
0011 Select PLL1 reference manually, Bit 0.
0100 Put the chip into sleep mode.
0101 Issue a mute.
0110 Select the internal VCO type manually.
0111 Select high performance mode for PLL2 and the internal VCO.
1000 Issue a pulse generator request.
1001 Issue a reseed request.
1010 Issue a restart request.
1011 Force the chip into fanout mode.
1100 Reserved.
1101 Issue a slip request
1110 Reserved.
1111 Reserved.
0 GPIx enable GPIx function enable. Before changing the function of the pin,
disable it first, and then reenable it after the function change.1
1
Note that it is possible to have a GPIOx pin configured as both an output and an input.

Table 55. GPOx Control

Address Bits Bit Name Settings Description Access
0x0050, 0x0051, 0x0052, 0x0053 [7:2] GPOx Selection[5:0] Select the GPOx functionality RW
000000 Alarm signal
000001 SDATA from SPI communication
000010 CLKIN3/CLKIN3 LOS for CLKIN3/CLKIN3 input
000011 CLKIN2/CLKIN2 LOS for CLKIN2/CLKIN2input
000100 CLKIN1/CLKIN1 LOS for CLKIN1/CLKIN1 input
000101 CLKIN0/CLKIN0 LOS for CLKIN0/CLKIN0 input
000110 PLL1 holdover enabled signal from PLL1
000111 Lock detect signal from PLL1
001000 Acquiring lock signal from PLL1
001001 PLL1 near lock acquisition status signal from PLL1
001010 PLL2 lock detect signal from PLL2
001011 SYSREF sync status has not synchronized since reset
001100 Clock outputs phase status
001101 PLL1 and PLL2 lock detect is locked
001110 Sync request status signal
001111 PLL1 active CLKIN0/CLKIN0
010000 PLL1 active CLKIN1/CLKIN1
010001 PLL1 holdover ADC input range status
010010 PLL1 holdover ADC input status
010011 PLL1 VCXO status
010100 PLL1 active CLKINx/CLKINx status
010101 PLL1 FSM state, Bit 0
010110 PLL1 FSM state, Bit 1
010111 PLL1 FSM state, Bit 2

Rev. C | Page 59 of 71
HMC7044 Data Sheet
Address Bits Bit Name Settings Description Access
011000 PLL1 holdover exit phase, Bit 0
011001 PLL1 holdover exit phase, Bit 1
011010 Channel outputs FSM busy
011011 SYSREF FSM state, Bit 0
011100 SYSREF FSM state, Bit 1
011101 SYSREF FSM state, Bit 2
011110 SYSREF FSM state, Bit 3
011111 Force Logic 1 to GPO
100000 Force Logic 0 to GPO
100001 Reserved
100010 Reserved
100011 Reserved
100100 Reserved
100101 Reserved
100110 Reserved
100111 PLL1 holdover DAC averaged value, Bit 0
101000 PLL1 holdover DAC averaged value, Bit 1
101001 PLL1 holdover DAC averaged value, Bit 2
101010 PLL1 holdover DAC averaged value, Bit 3
101011 PLL1 holdover DAC current value, Bit 0
101100 PLL1 holdover DAC current value, Bit 1
101101 PLL1 holdover DAC current value, Bit 2
101110 PLL1 holdover DAC current value, Bit 3
101111 Reserved
110000 Reserved
110001 Reserved
110010 Reserved
110011 Reserved
110100 Reserved
110101 Reserved
110110 Reserved
110111 Reserved
111000 Reserved
111001 Reserved
111010 Reserved
111011 Reserved
111100 Reserved
111101 Holdover comparator status
111110 Pulse generator request status signal
111111 Reserved
1 GPOx mode Selects the mode of GPOx driver
0 Open-drain mode
1 CMOS mode
0 GPOx enable GPOx driver enable

Table 56. SDATA Control

Address Bits Bit Name Settings Description Access
0x0054 [7:2] Reserved Reserved RW
1 SDATA mode Selects the mode of SDATA driver
0 Open-drain mode
1 CMOS mode
0 SDATA enable SDATA driver enable

Rev. C | Page 60 of 71
Data Sheet HMC7044
SYSREF/SYNC Control (Register 0x005A to Register 0x005E)
Table 57. Pulse Generator Control
Address Bits Bit Name Settings Description Access
0x005A [7:3] Reserved Reserved. RW
[2:0] Pulse Generator SYSREF output enable with pulse generator.
Mode 000 Level sensitive. When the GPIx is configured to issue a pulse generator
Selection[2:0] request (GPIx Selection[3:0] = 1000), or a pulse generator request is issued
through the SPI or as a SYNC pin-based pulse generator, run the pulse
generator. Otherwise, stop the pulse generator.
001 1 pulse.
010 2 pulses.
011 4 pulses.
100 8 pulses.
101 16 pulses.
110 16 pulses.
111 Continuous mode (50% duty cycle).

Table 58. SYNC Control

Address Bits Bit Name Settings Description Access
0x005B [7:3] Reserved Reserved RW
2 SYNC retime
0 Bypass the retime (if using SYNC path with on-chip VCO)
1 Retime the external SYNC from Reference 0
1 SYNC through PLL2 Allow a reseed event to be through PLL2
0 SYNC polarity SYNC polarity (must be 0 if not using CLKIN0/CLKIN0 as the input)
0 Positive
1 Negative

Table 59. SYSREF Timer Control

Address Bits Bit Name Settings Description Access
0x005C [7:0] SYSREF 12-bit SYSREF timer setpoint LSB. This sets the internal beat frequency of the RW
Timer[7:0] master timer, which controls synchronization and pulse generator events. Set the
(LSB) 12-bit timer to a submultiple of the lowest output SYSREF frequency, and
program it to be no faster than 4 MHz.
0x005D [7:4] Reserved Reserved. RW
[3:0] SYSREF 12-bit SYSREF timer setpoint MSB.
Timer[11:8]
(MSB)

Table 60. SYSREF Miscellaneous Control

Address Bits Bit Name Settings Description Access
0x005E [7:0] Reserved Reserved RW

Clock Distribution Network (Register 0x0064 to Register 0x0065)

Table 61. External VCO Control
Address Bits Bit Name Settings Description Access
0x0064 [7:2] Reserved Reserved RW
1 Divide by 2 on external VCO enable Use divide by 2 on external VCO path
0 Low frequency external VCO path Changes bias to Class A for low frequency VCO

Rev. C | Page 61 of 71
HMC7044 Data Sheet
Table 62. Analog Delay Common Control
Address Bits Bit Name Settings Description Access
0x0065 [7:1] Reserved Reserved. RW
0 Analog delay low Analog delay is in low power mode, which can save power for low settings
power mode of analog delay but is not glitchless between setpoints.

Alarm Masks Registers (Register 0x0070 to Register 0x0071)

Table 63. PLL1 Alarm Mask Control
Address Bits Bit Name Settings Description Access
0x0070 7 PLL1 near lock mask If set, allow the PLL1 near lock signal to generate alarm signal RW
6 PLL1 lock acquisition mask If set, allow the PLL1 lock acquisition signal to generate alarm
signal
5 PLL1 lock detect mask If set, allow the PLL1 lock detect signal to generate alarm
signal
4 PLL1 holdover status mask If set, allow the PLL1 holdover status signal to generate alarm
signal
[3:0] PLL1 CLKINx/CLKINx Status Bit 0 If set, allow CLKIN0/CLKIN0 LOS to generate alarm signal
Mask[3:0] Bit 1 If set, allow CLKIN1/CLKIN1 LOS to generate alarm signal
Bit 2 If set, allow CLKIN2/CLKIN2 LOS to generate alarm signal
Bit 3 If set, allow CLKIN3/CLKIN3 LOS to generate alarm signal

Table 64. Alarm Mask Control

Address Bits Bit Name Settings Description Access
0x0071 [7:5] Reserved Reserved RW
4 Sync request mask If set, allow the sync request signals to generate alarm signal
3 PLL1 and PLL2 lock detect mask If set, allow the PLL1 and PLL2 lock detect signals to generate
alarm signal
2 Clock outputs phases status If set, allow the clock outputs phases status signal to generate
mask alarm signal
1 SYSREF sync status mask If set, allow the SYSREF sync status signal to generate alarm
signal
0 PLL2 lock detect mask If set, allow the PLL2 lock detect signal to generate alarm
signal

Product ID Registers (Register 0x0078 to Register 0x007A)

Table 65. Product ID
Address Bits Bit Name Settings Description Access
0x0078 [7:0] Product ID Value[7:0] (LSB) 24-bit product ID value low R
0x0079 [7:0] Product ID Value[15:8] (Mid) 24-bit product ID value high R
0x007A [7:0] Product ID Value[23:16] (MSB) 24-bit product ID value very high R

Alarm Readback Status Registers (Register 0x007B to Register 0x007F)

Table 66. Readback Register
Address Bits Bit Name Settings Description Access
0x007B [7:1] Reserved Reserved. R
0 Alarm signal Readback alarm status from SPI.

Rev. C | Page 62 of 71
Data Sheet HMC7044

Table 67. PLL1 Alarm Readback

Address Bits Bit Name Settings Description Access
0x007C 7 PLL1 near lock PLL1 near locked. Declare near locked when the counter reaches 1/16 of R
the programmable limit.
6 PLL1 lock acquisition PLL1 acquiring lock.
5 PLL1 lock detect PLL1 locked.
4 PLL1 holdover status PLL1 in holdover.
[3:0] CLKINx/CLKINx Bit 0 CLKIN0/CLKIN0 LOS.
LOS[3:0] Bit 1 CLKIN1/CLKIN1 LOS.
Bit 2 CLKIN2/CLKIN2 LOS.
Bit 3 CLKIN3/CLKIN3 LOS.

Table 68. Alarm Readback

Address Bits Bit Name Settings Description Access
0x007D [7:5] Reserved Reserved. R
4 Sync request status PLL2 locked (or disabled), but unsynchronized.
3 PLL1 and PLL2 lock PLL1 and PLL2 lock detect status.
detect 0 Either PLL1 or PLL2 is not locked or both PLL1 and PLL2 are not locked.
1 PLL1 and PLL2 are locked.
2 Clock outputs phases SYSREF alarm.
status 0 SYSREF of the HMC7044 is not valid; that is, its phase output is not stable.
1 SYSREF of the HMC7044 is valid and locked; that is, its phase output is stable.
1 SYSREF sync status SYSREF SYNC status alarm.
0 The HMC7044 has been synchronized with an external sync pulse or a
sync request from the SPI.
1 The HMC7044 never synchronized with an external sync pulse or a sync
request from the SPI.
0 PLL2 lock detect 1 PLL2 near locked. Declare near locked when counter reaches 1/16 of the
programmable limit.

Table 69. Latched Alarm Readback

Address Bits Bit Name Settings Description Access
0x007E 7 Reserved Reserved. R
6 PLL2 lock acquisition latched Readback record of PLL2 lock acquisition since the last clear event.
5 PLL1 lock acquisition latched Readback record of PLL1 lock acquisition since the last clear event.
4 PLL1 holdover latched Readback record of PLL1 holdover since the last clear event.
[3:0] CLKINx/CLKINx LOS Bit 0 Readback record of CLKIN0/CLKIN0 LOS since the last clear event.
Latched[3:0] Bit 1 Readback record of CLKIN1/CLKIN1 LOS since the last clear event.
Bit 2 Readback record of CLKIN2/CLKIN2 LOS since the last clear event.
Bit 3 Readback record of CLKIN3/CLKIN3 LOS since the last clear event.

Table 70. Alarm Readback Miscellaneous

Address Bits Bit Name Settings Description Access
0x007F [7:0] Reserved Reserved. R

Rev. C | Page 63 of 71
HMC7044 Data Sheet
PLL1 Status Registers (Register 0x0082 to Register 0x0087)
Table 71. PLL1 Status Registers
Address Bits Bit Name Settings Description Access
0x0082 7 Reserved Reserved R
[6:5] PLL1 Best Clock[1:0] Indicates which clock the LOS/priority encoder prefers if
automode reference switching is used
[4:3] PLL1 Active CLKINx/ Indicates which CLKINx/CLKINx input is currently in use
CLKINx[1:0]
[2:0] PLL1 FSM State[2:0] Sets the state PLL1 is in
000 Reset
001 Acquisition
010 Locked
011 Invalid
100 Holdover
101 DAC assisted holdover exit
0x0083 7 Reserved Reserved R
[6:0] Holdover DAC Averaged Average DAC code
Value[6:0]
0x0084 7 Holdover comparator value Holdover comparator output value (DAC output vs. PLL1 VTUNE) R
[6:0] Holdover DAC Current Current DAC code
Value[6:0]
0x0085 [7:4] Reserved Reserved R
3 PLL1 active CLKINx/CLKINx LOS of the currently active reference
LOS
2 PLL1 VCXO status Indicates whether any of the enabled references appears to run
faster than the VCXO
1 PLL1 holdover ADC status 0 ADC is acquiring
1 PLL1 VTUNE is moving quickly
0 PLL1 holdover ADC input 0 PLL1 VTUNE is in range
range status 1 PLL1 VTUNE is out of range
0x0086 [7:5] Reserved Reserved R
[4:3] PLL1 Holdover Exit The phase of the PLL1 holdover exit
Phase[1:0]
[2:0] Reserved Reserved
0x0087 [7:0] Reserved Reserved R

PLL2 Status Registers (Register 0x008C to Register 0x0090)

Table 72. PLL2 Status Registers
Address Bits Bit Name Settings Description Access
0x008C [7:0] PLL2 autotune value After autotune, this word is populated with the selected capacitor R
bank of the VCO
0x008D [7:0] PLL2 Autotune Signed 14-bit PLL2 VTUNE error count, LSB R
Error[7:0] (LSB)
0x008E 7 PLL2 autotune status 1 Autotune busy R
0 Done/not working
6 PLL2 autotune error sign Sign of PLL2 autotune error
0 Positive
1 Negative
[5:0] PLL2 Autotune Signed 14-bit PLL2 VTUNE error count, MSB
Error[13:8] (MSB)

Rev. C | Page 64 of 71
Data Sheet HMC7044
Address Bits Bit Name Settings Description Access
0x008F [7:4] PLL2 Autotune FSM Autotune FSM state R
State[3:0] 0000 Idle
0001 Startup
0010 Startup
0011 Reset
0100 Reset
0101 Reset
0110 Measure
0111 Wait
1000 Wait
1001 Update loop to state 18 times
1010 Round
1011 Finish
[3:0] PLL2 SYNC FSM State[3:0] PLL2 sync carry FSM state
0000 Idle
0100 Power up Section A of the FSM
0110 Power up Section B of the FSM
0111 Sending to N2
1110 Power down Section A of the FSM
1100 Power down Section B of the FSM
0x0090 [7:0] Reserved Reserved R

SYSREF Status Register (Register 0x0091)

Table 73. SYSREF Status Register
Address Bits Bit Name Settings Description Access
0x0091 [7:5] Reserved Reserved. R
4 Channel outputs One of clock outputs FSM requested clock, and it is running.
FSM busy
[3:0] SYSREF FSM Indicates the current step of the SYSREF reseed process. Note that the three
State[3:0] different progressions are caused by different trigger events (reseed, pulse
generator, reserved).
0000 Reset.
0010 Done.
0100 Get ready.
0101 Get ready.
0110 Get ready.
1010 Running (pulse generator).
1011 Start.
1100 Power up.
1101 Power up.
1110 Power up.
1111 Clear reset.

Rev. C | Page 65 of 71
HMC7044 Data Sheet
Other Controls (Register 0x0096 to Register 0x00B8)
For optimum performance of the chip, Register 0x0096 to Register 0x00B8 must be programmed to a different value than their default
value.

Table 74. Reserved Registers

Address Bits Bit Name Settings Description Access
0x0096 [7:0] Reserved Reserved RW
0x0097 [7:0] Reserved Reserved RW
0x0098 [7:0] Reserved Reserved RW
0x0099 [7:0] Reserved Reserved RW
0x009A [7:0] Reserved Reserved RW
0x009B [7:0] Reserved Reserved RW
0x009B [7:0] Reserved Reserved RW
0x009C [7:0] Reserved Reserved RW
0x009D [7:0] Reserved Reserved RW
0x009E [7:0] Reserved Reserved RW
0x009F [7:0] Reserved Clock output driver low power setting (set to 0x4D instead of default value) RW
0x00A0 [7:0] Reserved Clock output driver high power setting (set to 0xDF instead of default value) RW
0x00A1 [7:0] Reserved Reserved RW
0x00A2 [7:0] Reserved Reserved RW
0x00A3 [7:0] Reserved Reserved RW
0x00A4 [7:0] Reserved Reserved RW
0x00A5 [7:0] Reserved PLL1 more delay (PFD1, lock detect) (set to 0x06 instead of default value) RW
0x00A6 [7:0] Reserved Reserved RW
0x00A7 [7:0] Reserved Reserved RW
0x00A8 [7:0] Reserved PLL1 holdover DAC gm setting (set to 0x06 instead of default value) RW
0x00A9 [7:0] Reserved Reserved RW
0x00AB [7:0] Reserved Reserved RW
0x00AC [7:0] Reserved Reserved RW
0x00AD [7:0] Reserved Reserved RW
0x00AE [7:0] Reserved Reserved RW
0x00AF [7:0] Reserved Reserved RW
0x00B0 [7:0] Reserved VTUNE preset setting (set to 0x04 instead of default value) RW
0x00B1 [7:0] Reserved Reserved RW
0x00B2 [7:0] Reserved Reserved RW
0x00B3 [7:0] Reserved Reserved RW
0x00B4 [7:0] Reserved Reserved RW
0x00B5 [7:0] Reserved Reserved RW
0x00B6 [7:0] Reserved Reserved RW
0x00B7 [7:0] Reserved Reserved RW
0x00B8 [7:0] Reserved Reserved RW

Rev. C | Page 66 of 71
Data Sheet HMC7044
Clock Distribution (Register 0x00C8 to Register 0x0153)
The bit descriptions in Table 75 apply to all 14 channels.

Table 75. Channel 0 to Channel 13 Control

Address Bits Bit Name Settings 1 Description Access
0x00C8, 0x00D2, 0x00DC, 7 High performance High performance mode. Adjusts the divider and buffer RW
0x00E6, 0x00F0, 0x00FA, mode bias to improve swing/phase noise at the expense of
0x0104, 0x010E, 0x0118, power.
0x0122, 0x012C, 0x0136, 6 SYNC enable Susceptible to SYNC event. The channel can process a
0x0140, 0x014A SYNC event to reset its phase.
5 Slip enable Susceptible to slip event. The channel can process a slip
request from SPI or GPI. Note that if slip enable is true
but multislip is off, a channel slips by 1 VCO cycle on an
explicit slip request broadcast from the SPI/GPI.
4 Reserved Reserved.
[3:2] Start-Up Mode[1:0] Configures the channel to normal mode with
asynchronous startup, or to a pulse generator mode
with dynamic start-up. Note that this must be set to
asynchronous mode if the channel is unused.
00 Asynchronous.
01 Reserved.
10 Reserved.
11 Dynamic.
1 Multislip enable Allow multislip operation (default = 0 for SYSREF, 1 for
DCLK).
0 Do not engage automatic multislip on channel startup.
1 Multislip events after SYNC or pulse generator request,
if slip enable, Bit = 1.
0 Channel enable Channel enable. If this bit is 0, channel is disabled.
0x00C9, 0x00D3, 0x00DD, [7:0] 12-Bit Channel 12-bit channel divider setpoint LSB. The divider RW
0x00E7, 0x00F1, 0x00FB, Divider[7:0] (LSB) supports even divide ratios from 2 to 4094. The
0x0105, 0x010F, 0x0119, supported odd divide ratios are 1, 3, and 5. All even and
0x0123, 0x012D, 0x0137, odd divide ratios have 50.0% duty cycle.
0x0141, 0x014B
0x00CA, 0x00D4, 0x00DE, [7:4] Reserved Reserved. RW
0x00E8, 0x00F2, 0x00FC, [3:0] 12-Bit Channel 12-bit channel divider setpoint MSB.
0x0106, 0x0110, 0x011A, Divider[11:8] (MSB)
0x0124, 0x012E, 0x0138,
0x0142, 0x014C
0x00CB, 0x00D5, 0x00DF, [7:5] Reserved Reserved. RW
0x00E9, 0x00F3, 0x00FD, [4:0] Fine Analog 24 fine delay steps. Step size = 25 ps. Values greater
0x0107, 0x0111, 0x011B, Delay[4:0] than 23 have no effect on analog delay.
0x0125, 0x012F, 0x0139,
0x0143, 0x014D
0x00CC, 0x00D6, 0x00E0, [7:5] Reserved Reserved. RW
0x00EA, 0x00F4, 0x00FE, [4:0] Coarse Digital 17 coarse delay steps. Step size = ½ VCO cycle. This flip
0x0108, 0x0112, 0x011C, Delay[4:0] flop (FF)-based digital delay does not increase noise
0x0126, 0x0130, 0x013A, level at the expense of power. Values greater than 17
0x0144, 0x014E have no effect on coarse delay.
0x00CD, 0x00D7, 0x00E1, [7:0] 12-Bit Multislip 12-bit multislip digital delay amount LSB. RW
0x00EB, 0x00F5, 0x00FF, Digital Delay[7:0] Step size = (delay amount: MSB + LSB) × VCO cycles. If
0x0109, 0x0113, 0x011D, (LSB) multislip enable bit = 1, any slip events (caused by GPI,
0x0127, 0x0131, 0x013B, SPI, SYNC, or pulse generator events) repeat the
0x0145, 0x014F number of times set by 12-Bit Multislip Digital
Delay[11:0] to adjust the phase by step size.

Rev. C | Page 67 of 71
HMC7044 Data Sheet
Address Bits Bit Name Settings 1 Description Access
0x00CE, 0x00D8, 0x00E2, [7:4] Reserved Reserved. RW
0x00EC, 0x00F6, 0x0100, [3:0] 12-Bit Multislip 12-bit multislip digital delay amount MSB.
0x010A, 0x0114, 0x011E, Digital Delay[11:8]
0x0128, 0x0132, 0x013C, (MSB)
0x0146, 0x0150
0x00CF, 0x00D9, 0x00E3, [7:2] Reserved Reserved. RW
0x00ED, 0x00F7, 0x0101, [1:0] Output Mux Channel output mux selection.
0x010B, 0x0115, 0x011F, Selection[1:0] 00 Channel divider output.
0x0129, 0x0133, 0x013D,
0x0147, 0x0151 01 Analog delay output.
10 Other channel of the clock group pair.
11 Input VCO clock (fundamental). Fundamental can also
be generated with 12-Bit Channel Divider[11:0] = 1.
0x00D0, 0x00DA, 0x00E4, [7:6] Force Mute[1:0] Idle at Logic 0 selection (pulse generator mode only). RW
0x00EE, 0x00F8, 0x0102, Force to Logic 0 or VCM.
0x010C, 0x0116, 0x0120, 00 Normal mode (selection for DCLK).
0x012A, 0x0134, 0x013E, 01 Reserved.
0x0148, 0x0152
10 Force to Logic 0.
11 Reserved.
5 Dynamic driver Dynamic driver enable (pulse generator mode only).
enable 0 Driver is enabled/disabled with channel enable bit
1 Driver is dynamically disabled with pulse generator
events.
[4:3] Driver Mode[1:0] Output driver mode selection.
00 CML mode.
01 LVPECL mode.
10 LVDS mode.
11 CMOS mode.
[2] Reserved Reserved.
[1:0] Driver Output driver impedance selection for CML mode.
Impedance[1:0] 00 Internal resistor disable.
01 Internal 100 Ω resistor enable per output pin.
10 Reserved.
11 Internal 50 Ω resistor enable per output pin.
0x00D1, 0x00DB, 0x00E5, [7:0] Reserved Reserved. RW
0x00EF, 0x00F9, 0x0103,
0x010D, 0x0117, 0x0121,
0x012B, 0x0135, 0x013F,
0x0149, 0x0153
1
X means don’t care.

Rev. C | Page 68 of 71
Data Sheet HMC7044

EVALUATION PCB SCHEMATIC

EVALUATION PCB RAMP UP
3°C/SECOND MAX
60 TO 150
SECONDS

For the circuit board used in the application, use RF circuit 260 – 5°C/260 + 0°C

TEMPERATURE (°C)
design techniques. Ensure that signal lines have 50 Ω 217°C

impedance. Connect the package ground leads and exposed pad 150°C TO 200°C
RAMP DOWN
directly to the ground plane (see Figure 52). Use a sufficient 6°C/SECOND MAX
number of via holes to connect the top and bottom ground
planes. The evaluation circuit board is available from Analog
60 TO 180 TIME (Second)
Devices upon request. SECONDS

13033-146
20 TO 40
The typical Pb-free reflow solder profile is shown in Figure 51. 480 SECONDS MAX SECONDS

Figure 51. Pb-Free Reflow Solder Profile

13033-048

Rev. C | Page 69 of 71
HMC7044 Data Sheet

13033-049
Figure 53. Evaluation PCB Layout, Bottom Side

Rev. C | Page 70 of 71
Data Sheet HMC7044

OUTLINE DIMENSIONS
10.10
10.00 SQ 0.30
9.90 0.25
PIN 1 0.18
PIN 1
INDICATOR 52 68 INDICATOR
1
51

0.50 EXPOSED
BSC PAD 6.40
6.30 SQ
6.20

35
17
34
0.60 18

1.20 BSC
TOP VIEW BOTTOM VIEW
0.50
8.00 REF
0.40
0.90
0.85 FOR PROPER CONNECTION OF
0.05 MAX THE EXPOSED PAD, REFER TO
0.80 THE PIN CONFIGURATION AND
0.02 NOM
FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
0.08
SEATING 0.20 REF

03-12-2015-A
PLANE
PKG-000000

COMPLIANT TO JEDEC STANDARDS MO-220-VNND-2

Figure 54. 68-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

10 mm × 10 mm Body, Very Thin Quad
(HCP-68-1)
Dimensions shown in millimeters
NOTE 1
NOTE 6 4.10
2.10 4.00 16.10
1.85 2.00 3.90 16.00
1.75 1.90 15.90 0.35
A Ø 1.5 ~ 1.6 0.30
1.65
0.25
24.30 11.60
24.00 11.50
10.40
23.70 11.40
10.30 NOTE 6 R0.3
10.20 MAX
NOTE 4

TOP VIEW Ø 1.5 MIN 1.20

10.40 A DETAIL A
1.10
10.30
1.00 NOTE 5
10.20 DIRECTION OF FEED
NOTE 4 SECTION A-A

0.25
NOTES:
1. 10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE ± 0.20
2. CAMBER IN COMPLIANCE WITH EIA 481
3. MATERIAL: CONDUCTIVE BLACK PO LYSTYRENE DETAIL A R 0.25
4. MEASURED ON A PLANE 0.30 mm ABOVE THE BOTTOM OF
THE POCKET
02-10-2016-A

5. MEASURED FROM A PLANE ON THE INSIDE BOTTOM OF

THE POCKET TO THE TOP SURFACE OF THE CARRIER
6. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED
AS TRUE POSITION OF POCKET, NOT POCKET HOLE

Figure 55. LFCSP Tape and Reel Outline Dimensions

Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Lead Finish MSL Rating Package Description Package Option Branding 2
HMC7044LP10BE –40°C to +85°C 100% matte tin MSL-3 68-Lead LFCSP_VQ HCP-68-1 7044
XXXX
HMC7044LP10BETR –40°C to +85°C 100% matte tin MSL-3 68-Lead LFCSP_VQ HCP-68-1 7044
XXXX
EK1HMC7044LP10B –40°C to +85°C Evaluation Kit
1
E = RoHS Compliant Part.
2
Four-digit lot number represented by XXXX.

©2015–2021 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D13033-9/21(C)

Rev. C | Page 71 of 71