ESRTOS Manual-2019 - Final
ESRTOS Manual-2019 - Final
-VI, Electronics
Experiment-1
Aim:- Using mixed C/C++ and assembly language programming, implement Arithmetic and Logic Unit
to perform following operations: Addition ,Subtraction, Multiplication, Division, AND, OR ,XOR, NOR,
left shift, right shift.
Learning Objective:-
Theory:-
● Assembly codes sensitive to the processor, memory, ports and devices hardware
● Gives a precise control of the processor internal devices
● Enables full use of processor specific features in its instruction set and its
● Machine codes are compact, processor and memory sensitive
● System needs a smaller memory.
● Memory needed does not depend on the programmer data type selection and rule-declarations
● Not the compiler specific and library-functions specific
● Device driver codes may need only a few assembly instructions.
● Bottom-up-design approach
Data types:
● auto
● unsigned
● static
● const
● register
● interrupt
● extern
● volatile
● volatile static
• Differs from a function in the sense that once a macro is defined by a name, the compiler
puts the corresponding codes at the macro at every place where that macro-name appears.
Algorithm:-
3. Use switch case logic to implement different Arithmetic and Logical functions.
ALU program:-
#include<stdio.h>
#include<conio.h>
#include<math.h>
void main()
{
int a,b, choice, result;
printf(“\n1. ADD \n2. SUB \n3. MUL \n4. DIV \n5. AND \n6. XOR \n7. OR \n8.EXIT”);
printf(“\nEnter your choice”);
scanf(“%d”,&choice);
printf(“\nEnter two numbers”);
scanf(“%d %d”,&a,&b);
switch(choice)
{
Case 1: asm{
mov ax, a;
mov bx, b;
add ax, bx;
mov result, ax;
}
printf(“\n Addition=%d”, result);
break;
Case 2: asm{
mov ax, a;
mov bx, b;
sub ax, bx;
mov result, ax;
}
printf(“\n Subtraction=%d”, result);
break;
Case 3: asm{
mov ax, a;
mov bx, b;
mul bx;
mov result, ax;
}
printf(“\n Multiplication=%d”, result);
break;
Case 4: asm{
mov ax, a;
mov bx, b;
ALU program:-
div bx;
mov result, ax;
}
printf(“\n Division=%d”, result);
break;
Case 5: asm{
mov ax, a;
mov bx, b;
AND ax, bx;
mov result, ax;
}
printf(“\n AND=%d”, result);
break;
Case 6: asm{
mov ax, a;
mov bx, b;
xor ax, bx;
mov result, ax;
}
printf(“\n XOR=%d”, result);
break;
Case 7: asm{
mov ax, a;
mov bx, b;
or ax, bx;
mov result, ax;
}
printf(“\n OR=%d”, result);
break;
case 8:
break;
default: printf(“\nEnter proper choice”);
}
getch():
}
OUTPUT
Experiment -2
Aim:- Design system based on 8051 microcontroller and PROTEUS for demonstration of traffic light.
Learning Objective:-
i)To study embedded c programming for 8bit microcontroller (8051).
ii)To study delay logic and switching of LED’s at different ports.
Theory: Traffic lights are interfaced to port1 and port 2 of 8051 microcontroller. According to sequence
of traffic lights GREEN, RED, ORANGE lights are made ON and OFF for specified time duration. At a
time only one road traffic will be on, remaining road will have RED signal.
Algorithm:-
Procedure :-
Conclusion:-
#include< reg51.h>
void delay()
int i,j;
for (i=0;i<1000;i++)
for (j=0;j<1000;j++);
void main()
while(1)
red_n = 1;
yellow_n = 0;
green_n = 0;
red_s = 0;
yellow_s = 0;
green_s = 1;
red_e = 0;
yellow_e = 1;
green_e = 0;
red_w = 1;
yellow_w = 0;
green_w = 0;
delay();
red_n = 0;
yellow_n = 1;
green_n = 0;
red_s = 1;
yellow_s = 0;
green_s = 0;
red_e = 0;
yellow_e = 0;
green_e = 1;
red_w = 1;
yellow_w = 0;
green_w = 0;
delay();
red_n = 0;
yellow_n = 0;
green_n = 1;
red_s = 1;
yellow_s = 0;
green_s = 0;
red_e = 1;
yellow_e = 0;
green_e = 0;
red_w = 0;
yellow_w = 1;
green_w = 0;
delay();
red_n = 1;
yellow_n = 0;
green_n = 0;
red_s = 0;
yellow_s = 1;
green_s = 0;
red_e = 1;
yellow_e = 0;
green_e = 0;
red_w = 0;
yellow_w = 0;
green_w = 1;
delay();
Experiment 3
LED blinking
The NXP’s (founded by Philips) LPC 1768 is ARM 32-bit Cortex-M3 Microcontroller with MPU, CPU
clock up to 100MHz, 512kB on-chip Flash ROM with enhanced Flash Memory Accelerator,
In-System Programming (ISP) and In-Application Programming (IAP),64kB RAM, Nested Vectored
Interrupt Controller, Eight channel General purpose DMA controller, AHB Matrix, APB.
Ethernet 10/100 MAC with RMII interface and dedicated DMA, USB 2.0 full-speed Device controller
and Host/OTG controller with DMA.
CAN 2.0B with two channels, Four UARTs, one with full Modem interface, Three I2C serial interfaces,
Three SPI/SSP serial interfaces, I2S interface, General purpose I/O pins, 12-bit ADC with 8 channels, 10-
bit DAC, Four 32-bit Timers with capture/compare, Standard PWM Timer block,Motor control PWM for
three-phase Motor control, Quadrature Encoder,Watchdog Timer, Real Time Clock with optional Battery
backup, System Tick Timer, Repetitive Interrupt Timer, Brown-out detect circuit,
Power-On Reset, Power Management Unit, Wakeup Interrupt Controller,Crystal oscillator, 4MHz
internal RC oscillator, PLL,JTAG and Serial Wire Debug/Trace Port with ETM
FIODIR :- Port Direction control register. This register individually controls the direction of each port
pin.
FIOSET:- Port Output Set register. This register controls the state of output pins in conjunction with the
IOCLR register. Writing ones produces highs at the corresponding port pins. Writing zeroes has no effect.
FIOCLR:-Port Output Clear register. This register controls the state of output pins. Writing ones
produces lows at the corresponding port pins and clears the corresponding bits in the IOSET register.
Writing zeroes has no effect.
Algorithm:-
Procedure :-
Conclusion:-
#include <lpc17xx.h>
for(i=0;i<ms;i++)
for(j=0;j<20000;j++);
int main()
char n;
while(1)
delay_ms(100);
delay_ms(100);
Output
Experiment 4
ADC
LPC1768 has an inbuilt 12 bit Successive Approximation ADC which is multiplexed among 8 input pins.
The ADC reference voltage is measured across VREFN to VREFP, meaning it can do the conversion
within this range. Usually the VREFP is connected to VDD and VREFN is connected to GND.
As LPC1768 works on 3.3 volts, this will be the ADC reference voltage.
The below block diagram shows the ADC input pins multiplexed with other GPIO pins.
The ADC pin can be enabled by configuring the corresponding PINSEL register to select ADC function.
When the ADC function is selected for that pin in the Pin Select register, other Digital signals are
disconnected from the ADC input pins.
AD0[7], 3-
ADC Registers
The below table shows the registers associated with LPC1768 ADC.
Register Description
ADGDR A/D Global Data Register: This register contains the ADC’s DONE bit and the
result of the most recent A/D conversion
ADDR0 - A/D Channel Data Register: Contains the recent ADC value for respective channel
ADDR7
ADSTAT A/D Status Register: Contains DONE & OVERRUN flag for all the ADC channels
Algorithm:-
1. Configure the GPIO pin for ADC function using PINSEL register.
2. Enable the Clock to ADC module.
3. Select the Particular channel for A/D conversion by setting the corresponding bits in ADCR.SEL
4. Set the ADC START bit for starting the A/D conversion for selected channel.
5. Wait for the conversion to complete, ADC_DONE bit will be set once conversion is over.
6. Read the 12-bit A/D value from ADC.RESULT.
Procedure :-
#include <lpc17xx.h>
#include <stdio.h>
//#include "ocf_lpc176x_lib.h" //contains uart, timer & fputc to retarget printf
#define VREF 3.3 //Reference Voltage at VREFP pin, given VREFN = 0V(GND)
#define ADC_CLK_EN (1<<12)
#define SEL_AD0_0 (1<<0) //Select Channel AD0.0
#define CLKDIV 1 //ADC clock-divider (ADC_CLOCK=PCLK/CLKDIV+1) = 12.5Mhz @ 25Mhz
PCLK
#define PWRUP (1<<21) //setting it to 0 will power it down
#define START_CNV (1<<24) //001 for starting the conversion immediately
#define ADC_DONE (1U<<31) //define it as unsigned value or compiler will throw #61-D warning
#define ADCR_SETUP_SCM ((CLKDIV<<8) | PWRUP)
int main(void)
{
int result = 0;
float volts = 0;
while(1)
{
LPC_ADC->ADCR |= START_CNV; //Start new Conversion
Output:
Experiment 5
PWM
Theory: LPC1768 has 6 PWM output pins which can be used as 6-Single edged or 3-Double edged.
There as seven match registers to support these 6 PWM output signals.
Below block diagram shows the PWM pins and the associated match (Duty Cycle) registers.
Register Configuration
The below table shows the registers associated with LPC1768 PWM.
TCR
31:4 3 2 1 0
MCR
31:21 20 19 18 -
PWMMRxI
This bit is used to Enable or Disable the PWM interrupts when the PWMTC matches PWMMRx (x:0-6)
0- Disable the PWM Match interrupt
1- Enable the PWM Match interrupt.
PWMMRxR
This bit is used to Reset PWMTC whenever it Matches PWMRx(x:0-6)
0- Do not Clear.
1- Reset the PWMTC counter value whenever it matches PWMRx.
PWMMRxS
This bit is used to Stop the PWMTC,PWMPC whenever the PWMTC matches PWMMRx(x:0-6).
0- Disable the PWM stop o match feature
1- Enable the PWM Stop feature. This will stop the PWM whenever the PWMTC reaches the Match
register value.
PCR
PWMSELx
This bit is used to select the single edged and double edge mode form PWMx (x:2-6)
0- Single Edge mode for PWMx
1- Double Edge Mode for PWMx.
PWMENAx
This bit is used to enable/disable the PWM output for PWMx(x:1-6)
0- PWMx Disable.
1- PWMx Enabled.
LER
31-7 6 5 4 3
LENx
This bit is used Enable/Disable the loading of new Match value whenever the PWMTC is reset(x:0-6)
PWMTC will be continuously incrementing whenever it reaches the PWMMRO, timer will be reset
depending on PWMTCR configuration. Once the Timer is reset the New Match values will be loaded
from MR0-MR6 depending on bits set in this register.
0- Disable the loading of new Match Values
1- Load the new Match values from MRx when the timer is reset.
PWM Working:
The TC is continuously incremented and once it matches the MR1(Duty Cycle) the PWM pin is pulled
Low. TC still continues to increment and once it reaches the Cycle time (Ton+Toff) the PWM module
does the following things:
1. Configure the GPIO pins for PWM operation in respective PINSEL register.
2. Configure TCR to enable the Counter for incrementing the TC, and Enable the PWM block.
3. Set the required pre-scalar value in PR. In our case it will be zero.
4. Configure MCR to reset the TC whenever it matches MR0.
5. Update the Cycle time in MR0. In our case it will be 100.
6. Load the Duty cycles for required PWMx channels in respective match registers MRx(x: 1-
6).
7. Enable the bits in LER register to load and latch the new match values.
8. Enable the required pwm channels in PCR register.
Procedure :-
Conclusion:-
#include <LPC17xx.h>
void initPWM(void);
void updatePulseWidth(unsigned int pulseWidth);
void delayMS(unsigned int milliseconds);
void initTimer0(void);
int main(void)
{
int pulseWidths[] = {1000,1250,1500,1750,2000};
const int num PulseWidths = 5;
int count=1;
int dir=0; //direction, 0 = Increasing, 1 = Decreasing
//SystemInit(); //gets called by Startup code before main()
initTimer0(); //Initialize Timer
initPWM(); //Initialize PWM
while(1)
{
updatePulseWidth(pulseWidths[count]); //Update Servo Pulse Width
delayMS(1000); //Wait for servo to reach the new position
if(dir) count--;
else count++;
}
//return 0; //normally this won't execute ever
}
void initPWM(void)
{
/*Assuming that PLL0 has been setup with CCLK = 100Mhz and PCLK = 25Mhz.*/
while(LPC_TIM0->TC < milliseconds); //wait until timer counter reaches the desired delay
LPC_TIM0->CTCR = 0x0;
LPC_TIM0->PR = 25000-1; //Increment TC at every 24999+1 clock cycles
//25000 clock cycles @25Mhz = 1 mS
Output:
Experiment 6
Aim: - Write a program in C/C++ to determine task schedulability of uniprocessor system using
necessary and sufficient conditions.
Learning Objective: - i) To learn the application of schedulability theorem from CPU utilization.
ii) Total utilization theorem (Sufficient condition)
n
∑ U i≤ 1
i=1
n 1
∑ U i ≤ n(2 n – 1)
i=1
Theory:-
If Ci is the execution time of task and Ti is its request period, then the processor utilization is defined as
the fraction of time during which the processor is busy running one of the tasks and is given as .
Corresponding to the priority assignment of a set of tasks, it is said that these tasks fully utilize the
processor if the priority assignment is feasible i.e if U <1 and an increase in the run time of any of the
tasks in the set will make the priority assignment infeasible i.e if U>1.
For a given fixed priority scheduling algorithm, the least upper bound of the utilization factor is the
minimum of the utilization factors over all sets of tasks that fully utilize the processor. This means that for
all task sets whose utilization factor is below this bound, there exists a priority assignment that is feasible.
The Scheduler schedules different processes to be assigned to the CPU based on particular scheduling
algorithm. There are six popular process scheduling algorithms which we are going to discuss in the
following section: First-Come, First-Served (FCFS) Scheduling Shortest-Job-Next (SJN) Scheduling
Priority Scheduling Shortest Remaining Time Round Robin(RR) Scheduling Multiple-Level Queues
Scheduling These algorithms are either non preemptive or preemptive. Non-preemptive algorithms are
designed so that once a process enters the running state, it cannot be preempted until it completes its
allotted time where as the preemptive scheduling is based on priority where a scheduler may preempt a
low priority running process anytime when a high priority process enters into a ready state. First Come
First Serve (FCFS) Jobs are executed on first come, first serve basis. It is a non preemptive scheduling
algorithm. Easy to understand and implement. Its implementation is based on FIFO queue. Poor in
performance as average wait time is high. The various types of scheduling task is
Round Robin Scheduling Round Robin is the preemptive process scheduling algorithm. Each process is
provided a fix time to execute called quantum. Once a process is executed for given time period. Process
is preempted and other process executes for given time period. Context switching is used to save states of
preempted processes.
Rate monotonic scheduling Algorithm works on the principle of preemption. Preemption occurs on a
given processor when higher priority task blocked lower priority task from execution. This blocking
occurs due to priority level of different tasks in a given task set. rate monotonic is a preemptive algorithm
which means if a task with shorter period comes during execution it will gain a higher priority and can
block or preemptive currently running tasks. In RM priorities are assigned according to time period.
Priority of a task is inversely proportional to its timer period. Task with lowest time period has highest
priority and the task with highest period will have lowest priority.
Algorithm:-
Conclusion:
#include<iostream.h>
#include<math.h>
#include<stdio.h>
#include<conio.h>
void main()
{
clrscr();
int a,temp,i,j,x=0;
float ut=0;
float u[10];
float t[10],c[10],p[10],r[10];
cout<<"Enter the no of task:=";
cin>> a;
for(i=0;i<a;i++)
{
cout<<"Enter period of task "<<i+1;
cout<<":=";
cin>>t[i];
p[i]=t[i];
cout<<"Enter CPU time of task "<<i+1;
cout<<":=";
cin>>c[i];
}
for(i=0;i<a-1;i++)
{
for(j=0;j<a;j++)
{
if(p[j]>p[j+1])
{
temp=p[j];
p[j]+p[j+1];
p[j+1]=temp;
}
}
}
for(i=0;i<a;i++)
{
for(j=0;j<a;j++)
{
if(t[i]==p[j])
cout<<"priority of Task "<<i+1<<"is: "<<j+1<<endl;
}
Task scheduling program:-
}
for(i=0;i<a;i++)
{
u[i]=c[i]/t[i];
ut=ut+u[i];
}
cout<<"Total Utilization is: "<<ut<<endl;
if(ut<1)
{
cout<<"Tasks are Schedulable";
Output: