Scribd
Upload
276 views1 page

Pe Ec802c

The document is a practice exam for a VLSI Design Automation course. It contains two sections - multiple choice questions worth 5 marks each (Section A) and short answer questions worth 5 marks each (Section B). The multiple choice questions cover topics like floorplanning tools, partitioning techniques, simulators, and VLSI design flow. The short answer questions ask about floorplanning goals, placement algorithm classification, high-level synthesis goals, and high-level synthesis flow. The exam is out of 25 total marks and must be completed within 60 minutes.

Uploaded by

Samaira Shahnoor Parvin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
276 views1 page

Pe Ec802c

The document is a practice exam for a VLSI Design Automation course. It contains two sections - multiple choice questions worth 5 marks each (Section A) and short answer questions worth 5 marks each (Section B). The multiple choice questions cover topics like floorplanning tools, partitioning techniques, simulators, and VLSI design flow. The short answer questions ask about floorplanning goals, placement algorithm classification, high-level synthesis goals, and high-level synthesis flow. The exam is out of 25 total marks and must be completed within 60 minutes.

Uploaded by

Samaira Shahnoor Parvin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 1

Bengal Institute of Technology & Management, Santiniketan

Department:- E.C.E. Year:- 4th Sem:- 8th


Subject:- VLSI Design automation Code:- PE-EC802C
Time:-60mins Full Marks:- 25

Group – A
(Multiple Choice Type Questions)
1. Choose the correct alternatives for the following: 5×1=5
i. In floorplanning, placement and routing are __________ tools.
a) Front end b) Back end c) Both a and b d) None of the above
ii. Partitioning technique is not suitable for microprocessor like circuits.
a) True b) False
iii. With partitioning, bypassing is performed using
a) buffers b) multiplexers c) multipliers d) dividers
iv. Which takes lots of simulating time?
a) circuit simulator b) timing simulator
c) logic level simulator
d) functional simulator
v. What is the design flow of VLSI system?
i. architecture design
ii. market requirement
iii. logic design
iv. HDL coding
a) ii-i-iii-iv b) iv-i-iii-ii c) iii-ii-i-iv d) i-ii-iii-iv

Group – B
(Short Answer Type Questions)
Answer the following 4 × 5 = 20
2. State the goals and objective of floorplanning.
3. How placement algorithms are classified?
4. What is the goal for allocation, scheduling and binding?
5. Describe the high level synthesis flow.

You might also like