Pentium 3 and 4 Assignment
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Prasin SPPentium 3 and 4 Assignment
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Prasin SPPentium III The Pentium III brand refers to Intel's 32-bit desktop and mobile microprocessors based on the
sixth-generation P6 microarchitecture. Pentium 3 is very similar to Pentium II-branded microprocessors. The most notable difference was the addition of the SSE instruction set (to accelerate floating point and parallel calculations). Other features include. L1-Cache: 16 + 16 KB (Data + Instructions) L2-Cache: 256 or 512 KB, fullspeed MMX, SSE, Hardware prefetch Socket 370 Front side bus: 133 MHz Clockrate: 10001400 MHz This is a modern Pentium III based computer. In order to separate slower devices and relieve the CPU there are North and South bridges North bridge dispatches CPU commands to SDRAM , cashe (level2), IO devices through PCI bus and video through AGP interface. South bridge contains USB,IDE controllers. IDE is an interface to CDROM and hard drives. PCI bus was developed by Intel for high performance peripheral devices, such as graphic accelerators, disk controllers. AGP port. AGP port provides high speed access to the memory and allows to share it with local video memory for 3D graphics applications. Pentium 4 It is a line of single-core desktop and laptop CPUs, introduced by Intel. It has a 7th-generation x86 NetBurst microarchitecture. Features include very deep instruction pipeline to achieve very high clock speeds (up to 3.8 GHz) SSE2 and SSE3 instruction sets to accelerate calculations, media processing, 3D graphics Later versions featured Hyper-Threading Technology (HTT), a feature to make one physical CPU work as two logical CPUs Architecture contains four main sections: In-Order Front End, The Out-Of-Order Execution Engine, The Integer and Floating-Point Execution Units, The Memory Subsystem. Pre-fetcher fetches instructions that are likely to be executed. BTB predicts branches (uses the past history of program execution to speculate where the program is going to execute next). Decoder decodes instructions into ops and delivers to trace cache which is L1 instruction cache of the Pentium 4. It stores decoded instructions and delivers to the out-of-order execution logic. Out-of-Order Execution Logic is where instructions are prepared for execution. It allows to execution of as many ready instructions as possible each clock cycle, even if they are not in the original program order.The Retirement Logic reorders the instructions executed out-of-order back to the original program order.
Integer and Floating-Point Execution Units consists of Level 1 data cache and execution units are where the integer, Floating-point/SSE instructions are executed. L1 data cache is used for most load and store operations. The Pentium 4 processor has a highly capable memory subsystem to enable the high-bandwidth stream-oriented applications such as 3D, video. This subsystem consists of: Level 2 (L2) Unified Cache and 400 MHz System Bus. L2 cache stores instructions and data that cannot fit in the Trace Cache and L1 data cache. System bus is used to access main memory when L2 cache has a cache miss, and to access the system I/O resources
