AL1402G

ADAT® Optical Decoder

Lead Free – Complies with RoHS Directive

General Description Features

The AL1402G OptoRec interface decodes a  Compatible with ADAT Type I and II
single datastream of the industry-standard formats
ADAT Optical protocol (U.S. patent  4 stereo pairs as inputs using standard
number 5,297,181) and produces four ADC formats
stereo pairs (8 channels) of digital audio  4 user bit outputs to receive time-code,
suitable for DACs or further processing. MIDI data, etc.
With an internal PLL to generate all  Internal PLL generates all required clocks
needed clock signals, the AL1402G from optical data or wordclock
requires no external clocks in master  Wordclock input to synchronize outputs to
mode, and only wordclock (Fs) for proper user’s system
operation in slave mode.
 Lead Free – Complies with RoHS
A companion encoder, the AL1401A Directive
OptoGen™, is also available.
Use of the ADAT Optical interface Applications
(including the OptoGen and OptoRec)
requires a license agreement (generally  Digital Mixing Boards
royalty-free) between the manufacturer
 Signal Processors
and Wavefront Semiconductor. Details
and agreement information are available  Digital Effects Boxes
upon request from Wavefront directly, or
on our web site.  Digital Recorders

 Computer Sound Boards

 Sound Reinforcement Products

Package

GND VDD
MODE0 LINMODE
FMT0 MUTE
FMT1 ERROR
MODE1 HOLDERR
OPDIGIN OPDIGTHRU
SVCO DVCO
WDCLK USER3
BCLK USER2
OUT 1/2 USER1
OUT 3/4 USER0
OUT 5/6 OUT 7/8
24 pin SOIC
300 mils wide
Wavefront Semiconductor  200 Scenic View Drive  Cumberland, RI 02864  U.S.A.
Tel: +1 401 658-3670  Fax: +1 401 658-3680  Email: [email protected]
On the web at www.wavefrontsemi.com
1
AL1402G-0605
Table of Contents
General Description ………….……………………………….............………….. 1
Features …………………………………………………………..…………….......... 1
Applications ……………………………………….........................……………... 1
Package …..………………………………....................................................... 1
Table of Contents ………………..……………………………………….............. 2
Pin Descriptions …………………………………………………………………….. 2
Electrical Characteristics ………………………………............…...……….… 3
Architecture Details …..........…………………………………………………….. 3
Serial Input Interface …...….............………………………………....... 3
Serial Input Format Selection .................……...........……… 3
Serial Input Formats ..............................……...........……… 4
Serial Input Format Timing ....................……...........……… 4
Wordclock Selection ……………….…............…..……..........……...... 5
Wordclock Mode Selection ......................……...........……… 5
Wordclock Modes ...................................……...........……… 5
Wordclock Muting ....................…..............…...........……… 5
ADAT Optical Datastream ………...……………............…..………..... 6
Reset Circuitry ................….……...……………............…..………..... 6
Clock Generator and PLL ….……...……………............…..………..... 6
Package Dimensions ………………………………………….…………………..... 7
Sample Application Schematic ….…………………………….………………… 8
Notice and Contact Information ………………………………………………... 9

Pin Descriptions

Pin# Name Pin Type Description

1 GND Ground Ground connection.
2 MODE0 In Mode 0, sets mode.
3 FMT0 In Format 0, sets data format.
4 FMT1 In Format 1, sets data format.
5 MODE1 In Mode 1, sets mode.
6 OPDIGIN In Input to optical receiver.
Master mode: DVCO-derived clock (nominal 12.288MHz, 256*Fs),
7 SVCO Out
Slave mode: WDCLK-derived clock.
8 WDCLK I/O Wordclock input/output (nominal 48kHz, Fs).
9 BCLK Out Bitclock output (nominal 3.072MHz, 64*Fs).
10 OUT 1/2 Out Channels 1&2 data output.
11 OUT 3/4 Out Channels 3&4 data output.
12 OUT 5/6 Out Channels 5&6 data output.
13 OUT 7/8 Out Channels 7&8 data output.
14 USER0 Out User 0 data bit output. Used to receive timecode.
15 USER1 Out User 1 data bit output. Used to receive MIDI data.
16 USER2 Out User 2 data bit output. Used to receive S/Mux indicator.
17 USER3 Out User 3 data bit output. Reserved.
18 DVCO Out Recovered clock from datastream (nominal 12.288MHz, 256*Fs).
19 OPDIGTHRU Out Regenerated OPDIGIN for daisy-chaining.
If high, ERROR pin stays high until cause of error removed AND
20 HOLDERR In
HOLDERR goes low.
Indicates lack of input or failure to synchronize to datastream.
21 ERROR Out
If high, data outputs muted but not clock outputs.
22 MUTE In Mute select: 1=Mute outputs, 0=No muting.
23 LINMODE In Tie high.
24 VDD Power VDD power pin.

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Electrical Characteristics
Symbol Description Min Typ Max Units
Recommended Operating Conditions
VDD Supply Voltage 4.5 5.0 5.5 V
IDD-MSTR Supply Current, Master 7.7 mA
IDD-SLAV Supply Current, Slave 5.4 mA
GND Ground 0 V
Fs Sample rate 30 48 55 kHz
Temp Temperature 0 25 70 C

Inputs (WDCLK, FMT0-1, OPDIGIN, MODE0-1 LINMODE, MUTE, HOLDERR)

VIH Logical “1” input voltage 0.75 VDD V
VIL Logical “0” input voltage 0.25 VDD V
IIH Logical “1” input current 1 μA
IIL Logical “0” input current 1 μA
CIN Logic input capacitance 5 pF
Outputs (WDCLK, DVCO, OPDIGTHRU, SVCO, BCLK, ERROR)
VOH Logical “1” output voltage 0.9 VDD V
VOL Logical “0” output voltage 0.1 VDD V
IOH Logical “1” output current -8 mA
IOL Logical “0” output current 8 mA

Outputs (OUT1/2-7/8, USER0-3)

VOH Logical “1” output voltage 0.9 VDD V
VOL Logical “0” output voltage 0.1 VDD V
IOH Logical “1” output current -2 mA
IOL Logical “0” output current 2 mA

Architecture Details

Serial Output Interface

The AL1402G OptoRec interface has been designed for ease of use and flexibility in systems
designed to interface to the ADAT protocol. It supports both left and right justified data formats
for ease of integration into existing devices as well as new devices. These formats allow it to
operate in parallel with many standard ADCs. The specific output format to be used is selected
by the format pins FMT1 and FMT0.

Serial Output Format Selection

FMT[1:0] Format
00 Right justified, BCLK falls on WDCLK edge.
01 Left justified, BCLK rises on WDCLK edge.
10 Chip reset.
11 Gated BCLK, BCLK rises on WCLK edge.

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Serial Output Formats

one period WordClock

WDCLK
Left Just 24 23
MSB
0 23
MSB
0
†
ADAT Type II  19 0 19 0
MSB MSB
†
ADAT Type I  15 0 15 0
MSB MSB

BCLK (rising)


Right Just 24 23 0 23 0
MSB MSB
†
ADAT Type II  19 0 19 0
MSB MSB
†
ADAT Type I  15 0 15 0
MSB MSB

BCLK (falling)

Left Just 24 23
MSB
0 23
MSB
0

Gated BCLK
*Note: The most significant bit is sign-extended to the left of the frame.
+Note: These diagrams represent how data would be framed from an ADAT Type I
or Type II device. They are not actual modes of the OptoRec. The left
justified mode is recommended for ADAT formats.

Serial Output Timing

WDCLK LEFT CHANNEL

tDS
OUT

tDU
USER VALID

Symbol Description Min Typ Max Units

tDS(Mstr) OUT setup time relative to Master WDCLK output -10 2 27 ns
tDS(Slav) OUT setup time relative to Slave WDCLK input -7 5 30 ns
tDU(Mstr) USER setup time relative to Master WDCLK output -10 0 25 ns
tDU(Slav) USER setup time relative to Slave WDCLK input -8 2 27 ns
Note: Above specifications hold after 3900 WDCLK cycles of valid input at OPDIGIN.

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Wordclock Selection
With the use of the MODE inputs, the user may choose the source of the wordclock used to
generate the output clocks for the OptoRec. When the OptoRec is in Master Mode, all outputs
are derived from the input ADAT Optical datastream on the OPDIGIN pin, and WDCLK is an
output. When the OptoRec is in Slave Mode, OUT1/2-7/8, USER0-3, BCLK, and SVCO are
synchronous to WDCLK, which is an input. While in Slave mode, WDCLK may be at an
arbitrary phase with respect to the incoming samples of OPDIGIN, but if the two frequencies are
not identical, samples will be dropped, repeated, or garbled. Generally, identical frequencies are
achieved by either using DVCO as the source from which WDCLK is generated, or creating
OPDIGIN from a source synchronized to WDCLK.

Wordclock Mode Selection

MODE[1:0] Mode
00 Master Mode, WDCLK is an output.
Slave Mode, WDCLK is an input. WDCLK MUST be
01
derived from the same clock supplying the source.
10 Reserved.
11 Reserved.

Wordclock Modes

Master Mode
WDCLK
1 2 3 4 5 124 125 126 127 128 129 130 131 132 133 252 253 254 255 256
SVCO
1 2 3 4 5 124 125 126 127 128 129 130 131 132 133 252 253 254 255 256
DVCO

Slave Mode
In Slave mode DVCO is not phase aligned with WDCLK and SVCO.

Wordclock Muting
The OptoRec in Master Mode can produce clock outputs running at uncontrolled frequencies if
the digital input becomes unstable after stable use, due mostly to poor connection of the optical
cable to the optical connector. Care should be taken when running the OptoRec with the
AL1201 DAC as the AL1201 DAC will output noise if the OptoRec WDCLK is at an uncontrolled
VCO frequency beyond the AL1201’s maximum. An external AND gate implementation may be
used to correct this. The inverted ERROR pin and the desired OptoRec output clock are inputs
to the AND gate and the desired mutable clock is the output, and the AND function will mute the
selected OptoRec clock when the ERROR pin is high (i.e. when unstable input is present at
OPDIGIN). In place of this circuit, the ERROR pin may be used as a mute select for any audio
output stage muting circuitry that is present in the system.

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ADAT Optical Datastream
The AL1402G provides support for both the ADAT Type I format (16-bit) and the ADAT Type II
format (20-bit). Data lengths of up to 24 bits are supported. USER0 is used to receive the ADAT
format 32-bit timecode, USER1 is used to receive MIDI data, USER2 is used to receive the
S/Mux data indicator, and USER3 is reserved and should be tied low.

Reset Circuitry
An OptoRec reset, initiated by setting FMT[1:0]=10, is synchronous, and a minimum duration of
1 DVCO clock period is required. At a nominal 12.288MHz, this translates to 82ns. A safety
margin is advised, and a pulse width of 100ns would be sufficient to reset the chip. This will
reset all internal counters and state registers to their initial state and disrupt the outputs.
However, PLL lock to OPDIGIN will not be disturbed.
The clock and data outputs of the OptoRec are undefined after power-up until a proper
datastream is well established on OPDIGIN. The clock outputs may be running at an
uncontrolled frequency during that time. In this case, the ERROR pin will be high, indicating
that the outputs are invalid. This may be prevented by using the FMT pins to reset the OptoRec
on power-up, thus stopping the VCO clocks and muting the data output. The FMT pins may
then be set to the value required in your system. Nevertheless the OptoRec will synchronize and
produce proper outputs when proper and valid inputs are provided, whether this reset procedure
is used or not.

Clock Generator and PLL

The OptoRec contains an internal PLL that locks to the embedded clock in the ADAT Optical
datastream and produces all necessary high frequency clocks and timing signals to operate the
device. This high quality PLL will reject any high-frequency jitter on the incoming datastream.
Receiving 8 channels of ADAT Optical data on OPDIGIN, the jitter was measured to be 1.5ns
typical on WDCLK.
Using the extracted clock, the PLL generates the DVCO output. The datastream is also
reconstructed using this PLL and outputted on OPDIGTHRU (clocked on the rising edge of
DVCO), and thus the OPDIGTHRU datastream is synchronized to the PLL's wordclock, as well as
to OPDIGIN.

Symbol Description Min Typ Max Units

tDI OPDIGIN setup time relative to Master WDCLK output -34 -53 -72 ns
tDT OPDIGTHRU setup time relative to Master WDCLK output -20 -4 5 ns

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The OptoRec contains a duplicate PLL that locks to the incoming clock signal on WDCLK when
in slave mode. Receiving 8 channels of ADAT Optical data on OPDIGIN, the jitter was measured
to be 1.26ns typical on BCLK.
The second PLL locks onto the wordclock selected by the user via the Master/Slave Mode
selection. In Master Mode, the selected wordclock comes from the first PLL, and SVCO, BCLK,
and WDCLK are all synchronized to it. In Slave Mode, WDCLK is an input, and is what SVCO
and BCLK are locked to.

Symbol Description Min Typ Max Units

tDB BCLK setup time relative to Slave WDCLK output 0 9 30 ns

The PLL allows a simplified user interface and eliminates the need of running high frequency
clocks to the part on PCB traces. This reduces unwanted RF noise and coupling problems that
can occur when such clock signals are required on input pins for a device.

Package Dimensions
Dimensions (Typical)
Inches Millimeters
A A 0.606” 15.40
B 0.295” 7.50
C 0.406” 10.30
D 0.100” 2.50
24 13
E 0.008” 0.20
F 0.025” 0.64
C B G 0.050” 1.27
H 0.017” 0.42
1 12
J 0.011” 0.27
K 0.352” 8.94
L 0.033” 0.83
Note: Dimension “A” does not include
mold flash, protrusions, or gate burrs.

7° nom
K

D 4° nom

E H J L
G
F

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Sample Application Schematic
The following schematic shows the OptoGen and OptoRec in a typical application. The OptoGen
accepts input from an ADC, then outputs data in the ADAT Optical format on the optical
transmitters. The OptoRec receives ADAT Optical data on the optical receivers, then outputs
data to a DAC.

+5V

0.1uF
+5V
5
NC
4
INPUT
VCC 3
OPTOGEN 0.1uF
8.2k 20
2
C_LIMIT VDD 11
1 19 IN 1/2 IN 1/2
GND OPDGOUT 12
IN 3/4 IN 3/4
NC 13
IN 5/6 IN 5/6
4 14
TOTX173* 6 WDCLK WDCLK IN 7/8 IN 7/8
OPTICAL OUT 5
RESET RESET
TIME CODE
6 USER0 15
WDCLKNEG 16
USER1 MIDI DATA
USER2 17
+5V 18 +5V
USER3
7
FMT0
8
FMT1
9
5 NC 2 NC FMT2
10
47uH +5V NC 3 NC GND FMT3
1 1
OUTPUT
VCC 3

2
GND1 4
GND2 +5V
0.1uF 0.1uF
TORX173* 6
OPTOREC
24
VDD
6 19
OPDIGIN OPDIGTHRU OPDIGTHRU
3 OUT 1/2 10 OUT 1/2
OPTICAL IN 4 FMT0
FMT1 OUT 3/4 11 OUT 3/4
OUT 5/6 12 OUT 5/6
OUT 7/8 13 OUT 7/8
ERROR
21
20 ERROR 14
HOLDERR USER0 TIME CODE
USER1 15
23 16
LINMODE USER2 NC
17 NC MIDI DATA
2 USER3
18
5 MODE0 DVCO
7
MODE1 SVCO
8 DVCO
22 WDCLK
9
MUTE BCLK
GND
1 SVCO (Master Mode, can be MCLK)

WDCLK (Slave Mode)

WDCLK (Master Mode)

BCLK (Master Mode)

* Optical I/O parts shown are Toshiba parts. The Sharp GP1F33RT or equivalent is also compatible.

LEFTIN LEFTOUT

RIGHTIN RIGHTOUT
INL/R OUTL/R
WDCLK WDCLK
BCLK BCLK
MCLK MCLK

ADC DAC

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 NOTICE
Wavefront Semiconductor reserves the right to make changes to their products
or to discontinue any product or service without notice. All products are sold
subject to terms and conditions of sale supplied at the time of order
acknowledgement. Wavefront Semiconductor assumes no responsibility for the
use of any circuits described herein, conveys no license under any patent or
other right, and makes no representation that the circuits are free of patent
infringement. Information contained herein is only for illustration purposes and
may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked, no responsibility is assumed for
inaccuracies.
Wavefront Semiconductor products are not designed for use in applications
which involve potential risks of death, personal injury, or severe property or
environmental damage or life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life
support system or to significantly affect its safety or effectiveness.
All trademarks and registered trademarks are property of their respective owners.

Contact Information:

Wavefront Semiconductor
200 Scenic View Drive
Cumberland, RI 02864 U.S.A.
Tel: +1 401 658-3670
Fax: +1 401 658-3680
On the web at www.wavefrontsemi.com
Email: [email protected]

Copyright © 2005 Wavefront Semiconductor

Application note revised September, 2005
Reproduction, in part or in whole, without the prior written consent of Wavefront
Semiconductor is prohibited.

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