Dr.

Praveen Kumar
School of Electronics Engineering (SENSE)
VIT-AP University
E-Mail: [email protected]
 CONTENTS

Module-2

 Binary adder and subtractor

 Ripple carry adders/subtractors and fast adders
 Binary decoders, encoders
 Multiplexers and de-multiplexers
 Logic functions using decoders and multiplexers
 Code converters
 Magnitude comparator

Combinational Circuit Design 2

 CONTENTS

Lecture-2

 4-bit binary Adder

 Fast Adders
 4-bit Adder-Subtractor
 BDC Adder

Number Systems 3
 BOOKS

Textbooks

1. M.Morris Mano, Michael D Ciletti, Digital Design, 5th edition, Pearson Publishers, 2013.
2. R.P. Jain, “Modern Digital Electronics”, 4th edition, TMH.

References

1. M.Morris Mano, Charles R. Kime, Tom Martin, Logic and Computer Design Fundamentals, 4th edition,
Pearson Publishers.
2. C. H. Roth and L. L. Kinney, Fundamentals of Logic Design, 5th edition, Cengage Publishers.

Combinational Circuit Design 4

Combinational Circuit Design 5
 BINARY ADDER

 A binary adder is a digital circuit that produces the arithmetic sum of 2 binary numbers.
 It is also called as ripple carry adder or parallel adder.
 Consider two 4-bit binary number A and B

A3 A2 A1 A0
1 1 Ci+1 Ci
A 1 0 1 1 A 1 0 1 1 Ai
B 0 0 1 1 +Bi
B3 B2 B1 B0
1 1 1 0 Si
B 0 0 1 1
Each bit position creates a
sum and carry

Combinational Circuit Design 6

 BINARY ADDER

 To demonstrate with the specific example, the two binary numbers A = 1011 and B = 0011.
Their sum S = 1110 is formed with the four-bit adder as follows:

Combinational Circuit Design 7

 BINARY ADDER

 A 4-binary adder required 4 full adders to design the combinational circuit.

Combinational Circuit Design 8

 FAST ADDER

 The addition of 2 binary numbers using parallel adder implies that all the bits of augend and addend
are available at the same time.
 From the 4-bit adder circuit, it can be observed that Ai and Bi are available at same time.
 However, the generation of Ci+1 is depending upon Ci. This means the input carry C3 does not settle to
its final value until C2 is available from the previous stage. Similarly, C2 has to wait for C1 and so on
down to C0.
 Thus, only after the carry propagates and ripples through all stages will the last output S3 and carry C4
settle to their final correct value.
 Hence, to generate the final carry C4, 8-gate levels are needed which leads to more propagation delay.
Therefore, carry lookahead logic can be implemented to reduce the propagation delay.
 These adders are called as fast adders or carry lookahead adder.

Combinational Circuit Design 9

FAST ADDER

Combinational Circuit Design 10

 FAST ADDER

 If we define two new

binary variables

the output sum and

carry can respectively be
expressed as

Here, Gi is called a carry generate, and it produces a carry of 1

when both Ai and Bi are 1, regardless of the input carry Ci. Pi is
called a carry propagate, because it determines whether a carry
into stage i will propagate into stage i + 1.

Combinational Circuit Design 11

 FAST ADDER

 The Boolean functions for the carry outputs of each stage and substitute the value of each Ci from the
previous equations:

Combinational Circuit Design 12

 FAST ADDER

 Therefore, the carry lookahead

generator logic can be
implemented as shown in the
figure.
 This logic circuit represents only
2 gate level implementation
instead of 8-level which reduces
the propagation delay.

Combinational Circuit Design 13

 FAST ADDER

 Hence, the addition of 2-binary

number can be achieved by using 4-
level gate implementation.

Combinational Circuit Design 14

 4-BIT BINARY ADDER-SUBTRACTOR

 The subtraction of two binary number can be achieved by using 2’s complement
method.
 The circuit for subtracting A – B consists of an adder with inverters placed between
each data input B and the corresponding input of the full adder. The input carry C0
must be equal to 1 when subtraction is performed.
 The operation thus performed becomes A, plus the 1’s complement of B, plus 1. This
is equal to A plus the 2’s complement of B.
 For unsigned numbers, that gives A – B if A ≥ B or the 2’s complement of (B – A) if
A < B.

Combinational Circuit Design 15

 4-BIT BINARY ADDER-SUBTRACTOR

ADDITION SUBTRACTION using 2’ s Complement

Ai Bi Ai Bi’

4-bit Parallel Adder C0 = 0 4-bit Parallel Adder C0 = 1

Ci+1 Si = Ai +Bi Ci+1 Si = Ai + (Bi’ + 1)

Combinational Circuit Design 16

 4-BIT BINARY ADDER-SUBTRACTOR

Logic Design
 The mode input M controls the operation. When M = 0, the circuit is an adder, and
when M = 1, the circuit becomes a subtractor.
 Each exclusive-OR gate receives input M and one of the inputs of B.
 When M = 0, we have B ⊕ 0 = B. The full adders receive the value of B, the input
carry is 0, and the circuit performs A plus B.
 When M = 1, we have B ⊕ 1 = B’ and C0 = 1. The B inputs are all complemented
and a 1 is added through the input carry.
 The circuit performs the operation A plus the 2’s complement of B.

Combinational Circuit Design 17

 4-BIT BINARY ADDER-SUBTRACTOR

Logic Design

M=0
an adder

M=1
a subtractor

Combinational Circuit Design 18

 4-BIT BINARY ADDER-SUBTRACTOR

4-bit binary adder-subtractor with overflow detection

 Consider the following example which considers numbers between -16 to 15 that requires total 5 bits
for representation, i.e., 4 bits for representing the numbers and one bit for sign.

−7 6 − 12 4
+8 −3 − 3 + 8
1 3 − 15 12
1 1 1 1 1 1 1 1 0 0
1 1001 0 0110 1 0100 0 0100
+ 0 1000 + 1 1101 + 1 1101 + 0 1000
--------- --------- --------- ---------
1 0 0001 1 0 0011 1 1 0001 0 0000

Combinational Circuit Design 19

 4-BIT BINARY ADDER-SUBTRACTOR

4-bit binary adder-subtractor with overflow detection

 From the example, it can be observed that the

− 12 13
overflow does not occur when the carry
− 5 + 6
generated from both the 3rd and 4th are same,
i.e., either both are 0 or 1 (bit positions are
− 17 19
from 0 to 4). (Examples of previous slide)
1 0 0 1 1
 However, that the overflow occurs when the
1 0100 0 1101
carry generated from both the 3rd and 4th are + 1 1011 + 0 0110
different, i.e., either 0, 1 or 1, 0. (Examples on --------- ---------
the right side) 1 0 1111 1 0011

Combinational Circuit Design 20

 4-BIT BINARY ADDER-SUBTRACTOR

4-bit binary adder-subtractor with overflow detection

 An Ex-OR gate can be used 2nd and

3rd bit carry in order to detect the
overflow.

 As it is 4-bit adder-subtractor circuit

so the signed number range is from
− 8 to 7 (3rd bit signed bit).

Combinational Circuit Design 21

 BCD ADDER

Addition Operation of BCD Codes

 During the addition of two decimal digits using BCD codes, the sum can’t be greater than

9 + 9 + 1 (Previous carry) = 19

 The range of the binary sum will be from 0 - 19 i.e., in BCD, it is from 0000 to 00011001 (0000 to
10011 in binary)

Method for BCD addition

 Add the two BCD numbers, using the rules for binary addition.
 If the sum is equal or less than 1001 (9) without any carry, then the BCD digit is a valid BCD digit.
 If sum ≥ 𝟏𝟎𝟏𝟎 (10), then the result is an invalid BCD digit, then add 0110 (6) to the binary sum to get
a valid BCD digit and can also produce a carry as well.

Combinational Circuit Design 22

 BCD ADDER

 There are 3 different cases can

be observed from the table in
which 6 will added to get valid
BCD digit.

1. If Z8 and Z2 are 1

2. If Z8 and Z4 are 1

3. If carry K is 1

 The Boolean logic can be

obtained as

Combinational Circuit Design 23

BCD ADDER

Output carry

Combinational Circuit Design 24

Please follow the instructions of the government and stay safe

Combinational Circuit Design 25