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HD74LS00P

This document provides information on the HD74LS00 quadruple 2-input NAND gate integrated circuit, including: 1) Packaging and ordering information for the device available in 14-pin DIP and SOP packages. 2) A diagram showing the pin arrangement and configuration of the device. 3) Circuit schematic and description of one of the four 2-input NAND gates. 4) Electrical specification tables listing the device's absolute maximum ratings, recommended operating conditions, and electrical characteristics.

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BIMO MODELADO
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0% found this document useful (0 votes)
136 views5 pages

HD74LS00P

This document provides information on the HD74LS00 quadruple 2-input NAND gate integrated circuit, including: 1) Packaging and ordering information for the device available in 14-pin DIP and SOP packages. 2) A diagram showing the pin arrangement and configuration of the device. 3) Circuit schematic and description of one of the four 2-input NAND gates. 4) Electrical specification tables listing the device's absolute maximum ratings, recommended operating conditions, and electrical characteristics.

Uploaded by

BIMO MODELADO
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

HD74LS00

Quadruple 2-Input NAND Gates


REJ03D0387–0200
Rev.2.00
Feb.18.2005

Features
• Ordering Information

Package Code Package Taping Abbreviation


Part Name Package Type
(Previous Code) Abbreviation (Quantity)
PRDP0014AB-B
HD74LS00P DILP-14 pin P —
(DP-14AV)
PRSP0014DF-B
HD74LS00FPEL SOP-14 pin (JEITA) FP EL (2,000 pcs/reel)
(FP-14DAV)
PRSP0014DE-A
HD74LS00RPEL SOP-14 pin (JEDEC) RP EL (2,500 pcs/reel)
(FP-14DNV)
Note: Please consult the sales office for the above package availability.

Pin Arrangement

1A 1 14 VCC

1B 2 13 4B

1Y 3 12 4A

2A 4 11 4Y

2B 5 10 3B

2Y 6 9 3A

GND 7 8 3Y

(Top view)

Rev.2.00, Feb.18.2005, page 1 of 5


HD74LS00

Circuit Schematic (1/4)

VCC
8k 75

20k

Inputs
A 4.5k Output
B Y

1.5k 3k

GND

Absolute Maximum Ratings


Item Symbol Ratings Unit
Supply voltage VCC Note 7 V
Input voltage VIN 7 V
Power dissipation PT 400 mW
Storage temperature Tstg –65 to +150 °C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.

Recommended Operating Conditions


Item Symbol Min Typ Max Unit
Supply voltage VCC 4.75 5.00 5.25 V
IOH — — –400 µA
Output current
IOL — — 8 mA
Operating temperature Topr –20 25 75 °C

Rev.2.00, Feb.18.2005, page 2 of 5


HD74LS00

Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
VIH 2.0 — — V
Input voltage
VIL — — 0.8 V
VOH 2.7 — — V VCC = 4.75 V, VIL = 0.8 V, IOH = –400 µA
Output voltage — — 0.5 IOL = 8 mA
VOL V VCC = 4.75 V, VIH = 2 V
— — 0.4 IOL = 4 mA
IIH — — 20 µA VCC = 5.25 V, VI = 2.7 V
Input current IIL — — –0.4 mA VCC = 5.25 V, VI = 0.4 V
II — — 0.1 mA VCC = 5.25 V, VI = 7 V
Short-circuit output
IOS –20 — –100 mA VCC = 5.25 V
current
ICCH — 0.8 1.6 mA VCC = 5.25 V
Supply current
ICCL — 2.4 4.4 mA VCC = 5.25 V
Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Note: * VCC = 5 V, Ta = 25°C

Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol min. typ. max. Unit Condition
tPLH — 9 15 ns
Propagation delay time CL = 15 pF, RL = 2 kΩ
tPHL — 10 15 ns
Note: Refer to Test Circuit and Waveform of the Common Item "TTL Common Matter (Document No.: REJ27D0005-
0100)".

Rev.2.00, Feb.18.2005, page 3 of 5


HD74LS00

Package Dimensions
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]
P-DIP14-6.3x19.2-2.54 PRDP0014AB-B DP-14AV 0.97g

14 8

E
1 7
b3

Reference Dimension in Millimeters


Symbol
Min Nom Max

A
e1 7.62
A1

D 19.2 20.32
E 6.3 7.4
A 5.06
L

A1 0.51
bp 0.40 0.48 0.56
e bp θ c b3 1.30
c 0.19 0.25 0.31
e1
θ 0° 15°
e 2.29 2.54 2.79
Z 2.39
( Ni/Pd/Au plating ) L 2.54

JEITA Package Code RENESAS Code Previous Code MASS[Typ.]


P-SOP14-5.5x10.06-1.27 PRSP0014DF-B FP-14DAV 0.23g

NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
*1 DO NOT INCLUDE MOLD FLASH.
D F 2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
14 8

bp
HE
E

c
*2

Index mark Dimension in Millimeters


Reference
Symbol
Min Nom Max
Terminal cross section D 10.06 10.5

( Ni/Pd/Au plating ) E 5.50


A2
1 7
A1 0.00 0.10 0.20
e *3
bp
Z
x M A 2.20
L1 bp 0.34 0.40 0.46
b1
c 0.15 0.20 0.25
c 1
A

θ 0° 8°
HE 7.50 7.80 8.00
θ e 1.27
A1

y L x 0.12
y 0.15
Detail F Z 1.42
L 0.50 0.70 0.90
L 1 1.15

Rev.2.00, Feb.18.2005, page 4 of 5


HD74LS00

JEITA Package Code RENESAS Code Previous Code MASS[Typ.]


P-SOP14-3.95x8.65-1.27 PRSP0014DE-A FP-14DNV 0.13g

NOTE)
*1
D F 1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
14 8 INCLUDE TRIM OFFSET.

bp

HE
E
Index mark

c
*2
Reference Dimension in Millimeters
Symbol
Min Nom Max
Terminal cross section D 8.65 9.05

( Ni/Pd/Au plating ) E 3.95


A2

1 7 A1 0.10 0.14 0.25

Z e *3
bp A 1.75
x M
bp 0.34 0.40 0.46
L1
b1
c 0.15 0.20 0.25
c 1

θ 0° 8°
A

HE 5.80 6.10 6.20


θ e 1.27

A1
L x 0.25

y y 0.15
Detail F Z 0.635
L 0.40 0.60 1.27
L 1 1.08

Rev.2.00, Feb.18.2005, page 5 of 5

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