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The document contains 13 true/false questions and 13 multiple choice questions about computer systems and operating systems. It covers topics like processor functions, interrupts, memory hierarchies, caches, and input/output. The key points addressed are the roles of main components like processors and memory, how interrupts work, techniques for improving processor efficiency like multiprogramming, and memory optimization methods like cache.

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56 views4 pages

Sheet 1

The document contains 13 true/false questions and 13 multiple choice questions about computer systems and operating systems. It covers topics like processor functions, interrupts, memory hierarchies, caches, and input/output. The key points addressed are the roles of main components like processors and memory, how interrupts work, techniques for improving processor efficiency like multiprogramming, and memory optimization methods like cache.

Uploaded by

Rago Rago
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Operating Systems, Chapter 1

Chapter 1 – Computer Systems Overview

True / False Questions:


1. T / F – One of the processor’s main functions is to exchange data with memory.

2. T / F – The Program Status Word contains status information in the form of


condition codes, which are bits typically set by the programmer as a result of
program operation.

3. T / F – The processing required for a single instruction on a typical computer


system is called the Execute Cycle.

4. T / F – A fetched instruction is normally loaded into the Instruction Register (IR).

5. T / F – An interrupt is a mechanism used by system modules to signal the


processor that normal processing should be temporarily suspended.

6. T / F – To accommodate interrupts, an extra fetch cycle is added to the


instruction cycle.

7. T / F – The minimum information that must be saved before the processor


transfers control to the interrupt handler routine is the program status word
(PSW) and the location of the current instruction.

8. T / F – One approach to dealing with multiple interrupts is to disable all interrupts


while an interrupt is being processed.

9. T / F – Multiprogramming allows the processor to make use of idle time caused


by long-wait interrupt handling.

10. T / F – In a two-level memory hierarchy, the Hit Ratio is defined as the fraction of
all memory accesses found in the slower memory.

11. T / F – Cache memory exploits the principle of locality by providing a small, fast
memory between the processor and main memory.

12. T / F – In cache memory design, block size refers to the unit of data exchanged
between cache and main memory

13. T / F – The primary problem with programmed I/O is that the processor must
wait for the I/O module to become ready and must repeatedly interrogate the
status of the I/O module while waiting.
Operating Systems, Chapter 1
Multiple Choice Questions:

1. The four main structural elements of a computer system are:


a. Processor, Registers, I/O Modules & Main Memory
b. Processor, Registers, Main Memory & System Bus
c. Processor, Main Memory, I/O Modules & System Bus
d. None of the above

2. Address registers may contain:

a. Memory addresses of data


b. Memory addresses of instructions
c. Partial memory addresses
d. All of the above

3. A Control/Status register that contains the address of the next instruction to be


fetched is called the:

a. Instruction Register (IR)


b. Program Counter (PC)
c. Program Status Word (PSW)
d. All of the above

4. The two basic steps used by the processor in instruction processing are:

a. Fetch and Instruction cycles


b. Instruction and Execute cycles
c. Fetch and Execute cycles
d. None of the above

5. A fetched instruction is normally loaded into the:

a. Instruction Register (IR)


b. Program Counter (PC)
c. Accumulator (AC)
d. None of the above

6. A common class of interrupts is:

a. Program
b. Timer
c. I/O
d. All of the above

7. When an external device becomes ready to be serviced by the processor, the


device sends this type of signal to the processor:

a. Interrupt signal
b. Halt signal
Operating Systems, Chapter 1
c. Handler signal
d. None of the above

8. Information that must be saved prior to the processor transferring control to the
interrupt handler routine includes:

a. Processor Status Word (PSW)


b. Processor Status Word (PSW) & Location of next instruction
c. Processor Status Word (PSW) & Contents of processor registers
d. None of the above

9. One accepted method of dealing with multiple interrupts is to:

a. Define priorities for the interrupts


b. Disable all interrupts except those of highest priority
c. Service them in round-robin fashion
d. None of the above

10. In a uniprocessor system, multiprogramming increases processor efficiency by:

a. Increasing processor speed


b. Taking advantage of time wasted by long wait interrupt handling
c. Eliminating all idle processor cycles
d. All of the above

11. As one proceeds down the memory hierarchy (i.e., from inboard memory to
offline storage), the following condition(s) apply:

a. Increasing cost per bit


b. Decreasing capacity
c. Increasing access time
d. All of the above

12. Small, fast memory located between the processor and main memory is called:

a. WORM memory
b. Cache memory
c. CD-RW memory
d. None of the above

13. Direct Memory Access (DMA) operations require the following information from
the processor:

a. Address of I/O device


b. Starting memory location to read from or write to
c. Number of words to be read or written
d. All of the above

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