Assignment 4

Implement a synchronous arbitrary counter with states 3 -> 0 -> 1 -> 5 -> 2 -> 7 -> 6 -> 4 -> 9 -> 12. The active low
set signal is used to initialize the counter at any state (valid or invalid) with the input specified using init vector and at
each negative edge of clock signal clk it goes to the next state. At each transition from current state to next state the
counter produces the state count and an output (out) 0, except for the transition from state 12 -> 3 it produces an
output (out) 1 along with the count.  The active low reset signal is used to initialize the counter to state 3.
module arb_counter (out, count, init, set, reset, clk);
input set, reset clk;
input [?:0] init;
output [?:0] count;
output out;
From any invalid state the counter will always move to state 5 on the next clock edge. Specify the size of the init and
count vector according to the requirement.
Sample Test Cases

Input Output
Test 0
Pass: for init(count,out)=( 3, 0), after period = 3 arb_counter(count,
Case out)=( 5, 0)
1
Test 1
Pass: for init(count,out)=( 6, 0), after period = 4 arb_counter(count,
Case out)=( 3, 1)
2
Test 2
Pass: for init(count,out)=(15, 0), after period = 1 arb_counter(count,
Case out)=( 5, 0)
3
Test 3
Pass: for init(count,out)=( 3, 0), after period =10 arb_counter(count,
Case out)=( 3, 1)
4
Test 4
Pass: for init(count,out)=( 6, 0), after period =10 arb_counter(count,
Case out)=( 6, 0)
5
Test 5
Pass: for init(count,out)=( 7, 0), after period = 5 arb_counter(count,
Case out)=( 3, 1)
6
Test 6
Pass: for init(count,out)=( 9, 0), after period = 1 arb_counter(count,
Case out)=(12, 0)
7
Test 7
Pass: for init(count,out)=(12, 0), after period = 1 arb_counter(count,
Case out)=( 3, 1)
8

// Write the arb_counter modules here

//************************************************************************
//Sample Solution
//************************************************************************
//Arbitrary counter
module arb_counter (out, count, init, set, reset, clk);
 input set, reset, clk;
input [3:0] init;
output [3:0] count;
output out;
reg [3:0] count;
reg out;

always @(negedge clk or negedge set or negedge reset)

begin
if (!set) begin count = init; out = 0; end
else if (!reset) begin count = 4'b0011; out = 0; end
else begin
case (count)
4'b0011: begin
count = 4'b0000;
out = 0;
end

4'b0000: begin
count = 4'b0001;
out = 0;
end

4'b0001: begin
count = 4'b0101;
out = 0;
end

4'b0101: begin
count = 4'b0010;
out = 0;
end

4'b0010: begin
count = 4'b0111;
out = 0;
end

4'b0111: begin
count = 4'b0110;
out = 0;
end

4'b0110: begin
count = 4'b0100;
out = 0;
end

4'b0100: begin
 count = 4'b1001;
out = 0;
end

4'b1001: begin
count = 4'b1100;
out = 0;
end

4'b1100: begin
count = 4'b0011;
out = 1;
end

default: begin
count = 4'b0101;
out = 0;
end
endcase
end
end
endmodule
//************************************************************************
//End of Sample Solution
//************************************************************************
`timescale 1ns/1ps
module arb_counter_tb;
reg set, reset, clk;
reg [3:0] init;
wire [3:0] count;
wire out;
reg [3:0] count_p, count_c;
reg out_p, out_c;

arb_counter SA(out, count, init, set, reset, clk);

parameter STDIN = 32'h8000_0000;

integer testid;
integer ret;

initial
begin
clk=1'b1;
forever #10 clk=~clk;
end
//3 -> 0 -> 1 -> 5 -> 2 -> 7 -> 6 -> 4 -> 9 -> 12
initial
begin
ret = $fscanf(STDIN,"%d",testid);
case(testid)

0: begin //reset the counter

#2 set=1'b1; reset=1'b0;
#5 count_p=count; out_p = out; reset=1'b1;
//#20 $display("%d", count);
#60 count_c=count; out_c = out;
end

1: begin //set the counter

#2 set=1'b0; reset=1'b1; init=4'b0110;
#5 count_p=count; out_p = out; set=1'b1;
#80 count_c=count; out_c = out;
end

2: begin //set the counter

#2 set=1'b0; reset=1'b1; init=4'b1111;
#5 count_p=count; out_p = out; set=1'b1;
#20 count_c=count; out_c = out;
end

3: begin //set the counter

#2 set=1'b1; reset=1'b0;
#5 count_p=count; out_p = out; reset=1'b1;
#200 count_c=count; out_c = out;
end

4: begin //set the counter

#2 set=1'b0; reset=1'b1; init=4'b0110;
#5 count_p=count; out_p = out; set=1'b1;
#200 count_c=count; out_c = out;
end

5: begin //set the counter

#2 set=1'b0; reset=1'b1; init=4'b0111;
#5 count_p=count; out_p = out; set=1'b1;
#100 count_c=count; out_c = out;
end

6: begin //set the counter

#2 set=1'b0; reset=1'b1; init=4'b1001;
#5 count_p=count; out_p = out; set=1'b1;
#20 count_c=count; out_c = out;
end
 7: begin //set the counter
#2 set=1'b0; reset=1'b1; init=4'b1100;
#5 count_p=count; out_p = out; set=1'b1;
#20 count_c=count; out_c = out;
end

default: begin
$display("Bad testcase id %d",testid);
$finish();
end

endcase
//*******************************************************************************

2. Implement a serial adder that adds two numbers serially bit-by-bit, and produces the sum serially bit-by-bit. The
state transition diagram will consist of two states indicating the carry status, and can be realized using a single state
variable. The reset signal is used to initialize the carry to 0. Suppose we want to add two numbers 01011 and
10011. The inputs are applied sequentially (least significant bit first) to the a and b inputs in synchronism with the
raising edge of clock as (1,1),  (1,1), (0,0), (1,0) and (0,1). The sum bits are generated on output s sequentially (least
significant bit first) as 0, 1, 1, 1, 1.
module serialadd (a, b, s, reset, clk);
input  a, b, reset, clk;
output s;
Sample Test Cases

Input Output
0 Pass: for a (01011) + b (10011) = s (11110)
Test Case 1
1 Pass: for a (10111) + b (01111) = s (00110)
Test Case 2
2 Pass: for a (10110) + b (00110) = s (11100)
Test Case 3
3 Pass: for a (01000) + b (10001) = s (11001)
Test Case 4
4 Pass: for a (00001) + b (11111) = s (00000)
Test Case 5
5 Pass: for a (11111) + b (00000) = s (11111)
Test Case 6
6 Pass: for a (11111) + b (11111) = s (11110)
Test Case 7
7 Pass: for a (00000) + b (00000) = s (00000)
Test Case 8

//************************************************************************
//Sample Solution
//************************************************************************
//serial adder
module serialadd (a, b, s, reset, clk);
input a, b, reset, clk;
 output s;
reg s, cfsm, cfsm_nxt;

always @(posedge(clk) or posedge(reset)) begin

if (reset) cfsm <= 1'b0;
else begin
case ({a,b})
2'b00, 2'b11: begin
s = cfsm;
end
2'b01, 2'b10: begin
s = !cfsm;
end
endcase
case (cfsm)
1'b0: begin
if (a&b)
cfsm_nxt = 1'b1;
else
cfsm_nxt = cfsm;
end
1'b1: begin
if (!(a|b))
cfsm_nxt = 1'b0;
else
cfsm_nxt = cfsm;
end
endcase
cfsm <= cfsm_nxt;
end
end

endmodule
//************************************************************************
//End of Sample Solution
//************************************************************************
`timescale 1ns/1ps
module serialadd_tb;
reg a, b, reset, clk;
reg [3:0] s_t;
reg [4:0] a_t, b_t;
wire s;

serialadd SA(a, b, s, reset, clk);

parameter STDIN = 32'h8000_0000;

integer testid;
integer ret;
initial
begin
clk=1'b0;
forever #10 clk=~clk;
end

initial
begin
ret = $fscanf(STDIN,"%d",testid);
case(testid)

0: begin //add 11 and 19

#2 reset = 1'b1; a = 1'b0; b = 1'b0; a_t=11; b_t=19;
#5; reset = 1'b0; a = a_t[0]; b = b_t[0];
#15; s_t[0] = s;

#5; a = a_t[1]; b = b_t[1];

#15; s_t[1] = s;

#5; a = a_t[2]; b = b_t[2];

#15; s_t[2] = s;

#5; a = a_t[3]; b = b_t[3];

#15; s_t[3] = s;

#5; a = a_t[4]; b = b_t[4];

end

1: begin //add 23 and 15

#2 reset = 1'b1; a = 1'b0; b = 1'b0; a_t=23; b_t=15;
#5; reset = 1'b0; a = a_t[0]; b = b_t[0];
#15; s_t[0] = s;

#5; a = a_t[1]; b = b_t[1];

#15; s_t[1] = s;

#5; a = a_t[2]; b = b_t[2];

#15; s_t[2] = s;

#5; a = a_t[3]; b = b_t[3];

#15; s_t[3] = s;

#5; a = a_t[4]; b = b_t[4];

end

2: begin //add 22 and 6

#2 reset = 1'b1; a = 1'b0; b = 1'b0; a_t=22; b_t=6;
#5; reset = 1'b0; a = a_t[0]; b = b_t[0];
#15; s_t[0] = s;
 #5; a = a_t[1]; b = b_t[1];
#15; s_t[1] = s;

#5; a = a_t[2]; b = b_t[2];

#15; s_t[2] = s;

#5; a = a_t[3]; b = b_t[3];

#15; s_t[3] = s;

#5; a = a_t[4]; b = b_t[4];

end

3: begin //add 8 and 17

#2 reset = 1'b1; a = 1'b0; b = 1'b0; a_t=8; b_t=17;
#5; reset = 1'b0; a = a_t[0]; b = b_t[0];
#15; s_t[0] = s;

#5; a = a_t[1]; b = b_t[1];

#15; s_t[1] = s;

#5; a = a_t[2]; b = b_t[2];

#15; s_t[2] = s;

#5; a = a_t[3]; b = b_t[3];

#15; s_t[3] = s;

#5; a = a_t[4]; b = b_t[4];

end

4: begin //add 1 and 31

#2 reset = 1'b1; a = 1'b0; b = 1'b0; a_t=1; b_t=31;
#5; reset = 1'b0; a = a_t[0]; b = b_t[0];
#15; s_t[0] = s;

#5; a = a_t[1]; b = b_t[1];

#15; s_t[1] = s;

#5; a = a_t[2]; b = b_t[2];

#15; s_t[2] = s;

#5; a = a_t[3]; b = b_t[3];

#15; s_t[3] = s;

#5; a = a_t[4]; b = b_t[4];

end

5: begin //add 31 and 0

#2 reset = 1'b1; a = 1'b0; b = 1'b0; a_t=31; b_t=0;
 #5; reset = 1'b0; a = a_t[0]; b = b_t[0];
#15; s_t[0] = s;

#5; a = a_t[1]; b = b_t[1];

#15; s_t[1] = s;

#5; a = a_t[2]; b = b_t[2];

#15; s_t[2] = s;

#5; a = a_t[3]; b = b_t[3];

#15; s_t[3] = s;

#5; a = a_t[4]; b = b_t[4];

end

6: begin //add 31 and 31

#2 reset = 1'b1; a = 1'b0; b = 1'b0; a_t=31; b_t=31;
#5; reset = 1'b0; a = a_t[0]; b = b_t[0];
#15; s_t[0] = s;

#5; a = a_t[1]; b = b_t[1];

#15; s_t[1] = s;

#5; a = a_t[2]; b = b_t[2];

#15; s_t[2] = s;

#5; a = a_t[3]; b = b_t[3];

#15; s_t[3] = s;

#5; a = a_t[4]; b = b_t[4];

end

7: begin //add 0 and 0

#2 reset = 1'b1; a = 1'b0; b = 1'b0; a_t=0; b_t=0;
#5; reset = 1'b0; a = a_t[0]; b = b_t[0];
#15; s_t[0] = s;

#5; a = a_t[1]; b = b_t[1];

#15; s_t[1] = s;

#5; a = a_t[2]; b = b_t[2];

#15; s_t[2] = s;

#5; a = a_t[3]; b = b_t[3];

#15; s_t[3] = s;

#5; a = a_t[4]; b = b_t[4];

end
 default: begin
$display("Bad testcase id %d",testid);
$finish();
end

endcase