VHDL

HDLs are indeed similar to programming languages but not exactly the same. We
utilize a programming language to build or create software, whereas we use a
hardware description language to describe or express the behavioral characteristics
of digital logic circuits.

We utilize HDLs for designing processors, motherboards, CPUs (i.e., computer

chips), as well as various other digital circuitry.

Hardware description languages allow you to describe a circuit using words and
symbols, and then development software can convert that textual description into
configuration data that is loaded into the FPGA in order to implement the desired
functionality.

A hardware description language (HDL) is a

programming language used to describe the
behavior or structure of digital circuits (ICs).
HDLs are also used to stimulate the circuit and check its response.
When we write a computer program or firmware module, we understand that the
processor will execute lines of code one at a time, following the top-to- bottom
organization that we use when reading text on a page.
In HDL code, we are describing digital hardware, and separate portions of this
hardware can operate simultaneously, despite the fact that the corresponding lines
of code are written using a top-to-bottom organization.
As digital systems have become more complex, detailed design of the systems at the
gate and flip-flop level has become very tedious and time consuming. For this
reason, the use of hardware description languages in the digital design process
continues to grow in importance. A hardware description language allows a digital
system to be designed and debugged at a higher level before implementation at the
gate and flip-flop level. The two most popular hardware description languages are
VHDL and Verilog. Both VHDL and Verilog are officially endorsed IEEE (Institute
of Electrical and Electronics Engineers) standards.
Difference between Hardware Description Language and Software
Language:
Sr.No Hardware Description Language Software Language
1 HDL defines the structure and behavior Software language writes a set
of electronic circuits and mostly, digital of instructions to allow a CPU
logic circuits. to perform a particular task.
2 It defines the behavior of digital It helps to develop a variety of
circuits applications
3 It is more complex to work with. It is not as complex to work
with.
4 This design is based on the creation This is used to create
and use of textual-based descriptions of executable software
circuits. applications that will operate
on a suitable processor.
5 It is a language which is having It is a language that can
syntactic and semantic support for translate machine instructions
supporting the temporal behavior and and execute them on a
spatial structure of hardware. computer.

6 Examples : Verilog and VHDL. Examples: Java, C, C++, etc.

VHDL is a hardware description language that is used to describe the behavior and
structure of digital systems. The acronym VHDL stands for VHSIC Hardware
Description Language, and VHSIC in turn stands for Very High Speed Integrated
Circuit. However, VHDL is a general-purpose hardware description language which
can be used to describe and simulate the operation of a wide variety of digital
systems. Keep in mind it’s H D L…

– Used to ‘DESCRIBE’ Hardware…

– That means one should know what Hardware is to be described…

– We can also use VHDL as a general-purpose parallel programming

language.
VHDL is an international IEEE standard specification language (IEEE 1076-1993)
for describing digital hardware used by industry worldwide. VHDL is one of the
standard hardware description language used to design digital systems.
VHDL canbe used to design the lowest level (gate level) of a digital
system to the highestlevel (VLSI module).
Other HDLs
• Verilog
– Syntax like C… quite common in US markets.
• SystemC
– C++ based library. Quite useful for rapid prototyping.
– Evolve simulation/abstract system description into detailed hardware as time
progresses.
• System Verilog
– Evolved version of Verilog with even advanced Verification constructs.
• Matlab Simulink
– Specially useful for DSP applications.

Advantages of VHDL
– It’s like the assembly language of HDLs.
– Simple

– Extremely typed – very difficult to make mistakes.

– Provides technology independence. VHDL projects are also portable,

which means that you can generate a project for one element base and then port it
on another element base, such as VLSI, with a variety of technologies.
– Describes a wide variety of digital hardware

– VHDL is a dataflow language, which means it can

simultaneously consider every statement for execution
(Parallel execution). This is in direct contrast to procedural computing
languages like C, assembly code, and BASIC. Each of these languages runs a
sequence of statements, both sequentially and a single instruction at a time.

– Supports a variety of design methodologies: Behavioral

modeling, Dataflow or RTL (Register Transfer Language)
Modeling and Structural or gate level modeling.
– Supports Design Synthesis: Hardware implementation of the design obtained
directly from VHDL code.
 0
1 Vcc1 5

VHDL a1 b1

VHDL 2
a2 b2
6

CODE Synthsize 3
a3
FPLD b3
7

4 8

Software a4
GND
0
b4

Difference between VHDL and Verilog

VHDL Verilog

Strongly typed Weakly typed

Easier to understand Less code to write

More natural in use More of a hardware modeling language

Wordy Concise, Brief

Non-C-like syntax Similarities to the C language

Variables must be described by data A lower level of programming

type constructs

Widely used for FPGAs and military A better grasp on hardware modeling

More difficult to learn Simpler to learn

VHDL Components

VHDL Terminologies
1) Entity: All designs are expressed in terms of entities. An entity is
themost basic building block in a design.
2) Architecture: All entities that can be simulated have an architecture
description. The architecture describes the behavior
of the entity. A single entity can have multiple
architectures. One architecture might be behavioral while
another might be a structural description of the design.
3) Configuration: A configuration statement is used to bind a
component instance to an entity-architecture pair. A
configuration can be considered like a parts list
for a design. It describes which behavior to use for each entity,
much like a parts list describes which part to use for each part in
the design.
4) Package: A package is a collection (library) of
commonly used data types and subprograms
used in a design. Think of a package as a tool- box that
contains tools used to build designs.
5) Driver. This is a source on a signal. If a signal is driven by two
sources, then when both sources are active, the signal will have
two drivers.
 6) Bus. The term “bus” usually brings to mind a group of signals
or a particular method of communication used in the design of
hardware. In VHDL, a bus is a special kind of signal that may
have its drivers turned off.
7) Attribute: An attribute is data that are
attached to VHDL objects or predefined data
about VHDL objects (type of objects like type
of variables in C). Examples are the current drive
capability of a buffer or the maximum operating temperature
of the device.
8) Generic: A generic is VHDL’s term for a parameter
that passes information to an entity. For
instance, if an entity is a gate level model with a
rise and a fall delay, values for the rise and
fall delays could be passed into the entity
with generics.
The following is an example of an entity for an AND gate that
has threegenerics associated with it:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY test IS

GENERIC(rise, fall:TIME; load : INTEGER);

PORT ( ina, inb, inc, ind : IN std_logic;

out1, out2 : OUT std_logic);
END test;
This entity allows the designer to pass in a value for the rise and fall
delays, as well as the loading that the device has on its output. The
generics rise, fall, and load contain the values that were passed in by
the component instantiation statement.

ARCHITECTURE test_arch OF test IS

COMPONENT AND2
 GENERIC(rise, fall : TIME; load : INTEGER);

PORT ( a, b : IN std_logic;
c : OUT std_logic);
END COMPONENT;
BEGIN
U1: AND2
GENERIC MAP(10 ns, 12 ns, 3 )
PORT MAP (ina, inb, out1 );

U2: AND2
GENERIC MAP(9 ns, 11 ns, 5 )

PORT MAP (inc, ind, out2 );

END test_arch;
U1 and U2 are two AND gates with 2 inputs (a,b and c,d) and 1
output (out1 and out2).
9) Process. A process is the basic unit of execution in VHDL. All
operations that are performed in a simulation of a VHDL
description are broken into single or multiple processes.

VHDL can describe a digital system at several different levels—

behavioral, dataflow, and structural. For example, a binary adder
could be described at the behavioral level in terms of its function of
adding two binary numbers, without giving any implementation details.
The same adder could be described at the data flow level by giving the
logic equations for the adder. Finally, the adder could be described at the
structural level by specifying the interconnections of the gates
which make up the adder.
Dataflow Description
The gate circuit of Figure has five signals: A, B, C, D, and E. The symbol “<=” is
the signal assignment operator which indicates that the value computed on the right-
hand side is assigned to the signal on the left side. A behavioral
description of the circuit in Figure is

E <= D or (A and B);

This is Instantiation Statement.

Parentheses are used to specify the order of operator execution.

The two assignment statements in Figure give a dataflow

description of the circuit where it is assumed that each gate has a 5-ns
propagation delay. When the statements in Figure are simulated, the first
statement will be evaluated anytime A or B changes, and the second statement will be
evaluated any time C or D changes.

Suppose that initially A = 1, and B = C = D = E = 0. If B changes to 1 at time 0, C

will change to 1 at time = 5 ns. Then, E will change to 1 at time = 10 ns.

Structural Description
The circuit of Figure can also be described using structural VHDL code. To do so
requires that a two-input AND-gate component and a two-input
OR-gate component be declared and defined. Components may be
declared and defined either in a library or within the
architecture part of the VHDL code.

Instantiation statements are used to specify how

components are connected. Each copy of a component requires a
separate instantiation statement to specify how it isconnected to other components
and to the port inputs and outputs. An instantiation statement is a concurrent
statement that executes anytime one of the input signals in its port map changes.
The circuit of Figure is described by instantiating the AND gate and the OR gate as
follows:
Gate1: AND2 port map (A, B, C);

Gate2: OR2 port map (C, D, E);

The port map for Gate1 connects A and B to the AND-gate
inputs, and it connects D to the AND-gate output. Since an
instantiation statement is concurrent, wheneverA or B changes, these changes go to
the Gate1 inputs, and then the component computes a new value of C. Similarly,
the second statement passes changes in C or D to the Gate2 inputs, and then the
component computes a new value of E.
This is exactly how the real hardware works. (The order in which the instantiation
statements appear is irrelevant.) Instantiating a component is different than calling a
function in a computer program. A function returns a new value whenever it is
called, but an instantiated component computes a new output value whenever its
input changes.
Here, we call the module F a design entity, and the inputs and outputs are called
ports.

Lexical Elements
Lexical elements are basic syntactical units in a VHDL program and include
1) Comments:
Comments start with two dashes, e.g.,
-- This is a comment in VHDL
2) Identifiers:
An identifier can only contain alphabetic letters, decimal digits
and underscore; the first character must be a letter and the last character
cannot be an underscore. Also,two successive underscores are not allowed.
Valid examples:
A10, next_state, NextState, mem_addr_enable
Invalid examples:
sig#3, _X10, 7segment, X10_, hi_ _there
 3) Reserved words

4) Numbers:
Integer: 0, 1234, 98E7
Real: 0.0, 1.23456 or 9.87E6
Base 2: 2#101101#

5) Characters
‘A’, ‘Z’, ‘1’

6) Strings
“Hello”, “1100111”
Note that 0 and ‘0’ are different

7) VHDL is case INsensitive, i.e., the following identifiers are the same
nextstate,NextState, NEXTSTATE, nEXTsTATE.
8) Use CAPITAL_LETTERs for constant names and the suffix_n to indicate active
low signals

9) Each VHDL Statements is terminated using a semicolon.

 Signal Assignment Statements
VHDL signal assignment statements, such as the ones in Figure 10-1, are examples
of concurrent statements. The VHDL simulator monitors the right side of each
concurrent statement, and any time a signal changes, the expression on the right side
is immediately re-evaluated. The new value is assigned to the signal on the left side
after an appropriate delay. This is exactly the way the hardware works. Any time a
gate input changes, the gate output is recomputed by the hardware, and the output
changes after the gate delay.
C <= A AND B after 5 ns
F<= D OR E after 10 ns

Propagation Delay
When we initially describe a circuit, we may not be concerned about propagation
delays. If we write
C <= A and B;
E <= C or D;

this implies that the propagation delays are 0 ns. In this case, the
simulator will assume an infinitesimal delay referred to as Δ (delta).
Assume that initially A = 1 and B = C = D = E = 0. If B is changed to 1 at time = 1
ns, then C will change at time 1 + Δ and E will change at time 1 + 2 Δ.
Unlike a sequential program, the order of the above
concurrent statements is unimportant. If we write

E <= C or D;

C <= A and B;
the simulation results would be exactly the same as before. In general, a signal
assignment statement has the form

signal_name <= expression [after delay];

The expression is evaluated when the statement is executed, and the signal on the
left side is scheduled to change after delay.
Example:
WITH sel SELECT
q <= i0 AFTER 10 ns WHEN 0,

(i.e WHEN sel = 0. So

WHEN value indicates

value of ‘sel’)

i1 AFTER 10 ns WHEN 1,
i2 AFTER 10 ns WHEN 2,
i3 AFTER 10 ns WHEN 3,
‘X’ AFTER 10 ns WHEN OTHERS;

sel <=0 WHE a = ‘0’ AND b = ‘0’ ELSE

N
1 WHE a = ‘1’ AND b = ‘0’ ELSE
N
2 WHE a = ‘0’ AND b = ‘1’ ELSE
N
3 WHE a = ‘1’ AND b = ‘1’ ELSE
N
4 ;

Repeated Execution
Even if a VHDL program has no explicit loops, concurrent statements may execute
repeatedly as if they were in a loop. Figure shows an inverter with the output
connected back to the input. If the output is ‘0’, then this ‘0’ feeds back to the input
and the inverter output changes to ‘1’ after the inverter delay, assumed to be 10 ns.
Then, the ‘1’ feeds back to the input, and the output changes to ‘0’ after the inverter
delay. The signal CLK will continue to oscillate between ‘0’ and ‘1’, as shown in
 the waveform. The corresponding concurrent VHDL statement will produce the
same result. If CLK is initialized to ‘0’, the statement executes and CLK changes to
‘1’ after 10 ns. Because CLK has changed, the statement executes again, and CLK
will change back to ‘0’ after another 10 ns. This process will continue indefinitely.

Syntax Rules
In general, VHDL is not case sensitive, that is, capital and
lower case letters are treated the same by the compiler and
the simulator. Thus, the statements
Clk <= NOT clk After 10 NS;
and CLK <= not CLK after 10 ns;
would be treated exactly the same.

Signal names and other VHDL identifiers may contain letters, numbers, and the
underscore character (_). An identifier must start with a letter, and it cannot end with
an underscore. Thus, C123 and ab_23 are legal identifiers, but 1ABC and ABC_ are
not. Every VHDL statement must be terminated with a
semicolon. Spaces, tabs, andcarriage returns are treated in the same way. This
means that a VHDL statement can be continued over several lines, or several
statements can be placed on one line. In a line of VHDL code, anything
following a double dash (--) is treated as a comment.Words such
as and, or, and after are reserved words (or keywords) which have a special
meaning to the VHDL compiler.
Figure shows three gates that have the signal A as a common input and the corresponding
VHDL code. The three concurrent statements execute simultaneously
whenever A changes, just as the three gates start processing the
signal change at the same time. This is Instantiation. If all 3 gates
have same propagation delays, output D,E and F after at the same
time. However, if the gates have different delays, the gate outputs
can change at different times. If the gates have delays of 2 ns, 1 ns,
and 3 ns, respectively, and A changes at time 5 ns, then the gate
outputs D, E, and F can change at times 7 ns, 6 ns, and 8 ns,
respectively. The VHDL statements work in the same way. Even
though the statements execute simultaneously, the signals D, E,
and F areupdated at times 7 ns, 6 ns, and 8 ns.

Signal of type ‘Bit’ or ‘Bit-Vector’

In these examples, every signal is of type bit, which means it can have
a value of ‘0’ or ‘1’. (Bit values in VHDL are enclosed in single
quotes to distinguish them from integer values.) In digital design,
we often need to perform the same operation on a group of signals. A one-
dimensional array of bit signals is referred to as a bit-vector.

If a 4-bit vector named B has an index range 0 through 3,

then the four elements of the bit-vector are designated B(0),
B(1), B(2), and B(3). The statement
B<= “0110”
assigns ‘0’ to B(0), ‘1’ TO B(1), ‘1’ to B(2) and ‘0’ to B(3)
Figure shows an array of four AND gates. The inputs are
represented by bit-vectors A and B, and the outputs
by bit-vector C. Although we can write four VHDL
statements to represent the four gates, it is much
more efficient to write a single VHDL statement that
performs the and operation on the bit-vectors A and
B. When applied to bit-vectors, the and operator performs the and
operation on correspondingpairs of elements.

VHDL Models for Multiplexers

Conditional Signal Assignment Statement

Figure shows a 2-to-1 multiplexer (MUX) with two data inputs and one
control input. The MUX output is F = A’.I0 + A·I1. The
corresponding VHDL statement is F <= (not A and I0) or
(A and I1);
 Alternatively, we can represent the MUX by a Conditional Signal
Assignment Statement, as shown in Figure. This statement
executes whenever A, I0, or I1 changes. The MUX output is I0 when A
= ‘0’, and else it is I1. In the conditional statement, I0, I1, and F can
either be bits or bit-vectors.
The general form of a conditional signal assignment statement is:

signal_name <= expression1

when condition1

else expression2

when condition2

[else expressionN];

This concurrent statement is executed whenever a

change occurs in a signal used in one of the
expressions or conditions. If condition1 is true, signal_name
is set equal to the value of expression1, or else if condition2 is true,
signal_name is set equal to the value of expression2, etc. The line in
square brackets is optional.

Figure shows how two cascaded MUXes can be represented by a

conditional signal assignment statement. The output MUX selects A
when E = ‘1’; or else it selects the output of the first MUX, which is
B when D = ‘1’, or else it is C.
Figure shows a 4-to-1 MUX with four data inputs and two control inputs, A
and B. The control inputs select which one of the data inputs is
transmitted to the output. The logic equation for the 4-to-1 MUX is

F = A’B’I0 + A’BI1 + AB’I2 + ABI3

Thus, one way to model the MUX is with the VHDL statement

F <= (not A and not B and I0) or

(not A and B and I1) or

(A and not B and I2) or

(A and B and I3);

Another way to model the 4-to-1 MUX is to use a conditional assignment

statement:
F <= I0 when A&B = “00”

else
I1 when

A&B=“01”

else
I2 when

A&B=“10”

else I3;

The expression A&B means A concatenated with B,

that is, the two bits A and B are merged together to
form a 2-bit vector. This bit vector is tested, and the
appropriate MUX input is selected. For example, if A = ‘1’
and B = ‘0’, A&B = “10” and I2 is selected.
Instead of concatenating A and B, we could use a more complex condition:
F <= I0 when

A =‘0’ and B=‘0’

else I1 when

A = ‘0’ and B = ‘1’

else I2 when A

= ‘1’ and B = ‘0’

else I3;

Select Statement
A third way to model the MUX is to use a selected signal
assignment statement, as shown in Figure . A&B cannot be used in
this type of statement, so

we first set Sel equal to A&B. The value of Sel then

selects the MUX input that is assigned to F.

The general form of a selected signal assignment statement is

 with expression_s select

signal_s <= expression1 [after

delay-time] when choice1,

expression2 [after delay-

time] when choice2,

...
[expression_n [after delay-time] when others];

This concurrent statement executes whenever a signal changes in any of

the expressions. First, expression_s is evaluated. If it
equals choice1, signal_s is set equal to expression1;
if it equals choice2, signal_s is set equal to
expression2; etc. If all possible choices for the value of
expression_s are given, the last line should be omitted; otherwise, the
last line is required. When it is present, if expression_s is not equal to any
of the enumerated choices, signal_s is set equal to expression_n. The
signal_s is updated after the specified delay-time, or
after Δ if the “after delay- time” is omitted.

Sequential Statements
1) IF Statement
IF condition THEN sequence_of_statements
{ELSIF condition THEN sequence_of_statements}
[ELSE
sequence_of_statements]
END IF;
Example:

IF (day = sunday) THEN weekend := TRUE;

ELSIF (day = saturday) THENweekend := TRUE;
ELSE
weekday := TRUE;
END IF;

2) CASE Statement
Example:
TYPE vectype IS ARRAY(0 TO 1) OF BIT;
VARIABLE bit_vec : vectype;
.
CASE bit_vec IS
WHEN “00” =>RETURN 0;
WHEN “01” =>RETURN 1;
WHEN “10” =>RETURN 2;
WHEN “11” =>RETURN 3;
END CASE;

3) LOOP Statement
Example:

WHILE (day = weekday) LOOP

day := get_next_day(day);
END LOOP;
4) PROCESS Statement
In VHDL, sequential statements are executed within a process block. The sensitivity list
contains all of the inputs to the process block.

Syntax is:
[label:] process (sensitivity list)
constant or variable declarations
begin
sequential statements;
end process [label];

Example:

PROCESS(i)
BEGIN
x <= i + 1; -- x is a signal
FOR i IN 1 to a/2 LOOP
q(i) := a; -- q is a variable
END LOOP;
END PROCESS;
 5) NEXT Statement:
The process statement contains one LOOP statement. This LOOP statement logically
“and”s the bits of arrays a and b and puts the results in array q. The NEXT statement
allows the designer the ability to stop execution of this iteration and go on to the next
iteration. There are other cases when the need exists to stop execution of a loop
completely. This capability is provided with the EXIT statement. This behavior
continues whenever the flag in array done is not true. If the done flag is already set for
this value of index i, then the NEXT statement is executed. If the value of the done
array is not true, then the NEXT statement is not executed, and execution continues with
the statement contained in the ELSE clause for the IF statement.

Example:
PROCESS(A, B)
CONSTANT max_limit : INTEGER := 255;BEGIN
FOR i IN 0 TO max_limit LOOP
IF (done(i) = TRUE) THEN
NEXT;
ELSE
done(i) := TRUE;
END IF;
q(i) <= a(i) AND b(i);
END LOOP;
END PROCESS;
6) EXIT Statement

During the execution of a LOOP statement, it may be necessary to jump out of the loop.
This can occur because a significant error has occurred during the execution of the model
or all of the processing has finished early. The VHDL EXIT statement allows the
designer to exit or jump out of a LOOP statement currently in execution.
Example:
PROCESS(a)
variable int_a : integer;
BEGIN
int_a := a;

FOR i IN 0 TO max_limit LOOP

IF (int_a <= 0) THEN -- less than or
EXIT; -- equal to
ELSE
int_a := int_a -1;
q(i) <= 3.1416 / REAL(int_a * i); -- signal
END IF; -- assign
END LOOP;

y <= q;

END PROCESS;
 7) WAIT Statements

The WAIT statement gives the designer the ability to suspend the sequential execution of
a process or subprogram. The conditions for resuming execution of the suspended process
or subprogram can be specified by the following three different means:
WAIT ON signal changes
WAIT UNTIL an expression is true
WAIT FOR a specific amount of time

PROCESS
BEGIN
WAIT UNTIL clock = ‘1’ AND clock’EVENT;
q <= d;
END PROCESS;

This process is used to generate a flip-flop that clocks the value of d into q when the
clock input has a rising edge. The attribute ‘EVENT attached to input clock is true
whenever the clock input has had an event during the current delta timepoint. The
effect is that the process is held at the WAIT statement until the clock has a rising
edge. Then the current value of d is assigned to q.
Reading this description into a synthesis tool creates a D flip-flop without a set or reset
input. A synchronous reset can be created by the following:

PROCESS
BEGIN
WAIT UNTIL clock = ‘1’ AND clock’EVENT;
IF (reset = ‘1’) THEN
q <= ‘0’;
ELSE
q <= d;
END IF;
END PROCESS;

Finally, an asynchronous reset can be added as follows:

PROCESS
BEGIN
IF (reset = ‘1’) THEN
q <= ‘0’;
ELSIF clock’EVENT AND clock = ‘1’ THEN
q <= d;
END IF;

WAIT ON reset, clock;

END PROCESS;
VHDL Modules/Structure

To write a complete VHDL module, we must declare all of the input and output
signals using an entity declaration, and then specify the internal operation of the
module using an architecture declaration.

As an example, consider above Figure. The entity declaration gives the name “two_gates” to the
module. The port declaration specifies the inputs and outputs to the module. A, B, and D are
input signals of type bit, and E is an output signal of type bit. The architecture is named “gates”.
The signal C is declared within the architecture because it is an internal signal. The two
concurrent statements that describe the gates are placed between the keywords begin and end.

When we describe a system in VHDL, we must specify an entity and an architecture at the top
level, and also specify an entity and architecture for each of the component modules that are
part of the system (see below figure).
Entity Declaration

Each entity declaration includes a list of interface signals that can be used to connect to other
modules or to the outside world. We will use entity declarations of the form:
entity entity-name is
[port(interface-signal-declaration);]
end [entity] [entity-name];
A system (an entity) can be specified with different architectures.