04-Oct-22

Microprocessor and Interfacing

Chapter 5

Interfacing I/O Devices

Eng. Elayan Abu Gharbyeh
2022

Chapter 5: Interfacing I/O Devices 1

Interfacing I/O Devices

• Using I/O devices data can be transferred
between the microprocessor and the outside
world.
• This can be done in groups of 8 bits using the
entire data bus. This is called parallel I/O.
• The other method is serial I/O where one bit is
transferred at a time using the SID and SOD pins
on the Microprocessor.

Chapter 5: Interfacing I/O Devices 2

1
 04-Oct-22

Dealing with I/O Devices

• There are two ways to deal with I/O devices.
– Consider them like any other memory location.
– They are assigned a 16-bit address within the address
range of the 8085.
– The exchange of data with these devices follows the
transfer of data with memory. The user uses the same
instructions used for memory.
– This is called memory-mapped I/O.
– Treat them separately from memory:
– I/O devices are assigned a “port number” within the 8-bit
address range of 00H to FFH.
– The user in this case would access these devices using
the IN and OUT instructions only.
– This is called I/O-mapped I/O or Peripheral-mapped I/O.

Chapter 5: Interfacing I/O Devices 3

Basic interfacing concepts

• The first step in interfacing an I/O device would
be to determine which instructions will be used to
access it.
– If you want the user to use the IN/OUT
instructions, then it should be interfaced as a
peripheral-mapped I/O device.
– If the user should use regular data transfer
instructions (LDA, STA, etc.) then it should be
interfaced as a memory-mapped I/O device.

Chapter 5: Interfacing I/O Devices 4

2
 04-Oct-22

Peripheral I/O instructions

• There are two instructions:
– IN brings data (8-bits) from an input device to the
accumulator
– OUT sends data (8-bits) from the accumulator to
an output device.
– They are both 2 byte instructions with the second
byte holding the 8-bit address of the device.

• Note: Given that there are separate instructions

for input and output, the 8085 can actually
communicate with 256 different input devices
AND an additional 256 different output devices.
Chapter 5: Interfacing I/O Devices 5

OUT instruction
• The OUT instruction is described as follows:
OUT 8-bit Port Address
• This is a two-byte instruction with the hex. Opcode D3, and the
second byte is the port address of an output device.
• This instruction transfers (copies) data from the accumulator to
the output device.
• For example, OUT 01H instruction will be stored in memory as:
Memory Machine code Mnemonics Memory Contents
address

2050 D3 OUT 01H ; D3H

2051 01 ; 01H

Chapter 5: Interfacing I/O Devices 6

3
 04-Oct-22

The execution of the OUT instruction

• The OUT instruction requires 3 machine cycles
and 10 T-states.
– The first cycle is an opcode fetch cycle to fetch
the 1st byte of the instruction from memory (OUT).
– The second cycle is a memory read cycle to bring
the 8-bit port number from the next location.
– The third cycle is an I/O write cycle.
• In this cycle, the 8085 places the port number on AD0-
AD7 AND A8-A15 and the signal WR is set low (active).
– Since the device address is placed on both AD0-AD7 as
well as A8-A15, there is no need for de-multiplexing AD0-
AD7. A8-A15 can be used directly to identify the device.

Chapter 5: Interfacing I/O Devices 7

Timing For Execution of OUT 01H Instruction

Chapter 5: Interfacing I/O Devices 8

4
 04-Oct-22

IN instruction
• The IN instruction is described as follows:
IN 8-bit Port Address
• This is a two-byte instruction with the hex. Opcode DB, and the
second byte is the port address of an input device.
• This instruction reads (copies) data from an input device and
places the data byte in the accumulator.
• For example, IN 84H instruction will be stored in memory as:
Memory Machine code Mnemonics Memory Contents
address

2065 DB IN 84H ; DBH

2066 84 ; 84H

Chapter 5: Interfacing I/O Devices 9

The execution of the IN instruction

• The execution of the IN instruction is almost
identical to that of the OUT instruction. 3 machine
cycles, 10 T-states.
– The first machine cycle is the opcode fetch.
– The second cycle is the memory read to get the
port number.
– The third is an I/O Read cycle.
• Again, in T1 the port address (8-bits) is placed on both
AD0- AD7, and A8-A15. The IO/M signal is set high to
indicate an I/O operation. At the beginning of T2, the RD
signal is set low (active) and the I/O device responds by
placing the 8-bit data on the data bus.

Chapter 5: Interfacing I/O Devices 10

5
 04-Oct-22

Timing For Execution of IN 84H H Instruction

Chapter 5: Interfacing I/O Devices 11

Device Selection and Data Transfer

Steps for interfacing an I/O device:
• Decode the address bus to generate a unique
pulse corresponding to the device address on the
bus; this is called the device address pulse.

• Combine (AND) the device address pulse with

the appropriate control signal to generate a
device select pulse.

• Use the device select pulse to activate the

interfacing device (I/O port).
The following block diagram illustrate these steps:

Chapter 5: Interfacing I/O Devices 12

6
 04-Oct-22

Block Diagram of I/O Interface

Chapter 5: Interfacing I/O Devices 13

Ex: A practical decoding circuit for the output

device (LED port) with address 01H

Chapter 5: Interfacing I/O Devices 14

7
 04-Oct-22

Device Address Decoding

• Absolute decoding: All eight address lines are
decoded (like the last example, the device will be
selected only with the address 01H)
• Partial decoding: To minimize the cost, some of
the address lines can be decoded (as in the
following Figure, the device has multiple
addresses: 00H,01H, 02h, 03H)
• Linear decoding: only one address line is used
for device selection(if only A0 address line is
combined with the control signal the device will
be selected for all even addresses 00H, 02H
,04H, ……)
Chapter 5: Interfacing I/O Devices 15

Ex: Partial Decoding: Output Latch with Multiple

Addresses

Chapter 5: Interfacing I/O Devices 16

8
 04-Oct-22

Interfacing I/Os Using decoders

Chapter 5: Interfacing I/O Devices 17

Interfacing Output Displays

Two types of displays:

1. LED display for Binary data.

1. Seven– segment LED display.

Chapter 5: Interfacing I/O Devices 18

9
 04-Oct-22

LED Display for Binary Data

• Let’s first design the external circuit.
– The data on the data bus from the microprocessor
stays for an extremely short amount of time. So, in
order to keep it long enough for displaying on the
LEDs, we will interface an external latch.

– The following Figure shows interfacing LED output

port using of latches

Chapter 5: Interfacing I/O Devices 19

Interfacing LED Output Port

Chapter 5: Interfacing I/O Devices 20

10
 04-Oct-22

Interfacing LED Output Port (the program)

– a LED will be ON when the corresponding bit on
the data bus is 0.

• A program to display binary data at the port:

MVI A, Data ;load the data to be displayed
OUT FF ;send the data to output port FF
HLT ;End

Chapter 5: Interfacing I/O Devices 21

Seven-Segment LED display

Seven-Segment LED: segments and types:
• Common-Anode LED
• Common-Cathode LED

Chapter 5: Interfacing I/O Devices 22

11
 04-Oct-22

Interfacing Seven-Segment LED

Chapter 5: Interfacing I/O Devices 23

Interfacing Seven-Segment LED

• In this circuit, for example, to display digit 7 at the
LED, the requirements are as follows:
• It is a common-anode seven-segment LED, and
logic 0 is required to turn on a segment.
• To display digit 7, segments A, B, and C should
be turned on.
• The binary code should be:
– Data lines D7 D6 D5 D4 D3 D2 D1 D0
– Bits X 1 1 1 1 0 0 0
– Segments NC G F E D C B A
– Code = 78H

Chapter 5: Interfacing I/O Devices 24

12
 04-Oct-22

Interfacing Seven-Segment LED

• Output port address:
A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 1 0 1 = F5H

• Instructions to display digit 7 at the port:

MVI A , 78H
OUT F5H
HLT

Chapter 5: Interfacing I/O Devices 25

Interfacing Input devices

Data input from DIP switches:

• The binary value from the switches will have to be
carried by the data bus.
• However, the data bus is a shared bus.
• So, the switches must be connected to the data
bus using Tri-state buffers.
• Similar to the latch, the buffers must be enabled
only on I/O Read operation from this I/O port.

Chapter 5: Interfacing I/O Devices 26

13
 04-Oct-22

Interfacing DIP Switches

Chapter 5: Interfacing I/O Devices 27

Interfacing DIP Switches

• Input port address: (Multiple port addresses)
A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 x x 1 0 0
0 0 = 84H
0 1 = 8CH
1 0 = 94H
1 1 = 9CH

• To read input port:

IN 84H

Chapter 5: Interfacing I/O Devices 28

14
 04-Oct-22

Interfacing a Memory-Mapped I/O device

• Instead of using 8-bit address, the full 16-bits of the
address bus must be used.
• Instead of using IOR and IOW, use MEMR and MEMW.

• For example, to write data to output port with address

8000H, we can use: STA 8000H
Address Code instruction
2050 32H STA 8000H
2051 00H
2052 80H
• Following is the timing for execution for this instruction.

Chapter 5: Interfacing I/O Devices 29

Timing for Execution of the STA 8000H

Chapter 5: Interfacing I/O Devices 30

15
 04-Oct-22

Application: Safety-Control System Using

Memory-Mapped I/O Techniques

Chapter 5: Interfacing I/O Devices 31

Application: Program

• A program to operate devices according to switch

positions :

READ: LDA FFF9H ; read switches

STA FFF8H ; send to output port
JMP READ ; read again

• What is the problem with this program???

Chapter 5: Interfacing I/O Devices 32

16
 04-Oct-22

• The last program should be modified as:

READ: LDA FFF9H ; read switches

CMA ; complement switch readings
STA FFF8H ; send to output port
JMP READ ; read again

Chapter 5: Interfacing I/O Devices 33

17