ECEN620: Network Theory

Broadband Circuit Design

Fall 2022

Lecture 3: Phase-Locked Loop Systems

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• HW1 due Sept 22, 11:59PM
• Turn in via Canvas

• HW2 due Oct 6

• Requires transistor-level design
• For 90nm CMOS device models, see
https://people.engr.tamu.edu/spalermo/ecen689/cadence_90nm_2021.pdf
• Can use other technology models if they are a
90nm or more advanced CMOS node

2
Reading/References
• Chapter 2, 3, 5, & 12 of Phaselock Techniques, F. Gardner, John Wiley &
Sons, 2005.
• https://onlinelibrary.wiley.com/doi/book/10.1002/0471732699

• Charge-Pump PLL Design Procedure Paper (OSU)

• Chapter 1-3.4 of “Low-Power Low-Jitter On-Chip Clock Generation,” M.

Mansuri, Ph.D. thesis, UCLA, 2003.
• Posted on website

• Other references
• M. Perrott, High Speed Communication Circuits and Systems Course, MIT
Open Courseware
• Chapter 2 of Phase-Locked Loops, 3rd Ed., R. Best, McGraw-Hill, 1997.
• Chapter 4 of Phase-Locked Loops for Wireless Communications, D. Stephens,
Kluwer, 2002.

3
Agenda
• PLL Overview
• PLL Linear Model
• PLL Stability
• Analog Charge Pump PLL Design Procedure
• PLL Noise Transfer Functions
• PLL Transient Behavior
• PLL Time Domain Modeling
4
PLL Block Diagram
PFD
Fin D UP ICP Fout = N*Fin
Q
in(t) R
Vctrl
VCO out(t)
fb(t) R DN
Q R C2
D
ICP
C1

Divider

1/N

• A phase-locked loop (PLL) is a negative feedback

system where an oscillator-generated signal is
phase AND frequency locked to a reference signal
5
PLL Applications
• PLLs applications
• Frequency synthesis
• Multiplying a 100MHz reference clock to 10GHz
• Skew cancellation
• Phase aligning an internal clock to an I/O clock
• Clock recovery
• Extract from incoming data stream the clock frequency and
optimum phase of high-speed sampling clocks
• Modulation/De-modulation
• Wireless systems
• Spread-spectrum clocking

6
Embedded Clock (CDR) I/O Circuits
• TX PLL

• TX Clock Distribution

• CDR
• Per-channel PLL-based
• Dual-loop w/ Global PLL &
• Local DLL/PI
• Local Phase-Rotator PLLs
• Global PLL requires RX
clock distribution to
individual channels

7
Xilinx 0.5-32Gb/s Transceiver Clocking
Channels 1-4
Frac-N LC PLL1, 2 Technology CMOS 16nm FinFET
Power Supply (Vavcc, Vavtt, Vaux) 0.9 V, 1. 2V, 1.8 V
∑ Transmitter Frequency range 500 Mb/s – 32.75 Gb/s
DCC Transceiver Quad area 2.625 mm × 2.218 mm
VCOLB LC PLL range 8-16.375 GHz
Receiver Ring PLL range 2-6.25 GHz
VCOHB
TX PRBS7 jitter at 32.75Gb/s TJ: 5.39 ps, RJ: 190 fs
PI (D,X,S) 32.75Gb/s RX JTOL @ 30MHz 0.45 UI
PPF 2 IQ CAL @ 100MHz 0.6 UI
Channel loss at 32.75Gb/s 30 dB
DCC
Measured BER at 32.75Gb/s < 10-15
Ring PLL Power at 32.75Gb/s with DFE 577mW/ch (17.6pJ/b)

I/Q1, I/Q2
Active Inductor based Clock Distribution
[Upadhyaya VLSI 2016]

• LC-PLL with 2 LC-VCOs used to cover high data rates

(8-32Gb/s)
• Ring-PLL used for lower data rates
• CML clock distribution with active inductive loads used
for low jitter
8
Agenda
• PLL Overview
• PLL Linear Model
• PLL Stability
• Analog Charge Pump PLL Design Procedure
• PLL Noise Transfer Functions
• PLL Transient Behavior
• PLL Time Domain Modeling
9
Charge Pump PLL
PFD
Fin D UP ICP Fout = N*Fin
Q
in(t) R
Vctrl
VCO out(t)
fb(t) R DN
Q R C2
D
ICP
C1

Divider

1/N

• Charge pump PLL is a common implementation

• Type-2 (2 integrators) allows for ideally zero phase error between
the input and feedback phase
• Requires a stabilizing zero that is realized with the filter resistor
• A secondary capacitor C2 is often added for additional filtering to
reduce reference spurs
• Modeled as a third-order system
10
Linear PLL Model
Phase Detector Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
N
Divider

• Phase is the key variable of interest

• Output phase response to a stimulus injected at a given point in the loop
• Phase error response is also informative
• Linear “small-signal” analysis is useful for understand PLL dynamics if
• PLL is locked (or near lock)
• Input phase deviation amplitude is small enough to maintain operation in
lock range
11
Understanding PLL Frequency Response
Input phase response VCO output phase response
out out
in vco

f f
• Frequency domain analysis can tell us how well the PLL
tracks the input phase as it changes at a certain frequency

• PLL transfer function is different depending on which point

in the loop the output is responding to
12
Phase Detector
Phase Detector IN
Loop Filter
FB
e ve vctrl
in  KPD F(s) 
avg 𝑣 𝑡 𝐾 Δ𝜙
fb
avg{ve(t)}
• Detects phase difference between feedback clock
and reference clock
• The loop filter will filter the phase detector output, KPD
thus to characterize phase detector gain, extract

average output voltage
• The KPD factor can change depending on the
specific phase detector circuit
K PD units are V/rad when used with a dimension - less filter

K PD units are rad -1 (averaged) or A/rad when combined with the charge - pump

when used with a impedance filter 13

Dimension-Less Loop Filter
Example: Passive Lag-Lead Loop Filter
[Allen]

1  s 2
F s  
1  s 1   2 

 1  R1C  2  R2C

• Lowpass filter extracts average of phase

detector signal
• No units for the dimension-less loop filter 14
 Averaged PFD Transfer Characteristic
UP=1 & DN=-1 avg{ve(t)}
PFD 1
D
Q UP
in R
-4 -2
in-fb
1 2 4
fb R
Q DN
D 2
-1

• Constant slope and polarity asymmetry about zero phase

allows for wide frequency range operation
• The averaged PFD gain is 1/(2) with units of rad-1

15
Charge Pump
• Converts PFD output
ICP
signals to charge
UP Charging
Vctrl
DN Discharging R C2 • Charge is proportional
ICP to PFD pulse widths
C1
F(s)

Un - Averaged Charge - Pump Gain  I CP Amps

I CP  Amps 
Averaged Charge - Pump Gain   
2  rad 
I  Amps 
Total PFD & Charge - Pump Gain  CP  
2  rad 
This gain can vary if a different phase detector is used
16
Loop Filter
w/o C2
ICP  1 
R s  
UP Charging RC
Vctrl F s    1

s
DN Discharging R C2 w/ C2
ICP  1  1 
C1   s  
C RC1 
F(s) F s    2 
 C  C2 
s s  1 
 RC1C2 

• Lowpass filter extracts average of phase

detector error pulses
• The units of the filter are ohms
17
Voltage-Controlled Oscillator
out

0 KVCO
vctrl(t) VCO out(t)

Vctrl
Vctrl0
𝜔 𝑡 𝜔 Δ𝜔 𝑡 𝜔 𝐾 𝑣 𝑡

• Time-domain phase relationship

Laplace Domain Model
𝜙 𝑡 Δ𝜔 𝑡 𝑑𝑡 𝐾 𝑣 𝑡 𝑑𝑡

rad
KVCO units are KVCO
sV vctrl(t) out(t)
2 1MHz  rad s
 2  10 6
V sV
18
Loop Divider

out(t) 1 fb(t)
N

out(t)
fb(t)
N=8
• Time-domain model • The loop divider is
1 dimension-less in the PLL
 fb t   out t 
N linear model
1 1
 fb t    out t dt  out t 
N N
19
Phase & Frequency Relationships
Angular Frequency is the first derivative (rate of change vs time) of phase

d  t 
  t 
dt
t

 t      d
o

Consider a sinusoid u1 t  with angular frequency 1 t  and phase 1 t 

u1 t   sin 1 t t  1 t 
[Best]
• Phase Step
1 t   u t 
u1 t   sin 1 t    u t 

No change in frequency


20
Phase & Frequency Relationships
• Frequency Step 1 t   0  
u1 t   sin 0t  t   sin 0t  1 t 

where 1 t   t

A frequency step produces a ramp in phase

[Best]

1 t   t

21
 Phase & Frequency Relationships

1 t   0    t
• Frequency Ramp
  t
    2 


 
u1 t   sin    0     d   sin 0t  t  sin 0t  1 t 
0     2 
 

 2
where 1 t   t
2
[Best] A frequency ramp produces a quadratic change in phase


0 0    t


 2
1 t   t
2
22
Open-Loop PLL Transfer Function
Phase Detector
Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
N
Divider

Forward Path Gain: 𝐺 𝑠

Open-Loop Response:

• Open-loop response generally decreases with frequency

23
 Closed-Loop PLL Transfer Function
Phase Detector Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
N
Divider
Forward Path Gain  G s 

 out s  G s  K PD KVCO F s 
Loop Gain
K PD KVCO F s  G s  H s    
l1  
sN

N  ref s  1  G  s  s
K PD KVCO F s 
Forward Path Determinant 1  1  0  1 N N
 G s   G s 
System Determinant   1   
 N 
  0 1
N
• Low-pass response whose
overall order is set by F(s) 24
 PLL Error Transfer Function
Phase Detector Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
N
Divider
Forward Path Gain  1
 s  1 s
Loop Gain E s   e  
 ref s  1  G s  s  K PD KVCO F s 
K PD KVCO F s  G s 
l1  
sN

N
N N
Forward Path Determinant 1  1  0  1 • Ideally, we want this to be zero
 G s   G s  • Phase error generally increases with
System Determinant  1     0 1
 N  N frequency due to this high-pass response
25
PLL Order and Type
• The PLL order refers to the number of poles in the
closed-loop transfer function
• This is typically one greater than the number of loop
filter poles

• The PLL type refers to the number of integrators

within the loop
• A PLL is always at lease Type 1 due to the VCO
integrator

• Note, the order can never be less than the type

26
 First-Order PLL
Phase Detector
Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s
F s   K1
fb
K PD KVCO K1 NK DC
1 Forward Path Gain : G s   
N s s
Divider sG s  K PD KVCO K1
DC Loop Gain Magnitude : K DC  lim 
s 0 N N
• Simple first-order low-pass K PD KVCO K1 N3dB NK DC
Transfer Function : H s    
transfer function s  PD VCO 1 s  3dB s  K DC
K K K
N
• Closed-loop bandwidth is K PD KVCO K1
equal to the DC loop gain Closed - Loop Bandwidth :  3 dB   K DC
N
magnitude s s s
Error Function : E s    
s  PD VCO 1 s  3dB s  K DC
• Note, the “DC Loop Gain Magnitude” K K K
is not simply the PLL open-loop gain N
evaluated at s=0. It is
sG s 
K  lim DC .
s 0 N

• This expression cancels the VCO DC pole and allows a comparison between PLLs of
different orders and types. It is useful to predict the steady-state phase error. See
Gardner 2.2.3 and 5.1.1. 27
First-Order PLL Tracking Response
• The PLL’s tracking behavior, or how the phase error responds to an input
phase change, varies with the PLL type
• Phase Step Response [Best]
1 t   u t 
u1 t   sin 1 t    u t 

No change in frequency
• The final value theorem can be used to find the steady-state phase error
   s
lim   sE  s   lim 0
s 0
 s  s  0 s  K DC
• All PLLs should have no steady-state phase error with a phase step error
• Note, this assumes that the frequency of operation is the same as the VCO
center frequency (Vctrl=0). Working at a frequency other than the VCO
center frequency is considered having a frequency offset (step).

28
 First-Order PLL Tracking Response
[Best]
• Frequency Offset (Step)
1 t   0  
u1 t   sin 0t  t   sin 0t  1 t 

where 1 t   t

A frequency step produces a ramp in phase

• The final value theorem can be used to find the steady-

state phase error
    
lim 2 sE s   lim 
s 0
 s 
s 0 s  K DC K DC

• With a frequency offset (step), a first-order PLL will lock

with a steady-state phase error that is inversely
proportional to the loop gain
29
First-Order PLL Issues
• The DC loop gain directly sets the PLL bandwidth
• No degrees of freedom

• In order to have low phase error, a large loop gain is

necessary, which implies a wide bandwidth
• This may not be desired in applications where we would like to filter
input reference clock phase noise

• First-order PLLs offer no filtering of the phase detector

output
• Without this filtering, the PD may not be well approximated by a
simple KPD factor
• Multiplier PDs have a “second-harmonic” term
• Digital PDs output square pulses that need to be filtered

30
Second-Order Type-1 PLL
w/ Passive Lag-Lead Filter
Phase Detector
Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
N
Divider

Passive Lag-Lead Loop Filter

[Allen]

1  s 2
F s  
1  s 1   2 

 1  R1C  2  R2C
31
 Second-Order Type-1 PLL
w/ Passive Lag-Lead Filter
   1
1  s 2 NK DC  2  s  
F s   K K 1  s 2     1   2   2 
1  s 1   2  Forward Path Gain : G s   PD VCO
s1  s 1   2   1 
s s  
    
 1  R1C  2  R2C 1 2
sG s  K PD KVCO
DC Loop Gain Magnitude : K DC  lim 
s 0 N N
K PD KVCO 2  1  N n 
 s   n  2   s  n2
1   2   2   K PD KVCO 
Transfer Function : H s   N
2  1  K PD KVCO 2 N  K PD KVCO s 2  2 n s  n2
s    s 
  1   2  N  1   2 
   1
K DC  2  s  
N   1   2   2 
 1  K DC 2  K
s 2    s  DC
 1   2  1   2
K PD KVCO
Natural Frequency : n 
N  1   2 
n  N 
Damping Factor :    2   1
2  K PD KVCO  Note :  

2Q
 Nn2 
s s
 K PD KVCO 

Error Function : E s   2
s  2 n s  n2 32
Second-Order Type-1 PLL Tracking Response
• Phase Step Response
 Nn2 
s s  
    K PD KVCO 
lim   sE  s   lim 0
s 0
 s  s  0 s  2 n s  n
2 2

Again, phase error should be zero with a phase step

• Frequency Offset (Step)

 Nn2 
  s  
   K PD KVCO  
lim 2 sE s   lim 2  
s 0
 s  s  0 s  2 n s  n 2
K DC

• A second-order type-1 PLL will still lock with a phase error if

there is a frequency offset!

33
Second-Order Type-1 PLL Properties
• While the second-order type-1 PLL will still lock
with a phase error with a frequency offset, it is
much more useful than a first-order PLL
• There are sufficient design parameters (degrees of
freedom) to independently set n, , and KDC
• The loop filter conditions the phase detector
output for proper VCO control
• Loop stability needs to be considered for the
second-order system

34
Second-Order Type-2 PLL
w/ Passive Series-RC Lag-Lead Filter
Phase Detector
Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
N

Passive Series-RC Loop Filter Divider

 1 
R s  
F s    
RC
s

• Note, this type of loop filter is typically used with a charge-

pump driving it. Thus, the filter transfer function is equal
to the impedance.
35
 Second-Order Type-2 PLL
w/ Passive Series-RC Lag-Lead Filter
 1 
R s  
F s    
RC 
K PD KVCO R s 
1 

s  RC 
Forward Path Gain : G s  
s2
sG s 
DC Loop Gain Magnitude : K DC  lim 
s 0 N

 1   n 
K PD KVCO R s   N 2  s  2 
n
 RC   
Transfer Function : H s    2 2
K K R K K
s 2   PD VCO  s  PD VCO s  2 n s  n
 N  NC
K PD KVCO
Natural Frequency : n 
NC
n
Damping Factor :   RC
2
s2
Error Function : E s  
s 2  2 n s  n2

36
Second-Order Type-2 PLL Tracking Response
• Phase Step Response
    s 2
lim sE s   lim 0
s 0
 s  s  0 s  2 n s  n
2 2

Again, phase error should be zero with a phase step

• Frequency Offset (Step)

    s
lim 2 sE s   lim 2 0
s 0
 s  s  0 s  2 n s  n
2

• A second-order type-2 PLL will lock with no phase error with

a frequency offset!

37
Second-Order Type-2 PLL Properties
• A big advantage of the type-2 PLL is that it has
zero phase error even with a frequency offset
• This is why type-2 PLLs are very popular

• A type-2 PLL requires a zero in the loop filter for

stability.
• Note, this is not required in a type-1 PLL

• This zero can cause extra peaking in the

frequency response
• Important to minimize this in some applications, such
as cascaded CDR systems

38
Agenda
• PLL Overview
• PLL Linear Model
• PLL Stability
• Analog Charge Pump PLL Design Procedure
• PLL Noise Transfer Functions
• PLL Transient Behavior
• PLL Time Domain Modeling
39
Feedback Configuration
[Karsilayan]

Here f = feedback factor

𝑉 𝑎
𝑎 𝑠 𝑠 𝑠
𝑉 1
𝑝
𝑎
𝑉 𝑎 𝑠 1 𝑎 𝑓
𝐴 𝑠
ACL(s) 𝑠 𝑠
𝑉 1 𝑎 𝑠 𝑓 1
1 𝑎 𝑓 𝑝

1
If a0 is large : ACL 0    p  a0 p1 f
f
40
Note: a(s) can have higher-order poles
[Karsilayan]

41
[Karsilayan]

42
[Karsilayan]

43
 First-Order PLL
Phase Detector
Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
F s   K1
N
K PD KVCO K1 NK DC
Divider Forward Path Gain : G s   
s s
sG s  K PD KVCO K1
DC Loop Gain Magnitude : K DC  lim 
s 0 N N
K PD KVCO K1 N3dB NK DC
Transfer Function : H s    
s  PD VCO 1 s  3dB s  K DC
K K K
N
K K K
Closed - Loop Bandwidth : 3dB  PD VCO 1  K DC
N
s s s
Error Function : E s    
s  PD VCO 1 s  3dB s  K DC
K K K
N

44
First-Order PLL Stability
G  j 
• Open-loop Bode 20 log10
N
(dB)

plots are useful for G s  

K PD KVCO K1 NK DC
s

s
checking stability via
the phase margin

• A first-order PLL is
inherently stable and
always has 90
phase margin

45
 Second-Order Type-1 PLL
w/ Passive Lag-Lead Filter
   1
1  s 2 NK DC  2  s  
F s   K K
Forward Path Gain : G s   PD VCO
1  s 2     1   2   2 
1  s 1   2  s1  s 1   2   1 
s s  
  1   2
 1  R1C  2  R2C sG s  K PD KVCO
DC Loop Gain Magnitude : K DC  lim 
s 0 N N
K PD KVCO 2  1  N n 
 s   n  2   s  n2
1   2   2   K PD KVCO 
Transfer Function : H s   N
 1  K PD KVCO 2 N  K PD KVCO s 2  2 n s  n2
s 2    s 
  1   2  N  1   2 
   1
K DC  2  s  
N   1   2   2 
 1  K DC 2  K
s 2    s  DC
 1   2  1   2
K PD KVCO
Natural Frequency : n 
N  1   2 
n  N 
Damping Factor :    2  
2  K PD KVCO 
 N  2 
s s  n 
 K K 

Error Function : E s   2
PD VCO 
s  2 n s  n2 46
 Second-Order Type-1 PLL
w/ Lag-Lead Filter Stability
• Assuming a decade spacing between filter pole and zero
G  j     1
20 log10 (dB) NK DC  2  s  
N
G s     1   2   2 
 1 
s s  
 1   2 

Normalizing
KDC for =1
Norm. KDC Zeta PM
0.1 0.38 42.5
1 1 77
10 3.09 88.7

• A larger KDC provide a more stable system

47
Second-Order Type-1 PLL w/ Lag-Lead Filter
Output Response w/ Phase Step

Norm. KDC Zeta PM
0.1 0.38 42.5
1 1 77
10 3.09 88.7

• Note, time axis is scaled by sqrt(KDC) in order to view the

phase step plots on one graph 48
Root Locus
• A Root-Locus Plot is a plot of the closed-loop poles in the
complex s-plane as the loop gain changes from zero to
very large
• Useful in visualizing system stability and sensitivity to
variations in loop gain
• For stability, all poles should lie within the left-half plane,
i.e no poles should be in the right-half plane
• A good design ensures that the poles have sufficient
margin from the imaginary axis for proper stability,
damping, and acceptable gain peaking

49
Second-Order Type-1 PLL
w/ Passive Lag-Lead Filter Root Locus
   1    1
K DC  2  s   K DC  2  s  
G s    1   2   2    1   2   2 
Open - Loop :  Closed - Loop : H s   N
N  1   1  K DC 2  K
s s   s 2    s  DC
 1   2   1   2  1   2
2=1, 1=9
• Initial pole values with
zero loop gain are the
open-loop poles
1
p1  0 p2    0.1
1   2

• Final pole values with

infinite loop gain are the
open-loop zeros
1
p1    1 p2  
2

50
Second-Order Type-1 PLL
w/ Passive Lag-Lead Filter Root Locus
   1    1
K DC  2  s   K DC  2  s  
G s    1   2   2    1   2   2 
Open - Loop :  Closed - Loop : H s   N
N  1   1  K DC 2  K
s s   s 2    s  DC
 1   2   1   2  1   2
2=1, 1=9

0.1*K1  =0.38
K1 for =1

For ≤1

10*K1  =3.09

51
 Second-Order Type-1 PLL w/ Passive Lag-Lead
Filter Closed-Loop Response
   1    1
K DC  2  s   K DC  2  s  
G s    1   2   2    1   2   2 
Open - Loop :  Closed - Loop : H s   N
N  1   1  K DC 2  K
s s   s 2    s  DC
 1   2   1   2  1   2
20*log10|H(j)|
Normalized Phase Step Response

Norm. KDC Zeta PM
0.1 0.38 42.5
1 1 77
10 3.09 88.7

/n t*sqrt(KDC)
• A larger KDC provide a more stable system and wider loop bandwidth
52
 Second-Order Type-2 PLL
w/ Passive Series-RC Lag-Lead Filter
 1 
R s   K PD KVCO R
Define a loop gain factor K 
F s    
RC
N
s
 1   1 
K PD KVCO R s   NK  s  
Forward Path Gain : G s    RC 
  RC 
s2 s2

 1    
N 2 n  s  n  NK  s 
1 
K PD KVCO R s   
 RC   2   RC 
Transfer Function : H s    2
K K R K K s  2 n s  n s 2  Ks  K
2
s 2   PD VCO  s  PD VCO
 N  NC RC

K PD KVCO K
Natural Frequency : n  
NC RC
n 1
Damping Factor :   RC  KRC
2 2
s2
Error Function : E s  
s 2  2 n s  n2

53
Second-Order Type-2 PLL w/ Passive Series-RC
Lag-Lead Filter Root Locus
 1   1 
K s   NK  s  
G s   RC   RC 
Open - Loop :  Closed - Loop : H s  
N s2 K
s 2  Ks 
RC
R=1, C=1
• Initial pole values with
zero loop gain are the
open-loop poles
p1  0 p2  0

• Final pole values with

infinite loop gain are the
open-loop zeros
1
p1    1 p2  
RC

54
Second-Order Type-2 PLL w/ Passive Series-RC
Lag-Lead Filter Root Locus
 1   1 
K s   NK  s  
G s   RC   RC 
Open - Loop :  Closed - Loop : H s  
N s2 K
s 2  Ks 
RC
R=1, C=1

0.1*K1  =0.38
K1 for =1

10*K1  =3.09

55
 Second-Order Type-2 PLL
w/ Passive Series-RC Lag-Lead Filter Stability

G  j 
20 log10 (dB)
 1 
N
NK  s  
G s    RC 
s2
Normalizing K
for =1
Norm. KDC Zeta PM
0.1 0.38 35
1 1 76.2
10 3.09 88.6

• A larger K provide a more stable system

56
 Second-Order Type-2 PLL w/ Passive Series-RC
Lag-Lead Filter Closed-Loop Response
 1   1 
K s   NK  s  
G s   RC   RC 
Open - Loop :  Closed - Loop : H s  
N s2 K
s 2  Ks 
RC
20*log10|H(j)|
Normalized Phase Step Response

Norm. KDC Zeta PM
0.1 0.38 35
1 1 76.2
10 3.09 88.6

/n t*sqrt(KDC)
• A larger KDC provide a more stable system and wider loop bandwidth
57
Typical Charge-Pump PLL Loop Filter
VDD
w/o C2
 1 
I R s  
RC1 
Charging VCO Control F s   
Voltage s
w/ C2
C1 C2
Discharging  1  1 
  s  
C RC1 
I R F s    2 
 C  C2 
F(s) s s  1


RC1C2 
VSS

• A secondary capacitor C2 is often added for

additional filtering to reduce reference spurs
• This introduces an extra pole and potential stability
concerns
58
 Third-Order Type-2 PLL w/ Passive Series-RC
Lag-Lead Filter & Additional Pole
 1  1  Define a loop gain factor K 
K PD KVCO R
  s   N
C RC
F s    2  1
 1  1   1 
 C1  C2  K PD KVCO   s   NK  s  
s s   Forward Path Gain : G s  
C
 2  RC 1
  RC1

 RC C
1 2   C  C2   C  C2 
s 2  s  1  RC2 s 2  s  1 
 RC C
1 2   RC C
1 2 

 1  1   1 
K PD KVCO   s   NK  s  
C
 2  RC 1  RC 1
Transfer Function : H s   
 C  C2  2  K PD KVCO  K PD KVCO  C  C2  2 K
s 3   1  s    s  RC2 s 3   1  s  Ks 
 RC1C2   NC2  NRC1C2  C1  RC1

 C  C2   C  C2 
s 2  s  1  RC2 s 2  s  1 
 RC C
1 2   RC C
1 2 
Error Function : E s   
 C  C2  2  K PD KVCO  K PD KVCO  C  C2  2 K
s 3   1  s    s  RC2 s 3   1  s  Ks 
 RC1C2   NC2  NRC1C2  C1  RC1

If the third - pole is at a high frequency, can approximate as a second - order system with

K PD KVCO K
Natural Frequency : n  
NC1 RC1

n 1
Damping Factor :   RC1  KRC1
2 2
59
Third-Order Type-2 PLL w/ Passive Series-RC
Lag-Lead Filter & Additional Pole Root Locus
1 1
𝐺 𝑠 𝐾 𝑠 𝑁𝐾 𝑠
𝑅𝐶 𝑅𝐶
Open Loop: Closed Loop: 𝐻 𝑠
N 𝐶 𝐶 𝐶 𝐶 𝐾
𝑅𝐶 𝑠 𝑠 𝑅𝐶 𝑠 𝑠 𝐾𝑠
𝑅𝐶 𝐶 𝐶 𝑅𝐶

R=1, C1=1, C2=0.1

• Initial pole values with
zero loop gain are the
open-loop poles
C1  C2
p1  0 p2  0 p3    11
RC1C2

• Final pole values with

infinite loop gain
1
p1    1 p2,3  5  j
RC

60
Third-Order Type-2 PLL w/ Passive Series-RC
Lag-Lead Filter & Additional Pole Root Locus
1 1
𝐺 𝑠 𝐾 𝑠 𝑁𝐾 𝑠
𝑅𝐶 𝑅𝐶
Open Loop: Closed Loop: 𝐻 𝑠
N 𝐶 𝐶 𝐶 𝐶 𝐾
𝑅𝐶 𝑠 𝑠 𝑅𝐶 𝑠 𝑠 𝐾𝑠
𝑅𝐶 𝐶 𝐶 𝑅𝐶

R=1, C1=1, C2=0.1

0.1*K1  =0.38
K1 for =1

*A third-order system
doesn’t formally have a 
value. Here we are using
the same loop parameter
values as the second-
order type-2 PLL for a
given .

61
 Second-Order Type-2 PLL
w/ Passive Series-RC Lag-Lead Filter Stability

G  j 
20 log10 (dB)
 1 
N
NK  s  
G s    RC 
s2
Normalizing K
for =1
Norm. K Zeta PM
0.1 0.38 35
1 1 76.2
10 3.09 88.6

• A larger K provide a more stable system

62
 Third-Order Type-2 PLL w/ Passive Series-RC
Lag-Lead Filter & Additional Pole Stability

 1 
G  j  NK  s  
20 log10 (dB)
 RC1
N
G s  
 C  C2 
RC2 s 2  s  1 
 RC C
1 2 

Normalizing K
for =1
Norm. K Zeta* PM
0.1 0.38 30
1 1 55
10 3.09 27

*A third-order system
doesn’t formally have a 
value. Here we are using
the same loop parameter
values as the second-
order type-2 PLL for a
given .

• A larger K may not provide a more stable system

63
 Third-Order Type-2 PLL Closed-Loop Response
1 1
𝐺 𝑠 𝐾 𝑠 𝑁𝐾 𝑠
𝑅𝐶 𝑅𝐶
Open Loop: Closed Loop: 𝐻 𝑠
N 𝐶 𝐶 𝐶 𝐶 𝐾
𝑅𝐶 𝑠 𝑠 𝑅𝐶 𝑠 𝑠 𝐾𝑠
𝑅𝐶 𝐶 𝐶 𝑅𝐶

20*log10|H(j)|
Normalized Phase Step Response

Norm. K Zeta* PM
0.1 0.38 30
1 1 55
10 3.09 27

/n t*sqrt(KDC)
• If K is increased too high frequency peaking and transient ringing occurs!
64
Instability and the Nyquist Criterion
[Karsilayan]

1
For a PLL T s  is the forward gain G s  multiplied by the feedback factor
N
G s 
T s  
N
65
 G s 
For a PLL : T s  
N

Frequency Sweep of Loop Gain, T(s)

[Karsilayan]

66
Agenda
• PLL Overview
• PLL Linear Model
• PLL Stability
• Analog Charge Pump PLL Design Procedure
• PLL Noise Transfer Functions
• PLL Transient Behavior
• PLL Time Domain Modeling
67
Linear PLL Model
Phase Detector Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
N
Divider

𝐼
For Charge Pump PLL: 𝐾
2𝜋
1 1
𝑠
𝐶 𝑅𝐶
𝐹 𝑠
𝐶 𝐶
𝑠 𝑠
𝑅𝐶 𝐶
𝐾 𝐾 1
𝜙 𝑠 𝑠
𝐶 𝑅𝐶
𝐻 𝑠
𝜙 𝑠 𝐶 𝐶 𝐾 𝐾 𝐾 𝐾
𝑠 𝑠 𝑠
𝑅𝐶 𝐶 𝑁𝐶 𝑁𝑅𝐶 𝐶
68
14GHz PLL Closed-Loop Transfer Function
Parameter
Fref 156.25MHz
N 90
Fvco 14GHz
fu 2MHz
m 60°
f3dB 3.1MHz
Kvco 2π*1GHz/V
R 4k
C1 74pF
C2 5.8pF
Icp 310uA

𝐾 𝐾 1
𝜙 𝑠 𝑠
𝐶 𝑅𝐶
𝐻 𝑠
𝜙 𝑠 𝐶 𝐶 𝐾 𝐾 𝐾 𝐾
𝑠 𝑠 𝑠
𝑅𝐶 𝐶 𝑁𝐶 𝑁𝑅𝐶 𝐶
69
PLL Loop Gain
Phase Detector
Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
N
Divider

1
𝐾 𝐹 𝑠 𝐾 𝐾 𝐾 𝑠
𝑅 𝐶
𝐿𝐺 𝑠
𝑁𝑠 𝐶 𝐶
𝑁𝐶 𝑠 𝑠
𝑅 𝐶𝐶

1 𝐶 𝐶
𝜔 , 𝜔 𝜔 0, 𝜔
𝑅 𝐶 𝑅 𝐶𝐶

70
Loop Gain Response
𝐾 𝐾 𝑠 𝜔
𝐿𝐺 𝑠 𝜔 𝜔 0
|LG|(dB) 𝑁𝐶 𝑠 𝑠 𝜔
1
𝜔
𝑅 𝐶
𝐶 𝐶
z u p3 𝜔
0  𝑅 𝐶𝐶

LG
𝜔 𝜔
Φ tan tan
-135° m 𝜔 𝜔

-180°

71
Design Procedure for Max m
𝐾 𝐾 𝑠 𝜔 PLL Specs
𝐿𝐺 𝑠
|LG|(dB) 𝑁𝐶 𝑠 𝑠 𝜔 Parameter
Fref 156.25MHz
N 90
Fvco 14GHz
z u p3
0  fu 2MHz
m 60°

Kvco 2π*1GHz/V

LG R ??
C1 ??

-135° m C2 ??
Icp ??

-180°

• Design procedure maximizes phase margin for a given fu

and m specification [Hanumolu TCAS1 2004] 72
Design Procedure for Max m
1. Set loop filter capacitor ratio based on m
𝐶
𝐾 2 𝑡𝑎𝑛 Φ 𝑡𝑎𝑛 Φ 𝑡𝑎𝑛 Φ 1
𝐶
Φ 60° → 𝐾 12.9
2. Set loop filter values based on u & with R set for low noise
𝜔
𝜔
1 𝐾
1 𝐶
𝐶 , 𝐶
𝜔 𝑅 𝐾
𝜔 2𝜋 ∗ 2𝑀𝐻𝑧 → 𝜔 2𝜋 ∗ 536𝑘𝐻𝑧
Set 𝑅 4𝑘Ω → 𝐶 74𝑝𝐹 & 𝐶 5.8𝑝𝐹
3. Set Icp to achieve required loop gain

N𝐶 𝜔 𝜔 𝜔
𝐼
𝐾 𝜔 𝜔 𝜔 2𝜋 ∗ 7.45𝑀𝐻𝑧 → 𝐼 310𝜇𝐴
73
Simulated Responses
𝐾 𝐾 1
𝐾 𝐾 𝑠 𝜔 𝜙 𝑠 𝑠
𝐶 𝑅𝐶
𝐿𝐺 𝑠 𝐶 𝐶 𝐾 𝐾 𝐾 𝐾
𝑁𝐶 𝑠 𝑠 𝜔 𝜙 𝑠 𝑠 𝑠 𝑠
𝑅𝐶 𝐶 𝑁𝐶 𝑁𝑅𝐶 𝐶

• Design achieves fu=2MHz and m=60°

• Closed loop response has f3dB=3.1MHz
74
Agenda
• PLL Overview
• PLL Linear Model
• PLL Stability
• Analog Charge Pump PLL Design Procedure
• PLL Noise Transfer Functions
• PLL Transient Behavior
• PLL Time Domain Modeling
75
Common PLL Noise Sources
Phase Detector
Sin SiCP Loop Filter SvR VCO SVCO
e Vctrl KVCO
in   KPD  F(s)   out
s

fb
1
N
Divider

𝑆 𝑆 𝑁𝑇𝐹 𝑠

𝑆 𝑆 𝑁𝑇𝐹 𝑠

𝑆 𝑆 𝑁𝑇𝐹 𝑠

𝑆 𝑆 𝑁𝑇𝐹 𝑠

𝑆 𝑆 𝑆 𝑆 𝑆
76
Noise Transfer Functions
𝜙 𝑠 𝑁 𝐿𝐺 𝑠
𝑁𝑇𝐹 𝑠
𝜙 𝑠 1 𝐿𝐺 𝑠
𝑁
𝜙 𝑠 𝐿𝐺 𝑠
𝐾
𝑁𝑇𝐹 𝑠
𝑖 𝑠 1 𝐿𝐺 𝑠
𝐾
𝜙 𝑠 𝑠
𝑁𝑇𝐹 𝑠
𝑣 𝑠 1 𝐿𝐺 𝑠
𝜙 𝑠 1
𝑁𝑇𝐹 𝑠
𝜙 𝑠 1 𝐿𝐺 𝑠

• Input reference and charge pump noise is low-pass filtered

• Loop filter noise (VCO input noise) is band-pass filtered
• VCO output phase noise is high-pass filtered
77
PLL Phase Noise & Jitter [Turker ISSCC 2018]

• PLL time-domain jitter is obtained by • We can model an individual

integrating the output phase noise noise source’s contribution
2 2
𝜎, 𝑆 𝑓 𝑑𝑓 𝜎, 𝑆 𝑓 𝑁𝑇𝐹 𝑓 𝑑𝑓
𝜔 𝜔

𝜎, 𝜎,

RMS Jitter 𝜎 𝜎,
78
Wireline Transceiver Jitter Modeling

[Richmond SiLabs]

• Relative jitter (dynamic phase error) between the RX CDR-generated

sampling clock and input data sets the system timing margin
• This CDR high-pass response provides additional filtering
• Modeled as a 4MHz 1st-order response (IEEE 802.3 & OIF-CEI)
2
𝜎 , 𝑆 𝑓 𝑁𝑇𝐹 𝑓 𝐶𝐷𝑅 𝑓 𝑑𝑓
𝜔 79
Input Reference Noise
Phase Noise at 156.26MHz
Silicon Labs Ultra Low
Jitter Crystal Oscillator

• Reference jitter j,in = 226fsrms (10kHz – 10MHz)

80
Input Reference Noise
𝐾 𝐾 1
𝑠
𝐶 𝑅𝐶
𝑁𝑇𝐹 𝑠
𝐶 𝐶 𝐾 𝐾 𝐾 𝐾
𝑠 𝑠 𝑠
𝑅𝐶 𝐶 𝑁𝐶 𝑁𝑅𝐶 𝐶

• After PLL: j,in = 217fsrms (10kHz – 10MHz)

• Including CDR: j,in = 45fsrms (100Hz – 7GHz)
81
 Charge Pump Noise
Tref
MP Trst=40ps, Tref=6.4ns
VBP in,MP
IN
FB
UP
iCP UP
DN
DN
VBN in,MN
Trst
MN iCP

𝑇
𝑆 𝑆 𝑆
𝑇 , ,

• Charge pump noise current is injected into the loop filter

during the PFD reset time
• Trade-off between charge pump noise contribution and
deadzone robustness
• Transistor flicker noise can contribute significantly to PLL
in-band phase noise 82
Charge Pump Noise
𝐾 1
𝑠
𝐶 𝑅𝐶
𝑁𝑇𝐹 𝑠
𝐶 𝐶 𝐾 𝐾 𝐾 𝐾
𝑠 𝑠 𝑠
𝑅𝐶 𝐶 𝑁𝐶 𝑁𝑅𝐶 𝐶

• After PLL: j,CP = 205fsrms (10kHz – 10MHz)

• Including CDR: j,CP = 52fsrms (100Hz – 7GHz)
83
Loop Filter R Noise

ICP
UP w/ 4k Resistor
Charging
Vctrl
𝑆 4𝑘𝑇𝑅 162𝑑 𝐵 ⁄𝐻 𝑧
DN Discharging R C2
ICP
C1
F(s)

• Trade-off between resistor noise, loop filter

capacitor size, and charge pump noise
• Smaller resistor results in larger capacitors (higher area)
and larger charge pump current (higher SiCP)
84
Loop Filter R Noise
𝐶 𝐶
𝐾 𝑠 𝑠
𝑅𝐶 𝐶
𝑁𝑇𝐹 𝑠
𝐶 𝐶 𝐾 𝐾 𝐾 𝐾
𝑠 𝑠 𝑠
𝑅𝐶 𝐶 𝑁𝐶 𝑁𝑅𝐶 𝐶

• After PLL: j,R = 128fsrms (10kHz – 10MHz)

• Including CDR: j,R = 81fsrms (100Hz – 7GHz)
85
VCO Noise
LC-Oscillator
w/ Differential Tank & Noise Sources
C1

Rp

in,Rp

L1
Vout

in,M1 in,M2
M1 M2

Vbias in,M3
M3

• LC-VCO phase noise sources

• Finite tank quality factor
• Cross-coupled pair
• Tail current source 86
VCO Noise
𝐶 𝐶
𝑠 𝑠
𝑅𝐶 𝐶
𝑁𝑇𝐹 𝑠
𝐶 𝐶 𝐾 𝐾 𝐾 𝐾
𝑠 𝑠 𝑠
𝑅𝐶 𝐶 𝑁𝐶 𝑁𝑅𝐶 𝐶

• After PLL: j,VCO = 257fsrms (10kHz – 10MHz)

• Including CDR: j,R = 125fsrms (100Hz – 7GHz)
87
Total Noise
PLL Output
VCO Ref Clk
28%
38%

Charge Pump
25%
Loop Filter
9%

Jitter
Variance Ref Clk
7%
Charge Pump
10%

VCO Loop Filter

58% 25%

After CDR

• After PLL: j,Total = 414fsrms (10kHz – 10MHz)

• Reference clock and charge pump noise dominates at low frequency
• VCO dominates near loop bandwidth and higher
• Including CDR: j,Total = 164fsrms (100Hz – 7GHz)
• Now VCO noise clearly dominates total
• Loop resistor noise is a larger percentage 88
PLL Noise Transfer Function Take-Away Points

• The way a PLL shapes phase noise depends

on where the noise is introduced in the loop
• Optimizing the loop bandwidth for one noise
source may enhance other noise sources
• Generally, the PLL low-pass shapes input
phase noise, band-pass shapes VCO input
voltage noise, and high-pass shapes
VCO/clock buffer output phase noise

89
Agenda
• PLL Overview
• PLL Linear Model
• PLL Stability
• Analog Charge Pump PLL Design Procedure
• PLL Noise Transfer Functions
• PLL Transient Behavior
• PLL Time Domain Modeling
90
Linear PLL Model
Phase Detector Loop Filter VCO

e Vctrl KVCO
in  KPD F(s) out
s

fb
1
N
Divider
• If the phase input 𝜙 𝑠 1 𝑠
amplitude is small, then 𝐸 𝑠
𝜙 𝑠 𝐺 𝑠 𝐾 𝐾 𝐹 𝑠
1 𝑠
the linear model can be 𝑁 𝑁

used to predict the

• Ideally, we want this to be zero
transient response
• Phase error generally increases with
frequency due to this high-pass response

91
First-Order PLL Tracking Response
s s K K K
F s   K1 , E s    , K DC  3dB  PD VCO 1
s  PD VCO 1 s  3dB
K K K N
N
• Phase Step Response
   s 2
Using the Final Value Theorem : lim sE s   lim 0
s 0
 s  s  0 s s  K DC 

Phase error should be zero with a phase step

   s 
   e  K DC t
1
Transient Response : L 
 s  s  K DC 
Transient Response is an exponentialy decaying step

92
First-Order PLL Tracking Response
s s K K K
F s   K1 , E s    , K DC  3dB  PD VCO 1
s  PD VCO 1 s  3dB
K K K N
N
• Frequency Offset (Step) Response

    s 2 
Using the Final Value Theorem : lim 2 sE s   lim 2 
s  0 s s  K
 s  DC  K DC
s 0

The phase error is inversely proporitio nal to the loop gain with a frequency offset

   s   
Transient Response : L  2 
1
  1  e K DC t 
 s  s  K DC  K DC
Transient Response is an exponentialy rising step

93
First-Order PLL Tracking Response
s s K K K
F s   K1 , E s    , K DC  3dB  PD VCO 1
s  PD VCO 1 s  3dB
K K K N
N
• Frequency Ramp Response
Assume that the input frequency is changing linearly with time at a rate of  rad/sec 2 

t 2
ref t  
2
 s 2
Using the Final Value Theorem : lim 3 sE s   lim 3 
s  0 s s  K
  DC 
s 0 s

The phase error will grow to infinity if K DC is finite

   s  
Transient Response : L  3 
1
  2 K DC t  e  K DC t  1
 s  s  K DC  K DC
94
Second-Order Type-1 PLL Tracking Response
 Nn2   1 
s s   s s  
F s  
1  s 2
, E s   2
K PD KVCO 
  1   2  K K
, K DC  PD VCO
1  s 1   2  s  2n s  n2  1  K DC 2  K N
s 2    s  DC
 1   2  1   2
• Phase Step Response
 1 
 s 2  s  
Using the Final Value Theorem : lim
  
 sE s   lim  1   2  0
 s 0 
s 0
 s   1  K DC 2  K 
s s 2    s  DC 
  1   2  1   2 
Phase error should be zero with a phase step

  1  
 s  s 
     
1     2  
Transient Response : L  
1

  s   1  K   K
s  
2 DC 2
 s  DC 
   1   2   1   2 
Try to compute this yourself
95
Second-Order Type-1 PLL Tracking Response
 Nn2   1 
s s   s s  
F s  
1  s 2
, E s   2
K PD KVCO 
  1   2  K K
, K DC  PD VCO
1  s 1   2  s  2n s  n2  1  K DC 2  K N
s 2    s  DC
 1   2  1   2
• Frequency Offset (Step) Response
 1 
s 2  s  
  
Using the Final Value Theorem : lim 2 sE s   lim  1   2  

s 0
 s  s 0   1  K DC 2  K  K DC
s 2  s 2    s  DC 
  1   2  1   2 
The phase error is inversely proporitio nal to the loop gain with a frequency offset

   1  
  s s   
        2  
Transient Response : L1  2  1

  s   1  K   K
 s  
2 DC 2
 s  DC 
    1   2   1   2 
Try to compute this yourself
96
Second-Order Type-1 PLL Tracking Response
 Nn2   1 
s s   s s  
F s  
1  s 2
, E s   2
K PD KVCO 
  1   2  K K
, K DC  PD VCO
1  s 1   2  s  2n s  n2  1  K DC 2  K N
s 2    s  DC
 1   2  1   2
• Frequency Ramp Response
 1 
s 2  s  

Using the Final Value Theorem : lim 3 sE s   lim  1   2  
 
s 0 s s 0   1  K DC 2  K 
s 3  s 2    s  DC 
  1   2  1   2 
The phase error will grow to infinity if K DC is finite

   1  
  s 
 s  
 
       2  
Transient Response : L1  3  1

  s   1  K   K
 s 2   DC 2
 s  DC 
    1   2   1   2 
Try to compute this yourself
97
Second-Order Type-2 PLL Tracking Response
 1 
R s   2 2
s s K PD KVCO R
F s     , E s  
RC
 , K 
s s 2  2 n s  n2 s 2  Ks  K N
RC
• Phase Step Response

    s 3
Using the Final Value Theorem : lim sE s   lim
s 0 
0
s 0
 s  K 
s s  Ks 
2

 RC 
Phase error should be zero with a phase step

  
 
1   
2
s
Transient Response : L   K

 s  s 2  Ks  
  RC 

98
Second-Order Type-2 PLL
Phase Step Response
  
 
1   
2
s
Transient Response : L   K

 s  s  Ks 
2 
  RC 

n 1
  RC  KRC
2 2

99
Second-Order Type-2 PLL Tracking Response
 1 
R s   2 2
s s K PD KVCO R
F s     , E s  
RC
 , K 
s s 2  2 n s  n2 s 2  Ks  K N
RC

• Frequency Offset (Step) Response

    s 3
Using the Final Value Theorem : lim 2 sE s   lim 0
s 0
 s  s 0  K 
s  s  Ks 
2 2

 RC 
The phase error goes to zero with a Type - 2 PLL

  
 
1   
2
s
Transient Response : L  2  
K
 s  s 2  Ks  
  RC 

100
Second-Order Type-2 PLL
Frequency Step Response
  
 
1   
2
s
Transient Response : L  2  
K
 s  s  Ks 
2 
  RC 

n 1
  RC  KRC
2 2

101
Second-Order Type-2 PLL Tracking Response
 1 
R s   2 2
s s K PD KVCO R
F s     , E s  
RC
 , K 
s s 2  2 n s  n2 s 2  Ks  K N
RC
• Frequency Ramp Response

 s 3 
Using the Final Value Theorem : lim 3 sE s   lim  2
 
s 0 s s 0  K  n
s 3  s 2  Ks  
 RC 
A second - order type - 2 PLL can track a frequency ramp with a dynamic phase lag

  
 
1   
2
s
Transient Response : L  3  
 s  s  Ks  K 
 2

  RC 

102
Second-Order Type-2 PLL
Frequency Ramp Response
  
 
1   
2
s
Transient Response : L  3  
K
 s  s 2  Ks  
  RC 

n 1
  RC  KRC
2 2

103
Ideal Phase Detector
Phase Detector
Loop Filter

e ve vctrl
in  KPD F(s)

fb

• An ideal phase detector has the

same gain (slope) over a 2 range

• This allows the linear PLL model to

be used for all phase relationships

104
Real Phase Detectors
• Many phase detectors
are nonlinear and do
not display the same
gain for a given phase
relationship

• This implies that the

PLL cannot be
described by the linear
model for large input
phase deviations
105
PLL Frequency Step Response:
Linear vs Behavioral Model
  Mrad/sec
Frequency Step Input: ref(s)= =
s2 32s2

No Cycle Slips Observed

with Linear Model

Cycle Slips

• Due to non-linearities in loop components

(primarily the PD), a real PLL’s response
can vary significantly from the linear model
106
PLL Hold Range (Sinusoidal PD)
• A PLL Hold Range is the input frequency range over which the PLL can
maintain static lock

w/ Linear Model the Steady - State Phase Error is e 
K DC

K PD KVCO K1
First - Order : K DC 
N
K PD KVCO
Second - Order Type - 1 : K DC 
N
Second - Order Type - 2 : K DC  

With a sinusoidal phase detector, the phase error is


sine 
K DC

Since sine cannot exceed 1 , the lock frequency is constrained to   K DC

Hold Range :  H  K DC rad/sec 

• The hold range is finite for a type-1 PLL, and theoretically infinite for a
type-2 PLL. However in practice it will be limited by another PLL block,
such as the VCO tuning range.
107
First-Order PLL Phaselock Acquisition
(Sinusoidal PD)
Phase Detector Loop Filter VCO

e KPD* Vctrl KVCO

in  F(s) out
sin(x) s

fb

Assuming a simple first - order PLL with a sinusoidal PD

F  s   K1  1

VCO Instantaneous Frequency : o  KVCO vc t 

Sinusoidal Phase Detector Output : K PD sin e 

Assume the input signal is at a frequency different from o , such that the

input phase is ref t and   ref  o

108
First-Order PLL Phaselock Acquisition
(Sinusoidal PD)
Phase Detector Loop Filter VCO

e KPD* Vctrl KVCO

in  F(s) out
sin(x) s

fb

The PLL output phase is

t t
out t   ot   KVCO vc  d  out 0   ot   KVCO K PD sin e  d  out 0 
o o

The PLL phase error is

t
e  ref  out  ref  o t   KVCO K PD sin e  d  out 0 
o

Differentiating this w.r.t. time yields the following nonlinear differential equation
de t 
   K sin e t  where K  KVCO K PD
dt 109
First-Order PLL Hold Range (Sinusoidal PD)

If the PLL is locked,

de t 
   K sin e    0
dt

sin e  
K
Since sine cannot exceed 1 , the lock frequency is constrained to   K

Hold Range :  H  K rad/sec 

110
 First-Order PLL Phaselock Acquisition
(Sinusoidal PD) 
e
Normalized Frequency Error,
Normalizing the first - order PLL differential equation by K K

e 
  sin e 
K K

d e
In the phase - plane plot, there are 2 nulls where 0
dt
Phase Error, e
Negative - slope nulls are stable lock points,

while positive - slope nulls are unstable

• Every cycle (2 interval) contains a stable null, thus e

cannot change by more than one cycle before locking
• There is no cycle slipping in the locking process
• A cycle slip occurs when the phase error changes by more
than 2 without locking
111
First-Order PLL Phaselock Acquisition Time
(Sinusoidal PD)
In order to find the phaselock acquistion time, we need to formally solve
t
e t   t   KVCO K PD sin e  d  out 0 
o

If  is zero and e 0  is small, such that sin e   e ,

the approximate solution is the linear model phase step response

e t   out 0 e  Kt
However, if e 0  is large, the response will deviate

from this linear approximation and can increase significan tly

112
First-Order PLL Lock Failure (Sinusoidal PD)
First-Order PLL VCO Control Voltage

Hold Range :  H  K rad/sec 

• If the frequency offset exceeds the PLL hold

range, the phase error will oscillate
asymmetrically as the PLL undergoes cycle slips
113
Second-Order Type-2 PLL Phaselock
Acquisition (Sinusoidal PD)
Phase Detector Loop Filter VCO

e KPD* Vctrl KVCO

in  F(s) out
sin(x) s

fb

Assuming a second - order type - 2 PLL with a sinusoidal PD

 2s  1  2 1
F s    
 1s  1  1s
The filter response in the time - domain can be expressed as

2 1 t 2 1 t
vc t   ve t    ve  d  K PD sin e     K PD sin e  d
1 1 0 1 1 0
The PLL output phase is
t
 t 2 t
1 t  
out t   ot   KVCO vc  d  out 0   ot  KVCO K PD   sin e  d     sin e  d d   out 0 
o  0 1 0  1 0   114
Second-Order Type-2 PLL Phaselock
Acquisition (Sinusoidal PD)
Phase Detector Loop Filter VCO

e KPD* Vctrl KVCO

in  F(s) out
sin(x) s

fb

The PLL phase error is

 t 2 t
1 t  
e  ref  out  ref 
 o t  KVCO K PD   sin e  d     sin e  d d   out 0 
 
 0 1 0 1 0  
Differentiating this twice w.r.t. time yields the following nonlinear differential equation
  2 
1 
e   KVCO K PD  cose e  sin e 
 1 1 
115
Second-Order Type-2 PLL Phaselock
Acquisition (Sinusoidal PD)

For this Second - Order Type - 2 PLL, the natural frequency and damping factor are

K PD KVCO  22 K PD KVCO
 
2
,  
n
1 4 1

Substituti ng this into the nonlinear differential equation yields the following
 
e  2 n cose e  n2 sin e   0

• No closed form solution exists, and numerical

techniques are required to solve
116
 Second-Order Type-2 PLL Phaselock
Acquisition (Sinusoidal PD)
 
e  2 n cose e  n2 sin e   0

Acquisition with a phase error



% of cycle e and e vs time Phase Plane Plot : e vs e

rads

117
Second-Order PLL Phase Plane Plots
(Sinusoidal PD)
• An unstable singularity is
 
called a Saddle Point e  2 n cose e  n2 sin e   0

• A trajectory that terminates on

a saddle point is called a
“Separatrix”

• If a trajectory lies between the

2 separatrices, it will lock
without cycle slipping

• If a trajectory lies outside the

2 separatrices, it will cycle
slippling one or more times
before locking (if at all)
118
Second-Order PLL Pull-Out Range and Lock
Time (Sinusoidal PD)
• The Pull-Out Range is the maximum frequency step that
can occur before the loop locks without cycle slipping
 PO  1.8n   1

for  between 0.5 and 1.4

If a frequency step is less than the pull - out range, the PLL acquistion time can be approximat ed as

4.2f 
2
4
tacq  t phase  t freq  
n BL3

for phase error less than 10%

Here, BL is the PLL noise bandwidth


BL   H  f  df
2
(Hz)
0

 2s  1  2 1
Assuming F s     ,
 1s  1  1s

n  1 
BL     (Hz)
2  4 
119
Second-Order PLL Locking Outside of the
Pull-Out Range (Sinusoidal PD)

• Multiple cycle slips are observed before the loop locks

120
Agenda
• PLL Overview
• PLL Linear Model
• PLL Stability
• Analog Charge Pump PLL Design Procedure
• PLL Noise Transfer Functions
• PLL Transient Behavior
• PLL Time Domain Modeling
121
Time Domain Model
• Time domain models captures the discrete-time operation
of the PLL architectures
• Interaction between charge pump and loop filter
• Cycle slipping behavior
• Allows modeling of non-linear control systems
• Dynamic loop bandwidth control
• Automatic frequency band selection
• Potential implementation tools
• Matlab Simulink
• CppSim
• Cadence
122
Simulink Model

PFD
Loop Filter

123
Frequency Step w/ Simulink Model
• VCO control voltage response to input frequency step
KVCO=2*1GHz/V (LC Osc) KVCO=2*10GHz/V (Ring Osc)

• Voltage spikes due to charge pump current driving loop filter resistor
• Cycle slipping occurs during lock acquisition due to large initial
frequency difference
124
CppSim Model [Perrott/Meninger]

• https://cppsim.com/
• C++ based allows for rapid
simulation of advanced architectures
• Many useful building blocks included

125
Cadence Verilog-A Model

VCO (Square Wave)

Verilog-A Code Snippet

126
Conclusion
• The way a PLL shapes noise depends on
where the noise is introduced in the loop

• Optimizing the loop bandwidth for one noise

source may enhance other noise sources

• Time domain modeling captures loop

nonlinearities and allows for verification of
advanced control schemes
127
Next Time
• Phase Detector Circuits

128