ECEN620: Network Theory

Broadband Circuit Design

Fall 2022

Lecture 4: Phase Detector Circuits

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• HW1 due Sept 22, 11:59PM
• Turn in via Canvas

• HW2 due Oct 6

• Requires transistor-level design
• For 90nm CMOS device models, see
https://people.engr.tamu.edu/spalermo/ecen689/cadence_90nm_2021.pdf
• Can use other technology models if they are a
90nm or more advanced CMOS node

2
Agenda
• Phase Detector Circuits
• Mixer PD
• XOR PD
• J-K Flip-Flop PD
• Phase-Frequency Detector (PFD)

3
References
• RF Microelectronics, B. Razavi, Prentice
Hall, 1998.
• Design of Integrated Circuits for Optical
Communications, B. Razavi, McGraw-Hill,
2003.
• Monolithic Phase-Locked Loops and Clock
Recovery Circuits, B. Razavi, Wiley, 1996.
• M. Perrott, High Speed Communication
Circuits and Systems Course, MIT Open
Courseware
4
Phase Detector
Phase Detector IN
Loop Filter
FB
e ve vctrl
in  KPD F(s) 
avg 𝑣 𝑡 𝐾 Δ𝜙
fb
avg{ve(t)}
• Detects phase difference between feedback clock
and reference clock
• The loop filter will filter the phase detector output, KPD
thus to characterize phase detector gain, extract

average output voltage
• The KPD factor can change depending on the
specific phase detector circuit
K PD units are V/rad when used with a dimension - less filter

K PD units are rad -1 (averaged) or A/rad when combined with the charge - pump

when used with a impedance filter 5

Analog Multiplier Phase Detector
A1 cos 1t
A1 A2 A1 A2
cos1  2 t     cos1  2 t   
2 2
A2 cos2t   
 is mixer gain

• If 1=2 and filtering out high-frequency term

A1 A2
y t   cos 
2
A1 A2   
• Near  lock region of /2: y t      
2  2 
A1 A2
K PD  
2

[Razavi]
6
Analog Mixer PD Properties
• The nominal lock point (zero frequency
offset or Type-2) with a mixer PD is a 90
static phase shift
• For many applications this is unimportant or
can be cancelled elsewhere
• The mixer cannot serve as a frequency
detector, as on average the output will be
zero for a frequency difference
• KPD is a function of the input amplitude,
which is not desired
7
Mixer Circuits

Active Mixers
Passive Mixer

8
XOR Phase Detector

[Razavi]

• Assuming logic 1=“+1” and 0=“-1”, the XOR PD will lock

when the average output is 0
• Generally, /2 is a stable lock point and -/2 is a metastable point
• Sensitive to clock duty cycle 9
XOR Phase Detector

Width is same for both

leading and lagging
phase difference! [Perrott]

10
Stable vs Metastable Lock Point

[Perrott]

(positive feedback operation) (negative feedback operation)

• The PLL should be configured in negative feedback based on the phase detector
gain
• However, the phase detector gain varies as a function of the phase error
• Generally, the PLL is designed to have a stable lock point with a π/2 phase offset
• - π/2 is a metastable lock point because it is in a positive feedback operation range
11
Cycle Slipping
• If there is a frequency difference between the input
reference and PLL feedback signals the phase detector can
jump between regions of different gain
• PLL is no longer acting as a linear system

[Perrott]

(positive feedback operation) (negative feedback operation)

12
Cycle Slipping

Cycle Slipping

[Perrott]

• If frequency difference is too large the PLL may not lock

13
XOR PD Properties
• The nominal lock point with an XOR PD is
also a 90 static phase shift
• Unlike the analog mixer, KPD is
independent of input amplitude and
constant over a  phase range
• The XOR PD is sensitive to input duty
cycle, and will lock with a phase error if the
input duty cycles are not 50%

14
 J-K Flip-Flop Phase Detector
J K
ref

div

ref

div

1
K PD 


15
J-K Flip-Flop Details
J K
ref

div

16
J-K Flip-Flop Phase Detector Harmonic Locking

ref

div

ref

div

• Harmonic signals can display the same DC output,

leading to potential locking to harmonics
17
J-K Flip-Flop PD Properties
• The nominal lock point with an J-K Flip-
Flop PD is a 180 static phase shift
• The J-K Flip-Flop PD is not sensitive to
input duty cycle
• The J-K Flip-Flop displays a constant KPD
over a 2 range
• There is the potential to lock to harmonics
of the reference clock

18
 Phase Frequency Detector (PFD)
• Phase Frequency Detector allows for
PFD wide frequency locking range,
D
CLKIN R
Q UP potentially entire VCO tuning range
• 3-stage operation w/ UP & DN outputs
CLKFB R • Rising edge-triggered results in duty
Q DN
D cycle insensitivity
Tref CLKFB CLKIN
CLKIN CLKFB CLKIN
te UP=0 UP=0 UP=1
CLKFB DN=1 DN=0 DN=0

CLKIN CLKFB
UP Delay

DN
Trst RST=1
iCP

19
 Averaged PFD Transfer Characteristic
UP=1 & DN=-1 avg{ve(t)}
PFD 1
D
Q UP
in R

-4 -2
in-fb
fb R
Q DN 1 2 4
D
2
-1

• Constant slope and polarity asymmetry about zero phase

allows for wide frequency range operation
• The averaged PFD gain is 1/(2) with units of rad-1

20
PFD Deadzone
Tref
D UP ICP
Q CLKIN
in R
te
iCP CLKFB
fb R
R UP too narrow
D
Q C2
DN ICP
C1 DN
Trst
iCP

• If phase error is small, then short avg{ve(t)}

output pulses are produced by PFD (Zoomed)

• Cannot effectively propagate these

Dead
pulses to switch charge pump Zone
• Results in phase detector “dead in-fb

zone” which causes low loop gain

and increased jitter
21
PFD Operation w/ Reset Delay
• Solution is to add delay in PFD
reset path to force a minimum UP
D ICP
UP and DN pulse length in R
Q

iCP
• In locked state both UP and
Td
DN current sources are on for fb R
Q R C2
Trst, but ideally no net current D
DN ICP
is delivered to loop filter C1
Tref
CLKIN
te
CLKFB

UP reliable width

DN
Trst
iCP

22
 Problems Near 2
• PFD cannot react to input
rising edges during reset UP
D ICP
• This can result in the next in R
Q

rising edge driving the loop in iCP

the wrong direction Td
fb R
R
• Reset delay can increase D
Q C2
DN ICP
acquisition time and sets a C1
max PFD operating frequency
Tref missed edge!
CLKIN
te
CLKFB
UP

DN
Trst
iCP

wrong direction!
23
PFD Transfer Characteristic w/ Reset Delay
avg{ve(t)} Ideal PFD
wrong PFD w/ Trst
frequency 1
information!

-4 -2
in-fb
2 4

Trst
2
Tref
-1

• PFD reset delay generates wrong frequency information

• If this becomes a large percentage of the reference cycle,
then the PFD can fail to acquire frequency lock
𝑇
Max 𝑇
2
1
Max PFD Frequency
2𝑇
24
PFD Properties
• The nominal lock point with a PFD is 0
• The PFD is not sensitive to input duty cycle
• The PFD outputs “UP” and “DN” are not
complementary and stay high until reset by the
other, allowing for efficient frequency detection
• Near lock, the propagation of narrow pulses to
switch the charge pump can cause a phase
detector “dead zone”
• To prevent this, extra delay is generally inserted in the
PFD reset path
25
Detailed Optimized PFD Schematic

• Because the flip-flop data input is always

“1”, the logic can be optimized for higher
speed operation 26
Next Time
• Charge Pump Circuits

27