International Islamic University,

Islamabad
Digital System Design LAB

EXPERIMENT # 06: Timing Simulation & Design Implementation

(Combinational Logic)

Name of Student:

Roll No.:

Date of Experiment:

Report submitted on:

Marks obtained:

Remarks:

Instructor’s Signature:

Digital System Design Lab (EE-319L) Page 46

 Timing Simulation & Design Implementation
(Combinational Logic)
1. Objective
This lab exercise is designed to understand the concepts related to timing simulations
and implementing designs on Spartan 3E boards.

2. Resources Required
• A Computer
• Xilinx ISE
• Spartan 2 or Spartan 3 board

3. Introduction
Xilinx is the largest vendor in the programmable logic market. Its FPGAs are the most widely
used in the world. Currently its FPGAs are divided mainly in 3 families: Virtex-7(most
powerful), Kintex-7(mid-range) & Artix-7(least powerful) where 7 represents the current
generation. Initially there were only two, High Power (Virtex series) and High Volume
(Spartan Series). Spartan 3 has been one of the most widely used FPGA ever made and
currently many educational institutions use it to teach Digital Logic Design to its students.

3.1 Device Identification

a) Spartan 2

Digital System Design Lab (EE-319L) Page 47

b) Spartan 3E

3.2 Logic Synthesis

Logic Synthesis is the process of converting a high level description of the design into an
optimized, gate-level representation, using the cells in the technology library. Computer-aided
logic synthesis tools have greatly reduced the design cycle time and have improved
productivity. They allow designers to write technology independent, high-level descriptions
and produce technology-dependent, optimized, gate-level netlists. Both combinational and
sequential RTL descriptions can be synthesized.

3.3 Synthesis Design Flow

A logic synthesis tool accepts an RTL description, design constraints and a technology
library and produces an optimized gate-level netlist. Translation, logic optimization and
technology mapping are the internal processes in a logic synthesis tool and are normally
invisible to the user.

Digital System Design Lab (EE-319L) Page 48

The synthesis design flow can be shown as follows:

For more detail, see Chapter 14 of Verilog HDL by Samir Palinitkar.

3.4 Design Implementation

Design Implementation is the process of translating, mapping, placing, routing and generating
a BIT file for your design. The Design Implementation tools are embedded in the ISE software
for easy access and project management.

Synthesis and Design Implementation are two keywords that have been interchangeably used
to define the same process. In essence, Synthesis is a generic term used to explain this process
for programmable logic devices while Design Implementation is the term specifically used
by FPGA vendors like Xilinx to explain the same process.

3.4 Timing Simulation (Post-Route Simulation)

Timing Simulation uses the block and routing delay information from a routed design to give
a more accurate assessment of the behavior of the block under worst-case conditions. For this
reason, timing simulation is performed after the design has been placed and routed.

Timing (post-Place and Route) simulation is a highly recommended part of the HDL design
flow for Xilinx® devices. Timing simulation uses the detailed timing and design layout
information that is available after Place and Route. This enables simulation of the design, which
closely matches the actual device operation. Performing a timing simulation in addition to a
static timing analysis will help to uncover issues that cannot be found in a static timing analysis
alone. To verify the design, the design should be analyzed both statically and dynamically.
Note: Timing Simulation is done once the Design Implementation has been completed.

Digital System Design Lab (EE-319L) Page 49

4. Verilog Codes + Files (to be utilized in this lab)

4.1 4x1 Mux

module Mux4x1(out, i0, i1, i2, i3, s1, s0);

input i0, i1, i2, i3;
input s1, s0;
output out;

assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);

endmodule

4.2 UCF (pin locations file – created using PACE- PinOut Area Constraints Editor)

a)Spartan 3E b)Spartan 2

NET "i0" LOC = "V4" ;

NET "i1" LOC = "H13" ; NET "i0" LOC = "T8" ;
NET "i2" LOC = "K17" ; NET "i1" LOC = "P13" ;
NET "i3" LOC = "D18" ; NET "i2" LOC = "N12" ;
NET "out" LOC = "F9" ; NET "i3" LOC = "R13" ;
NET "s0" LOC = "L13" ; NET "out" LOC = "C8" ;
NET "s1" LOC = "L14" ; NET "s0" LOC = "P9" ;
NET "s1" LOC = "F14" ;

5. Design Implementation
a) Spartan 3E Starter Kit (Digilent Inc. – programmed through USB port)

1. Open Xilinx ISE. Goto File/New Project. Create a new project named Mux4x1. Choose
HDL as top-level source type.

2. Choose Spartan 3E as Family, XC3S500E as Device, FG320 as Package and -5 as Speed.

3. Choose XST(VHDL/Verilog) as Synthesis tool.

4. Add a new Verilog Module and write the code, mentioned above, in it.

Digital System Design Lab (EE-319L) Page 50

5. You can check the file for syntax errors using Synthesis/Check Syntax in the Processes
tab.

6. Open Assign Package Pins under User Constraints. Choose Yes on the next Dialog box to
get the following window.

7. Everything on the board is connected to the FPGA. The pin locations (pin-outs) can be
seen on the board under the respective item (in brackets) e.g

8. Enter the values as mentioned in the UCF file given in the previous section. (Students are
strongly encouraged to try their own combinations)

9. Save the file and chose XST Default < > in the next dialog box.

10. Run (or Rerun) by right-clicking on the Synthesize – XST then Implement Design then
Generate Programming File.

11. Before programming the FPGA, it is recommended that you perfom Timing Simulation
first. (See next section for instructions)

12. Open Configure Device (iMPACT) under Generate Programming File. Use first option
(JTAG) and press finish to add your device automatically to iMPACT.

Digital System Design Lab (EE-319L) Page 51

13. Choose the Mux4x1.bit file for the first device and bypass the remaining ones.

14. Right click on XC3S500E and choose Program. Click on OK and you device is
programmed as indicated by XC-Done LED (it glows) on the board.

15. The PROG button can be used to remove configuration from the FPGA manually. The
XC-Done LED stops glowing after pressing the PROG button. You can reprogram the FPGA
using Step 14.

Digital System Design Lab (EE-319L) Page 52

b) Spartan 2 XSA-200+XST 3.0 (XESS Corp. – programmed through LPT1 port)

The process is identical to the steps used for Spartan 3 kit barring a few steps. XESS Corp.
provides XSTOOLs for configuring their boards. It has GXSTEST & GXSLOAD which run
separately from Xilinx ISE.

1. Run GXSTEST and choose XSA-200 and click TEST. The device must successfully pass
the test. Check the connections if it fails.

2. Open Xilinx ISE. Goto File/New Project. Create a new project named Mux4x1. Choose
HDL as top-level source type.

3. Choose Spartan 2 as Family, XC2S200 as Device, FG256 as Package and -5 as Speed.

4. Choose XST(VHDL/Verilog) as Synthesis tool.

5. Follow Step 4 to Step 11 given for Spartan 3E. For pin-out values you have to check the
constraints file XSA+XST3-pins.xls. A sample UCF file is given in the last section.

6. Run GXSLOAD and choose XSA-200. Goto the project directory and locate Mux4x1.bit.
Drag the the file to GXSLOAD and drop on FPGA/CPLD.

7. Click on load and your device is programmed as indicated by DP pin of main 7 Segment
display of the board. This board also has a PROG button which removes the configuration
from the board manually.

Digital System Design Lab (EE-319L) Page 53

c) Addendum (Few problems that may occur even if the procedures are followed exactly
100%)

File doesn’t appear in Implementation mode:

1. All the procedures mentioned above are in Implementation mode. (Chosen from Sources
for (in the upper-left corner). It is also the default option for new projects.

2. If after saving your Verilog module file, it doesn’t appear in the Implementation mode, check
other modes to find it. It is usually placed in Behavioral Simulation mode.

3. When found, right-click the file, choose its properties and change Association from
Simulation Only to Synthesis/Imp + Simulation.

4. If not found in any mode then it might not be added to the project, right click your project
and choose Add Source to add the file to your project manually. Make sure to choose the right
Association in the dialog box that appears after adding the file.

4. Go back to the Implementation mode and follow the remaining procedure for your issued
board.

Options mentioned in the procedure don’t appear:

1. This problem may occur if the main module file (e.g for this lab Mux4x1.v) has not been
added to Implementation mode (check the solution mentioned above) or some other file has
been chosen in the Sources tab. Always remember to select your main/top module before
following the procedure for Implementing a Design on FPGA.

Digital System Design Lab (EE-319L) Page 54

6. Timing Simulation
The procedure for timing simulation is identical to Behavioral Modeling. It is done after you
have run Design Implementation Process.

1. Change Sources for (upper-left corner) from Implementation to Post-Route Simulation.

2. Create a file named Stimulus with type as Test Bench Waveform. Finish this task and in
the next dialog box choose Combinational under Clock Information. Change nothing else.

3. In this file, you can set values of inputs as you like. Experiment a bit!

4. In the Processes tab, run Xilinx ISE Simulator/Simulate Post-Place & Route Model.

Home Work:
Implement a 2x1 Mux on Spartan 3E board. Also perform its timing simulation. Submit the
code, synthesis report and wave files in the next lab. Implementation will be checked in the
next lab.

Hint: Only your code and UCF will change a little bit, the rest of the process is same.

Note:
a) This assignment must be submitted before the next lab.
b) The assignment submitted must be in proper format as instructed by the teacher to get
maximum marks.
c) Marks will be deducted on late submissions.
d) Cheating or using any unfair means will award ZERO marks.

Digital System Design Lab (EE-319L) Page 55

 International Islamic University, Islamabad
Digital System Design Lab

LAB WORKSHEET (Lab # 6)

Q.1 What is logic synthesis?
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

Q.2 What is the advantage of doing timing simulation?

________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

Q.3 Write the names of all the processes involved in logic synthesis.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

Digital System Design Lab (EE-319L)