International Islamic University,

Islamabad
Digital System Design LAB

EXPERIMENT # 05: Combinational & Sequential Circuits

Name of Student:

Roll No.:

Date of Experiment:

Report submitted on:

Marks obtained:

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Digital System Design Lab (EE-319L) Page 38

 Combinational & Sequential Circuits
1. Objective
This lab exercise is designed to understand the concepts related to the types of logic circuits
for Digital Systems i.e. Combinational & Sequential.

2. Resources Required
• A Computer
• Xilinx ISE
• ModelSim

3. Introduction
Logic circuits for digital systems may be divided into two categories:
a) Combinational
b) Sequential

3.1 Combinational Logic Circuit

A Combinational circuit consists of logic gates whose outputs at any time are determined from the
present combination of inputs. A combinational circuit performs an operation that can be specified
logically by a set of Boolean functions. Examples are Adder, Mux etc.

3.2 Sequential Logic Circuit

Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function
of the inputs and the state of the storage elements. Because the state of the storage elements is a
function of the previous inputs, the outputs of the sequential circuit depend not only on present
values of inputs, but also on past inputs, and the circuit behavior must be specified by a time
sequence of inputs and internal states. Examples are Register, Counter etc.
There are two main types of sequential circuits and their classification depends on the timings of
their signals. A synchronous sequential circuit is a system whose behavior can be defined from
the knowledge of its signal at discrete instants of time. The behavior of asynchronous sequential
circuit depends upon the input signals at any instant of time and the order in which the inputs
change. The asynchronous sequential circuits are also regarded as a combinational circuit with
feedback.

3.3 Register Transfer Level

In the digital design community, the term register transfer level (RTL) is frequently used for a
Verilog Description that uses a combination of behavioral and dataflow constructs and is
acceptable to logic synthesis tools.
Due to the wide usage of the term RTL, the module code files (containing a hardware description
code) written using any level of abstraction are also known as RTL code file.

Some remaining topics of the Behavioral Modeling (that were not discussed in last lab) are also
discussed in this lab.

3.4 Procedural Assignment

Procedural assignments update values of reg, integer, real, or time variables. The value placed on
a variable will remain unchanged until another procedural assignment updates the variable with a

Digital System Design Lab (EE-319L) Page 39

different value. These are unlike continuous assignments discussed in Dataflow Modeling, where
one assignment statement can cause the value of the right-hand-side expression to be continuously
placed onto the left-hand-side net. The syntax for the simplest form of procedural assignment is
shown below.

assignment ::= variable_lvalue = [ delay_or_event_control ] expression

The left-hand side of a procedural assignment <lvalue> can be one of the following:

• A reg, integer, real, or time register variable or a memory element

• A bit select of these variables (e.g., addr[0])
• A part select of these variables (e.g., addr[31:16])
• A concatenation of any of the above

The right-hand side can be any expression that evaluates to a value. In behavioral modeling, all
operators discussed in Dataflow Modeling can be used in behavioral expressions. There are two
types of procedural assignment statements: blocking and nonblocking.

a) Blocking Assignments
Blocking assignment statements are executed in the order they are specified in a sequential block.
A blocking assignment will not block execution of statements that follow in a parallel block. The
= operator is used to specify blocking assignments.

Example: Blocking Statements

reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioral statements must be inside an initial or always block
initial
begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0; //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //initialize vectors
#15 reg_a[2] = 1'b1; //Bit select assignment with delay
#10 reg_b[15:13] = {x, y, z}; //Assign result of concatenation to
// part select of a vector
count = count + 1; //Assignment to an integer (increment)
end

In above example, the statement y = 1 is executed only after x = 0 is executed. The behavior in a
particular block is sequential in a begin-end block if blocking statements are used, because the
statements can execute only in sequence. The statement count = count + 1 is executed last. The
simulation times at which the statements are executed are as follows:

• All statements x = 0 through reg_b = reg_a are executed at time 0

• Statement reg_a[2] = 0 at time = 15
• Statement reg_b[15:13] = {x, y, z} at time = 25

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 • Statement count = count + 1 at time = 25
• Since there is a delay of 15 and 10 in the preceding statements, count = count + 1 will be
executed at time = 25 units

Note that for procedural assignments to registers, if the right-hand side has more bits than the
register variable, the right-hand side is truncated to match the width of the register variable. The
least significant bits are selected and the most significant bits are discarded. If the right-hand
side has fewer bits, zeros are filled in the most significant bits of the register variable.

b) Nonblocking Assignments
Nonblocking assignments allow scheduling of assignments without blocking execution of the
statements that follow in a sequential block. A <= operator is used to specify nonblocking
assignments. Note that this operator has the same symbol as a relational operator,
less_than_equal_to. The operator <= is interpreted as a relational operator in an expression
and as an assignment operator in the context of a nonblocking assignment. To illustrate the
behavior of nonblocking statements and its difference from blocking statements, let us consider
the following example.

Example: Nonblocking Assignments

reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioral statements must be inside an initial or always block
initial
begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0; //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //Initialize vectors
reg_a[2] <= #15 1'b1; //Bit select assignment with delay
reg_b[15:13] <= #10 {x, y, z}; //Assign result of concatenation
//to part select of a vector
count <= count + 1; //Assignment to an integer (increment)
end
In this example, the statements x = 0 through reg_b = reg_a are executed sequentially at time
0. Then the three nonblocking assignments are processed at the same simulation time.

reg_a[2] = 0 is scheduled to execute after 15 units (i.e., time = 15)

reg_b[15:13] = {x, y, z} is scheduled to execute after 10 time units (i.e., time = 10)
count = count + 1 is scheduled to be executed without any delay (i.e., time = 0)

Thus, the simulator schedules a nonblocking assignment statement to execute and continues to the
next statement in the block without waiting for the nonblocking statement to complete execution.
Typically, nonblocking assignment statements are executed last in the time step in which they are
scheduled, that is, after all the blocking assignments in that time step are executed.
In the example above, we mixed blocking and nonblocking assignments to illustrate their
behavior. However, it is recommended that blocking and nonblocking assignments not be
mixed in the same always block.

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3.5 Application of nonblocking assignments
Having described the behavior of nonblocking assignments, it is important to understand why they
are used in digital design. They are used as a method to model several concurrent data transfers
that take place after a common event. Consider the following example where three concurrent data
transfers take place at the positive edge of clock.

Consider the following example which is intended to swap the values of registers a and b at each
positive edge of clock, using two concurrent always blocks.

Example: Nonblocking Statements to Eliminate Race Conditions

//Illustration 1: Two concurrent always blocks with blocking statements
always @(posedge clock)
a = b;

always @(posedge clock)

b = a;

//Illustration 2: Two concurrent always blocks with nonblocking statements

always @(posedge clock)
a <= b;

always @(posedge clock)

b <= a;

In the above example, in Illustration 1, there is a race condition when blocking statements are
used. Either a = b would be executed before b = a, or vice versa, depending on the simulator
implementation. Thus, values of registers a and b will not be swapped. Instead, both registers will
get the same value (previous value of a or b), based on the Verilog simulator implementation.
However, nonblocking statements used in Illustration 2 eliminate the race condition. At the
positive edge of clock, the values of all right-hand-side variables are "read," and the right-hand-
side expressions are evaluated and stored in temporary variables. During the write operation, the
values stored in the temporary variables are assigned to the left-hand-side variables. Separating
the read and write operations ensures that the values of registers a and b are swapped correctly,
regardless of the order in which the write operations are performed.
The following example shows how nonblocking assignments shown in Illustration 2 could be
emulated using blocking assignments.

Example: Implementing Nonblocking Assignments using Blocking Assignments

//Emulate the behavior of nonblocking assignments by
//using temporary variables and blocking assignments
always @(posedge clock)
begin
//Read operation, store values of right-hand-side expressions in temporary variables
temp_a = a;
temp_b = b;
//Write operation, Assign values of temporary variables to left-hand-side variables
a = temp_b;
b = temp_a;
end

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For digital design, use of nonblocking assignments in place of blocking assignments is highly
recommended in places where concurrent data transfers take place after a common event. In such
cases, blocking assignments can potentially cause race conditions because the final result depends
on the order in which the assignments are evaluated. Nonblocking assignments can be used
effectively to model concurrent data transfers because the final resu lt is not dependent on
the order in which the assignments are evaluated. Typical applications of nonblocking assignments
include pipeline modeling and modeling of several mutually exclusive data transfers. On the
downside, nonblocking assignments can potentially cause a degradation in the simulator
performance and increase in memory usage.

It is preferred that we use Non-Blocking Assignments in Sequential Circuits while Blocking

statements are preferred in Combinational Circuits.

3.6 Loops
There are four types of looping statements in Verilog: while, for, repeat, and forever. The syntax
of these loops is very similar to the syntax of loops in the C programming language. All looping
statements can appear only inside an initial or always block. Loops may contain delay expressions.
For more detail, see Chapter 7 of Verilog HDL by Samir Palinitkar.

3.7 Sequential and Parallel Blocks

Block statements are used to group multiple statements to act together as one. There are two types
of blocks: sequential blocks and parallel blocks.

a) Sequential blocks
The keywords begin and end are used to group statements into sequential blocks. The statements
in a sequential block are processed in the order they are specified. A statement is executed only
after its preceding statement completes execution.

b) Parallel blocks
Parallel blocks, specified by keywords fork and join, provide interesting simulation features.
Parallel blocks provide a mechanism to execute statements in parallel. Statements in a parallel
block are executed concurrently. Ordering of statements is controlled by the delay or event control
assigned to each statement. If delay or event control is specified, it is relative to the time the block
was entered.
Notice the fundamental difference between sequential and parallel blocks. All statements in a
parallel block start at the time when the block was entered. Thus, the order in which the statements
are written in the block is not important.
For more detail, see Chapter 7 of Verilog HDL by Samir Palinitkar.

Digital System Design Lab (EE-319L) Page 43

4. Verilog Codes (to be utilized in this lab)
4.1 4- bit Counter
module Counter(q_out, CO, Count, Clk, Clr);

output CO;
output [3:0] q_out;
input Clk, Clr, Count;
reg [3:0] q_out;
assign CO = Count & (q_out == 4’b1111);

//always block makes sure that whenever there is a change in Clk, we enter this block
//The following code is for a synchronous counter. By using “always @ (posedge Clk or
//negedge Clr)” will make it an Asynchronous counter.
always @ (posedge Clk)
begin
if(~Clr)
begin
q_out <= 4’b0000;
end

else if (Count)
begin
q_out <= q_out + 1’b1;
end

else
begin
q_out <= q_out;
end
end
endmodule

4.2 Stimulus
module Stimulus;

wire CO;
wire [3:0] q_out;
reg Clk, Clr, Count;

//Module Instantiation
Counter C1(q_out, CO, Count, Clk, Clr);

//Clock Generator (Must for Sequential circuits)

initial
begin
Clk=1'b0;
forever
#1 Clk = ~Clk;
end

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//Values checking part
initial
begin
Clr = 0; Count = 1;
#5 Clr = 1; Count = 1;
#40 Clr = 1; Count = 0;
#10 Clr = 0; Count = 1;
#10 $stop;
#10 $finish;
end
endmodule

5. Lab Task
Implement a 16-bit Counter with parallel load. The Inputs and their functions are given in
the truth table. Also simulate your design for verification (Create a proper Stimulus or Test
Bench file).

Hint: Introduce a 16 bit input named value. When load is 1, then value is assigned to q_out which
must also be 16-bit. The rest is nearly identical to the code in Section 4. Remember it is positive
edge-triggered counter.

6. Home Work
Implement an Asynchronous Up-Down 8-bit Counter. Submit the code and wave files in the
next lab. Simulate in either ModelSim or Xilinx ISE.

Hint: Use the same approach as given in the Verilog codes given in Section 4. Introduce another
input up_down that when 1 increments q_out otherwise decrement it. This condition must be
nested under the condition where value of count is being checked as it behaves like an enable
switch. q_out’s size is 8-bit in this case. Remember it is positive edge-triggered counter.

Note:
a) This assignment must be submitted before the next lab.
b) The assignment submitted must be in proper format as instructed by the teacher to get
maximum marks.
c) Marks will be deducted on late submissions.
d) Cheating or using any unfair means will award ZERO marks.

Digital System Design Lab (EE-319L) Page 45

 International Islamic University, Islamabad
Digital System Design Lab

LAB WORKSHEET (Lab # 5)

Q.1 What are the types of logic circuits? Differentiate between them.
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Q.2 What is the difference between blocking and non-blocking assignments?

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Q.3 How many blocks are available in Verilog? Differentiate between them.
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Q.4 What is RTL Coding?

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Digital System Design Lab (EE-319L)