Introduction to VLSI System Design

Lecture: Fabrication and Layout

1
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and cross-
section of wafer in a simplified manufacturing process

2
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

3
Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

4
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

5
Detailed Mask Views
Six masks n well

 n-well
 Polysilicon
 n+ diffusion Polysilicon

 p+ diffusion
Contact
n+ Diffusion


 Metal p+ Diffusion

Contact

Metal

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Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
 Cover wafer with protective layer of SiO2 (oxide)
 Remove layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer
 Strip off SiO2

p substrate

7
Oxidation
Grow SiO2 on top of Si wafer
 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

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Photoresist
Spin on photoresist
 Photoresist is a light-sensitive organic polymer
 Softens where exposed to light

Photoresist
SiO2

p substrate

9
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist

Photoresist
SiO2

p substrate

10
Etch
Etch oxide with hydrofluoric acid (HF)
 Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

11
Strip Photoresist
Strip off remaining photoresist
 Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step

SiO2

p substrate

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n-well
n-well is formed with diffusion or ion implantation
Diffusion
 Place wafer in furnace with arsenic gas
 Heat until As atoms diffuse into exposed Si
Ion Implanatation
 Blast wafer with beam of As ions
 Ions blocked by SiO2, only enter exposed Si

SiO2

n well

13
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps

n well
p substrate

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Polysilicon
Deposit very thin layer of gate oxide
 < 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
 Place wafer in furnace with Silane gas (SiH4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

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Polysilicon Patterning
Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

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Self-Aligned Process
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

17
N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate

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N-diffusion cont.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion

n+ n+ n+

n well
p substrate

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N-diffusion cont.
Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

20
P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

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Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

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Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

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Photolithography

24
Basic Exposure Methods
~5:1 Exposure
1:1 Exposure 1:1 Exposure

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Reticle Pattern Transfer to Resist
UV light source

Shutter
Alignment laser

Shutter is closed during focus

and alignment and removed
Reticle (may contain one or
during wafer exposure
more die in the reticle field)

Projection lens (reduces the size of

reticle field for presentation to the
wafer surface)
Single field exposure, includes:
focus, align, expose, step, and
repeat process
Wafer stage controls
position of wafer in
X, Y, Z, q

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Stepper Exposure Field
UV light

Reticle field size

20 mm  15mm,
4 die per field

5:1 reduction lens

Image exposure on wafer

Serpentine 1/5 of reticle field
stepping pattern 4 mm  3 mm,
4 die per exposure

Wafer
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Photo-resist
Negative Resist
 Wafer image is opposite of mask image
 Exposed resist hardens and is insoluble
 Developer removes unexposed resist

Positive Resist
 Mask image is same as wafer image
 Exposed resist softens and is soluble
 Developer removes exposed resist

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 Negative Lithography

Areas exposed to light become

crosslinked and resist the
Ultraviolet light developer chemical.
Chrome island on
glass mask Island
Exposed area of
photoresist
Window
Photoresist
Shadow on
photoresist

Photoresist
Oxide Oxide
Silicon substrate Silicon substrate

Resulting pattern after

the resist is developed.

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 Positive Lithography

Ultraviolet light

Areas exposed to
light are dissolved.
Chrome island Shadow on
on glass mask photoresist Island
Window

photoresist
Photoresist

Exposed area
of photoresist
photoresist
Photoresist
oxide
Oxide oxide
Oxide
silicon
Silicon substrate
substrate silicon substrate
Silicon substrate

Resulting pattern after

the resist is developed.

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Bright Field and Dark Field Masks
Clear Field Mask Dark Field Mask

Simulation of metal interconnect lines Simulation of contact holes

(Negative resist lithography) (positive resist lithography)

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Resolution of Features
0.1
0.25

0.5

1.0
The dimensions of linewidths and spaces
must be equal. As feature sizes decrease,
it is more difficult to separate features
from each other.

2.0 32
Lens Capturing Diffracted Light
Quartz

UV
Mask

Diffraction patterns
Chrome

4 4
3 3
2 2
1 1
0

Lens

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Effect of Numerical Aperture (NA)
Pinhole masks

Lens NA Image
results

Bad

Poor

Good

Diffracted light
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Resolution for Given , NA and k
k = 0.6
k
R=
Illuminator,  NA
wavelength
Mask   R
365 nm 0.45 486 nm
i-line
Lens, NA 365 nm 0.60 365 nm
193 nm 0.45 257 nm
DUV
193 nm 0.60 193 nm
R
Wafer

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 Optical Proximity Effects

Rounded corners

Nonuniform CDs Shortened lines

36
 Optical Proximity Correction (OPC)

(a) Uncorrected design (b) Corrected (c) Feature

with feature assisting
biasing technique

37
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
 Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
rules
Express rules in terms of  = f/2
 E.g.  = 0.3 mm in 0.6 mm process

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Simplified Design Rules
Conservative rules to get you started

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Inverter Layout
Transistor dimensions specified as Width / Length
 Minimum size is 4 / 2,sometimes called 1 unit
 In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long

40
Gate Layout
Layout can be very time consuming
 Design gates to fit together nicely
 Build a library of standard cells
Standard cell design methodology
 VDD and GND should abut (standard height)
 Adjacent gates should satisfy design rules
 nMOS at bottom and pMOS at top
 All gates include well and substrate contacts

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Example: Inverter

42
Example: NAND3
Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32  by 40 

43
Stick Diagrams
Stick diagrams help plan layout quickly
 Need not be to scale
 Draw with color pencils or dry-erase markers

44
Examples of Stick Diagrams

45
Wiring Tracks
A wiring track is the space required for a wire
 4  width, 4  spacing from neighbor = 8  pitch
Transistors also consume one wiring track

46
Well spacing
Wells must surround transistors by 6 
 Implies 12  between opposite transistor flavors
 Leaves room for one wire track

47
Area Estimation
Estimate area by counting wiring tracks
 Multiply by 8 to express in 

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Example: O3AI
Sketch a stick diagram for O3AI and estimate area
 Y= (A+B+C)•D

49
Example: O3AI
Sketch a stick diagram for O3AI and estimate area
 Y= (A+B+C)•D

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