L9904

MOTOR BRIDGE CONTROLLER

1 FEATURES Figure 1. Package

■ OPERATING SUPPLY VOLTAGE 8V TO 28V,
OVERVOLTAGE MAX. 40V
■ OPERATING SUPPLY VOLTAGE 6V WITH
IMPLEMENTED STEPUP CONVERTER
■ QUIESCENT CURRENT IN STANDBY MODE SO20
LESS THAN 50µA
■ ISO 9141 COMPATIBLE INTERFACE
Table 1. Order Codes
■ CHARGE PUMP FOR DRIVING A POWER
MOS AS REVERSE BATTERY PROTECTION Part Number Package
■ PWM OPERATION FREQUENCY UP TO L9904 SO20
30KHZ L9904TR Tape & Reel
■ PROGRAMMABLE CROSS CONDUCTION
PROTECTION TIME
2 DESCRIPTION
■ OVERVOLTAGE, UNDERVOLTAGE, SHORT
CIRCUIT AND THERMAL PROTECTION Control circuit for power MOS bridge driver in auto-
motive applications with ISO 9141bus interface.
■ REAL TIME DIAGNOSTIC

Figure 2. Block Diagram

VS 10

R CP

Reference
1 - VCC
ST +
BIAS
Charge
11 CP
= V pump
STH
13 CB1
f ST 12 GH1

VCC Overvoltage

Undervoltage 14 S1
RDG

DG 2 Thermal shutdown
V S1TH = R S1
Control Logic

19 GL1
EN 4

REN R GL1

18 GL2
DIR 5
R GL2
R DIR
VCC
17 S2
R PWM
PWM 3
R S2
V S2TH =

PR 6 15 GH2
Timer
16 CB2

ISO-Interface
9 K
RX 7

R RX
= 0.5 • V
VCC VS

R TX
TX 8
I KH

20 GND

REV. 4
October 2005 1/17
L9904

Table 2. Pin Function

N° Pin Description
1 ST Open Drain Switch for Stepup converter
2 DG Open drain diagnostic output
3 PWM PWM input for H-bridge control
4 EN Enable input
5 DIR Direction select input for H-bridge control
6 PR Programmable cross conduction protection time
7 RX ISO 9141 interface, receiver output
8 TX ISO 9141 interface, transmitter input
9 K ISO 9141 Interface, bidirectional communication K-line
10 VS Supply voltage
11 CP Charge pump for driving a power MOS as reverse battery protection
12 GH1 Gate driver for power MOS highside switch in halfbridge 1
13 CB1 External bootstrap capacitor
14 S1 Source/drain of halfbridge 1
15 GH2 Gate driver for power MOS highside switch in halfbridge 2
16 CB2 External bootstrap capacitor
17 S2 Source/drain of halfbridge 2
18 GL2 Gate driver for power MOS lowside switch in halfbridge 2
19 GL1 Gate driver for power MOS lowside switch in halfbridge 1
20 GND Ground

Figure 3. Pin Connection (Top view)

ST 1 20 GND
DG 2 19 GL1
PWM 3 18 GL2
EN 4 17 S2
DIR 5 16 CB2
PR 6 15 GH2
RX 7 14 S1
TX 8 13 CB1
K 9 12 GH1
VS 10 11 CP
SO20

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 L9904

Table 3. Absolute Maximum Ratings

Symbol Parameter Value Unit
VCB1 , VCB2 Bootstrap voltage -0.3 to 40 V
ICB1 , ICB2 Bootstrap current -100 mA
VCP Charge pump voltage -0.3 to 40 V
ICP Charge pump current -1 mA
VDIR ,VEN Logic input voltage -0.3 to 7 V
,VPWM ,VTX
IDIR ,IEN Logic input current ±1 mA
,IPWM ,ITX
VDG ,VRX Logic output voltage -0.3 to 7 V
IDG ,IRX Logic output current -1 mA
VGH1, VGH2 Gate driver voltage -0.3 to VSX + 10 V
IGH1 , IGH2 Gate driver current -1 mA
VGL1 , VGL2 Gate driver voltage -0.3 to 10 V
IGL1 , IGL2 Gate driver current -10 mA
VK K-line voltage -20 to VS V
VPR Programming input voltage -0.3 to 7 V
IPR Programming input current -1 mA
VS1 , VS2 Source/drain voltage -2 to VVS + 2 V
IS1 , IS2 Source/drain current -10 mA
VST Output voltage -0.3 to 40 V
IST Step up output current -1 mA
VVSDC DC supply voltage -0.3 to 28 V
VVSP Pulse supply voltage (T < 500ms) 40 V
IVS DC supply current -100 mA

For externally applied voltages or currents exceeding these limits damage of the device may occur!
All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body
model with R=1.5kΩ, C=100pF and discharge voltage ±2kV, corresponding to a maximum discharge energy of
0.2mJ.

Table 4. Thermal Data

Symbol Parameter Value Unit
TJ Operating junction temperature -40 to 150 °C
TJSD Junction temperature thermal shutdown threshold min 150 °C
TJSDH Junction thermal shutdown hysteresis typ 15 °C
Rth j-amb Thermal resistance junction to ambient 1) 85 °C/W
1. see application note 110 for SO packages.

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L9904

Table 5. Electrical Characteristcs

(8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition Min. Typ. Max. Unit
Supply (VS)
VVS OVH Overvoltage disable HIGH 28 33 36 V
threshold
VVS OVh Overvoltage threshold hysteresis 2) 1.6 V
VVS UVH Undervoltage disable HIGH 6 7 V
threshold
VVS UVh Undervoltage threshold 0.66 V
hysteresis 2)
IVSL Supply current VEN = 0 ; VVS = 13.5V; TJ< 85°C 50 µA
IVSH Supply current, pwm-mode VVS= 13.5V; VEN= HIGH; 8.1 13 mA
VDIR= LOW; S1 = S2 = GND
fPWM = 20kHz; CCBX = 0.1µF;
CGLX = 4.7nF; CGHX = 4.7nF;
RPR = 10kΩ; CPR = 150pF
IVSD Supply current, dc-mode VVS= 13.5V; VEN= HIGH; 5.8 10 mA
VDIR= LOW; S1 = S2 = GND
VPWM = LOW; CGHX = 4.7nF
RPR = 10kΩ; CPR = 150pF
Enable input (EN)
VENL Low level 1.5 V
VENH High level 3.5 V
VENh Hysteresis threshold 2) 1 V
REN Input pull down resistance VEN = 5V 16 50 100 kΩ
H-bridge control inputs (DIR, PWM)
VDIRL Input low level 1.5 V
VPWML
VDIRH Input high level 3.5 V
VPWMH
VDIRh Input threshold hysteresis 2) 1 V
VPWMh
RDIR Internal pull up resistance VDIR = 0; VPWM = 0 16 50 100 kΩ
RPWM to internal VCC 3)
DIAGNOSTIC output (DG)
VDG Output drop IDG = 1mA 0.6 V
RDG Internal pull up resistance VDG = 0V 10 20 40 kΩ
to internal VCC 3)
Programmable cross conduction protection 4)
NPR Threshold voltage ratio VPRH/ RPR = 10kΩ 1.8 2 2.2
VPRL
IPR Current capability VPR = 2V -0.5 mA
ISO interface, transmission input (TX)
VTXL Input low level 1.5 V

4/17
 L9904

Table 5. Electrical Characteristcs (continued)

(8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition Min. Typ. Max. Unit
VTXH Input high level 3.5 V
VTXh Input hysteresis voltage 2) 1 V
RTX Internal pull up resistance to VTX = 0 10 20 40 kΩ
internal VCC 3)
ISO interface, receiver output (RX)
VRXL Output voltage high stage TX = HIGH; IRX = 0; VK = VVS 4.5 5.5 V
RRX Internal pull up resistance TX = HIGH; 5 10 20 kΩ
to internal VCC 3) VRX = 0V
RRXON ON resistance to ground TX = LOW; 40 90 Ω
IRX = 1mA
tRXH Output high delay time Fig. 1 0.5 µs
tRXL Output low delay time 0.5 µs
ISO interface, K-line (K)
VKL Input low level -20V 0.45 ·
VVS
VKH Input high level 0.55 · VVS
VVS
VKh Input hysteresis voltage 2) 0.025· 0.8V
VVS
IKH Input current VTX = HIGH -5 25 µA
RKON ON resistance to ground VTX = LOW; IK=10mA 10 30 Ω
IKSC Short circuit current VTX = LOW 40 130 mA
fK Transmission frequency 60 100 kHz
2. not tested in production: guaranteed by design and verified in characterization
3. Internal VVCC is 4.5V ... 5.5V
4. see page 18 for calculation of programmable cross conduction protection time
tKr Rise time VVS = 13.5V; Fig. 1 2 6 µs
External loads at K-line:
RK = 510Ω pull up
to VVS
CK = 2.2nF to GND
tKf Fall time 2 6 µs
tKH Switch high delay time 4 17 µs
tKL Switch low delay time 4 17 µs
tSH Short circuit detection time VVS = 13.5V; 10 40 µs
TX = LOW
VK > 0.55 · VVS
Charge pump
VCP Charge pump voltage VVS = 8V VVS+ VVS+
7V 14V
VVS = 13.5V VVS+ VVS+
10V 14V
VVS = 20V VVS+ VVS
10V +14V

5/17
L9904

Table 5. Electrical Characteristcs (continued)

(8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition Min. Typ. Max. Unit
ICP Charging current VVS = 13.5V -50 -75 µA
VCP= VVS + 8V
tCP Charging time 2) VVS = 13.5V 1.2 4 ms
VCP= VVS + 8V CCP = 10nF
fCP Charge pump frequency VVS = 13.5V 250 500 750 kHz
Drivers for external highside power MOS
VCB1 Bootstrap voltage VVS = 8V; ICBX = 0; VSX = 0 7.5 14 V
VCB2 VVS =13.5V; ICBX = 0; VSX = 0 10 14 V
VVS = 20V; ICBX = 0; VSX = 0 10 14 V
RGH1L ON-resistance of SINK stage VCBX = 8V; VSX = 0 10 Ω
RGH2L
IGHX = 50mA; TJ = 25°C
VCBX = 8V; VSX = 0 20 Ω
IGHX = 50mA; TJ = 125°C
RGH1H ON-resistance of SOURCE stage IGHX = -50mA; TJ = 25°C 10 Ω
RGH2H IGHX = -50mA; TJ = 125°C 20 Ω
VGH1H Gate ON voltage (SOURCE) VVS= VSX = 8V; IGHX = 0; VVS VVS
VGH2H CCBX = 0.1µF +6.5V +14V
VVS = VSX = 13.5V; IGHX = 0; VVS+ VVS
CCBX = 0.1µF 10V +14V
VVS = VSX = 20V; IGHX = 0; VVS VVS
CCBX = 0.1µF +10V +14V
RGH1 Gate discharge resistance EN = LOW 10 100 kΩ
RGH2
RS1 Sink resistance 10 100 kΩ
RS2
Drivers for external lowside power MOS
RGL1L ON-resistance of SINK stage IGLX = 50mA; TJ = 25°C 10 Ω
RGL2L IGLX = 50mA; TJ = 125°C 20 Ω
RGL1H, ON-resistance of SOURCE stage IGLX = -50mA; TJ = 25°C 10 Ω
RGL2H IGLX = -50mA; TJ = 125°C 20 Ω
VGL1H, Gate ON voltage (SOURCE) VVS = 8V; IGLX = 0 7V VVS
VGL2H VVS = 13.5V; IGLX = 0 10V VVS
VVS = 20V; IGLX = 0 10V 14V
RGL1 Gate discharge resistance EN = LOW 10 100 kΩ
RGL2
2. not tested in production: guaranteed by design and verified in characterization
Timing of the drivers
tGH1LH Propagation delay time Fig. 2 500 ns
tGH2LH VVS = 13.5V
VS1 = VS2 =0
CCBX = 0.1µF

RPR= 10kW

6/17
 L9904

Table 5. Electrical Characteristcs (continued)

(8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition Min. Typ. Max. Unit
tGH1LH Propagation delay time including Fig. 2 0.7 1 1.3 µs
tGH2LH cross conduction protection time VVS = 13.5V
tCCP VS1 = VS2 =0
tGH1HL Propagation delay time CCBX = 0.1µF 500 ns
tGH2HL
CPR= 150pF;
RPR= 10kΩ;
5)
tGL1LH Propagation delay time Fig. 2 500 ns
tGL2LH VVS = 13.5V
VS1 = VS2 =0
CCBX = 0.1µF

RPR= 10kΩ
tGL1LH Propagation delay time including Fig. 2 0.7 1 1.3 µs
tGL2LH cross conduction protection time VVS = 13.5V
tCCP VS1 = VS2 =0
tGL1HL Propagation delay time CCBX = 0.1µF 500 ns
tGL2HL
CPR= 150pF;
RPR= 10kΩ;
5)
tGH1r Rise time Fig. 2 1 µs
tGH2r VVS = 13.5V
VS1 = VS2 =0
tGH1f Fall time 1 µs
CCBX = 0.1µF
tGH2f
tGL1r Rise time CGHX = 4.7nF 1 µs
tGL2r CGLX = 4.7nF
tGL1f Fall time RPR= 10kΩ; 1 µs
tGL2f
Short Circuit Detection
VS1TH Threshold voltage 4 V
VS2TH
tSCd Detection time 5 10 15 µs
Step up converter (ST) (5.2V ≤ VVS < 10V)
VSTH ST disable HIGH threshold 10 V
VSTh ST disable threshold hysteresis 1 2 V
voltage 2)
RDSON Open drain ON resistance VVS = 5.2V; 20 Ω
IST = 50mA
fST Clock frequency 50 100 149 kHz
2. not tested in production: guaranteed by design and verified in characterization
5. tested with differed values in production but guaranteed by design and verified in characterization

7/17
L9904

Figure 4. Timing of the ISO-interface

V
TX

0.7 • V V C C

0.3 • V V C C 0.3 • V V C C

t
t KL t KH
V
K
tKf t Kr

80 %
I K > I K SC
0.55 • V V S
0.45 • V V S

20%

t
t RXL t RXH
VR X

0.7 • V VC C

0.3 • V V C C

t
op e n d r ain t SH
tr ansis tor at
K-pin

ON

O FF

Figure 5. Timing of the drivers for the external MOS regarding the inputs DIR and PWM

PWM
or 50%
DIR

tGHXLH tGHXr tGHXHL tGHXf t

80%

GHX 20%

tGLXHL tGLXf tGLXr

t
tGLXLH

80%

GLX 20%
t

8/17
 L9904

Figure 6. I(V) characteristics of the K-Line for TX = HIGH and VVS=13.5V

IK [mA]
0.2

0.1

Ω
k0
~5
0.0

-0.1

-0.2

Ω
0k
-0.3 ~5

-0.4

-0.5
-20 -10 0 10 20
VK [V]

Figure 7. Driving sequence

EN

≈
DIR
≈
braking
PWM
≈

GL2
≈

GH2

GL1
Note:
≈

Before standby mode

(EN=low) a braking phase
is mandatory to discharge GH1
the stored energy of the
motor.

9/17
L9904

Figure 8. Charging time of an external capacitor of 10nF connected to CP pin at VVS=8V and
VVS=13.5V
voltage [V]
Charging time of a 10nF load at CP
30
CP for VS=13.5V

25
CP for VS=8V
20

15

10
EN
5

0
0 1 2 3 4
time [ms]

Figure 9. Application Circuit Diagram

VBAT

D1

VS 10

R CP
CS1 CS2
Voltage Reference
VCC
ST 1 - BIAS
Regulator +
11 CP
Charge
= VSTH pump
13 CB1
f ST R C1
VCC 12 GH1

VCC Overvoltage
CB1
Undervoltage 14 S1
RDG

DG 2 Thermal shutdown
V S1TH =
R S1 M
Control Logic

19 GL1
R
EN 4

REN R GL1

18 GL2
R
DIR 5

µC R DIR
VCC
R GL2

17 S2
R PWM
PWM 3
R S2
V S2TH = CB2

PR 6 15 GH2 R
Timer

16 CB2
CPR RPR

ISO-Interface
9 K
RX 7 K-Line
R RX
= 0.5 • VVS
VCC

R TX
TX 8
I KH

GND 20 GND

10/17
 L9904

3 FUNCTIONAL DESCRIPTION

3.1 General
The L9904 integrated circuit (IC) is designed to control four external N-channel MOS transistors in H-Bridge con-
figuration for DC-motor driving in automotive applications. It includes an ISO9141 compatible interface. A typical
application is shown in fig.9.

3.2 Voltage supply

The IC is supplied via an external reverse battery protection diode to the VVS pin. The typical operating voltage
range is down to 8V.
The supply current consumption of the IC composes of static and a dynamic part. The static current is typically
5.8mA. The dynamical current Idyn is depending of the PWM frequency fPWM and the required gate charge QGate
of the external power mos transistor. The current can be estimated by the expression:
Idyn = 2 · fPWM · QGate
An external power transistor with a gate charge of QGate = 160nC and a PWM frequency of fPWM = 20kHz re-
quires a dynamical supply current of Idyn = 6.4mA.
The total supply current consumption is IVS = 5.8mA + 6.4mA = 12.2mA.

3.3 Extended supply voltage range (ST)

The operating battery voltage range can be extended down to 6V using the additional components shown in
fig.7. A small inductor of L~150µH (Ipeak~500mA) in series to the battery supply builts up a step up converter
with the switching open drain output ST. The switching frequency is typical 100kHz with a fixed duty cycle of
50%. The step up converter starts below VVS < 8V, increases the supply voltage at the VS pin and switches off
at VVS > 10V to avoid EME at nominal battery voltage. The diode D2 in series with the ST pin is necessary only
for systems with negative battery voltage. No additional load can be driven by the step up converter.

Figure 10.

L9904
VBAT L1 D1 VS

C1 C2

D2

ST -
+

= VSTH

f ST

11/17
L9904

3.4 Control inputs (EN, DIR, PWM)

The cmos level inputs drive the device as shown in fig.7 and described in the truth table.
The device is activated with enable input HIGH signal. For enable input floating (not connected) or VEN=0V the
device is in standby mode. When activating the device a wake-up time of 50µs is recommended to stabilize the
internal supplies.
The DIR and PWM inputs control the driver of the external H-Bridge transistors. The motor direction can be
choosen with the DIR input, the duty cycle and frequency with the PWM input. Unconnected inputs are defined
by internal pull up resistors. During wake-up and braking and before disactivating the IC via enable both inputs
should be driven HIGH.

Table 6. Truth table:

Driver stage for external
Status Control inputs Device status Diagnostic Comment
power MOS

EN DIR PWM TS OV UV SC GH1 GL1 GH2 GL2 DG

1 0 x x x x x x R7) R R7) R T standby mode

2 1 x x 1 0 0 0 L L L L L thermal
shutdown

3 1 x x 0 1 0 0 L L L L L overvoltage

4 1 x x 0 0 1 0 L L L L L undervoltage

5 1 x x 0 0 0 1 X6) X6) X6) X6 L short circuit 6)

6 1 0 0 0 0 0 0 L H H L H

7 1 x 1 0 0 0 0 L H L H H braking mode

8 1 1 0 0 0 0 0 H L L H H

Symbols: x Don't care R:Resistive output TS:Thermal shutdown

0: Logic LOW or not active L: Output in sink condition OV:Overvoltage
1: Logic HIGH or active H: Output in source condition UV:Undervoltage
T: Tristate SC:Short Circuit
6. Only those external MOS transistors of the H-Bridge which are in short circuit condition are switched off. All others remain driven
by DIR and PWM.
7. See Application Note AN2229

3.5 Thermal shutdown

When the junction temperature exceeds TJSD all driver are switched in sink condition (L), the K- output is off and
the diagnostic DG is LOW until the junction temperature drops below TJSD - TJHYST.

3.6 Overvoltage Shutdown

When the supply voltage VVS exceeds the overvoltage threshold VVSOVH all driver are switched in sink condi-
tion (L), the K- output is off and the diagnostic DG is LOW.

3.7 Undervoltage Shutdown

For supply voltages below the undervoltage disable threshold the gate driver remains in sink condition (L) and
the diagnostic DG is low.

12/17
 L9904

3.8 Short Circuit Detection

The output voltage at the S1 and S2 pin of the H-Bridge is monitored by comparators to detect shorts to ground
or battery. The activated external highside MOS transistor will be switched off if the voltage drop remains below
the comparator threshold voltage VS1TH and VS2TH for longer than the short current detection time tSCd. The
transistor remains in off condition, the diagnostic output goes LOW until the DIR or PWM input status will be
changed. The status doesn't change for the other MOS transistors. The external lowside MOS transistor will be
switched off if the voltage drop passes over the comparator threshold voltage VS1TH and VS2TH for longer than
the short current detection time tSCd. The transistor remains in off condition, the diagnostic output goes LOW
until the DIR or PWM input status will be changed. The status doesn't change for the other MOS transistors.

3.9 Diagnostic Output (DG)

The diagnostic output provides a real time error detection, if monitors the following error stacks: Thermal shut-
down, overvoltage shutdown , undervoltage shutdown and short circuit shutdown. The open drain output with
internal pull up resistor is LOW if an error is occuring.

3.10 Bootstrap capacitor (CB1,CB2)

To ensure, that the external power MOS transistors reach the required RDSON, a minimum gate source voltage
of 5V for logic level and 10V for standard power MOS transistors has to be guaranteed. The highside transistors
require a gate voltage higher than the supply voltage. This is achieved with the internal chargepump circuit in
combination with the bootstrap capacitor. The bootstrap capacitor is charged, when the highside MOS transistor
is OFF and the lowside is ON. When the lowside is switched OFF, the charged bootstrap capacitor is able to
supply the gate driver of the highside power MOS transistor. For effective charging the values of the bootstrap
capacitors should be larger than the gate-source capacitance of the power MOS and respect the required PWM
ratio.

3.11 Chargepump circuit (CP)

The reverse battery protection can be obtained with an external N-channel MOS transistor as shown in fig.6. In
this case its drain-bulk diode provides the protection. The output CP is intended to drive the gate of this tran-
sistor above the battery voltage to switch on the MOS and to bypass the drain-bulk diode with the RDSON. The
CP has a connection to VS through an internal diode and a 20kΩ resistor.

3.12 Gate drivers for the external N-channel power MOS transistors (GH1, GH2, GL1, GL2)
High level at EN activates the driver of the external MOS under control of the DIR and PWM inputs (see truth
table and driving sequence fig.4). The external power MOS gates are connected via series resistors to the de-
vice to reduce electro magnetic emission (EME) of the system. The resistors influence the switching behaviour.
They have to be choosen carefully. Too large resistors enlarge the charging and discharging time of the power
MOS gate and can generate cross current in the halfbridges. The driver assures a longer switching delay time
from source to sink stage in order to prevent the cross conduction.
The gate source voltage is limited to 14V. The charge/discharge current is limited by the RDSON of the driver.
The drivers are not protected against shorts.

3.13 Programmable cross conduction protection

The external power MOS transistors in H-Bridge ( two half bridges) configuration are switched on with an addi-
tional delay time tCCP to prevent cross conduction in the halfbridge. The cross conduction protection time
tCCP is determined by the external capacitor CPR and resistor RPR at the PR pin. The capacitor CPR is charged
up to the voltage limit VPRH. A level change on the control inputs DIR and PWM switches off the concerned ex-
ternal MOS transistor and the charging source at the PR pin. The resistor RPR discharges the capacitor CPR.
The concerned external power MOS transistor will be switched on again when the voltage at PR reaches the
value of VPRL. After that the CPR will be charged again. The capacitor CPR should be choosen between 100pF
and 1nF. The resistor RPR should be higher than 7kW. The delay time can be expressed as follows:

13/17
L9904

tCCP= RPR · CPR · ln NPR with NPR= VPRH / VPRL = 2

tCCP= 0.69 · RPR · CPR

3.14 ISO-Interface
The ISO-Interface provides the communication between the micro controller and a serial bus with a baud rate
up to 60kbit/s via a single wire which is VBAT and GND compatible. The logic level transmission input TX drives
the open drain K-output. The K output can be connected to a serial bus with a pull up resistor to VBAT. The K-
pin is protected against overvoltage, short to GND and VS and can be driven beyond VVS and GND. During lack
of VVS or GND the output shows high impedance characteristic. The open drain output RX with an internal pull
up resistor monitors the status at the K-pin to read the received data and control the transmitted data. Short
circuit condition at K-pin is recognized if the internal open drain transistor isn't able to pull the voltage potential
at K-pin below the threshold of 0.45·VVS. Then the RX stays in high condition. A timer starts and switches the
open drain transistor after typ. 20µs off. A next low at the TX input resets the timer and the open drain transistor
switches on again.

Figure 11. Functional schematic of the ISO-interface

RX

K
R RX

= 0.5 •V VS
VCC

R TX

TX
I KH

R R delay
Q
T SH
S

14/17
 L9904

Figure 12. SO20 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

B 0.33 0.51 0.013 0.200

C 0.23 0.32 0.009 0.013

D (1) 12.60 13.00 0.496 0.512

E 7.40 7.60 0.291 0.299

e 1.27 0.050

H 10.0 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.40 1.27 0.016 0.050

k 0˚ (min.), 8˚ (max.)

ddd 0.10 0.004

(1) “D” dimension does not include mold flash, protusions or gate
SO20
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.

0016022 D

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L9904

Table 7. Revision History

Date Revision Description of Changes

October 2002 1 First Issue on ST-Press DMS

January 2004 2 Migration from ST-Press to EDOCS DMS

May 2004 3 Change Maturity from Product Preview to Final.

October 2005 4 Inserted on pag 12 AN2229 ref.

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 L9904

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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