VLSI SoC Design using Veriloc * Rate it! SILICON Setting Standards in VLSI Design Verilog Labs The Verilog lab exercises are designed to make you understand the Verilog-HDL based design methodology, They are organised in a way that takes you step by step until you become familiar with the tools and language. The labs are designed to maximize your hands on introduction to Verilog coding. Over this period, you will gain the level of coding skill, syntax proficiency, and understanding that can only be achieved through meaningful practice and effort. The lab exercises are independent of any particular Verilog simulator or synthesizer or FPGA technology. Follow the below steps to make your machine ready to do the labs Lets get Started! 1, Download button Verilog labs by be available in the left bottom comer of the next screen, Download the king the button Unzip the downloaded folder and save the folder in the particular location in your mac! 3, There will be 6 Verilog Lab Exercise folders inside the "Verilog_Labs” folder. 4, To work on the Lab Fxercises, you need to install the FDA tools. 5. With the help of "EDA Tools - Installation Guide" video, install the EDA tools in your machine, 6. With the help of * EDA Tools - User Guide™ video, learn to do the labs using the EDA tools. 7. Ifyou find any difficulties to support@mav. son. com tall and use the EDA tool, please write tous at 8. After completing all the above steps, you are ready to do the labs. Follow the instructions sgiven in the Verilog lab manual to complete the lab exercises. 9, After completing each labs, Watch the "Solution to Lab” Videos for more explanations and to comect yourself, 10, Download the Solution codes from section “Solution - Verilog Labs" of all the labs for your reference, www mayen-silicon.comVLSI SoC Design using Verilog VID" y Rate it! AMAVER SILICON VLSI Training Center Sing Sante a St Design Verilog Labs Introduction to Lab Exercises ‘The lb exercises are designed 10 make you understand the Verilog-HDL based design methodology. They are organised in a way that akes you step by step until you bscome femiliat with the tools ad language. ‘The labs are designed to masitnize your hands on inoduction o Vatilog coding, Over this period, we will gain the level of coding still, syntax proficiency, and understanding that can only be achieved Uhrough meaning practice amd effort, ‘The first few fabs are to get you familice with the EDA tools that we will be using, and the basi steps involved in simolating and systhesizing « small design EDA Tools The lab exercises are independent of any pareular Verilog simulator or synthesizer ot FPGA. technology. I this Veilog training you will be using the following EDA tools for the detign vasification and implementation. Simnlator: Modelsion -Altera Synthesizer: Quartus Prime IT Naming Conventions > Use mezningiul names forthe ports and signals “> Filename should be same as the module name Use only lowercase letters swww.maver-silicen.com VLSI Training Center SILICO Seng Sans in V1 STDesten Contents Labl: Fumilarization with Verllog Syntax, Instantiation and Testbench Previous Ask Question l| Curriculum = Next | %eVLSI SoC Design using Verilac"#0= yrs! yr Rate it! ©) > Use meaningful names forthe ports and signals > File name should be same as the module name > Use only lowercase letters Ee! VLSI Training Cer AVE ysl ang ee Contents Labl: Fumillarization with Verilog Synta, Objective: fo undersiane th different modelling sy les in Verilog and ear diffrent port mpping ecthods Lab: ‘umiliarization with Verilog Operators Objective: To understand bow operators responds to urhaowa, know ad high impedance values in ani clse canstrut and teary operator Familiarization with Combinational Logic Design Objective: To undersand how blocking and now-blocking asignments wer with procedural delays Labé: Familiar jon with Sequential Desiga Objective: fo understand how evabhcsaable eynchroncus designs. tasks and furctions are impkemented LabS: Famitiarization with Memory design Objective: To undersand how file inpuvoutpu operations wark wih memory designs and farmer over dings implemented Labs: Famitinrization with FSM design (Objective: To understand how Moore/Mealy FSM output are caloustod with diferat coding styl. Previous “Ask Question Curriculum Next | »VLSI SoC Design u: Rate it! VLSI Training Cemter Sevan Stdards in VEST Design 1 Symtns, Instantiation and Testhench Exampl Write RIL description and testbench for the Full Adder cirsut using half adders and OR gate, The ‘lock diagram of Full adder, along with complete conneetions of full adder using two half adders and an OR gate is shown below a a sum a |—- sum HAL Haz e Full 8 Adder a we ce y ort Hscarry Step!. Draw truth table and analyse the inpuls and outputs for Full Adder circuit ‘Step2. Open Modelsim, create project inthe sim directory of Labl Steps, Add the RTL (nial adder, Fall_ adder), ‘Stop. Add the'TB files (ib/half_adder_tbiv & th/full_ adder tb.v) to the project. Open the file lab /alhalf_adderv Stepl. Understand the syntax and functionality of half-adder. Step. Close the file ‘Open the fle lab1ib/half adder tb.v ‘Step], Understand the test bench, ‘Step2. Close the file ‘Compile, elaborate and simulate the design and test bench of half adder. Synthesize the design ia Quartus 17 Open the file lab It'full_addery Step). Write down the port directions, Step2. Declare the intemal wires. Step3. Instantiate nwo Half-Adders Steps, Instantiate the OR StepS, Save and close the file wwwanaver-silicon.com Ask Question | Curriculum ||VLSI SoC Design using Verilog ‘iP: Rate it! ‘Stepl, Write down the port directions, ‘Step2, Declese the internal wires. ‘Steps, Instntiare two Hal Adders Step, Instantiate the OR wate Step, Save and close the fle wonwamavensiliconcom ARAVER, Sears ‘Open the file lab1/bfull_adder sh Suepl, Understand the sym. and resibenct, Step2, hnsiantiate the fll adder Step3, Save and close the fle, ‘Compile, elaborate and simulate the design and tec bench of fll adder. Symhesize the design in Quartus It | Curriculum || Ne Previous | Ask QuestiVLSI SoC Design using Verilog Ds yr yr yy Rate it! ‘vaywemaven-tilicon.ccm Ave A, VLSI Training Center Seuing Stains ia VEST Design LAB 2 - Fomiliarization with Verilog Operators Wite RTL descsiption and testbench for an Azidimetic Logic Unit using arithmetic and logical ‘operators. The blozk diagram and instrutions set for ALU are shown below. ‘The ALU performs 16 different operations using comand input on 8 bit inputs a and b, Lf die MSB. of the command input is low then the arithmetic operstions are performed. If the MSB of command input is high then the logical operations ate performed. The output is of 16 bit Input o¢ enables the ALL, ie her. 08 is low, curpat is at high ionpedance Temnere | Onnier | Sommer Open inn | —anransw | #o1ane | anak — ‘ep0001 | increment oy t Eiico coma, oot | Sua toma | 4pI010 . ay HSE reno | Dewement anes | tron f oni | wutsvawant | e010 ¥ emir [Bide any [eon “ apane | srinargeeny ten | aott10 zoom | swannoytm [eon Procedure: Open the fle eb2éealuy ‘Step, Write down the functionality of ALU based! on command (instruction set ven ‘Use erthmetic and logical operators & Swatch Case Statement of Verilog. Step2, Understand the wistate oumut loge, Step. Seve and close the fe (Open the Me lab2/bvaly_ tay Step. Iastantiae the ALU design ‘Step2, Write a task named "insilize" to initialize dhe inpus of DUT. Step3. Understand the complete test bench sad various tasks defined inside it. Step4, Save and close the file Compile, elaborate ané simulate the design and testbenck \wonw mavencsilicon com Previous Ask Question | Curriculum || Next |VLSI SoC Design using Veriloc r Rate It! t worwimaven-silicen.com UNAVEN, vs ogee Sing Sodas a VES Dest LAB 3-- Familiarization with Combinational Lozic Design. Example: Woite RTL (Behavicural) desesiption and rst bench for a 4:1 Multiplexer eireuit ‘The block diagram ‘of 4:1 multiplexer is shown below. ¥ Stepl, Draw truth table for 4:1 Multiplexer circuit. Procedure: (Open the file abana _L.v Stop!, Definy he port directions with proper dotalypes and ranges, Step2, Write the MUN behaviour as a parallel logic using case stalement in behavioural modelling, StepG. Save and close the file. Oper the ile abhi 1 thw Step]. Instondate ste design Step2 Define hody for the initialize ask to initialize inputs of DUT 100 Step). Declace tasks ith argumens for driving stimulus to DUT, Stept, Call he tasks from procedural block Siep. Use Smonitor (ak in parallel init Ulock to display inpurs and oupuis, Step. Use Sfinish tsk ro finish the simulation ina paralll initial block with appropriate delay. Compile, elaborate and run the simulation, ‘seu maven silicon corn Previous Ask Question || Curriculum || Next | %VLSI SoC Design using Verilog "12": fr Rate it! Seting Slandos in VLSI Design LAB 4- Familisrization with Sequential Design Example: ‘Write RTL description and tesibench or the D flip-fop, ‘The block diagram, input and output waveforms of D flip-flop is shown below. ‘ > gh a tock Ba Procedure: ‘Stepl, Draw state table of D ip-top. ‘Step2. Draw the input, output timing diagrams For D Fliplop ‘Open the file abn. Stepl: Declace Pont Directions ‘Step2. Write the behavioral logie for D ip-Nop functionality Sep3. Assign complement of q to qb. ‘Step. Save and close the fle he Glelabarbid th StopI. Define a parameter with name "eycle” which i equa 10 10. Step? ‘Stcp3, Understand the clock seneraton | Step. Understand the various tsksused and also how to use tasks in testoench StepS, Use Smoritor task ina paraltel inal block to display inpuls and ouputs Steps. Save and close the fle \wonw.rnavenssilicon com Previous Ask Question | Curriculum | | NextVLSI SoC Design using Verilog IE: yyy) Rate it! wowmavensilicon com avs iF, VLSI Training Center Seting Standards ia VISE Desi LAB 5 - Eamiiarization with Memory desizn Example: Write RTL description and wstbench forthe Single Port RAM, wich is 8 bit wide and has 16 memory Tcations, Tae data can be written on a memory location by providing is addross and making “we” bigh and “enable” low. The data ean be ceed fom a memory location by providing the edscess and raking enable" high and "we" lous This RAM has single port for data writing and reading, The block diagram ofthe single port RAMis shown below, eyata emis ane JESSE Prncedar ‘Step, Draw tho impor, output timing digerams for Single Port RAM, Open te fle lab5int/eara Step]. Declare an 8 bit wide merry having 16 Iecations Step2, Understand che loge fa weiting data inte a memary lneaton Siep3, Undersiand the logic af reeding data ‘tom a memoty location Stepé. Save and close the file (Open te file labo/tbiram_tb.v ‘Step, Instamiate the RAM module and eonncer the pons Step2, Define body for the task named stimulus to initialize the "add" and “tempa” inputs though & and j variables. sei for initialization of "adr and j for initialization of tema" Step3, Understand the various tutks defined in this testbench Step. Save and close the file Compile, elaborate and simulate the design and testben ‘worwmavensilicon com Previous | Ask Question Curriculum | Next | %VLSI So€ Design using Veriloc virve Rate it! swouwmavensiliean com d T i \ ¥ é| Ph VLSI Training Center Seung Stendirds iV Design LAB 6 - Familisrization with FSM design Example: Write RTL description and testbeneh for the Sequence Detcctor that detects “101” from input data stream. ‘The block diagram and state diagram forte “101” sequence detector are shown below: reset] wa—- | Procedure Step]. Draw the state transition d.agtom and state transition table for the given sequence detector Step? Draw the input, output firing diagrams for sequence detector ‘Oper the file absrnbiseg. det Stepl_ Declare the setes as parameter “IDLE'STATEL""STATE2" "STATE" and use binary ‘encoding for encoing these sare. Step2, Write down the port declarstions with proper directions, Step Wate down the soquemial logic For prcsant state Sreps, Understand the combinational logi for nes stare, pS. Write down the lagi for ostput dout (Opes the file absriblseg_sb.v Step, Generate clock, usiny parameier *eyele" Step2, Wate tcek named "initialize" to initialize he input din of sequence detector Sted, Write a task named "RESET to reset the design, use delay task for adding delay Steps, Weite a task samod "stimulus" which provides input to dosien on nogarive edze oF elock StepS. Understand the seracining Logic defined in the program. Step6. Save and close the file ‘Compile, elaborate and simulate the design and restbench. worumaven-siican.com Previous Ask Question || Curriculum || Next | %