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Sheet 4-1

This document describes the design of a simple CPU with instructions for load, store, add, and jump. It includes: 1. Microcode for the instructions and fetch cycle. Control signals for registers are added to the CPU diagram. Register transfers using the MDR and MAR are described. 2. An expanded CPU design with 8 instructions including load immediate, add register, and branch on carry. Microcode for 3 instructions is provided. Additional registers and control signals are added to the diagram. 3. A memory-reference instruction set is described. Logic circuits and PALASM programs are designed for the register and bus controls. 4. A register-reference instruction set is listed and logic circuits

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78 views3 pages

Sheet 4-1

This document describes the design of a simple CPU with instructions for load, store, add, and jump. It includes: 1. Microcode for the instructions and fetch cycle. Control signals for registers are added to the CPU diagram. Register transfers using the MDR and MAR are described. 2. An expanded CPU design with 8 instructions including load immediate, add register, and branch on carry. Microcode for 3 instructions is provided. Additional registers and control signals are added to the diagram. 3. A memory-reference instruction set is described. Logic circuits and PALASM programs are designed for the register and bus controls. 4. A register-reference instruction set is listed and logic circuits

Uploaded by

Omer Gad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE 204 Microprocessor

Institute of Aviation Engineering & Technology


Second Year First Term
Electronics and Communication Department 2021 / 2022
Sheet #4 Dr. Ibrahim Qamar
Eng. Amr Abdelraheem Tammam
Simple CPU Design
1. The The Figure shown shows a part of a simple CPU with Tri-state internal bus and separate external
memory bus. The CPU has 4 instructions: Load (LD A,XXX) 𝑞0 , Store (ST XXX,A) 𝑞1 , Add (ADD
A,XXX) 𝑞2 , and Jump if A is negative (BRN XXX) 𝑞3 .

R Memory
W
Address Data Bus
Bus
M M A
IR A D A ALU Z
Control Unit
R R
B

Internal CPU Bus


a. Write the microinstructions required for the instructions above and fetch cycle.
b. Add the control signal (e.g. clear Cl, Load L, Enable E, Increment Inc … etc.) required by the
instructions shown in the previous table for each register on the CPU figure.
c. Show on the figure how the registers are connected to the Tri-state Bus.
d. Add any required register not present in the CPU figure and its control signals.
e. Write the register transfers that use MDR and MAR as source or destination showing the control
functions required for these transfer.

2. The Figure shown below shows a part of a simple CPU with single-bus tri-state internal bus and separate
external memory bus. The CPU has 8 instructions and all registers are 16 bits. Three of these instructions
are:
(𝑞0 ) LD A,IMMD : A ← IMMD Load A with Immediate value,
(𝑞1 ) ADD A,R : A← A+R Add Register R to A and store result in A
(𝑞2 ) BRC XXX : if CF = 1 then PC ← XXX Jump to address XXX if Carry Flag =1
a. Write the microinstructions required by the fetch cycle and these 3 instructions.
R
Memory
W
Address Bus Data Bus

A
Control Unit M M
IR R A ALUR PC
A D
R R B
ALU

BUS (Internal CPU Bus)


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b. Add to this figure any register or circuit you need. Show on this figure the direction of the connection
of each register to the bus and the control signal or signals required for each register (for example. LD,
En, Cl, … etc.).
c. What is the maximum memory size of this CPU? ………… KBytes
d. Group the register transfers required by all instructions including fetch cycle showing the control
functions required by each transfer. Name these control signals 𝑥0 , 𝑥1 , …, 𝑥𝑁
e. Connect the control signals 𝑥0 , 𝑥1 , … , 𝑥𝑁 obtained in the previous step to the control signals of the
registers in the above figure (e.g. Cl, LD, En, … etc.).
f. What are the input signals of the Control Unit assume that the instruction decoder is included inside the
control unit.

3. The CPU architecture shown in figure I may execute some memory-reference instructions.
The instruction format used by this CPU consists of three main parts:
- The first is one bit that represent whether the operation
uses direct or indirect addressing mode.
- The second one is three bits long and it represents the
instruction code.
- The third one, that is twelve bits long, represents the memory location address in case of direct
memory addressing.
The instructions to be used are listed below, you are required to:
a. Design all logic circuits for the registers control as well as the bus control as function in the instruction
code and the timing signals. The design is built by ordinary gates.
b. Repeat part (a) using PAL chips PAL16L8 and write the corresponding PALASM programs.
Hexadecimal code
Symbol Description
I=0 I=1

AND 0XXX 8XXX And memory word to AC

ADD 1XXX 9XXX Add memory word to AC

LDA 2XXX AXXX Load memory word to AC

STA 3XXX BXXX Store content of AC in memory

BUN 4XXX CXXX Branch Unconditionally

BSA 5XXX DXXX Branch and save return address

ISZ 6XXX EXXX Increment and skip if zero


4. A second group of instructions named register-reference instructions may be executed by the CPU of
problem (4). Here all bits in the Instruction format are used as an instruction code. The instructions are listed
below.
a. Design all logic circuits for the registers control as well as the bus control as in the instruction code and
the timing signals. The design is built by ordinary gates.

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b. Design the CPU control unit in this case assuming ROM based design

Symbol Hexadecimal code Description


CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and B
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if B is zero
HLT 7001 Halt computer

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