This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2847709, IEEE
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IGBT Open-Circuit Fault Diagnosis in a

Quasi-Z-Source Inverter
Mokhtar Yaghoubi, Javad S.Moghani, Negar Noroozi, Student Member, IEEE, Mohammad
Reza Zolghadri, Senior Member, IEEE

Abstract—In this paper, a fast and practical method is degrading the power quality in the power system. Problems
proposed for open-circuit (OC) fault diagnosis (FD) in a such as abnormal stress on circuit elements can occur after
three-phase quasi-Z-source inverter (q-ZSI). Compared to OCF, causing further damage to the system [7]. As OC faults
the existing fast OC FD techniques in three-phase voltage- are prevalent in power device failures, OC FD is a basic step for
source inverters (VSIs), this method is more cost-effective increasing the reliability of a power system. In non-FT systems,
since no ultra-fast processor or high-speed measurement
is required. Additionally, the method is independent of the
using OC FD techniques prevents extra system damages. In FT
load condition. The proposed method is only applicable to systems, it also results in continuous operation after an OC
Z-source family inverters and is based on observing the fault. Speed, cost, reliability, and independence of the load
effect of shoot-through (SH) intervals on the system condition are the main factors for evaluating an OC FD method.
variables during switching periods. The proposed The approaches for OC FD are either current-based or voltage-
algorithm includes two consecutive stages: OC detection based [9]-[10] and each type has different strategies. Current-
and fault location identification. When both stages of the based methods have been considered widely in the literature
OC FD algorithm are done, a redundant leg is activated and [11]-[16]. In [10], a thorough review of these methods is
utilized instead of the failed leg. The accuracy of the presented. In most of these methods, the measured three-phase
proposed method is confirmed by the experimental results
from a low-voltage q-ZSI prototype.
currents are mathematically analyzed to recognize OCF.
Usually, no extra hardware is required in current-based
Index Terms— Quasi-Z-Source Inverter, Open-Circuit methods, making them cost-effective. Low speed, high
Fault, Fault Diagnosis Algorithm. complexity, limitation for multiple faults detection and
malfunction in small loads are the drawbacks of these
approaches [17]. In Table I, some common OC FD methods are
I. INTRODUCTION compared. Park’s vector approach presented in [18] (with
specification as shown in Table I), is a well-known FD method.
T ensure service continuity and increase the reliability of a
O
distributed generation (DG) power system, fault-tolerant
(FT) structures have been considered widely in recent literature
The main drawback is that the detection algorithm is too
complex to fit in a processor designed for power electronics
application. The normalized DC current method in [19] is based
[1]-[4]. A DG power system includes many parts such as the on Park’s vector approach which is not load-dependent (unlike
storage device, the processor unit, the sensors, the input source Park’s vector method). This method is not efficient when
and the power electronics converter. A failure could occur in closed-loop control is implemented. In the modified normalized
any of these parts. According to the study in [5], semiconductor DC current method, this problem is nearly solved [19]. The
and soldering faults cause approximately 34% of power device slope calculated from 𝑖𝑑 and 𝑖𝑞 samples (the current
failures. However, it is estimated that at least 80% of faults in components of Park’s vector), is used for FD in the slope
the converter part are due to semiconductor failures [6]. method [20], in which FD is load-dependent and rather slow. In
Power switch faults which are typically caused by high the AC current instantaneous frequency method, OCF is
thermal or electrical stress are categorized into two main detected from the calculation of the current space vector
groups: short-circuit (SC) and open-circuit (OC) faults [7]-[8]. frequency [20]. The location of the OCF is not recognized by
An OC fault (OCF) in a power converter could occur through a this FD procedure. In [21] another cost-effective and relatively
switch failure or a driver breakdown. Gate driver breakdown is fast current-based alternative is proposed which is also robust
the main cause of converter failure (53% of the converter faults) to load variation. In this method, the difference between the
and results in permanent IGBT OC [7]. reference and the output current is calculated. But this approach
Unlike an SC fault, which usually triggers the SC protection cannot be used in a system with an open-loop control. A similar
of the system, an OCF can remain undetected for a long time, technique, using the system mathematical model is proposed in
[22] for motor drive application. However, its implementation
Manuscript received Dec 13, 2017; revised Jan 25, 2018 and Apr 02,
is rather complex and demands high mathematical calculations.
2018; accepted May 29, 2018. In addition, extra measurement (phase voltage sensing) is
Mokhtar Yaghoubi and Javad S.Moghani are with the Department of needed for the FD procedure. Another model-based method is
Electrical Engineering of Amirkabir University of Technology, Tehran, presented in [23]. Although it is cost-effective as no extra
Iran (e-mail: [email protected], [email protected]).
Negar Noroozi and Mohammad Reza Zolghadri are with the
hardware is required, the accuracy of the FD is strongly
Department of Electrical engineering of Sharif University of Technology, dependent on the pre-assumed values for the system
Tehran, Iran (e-mail: [email protected], [email protected]). parameters. In practice, the method is inefficient.

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TABLE I
THE COMPARISON OF OC FD METHODS IN THREE-PHASE INVERTERS.
FD Time Load Implementation Extra
Method Required variables
(msec) Dependency complexity Cost
Park’s Vector Method [18] 20 High Medium 3-phase currents No
Normalized DC Current Method [19] 18.4 High Low 3-phase currents No
Modified Normalized DC Current Method [19] 18.4 Low Low 3-phase currents No
Slope Method [20] 38.3 High Low 3-phase currents No
AC Current Instantaneous Frequency Method [20] 20 Medium Low 3-phase currents No
The Reference Current Errors Method [21] 13 Low Low 3-phase currents No
Observer-Based Method [22] 19 Low Medium 3-phase currents/voltages Medium
Actual and Reference Quantity Comparison [24] 5 Low High phase, neutral and pole voltages High
Lower Switches Voltage Observation [8] 2.7 Low Medium lower switches voltage High
Instant Voltage Error [7] 2.5 Low Medium 3-phase currents /voltages Low
Real-Time FPGA-Based [25] 0.01 Low High pole voltages/device delays High
Switching Function Model-Based [26] 0.01-10 Low Medium lower switches voltage Medium

In Table I, the specification of some voltage-based FD portion of semiconductor failures is due to switch OC faults [7].
methods are also depicted. In “actual and reference quantity To cover OC faults at both AC and DC sides of a double-stage
comparison” the fault is recognized by comparing the reference PV converter, two separate FT strategies (for AC and DC
and the measured phase voltage values [24]. The method is stages) are required. FT topologies for DC/DC stage in PV
much faster than current-based methods, but it has a costly systems are presented in [34]-[35]. Due to a single-stage
implementation. Sensing the lower switch voltage is another structure and fewer semiconductor elements in q-ZSI,
fast voltage-based FD strategy [8]. It uses op-amp/flip-flop implementing FT strategies in q-ZSI has lower cost and higher
auxiliary circuits for FD, increasing the complexity of the reliability.
system. In [7], an OC FD is proposed based on three-phase FD is the main step in FT systems. In this paper, a novel
current, phase voltage, and DC link voltage measurements. The voltage-based OC FD technique is proposed for three-phase q-
method is fast but the many variables involved in FD could ZSI. The proposed method is much faster than most of the
make the method sensitive to noise. An ultra-fast FPGA-based approaches shown in Table I. This method is able to recognize
approach is proposed in [25]. It is not possible to implement this OC faults in just a few switching cycles. Despite the fast FD
technique in a usual DSP/microcontroller processor used in method in [25], no high-speed processor or ultra-fast
power electronics applications. The need for high-bandwidth measurement is required. In comparison to the existing
voltage measurement is another drawback of this method, techniques, the proposed method has a simpler implementation.
leading to a cost increase. In addition, the assumption on delays In addition, the CPU of the processor is not involved in the FD
in the response time of the circuit elements is required. This procedure during normal work conditions. To implement the
may affect the accuracy of the FD in practice. In [26] another proposed method, only a low-cost auxiliary circuit (including a
voltage-based method is proposed. It is based on the comparator and a resistive divider) is added to the system.
comparison of the lower switch voltage and the added Therefore, the cost of the system does not change significantly
photocoupler output. This approach is low-cost and fast, but it (unlike most voltage-based approaches [8], [24]-[26]). In
is dependent on the characteristics of the devices which can addition, this method is independent of the load condition since
change by thermal conditions or by aging.
In summary, in comparison to current-based FD methods,
_ VC2
voltage-based methods are much faster and have higher +
immunity to false alarms. However, voltage-based methods C2
iL1 L1 D L2 iL2
usually require additional measurement and extra hardware
leading to higher cost and complexity [24]-[26]. + +
+ SaH SbH ScH
The three-phase q-ZSI shown in Fig. 1, is a beneficial Vin VC1 vleg
structure for DG especially in photovoltaic (PV) applications C1
_ _ _ SaL SbL ScL
[27]-[29]. In addition to the single-stage buck-boost
characteristic, q-ZSI can absorb constant power from the input a b c
source. Compared to the traditional Z-source inverter (ZSI) the Lf Lf Lf
voltage on capacitor 𝐶2 (Fig. 1) is much less than that on 𝐶1 ia ib ic
[30], leading to reduced passive component rating and lower load
manufacturing cost. In [31], modeling and controller design of Z Z Z
q-ZSI is discussed. In [31]-[33], q-ZSI with battery storage for
hybrid PV application is presented.
To have a reliable PV power system, applying FT strategies
to q-ZSI has some advantages compared to the traditional
double-stage PV converters. As mentioned, a significant Fig. 1. Three-phase q-ZSI main topology.

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vleg V3 (010) V2 (110)

SH interval SH interval
VB A2
A3 A1
t θ=ωm t
V4 (011) V1 (100)
non-SH non-SH
interval interval
A4 A6
Fig. 2. The typical waveform across the leg terminals voltage. A5
V5 (001) V6 (101)
Timer counter/PRD Fig. 4. SVM vectors and phase regions [37].
0.5Tsw
0.5Tmax- ScL 𝑣𝑙𝑒𝑔 (depicted in Fig. 1), denotes the voltage across the leg
0.5Tmax+ ScH
SbL terminals. In Fig. 2, the typical waveform of 𝑣𝑙𝑒𝑔 is shown.
0.5Tmid- SbH
0.5Tmid+ During SH mode, 𝑣𝑙𝑒𝑔 is zero, while during non-SH mode, 𝑣𝑙𝑒𝑔
SaL is equal to the sum of the voltages across the input capacitors:
0.5Tmin- SaH
0.5Tmin+ t 0 𝑆𝐻 𝑚𝑜𝑑𝑒
𝑣𝑙𝑒𝑔 = { (1)
𝑣𝐶1 + 𝑣𝐶2 𝑛𝑜𝑛 𝑆𝐻 𝑚𝑜𝑑𝑒
SHa SHb SHc SHc SHb SHa
states: 000 100 110 111 110 100 000 t 𝑣𝐶1 and 𝑣𝐶2 are the voltages across 𝐶1 and 𝐶2 shown in Fig. 1.
As a control strategy in q-ZSI, the peak value of the leg
T0/2 Ta/2 Tb/2 T7 Tb/2 Ta/2 T0/2
terminals voltage (𝑣𝑐1 + 𝑣𝑐2 ) is regulated through SH duration
vleg / VB adjustment, where:
1 𝑣𝐶1 + 𝑣𝐶2 ≈ VB = 𝑉𝑖𝑛 × 𝐵 (2)
t 1
𝐵= (3)
1−2𝐷𝑠ℎ
TSH /6 TSH /6 TSH /6 TSH /6 TSH /6 TSH /6 TSW
B in (2)-(3) denotes the “boost factor” of the q-ZSI and 𝐷𝑠ℎ is
Fig. 3. Scalar implementation of SVM method in q-ZSI [37].
the relative SH state duration in a switching period. 𝑉𝐵 denotes
it is voltage-based. The FD procedure is based on observing the the peak value of the 𝑣𝑙𝑒𝑔 . When the source voltage is dropped,
SH intervals effect on the voltage across the legs (𝑣𝑙𝑒𝑔 in Fig. 𝐷𝑠ℎ is increased and the leg terminals peak voltage is kept
1). Therefore, it is not applicable in the traditional VSIs. In the nearly constant [36].
proposed FD algorithm, the detection of OCF and identifying For the scalar implementation of SVM vectors in a q-ZSI, SH
the failed leg are implemented in two consecutive stages. In the duration is divided into six separate intervals which are located
first stage, the algorithm confirms an OCF. Then the algorithm between the main SVM vectors [37]. In Fig. 3, the arrangement
starts to save the data from the system for a few switching of SH and the main SVM states are shown for 𝐴1 sector. In Fig.
cycles. Finally, by analyzing the data, the failed leg is 4, SVM sectors in αβ plane are depicted [37]. 𝑇𝑎 and 𝑇𝑏 in Fig.
recognized. In [35], using “redundant leg” is described as an 3 are the durations of the first and the second active vectors of
optimized and cost-effective solution for three-phase FT SVM method respectively. 𝑇𝑠ℎ is SH state length; 𝑇0 and 𝑇7
inverters. After identifying the failed leg by the proposed denote the duration of zero state in which the three lower and
algorithm, a redundant leg is replaced with the failed leg. the three upper switches are turned on. The calculation of the
In section II of this paper, the main structure of the three- compare signals values in q-ZSI (shown by 𝑇𝑚𝑖𝑛± , 𝑇𝑚𝑎𝑥± and
phase q-ZSI is reviewed. In section III, OC fault effect on q-ZSI
𝑇𝑚𝑖𝑑± in Fig. 3) is presented in [37]. The filled rectangles in Fig.
is analyzed. The OC FD algorithm is presented in section IV.
To verify the proper operation of the proposed algorithm, the 3 represent SH states; where 𝑆𝐻𝑖 (𝑖 = 𝑎, 𝑏, 𝑐) identifies the
experimental results for a low-voltage prototype are presented short-circuit leg in each SH state. As it is seen, during each SH
in section V. Finally, the conclusion of this paper is presented state only one leg becomes short-circuit. For example, the first
in section VI. SH in Fig. 3 is through leg “a”. The switching states are
symmetric to the center of the switching period.
II. AN INTRODUCTION TO QUASI-Z-SOURCE INVERTER
III. OPEN-CIRCUIT ANALYSIS IN QUASI-Z-SOURCE
q-ZSI shown in Fig.1 has two operating modes [36]:
INVERTER
1) Inverter Mode: In this mode, q-ZSI operates similarly to a
classic voltage source inverter (VSI). In this mode, the In the most probable OC fault case [7], IGBT is only affected
continuous input current flows through the input side diode (𝐷 and its antiparallel diode is sound. This fault is also called
in Fig. 1). “open-gate fault”. In this case, only one polarity of the output
2) Shoot-through Mode: During this mode, the inverter current is conducted by the freewheeling diode or the sound
becomes short-circuit intentionally through any phase legs. The switch of the leg. In Fig. 5(a), the output currents of the inverter
network diode is turned off via the reverse-bias voltage. are shown when the upper switch of leg “a” (𝑆𝑎𝐻 in Fig. 1) is
OC.

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15
10
ia, ib, ic (A)

5
0
-5
-10 ia
-15
0.1 0.15
t (sec)
(a)
15
10
ia, ib, ic (A)

5
0
ia Fig. 7. The leg voltage (normalized by 𝑉𝐵 ) during open-gate fault in
-5
𝑆𝑎𝐻 .
-10
-15
0.1 0.15
in Fig. 6(a)-(b) in the case of OC in a switch and a leg
t(sec) respectively. In both cases, the peak value of the leg terminals
(b) is dropped. 𝑣𝑙𝑒𝑔 during OCF in a switch is shown in Fig. 7. As
Fig. 5. The output currents during OCF in three-phase q-ZSI. (a) shown in Fig. 3 and Fig. 7, in normal work condition, six SH
open-gate fault in 𝑆𝑎𝐻 ; (b) OC in both switches of leg “a” (𝑆𝑎𝐻 and 𝑆𝑎𝐿 ). intervals are visible on 𝑣𝑙𝑒𝑔 during each switching period.
During OCF (in both leg and switch cases), the number of SH
It is also possible that the total leg becomes OC. This fault intervals recognizable from 𝑣𝑙𝑒𝑔 is decreased to four.
may happen by the intervention of the protection system [6]. In
Fig. 5(b), the output currents are shown for the case that both IV. OPEN-CIRCUIT FAULT DIAGNOSIS IN QUASI-Z-SOURCE
switches of leg “a” are OC. INVERTER
After an OCF in a switch, low-frequency harmonics appear
As it is mentioned, all SH states appear as zero-value
in the harmonic content of the qZSI state variables (𝑣𝐶1 , 𝑣C2 ,
intervals on 𝑣𝑙𝑒𝑔 . In this paper, “NFE” is defined as the number
𝑖𝐿1 , and 𝑖𝐿2 ) as well as the output power. The leg voltage peak
value is dropped as the SH state is not implemented by the of falling edges (FE) in 𝑣𝑙𝑒𝑔 waveform during half of the
faulty leg (the boost factor is decreased in practice). For the switching period. It can be said that when all SH states are
simulated q-ZSI, the normalized value of “𝑣𝐶1 + 𝑣𝐶2 ” is shown implemented properly, NFE is three. During OCF, NFE is
reduced to two since the SH state is not implemented by one
1.2
leg.
Assuming normal work condition in an ideal q-ZSI, 𝑡𝐹𝐸𝑖 (𝑖 =
(vC1+ vC2 ) / VB

1.1 OCF
1,2,3) is defined as the falling edge (FE) time at the beginning
1 of its SH state in a switching cycle (shown in Fig. 8). 𝑡𝐹𝐸𝑖 values
are calculated as:
0.9 𝑡𝐹𝐸1 = 0.25(𝑇𝑆𝑤 − 𝑇𝑎 − 𝑇𝑏 − 𝑇𝑠ℎ )
{ 𝑡𝐹𝐸2 = 𝑡𝐹𝐸1 + 𝑇𝑠ℎ /6 + 0.5𝑇𝑎 (4)
0.8 𝑡𝐹𝐸3 = 0.5𝑇𝑠𝑤 − 𝑡𝐹𝐸1 − 𝑇𝑠ℎ /6
0.08 0.1 0.12 0.14 0.16 0.18 0.2
t (sec) 𝜋
𝑇𝑎 /𝑇𝑠𝑤 = 𝑀𝑐 sin (𝑛 − 𝜃)
(a) 3
𝜋
𝑇𝑏 /𝑇𝑠𝑤 = 𝑀𝑐 sin(𝜃 − (𝑛 − 1) ) (5)
1.2 3

OCF { 𝑀𝑐 = √3𝑉𝑟𝑒𝑓 /𝑉𝐵

(vC1+ vC2 ) / VB

1.1
In (5), 𝑉𝑟𝑒𝑓 and 𝜃 are the reference vector amplitude and angle
1 in 𝛼𝛽 plane; “𝑛” is the sector number.
Each FE in Fig. 8 (FE1, FE2, and FE3) is implemented
0.9 through a separate leg. Table II shows the short-circuit leg for
each FE moment along SVM sectors. For example, the second
0.8
0.08 0.1 0.12 0.14 0.16 0.18 0.2
FE (FE2) during the third sector (𝐴3 ) is implemented through
t (sec) leg “c”.
(b) In practice, FE moments in 𝑣𝑙𝑒𝑔 occur with a little delay
Fig. 6. The leg voltage peak value (normalized by 𝑉𝐵 ) (a) open-gate
comparing to 𝑡𝐹𝐸𝑖 values in (4), mainly because of the IGBTs
fault in 𝑆𝑎𝐻 ; (b) OC in both switches of leg “a” (𝑆𝑎𝐻 and 𝑆𝑎𝐿 ).
turning-off delay.

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SH SH SH four capture registers (CAP1... CAP4). By each trigger, the

states: V0 / V7 Va Vb V7 / V0 t timer register can be saved sequentially in these registers.
To detect FE moments, 𝑣𝑙𝑒𝑔 should be digitized first. A
vleg / VB simple circuitry shown in Fig. 9 (a) is proposed for this purpose.
FE1 FE2 FE3
The leg voltage is scaled down by a resistive divider and is
t compared to a constant voltage (𝑉𝑐 ) by a digital comparator. The
0 tFE1 tFE2 tFE3 0.5 Tsw gain of the resistor divider is designed as:
Fig. 8. FE times (𝑡𝐹𝐸𝑖 ) in 𝑣𝑙𝑒𝑔 ; there are three falling edge moments 3
during normal work condition. 𝐾𝑟𝑑 = (6)
𝑉𝐵

TABLE II
Considering (6), the peak value of 𝑣𝑙𝑒𝑔 (≈ 𝑉𝐵 ) is scaled down
THE SHORT-CIRCUIT LEGS IN DIFFERENT SECTORS DURING HALF PERIOD. to 3𝑉 at the comparator input. 𝑉𝑐 is set at 1.5𝑉, covering nearly
half of the IGBT delay during digitalizing 𝑣𝑙𝑒𝑔 . The digital
𝑨𝟏 𝑨𝟐 𝑨𝟑 𝑨𝟒 𝑨𝟓 𝑨𝟔
output from the comparator (𝑣𝑐𝑎𝑝 ) is transferred to the capture
FE1 a c b a c b
unit. The detected FE moments, 𝑡𝑐𝑎𝑝𝑗 (𝑗 = 1,2,3 in normal
FE2 b a c b a c
condition and 𝑗 = 1,2 during OCF) are saved to the capture
FE3 c b a c b a registers (CAPj) as shown in Fig. 10. As mentioned, in practice,
the detected FE moments (𝑡𝑐𝑎𝑝𝑗 ) are not exactly equal to the
calculated times (𝑡𝐹𝐸𝑖 ) because of system delays. A delay
A. Falling edges Detection
margin (𝑡𝑑 ) is considered for each 𝑡𝑐𝑎𝑝𝑗 value to be considered
Most of the microcontrollers and DSPs designed for power as a correct FE detection. 𝑡𝑑 is selected due to the IGBTs typical
electronics applications have a “capture” unit used for motor
turning-off time (𝑡𝑜𝑓𝑓 ). In this paper, 𝑡𝑑 is considered 2𝜇𝑠𝑒𝑐
speed or duty cycle measurement. For example,
TMS320x28xxx family from Texas Instrument processors and which is 2.5 times larger than 𝑡𝑜𝑓𝑓 in the used IGBTs. If the
even lower speed processors like dsPIC30F4011 from difference between 𝑡𝑐𝑎𝑝𝑗 and 𝑡𝐹𝐸𝑖 is less than 2𝜇𝑠𝑒𝑐, 𝐹𝐸𝑖
Microchip contain this unit. The capture unit includes a high- detection is confirmed. In Fig. 10, the filled rectangles shows
bandwidth rising/falling-edge detector. When the edge detector the permitted delay margin.
is triggered, the DSP timer value can be saved to a capture
register. Multiple edges timing could also be retrieved from B. Open-Circuit Fault Diagnosis Algorithm
capture registers. TMS320F2808 used in this paper includes The OC FD algorithm proposed in this paper is based on
examining 𝑣𝑙𝑒𝑔 and its zero-value intervals; the missed zero–
DSP board
resistive divider value interval in 𝑣𝑙𝑒𝑔 identifies the OC leg. Comparing to OC
+
krd .vleg vcap 5v
Start
vleg CAP1
+ 0v CAP2
Vc _ CAP3
_ capture unit first stage NFE is saved
(OCF detection)
Comparator
NFE is less than 3
for three sequential no
Fig. 9. The capture unit interface, including the resistive divider and cycles ?
the comparator. yes
Set PF. NFE, tFEi and tCAPj are
vleg saved for the next 5 cycles.

yes More than two

Set DF (OCF is announced) cycles confirm OC?
t no
tFE1 tFE2 tFE3
vcap
second stage
tei,j values are calculated
t (identifying the failed leg)
tCAP1 tCAP2 tCAP3
DSP timer CAP3 The missed FE is identified.
CAP2
CAP1
t The failed leg is identified
using Table II.

td td td
End
Fig. 10. The timer values sent to capture registers (through to
detection of falling edges in 𝑣𝑙𝑒𝑔 ). Fig. 11. The proposed OC FD algorithm.

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C2 (which could have one or two failed switches), but it is not able
to determine the exact location of the failed switch. Meaning
L1 D L2 that by this algorithm it is not possible to recognize that the
upper, lower or both switches of the leg are failed. Since
replacing the total leg (instead of the failed switch) is introduced
a filter as an optimized FT strategy for three-phase inverters [35], this
Vin C1 b & strategy is used in this paper. Therefore, the determination of
c load the failed switch location is not necessary when the total leg is
redundant leg replaced with another one.

Fig. 12. The three-phase FT q-ZSI structure with a redundant leg.

V. THE EXPERIMENTAL RESULTS
A low-voltage q-ZSI prototype shown in Fig. 13 is
FD algorithms in traditional VSIs, this method has the
implemented. The switching and line frequencies are 20𝑘𝐻𝑧
advantages of being both fast and cost-effective. With this
and 50𝐻𝑧 respectively. The output voltage is 110𝑉 and 𝑉𝐵 is
method, it is possible to detect OCF in a few switching cycles
without the need to use an ultra-fast processor or high-speed 380𝑉. The maximum value of 𝐷𝑠ℎ and the minimum value of
measurement. In addition, the OC FD is independent of the load the input voltage in the prototype are 0.24 and 200V
condition. respectively. A 600V/15A power module (FSBS15CH60) is
In the proposed OC FD algorithm, OCF detection and the used in this prototype. Through adjusting SH state duration, the
failed leg identification are implemented in two consecutive leg voltage peak value (𝑣𝐶1 + 𝑣𝑐2 ) is kept nearly constant (≈
stages. In the first stage, the algorithm confirms an OCF. Then, 𝑉𝐵 = 380𝑉) when the input voltage varies. The PV input source
the CPU starts handling the saved data to identify the failed leg. is modeled with a DC supply voltage. The prototype provides
The NFE is checked for each switching cycle and if it is less 1.2𝑘𝑊 on the AC side. The digital signal processor,
than three for a few cycles, an OCF status is announced by the TMS320F2808, provides PWM and the protection commands.
algorithm. To avoid the effect of noise and disturbance, two The capture unit interface includes a resistive divider, a zener
binary variables are defined for the first stage of the algorithm diode (as a voltage limiter) and an inexpensive comparator
showing the status of “probable fault” and “definite fault” (PF (LM311). Three TRIAC switches are connected to the middle
and DF respectively). By repeating fault detection in three of the main legs and the redundant leg similar to Fig. 12.
sequential cycles, PF is set. Then, the NFE is checked for the As it is mentioned, 𝑣𝑙𝑒𝑔 has a pulsating form and its peak
next five cycles and 𝑡𝐶𝐴𝑃𝑗 and 𝑡𝐹𝐸𝑖 values are saved separately.
value is equal to the sum of the voltages across 𝐶1 and 𝐶2 . In
If the OCF condition is confirmed again (at least in three of the
Fig. 14, 𝑣𝑙𝑒𝑔 is shown. During SH states, 𝑣𝑙𝑒𝑔 is nearly equal to
five cycles), DF is set. In fact, the OCF status is announced by
setting DF. Then the second stage of the algorithm is started. In
Fig. 11 the proposed OC FD algorithm is depicted. The number
of cycles for setting DF and PF is selected based on the required
speed for FD and the reliability of the algorithm. Increasing the
number of investigated cycles results in decreasing the
misdetections and also the speed.
As mentioned, 𝑡𝐹𝐸1 , 𝑡𝐹𝐸2 , and 𝑡𝐹𝐸3 are calculated due to (4)-
(5). During OCF only 𝑡𝐶𝐴𝑃1 and 𝑡𝐶𝐴𝑃2 are retrieved from CAP1
and CAP2 registers. In the second stage of OC FD algorithm,
the difference between 𝑡𝐹𝐸𝑖 and 𝑡𝐶𝐴𝑃𝑗 is calculated as:
𝑡𝑒1,1 = |𝑡𝐶𝐴𝑃1 − 𝑡𝐹𝐸1 |
𝑡𝑒2,1 = |𝑡𝐶𝐴𝑃1 − 𝑡𝐹𝐸2 |
(7) Fig. 13. The designed three-phase q-ZSI prototype.
𝑡𝑒2,2 = |𝑡𝐶𝐴𝑃2 − 𝑡𝐹𝐸2 |
{𝑡𝑒3,2 = |𝑡𝐶𝐴𝑃2 − 𝑡𝐹𝐸3 |
Using Table III and 𝑡𝑒𝑖𝑗 values, the missed FE is identified and
using Table II, the failed leg is recognized.
After FD, the failed leg is disabled and a redundant leg is
added to the inverter circuit through a TRIAC switch as shown
in Fig. 12. The proposed algorithm can detect the failed leg
TABLE III
THE MISSED FE DETECTION FROM THE CALCULATED ERROR
condition the missed FE
𝑡𝑒1,1 > 𝑡𝑑 FE1
𝑡𝑒2,1 > 𝑡𝑑 & 𝑡𝑒2,2 > 𝑡𝑑 FE2
Fig. 14. The voltage across the leg terminals (𝑣𝑙𝑒𝑔 ); the SH states are
𝑡𝑒3,2 > 𝑡𝑑 FE3 detectable by zero-value intervals; the peak value is nearly 380v.

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(a) (a)

(b) (b)

(c) (c)
Fig. 15. The output currents of implemented q-ZSI; (a) during normal Fig. 16. 𝑣𝑐𝑎𝑝 comparing to 𝑣𝑙𝑒𝑔 in the implemented q-ZSI; (a) during
condition; (b) during OC in 𝑆𝑎𝐻 ; (c) during OC in 𝑆𝑎𝐻 and 𝑆𝑎𝐿 . normal condition; (b) during OC in 𝑆𝑎𝐻 ; (c) during OC in 𝑆𝑎𝐻 and 𝑆𝑎𝐿 .

zero.
during OCF is due to the reduction of the real SH duration. The
In Fig. 15(a)-(c), the output currents of the q-ZSI in normal
line-frequency harmonics are also seen after the OCF in Fig.
conditions and during OCF in a switch/leg are shown. In Fig.
17(a)-(b).
15 (a), the RMS value of the output current is equal to 3.5A per
In Fig. 18(a)-(b), DF and PF signals before and after OC fault
phase. In Fig 15(b), the leg “a” only conducts the current with
are depicted. The OC instant is highlighted with a dashed line
negative polarity due to the OCF in 𝑆𝑎𝐻 . The output currents
in Fig. 18(a)-(b). After three cycles from the OC instant, PF is
during OC in both switches of a leg are shown in Fig. 15(c). 𝑆𝑎𝐻
set. A few cycles later, DF is also set. Indeed, setting DF is the
and 𝑆𝑎𝐿 become OC simultaneously. After the fault, the current
declaration of definite OC fault by the algorithm. At this point
of phase “a” is zero.
the algorithm enters the second stage. As an example, the data
𝑣𝑙𝑒𝑔 and 𝑣𝑐𝑎𝑝 (the input of the capture unit) are measured and
shown in Fig. 16(a)-(c) for normal conditions and during OCF TABLE IV
in a switch/leg. Comparing Fig. 16(a) to Fig. 16(b)-(c) shows THE MISSED FE DETECTION FROM THE CALCULATED ERROR
that the number of SH states are reduced during OCF. The CAP1 CAP2 [𝑡𝑒𝑖𝑗 ](usec) Sector
disturbance originated from the OCF is visible on 𝑣𝑙𝑒𝑔 in Fig. Cycle 1 2076 2781 [16.50, 0.85, 6.78, 0.97] 1
16(b)-(c). The peak value of 𝑣𝑐𝑎𝑝 is constant and equals 5𝑉. In Cycle 2 2046 2786 [16.29, 0.85, 7.06, 0.96] 1
Cycle 3 2016 2793 [16.08, 0.84, 7.38, 0.98] 1
Fig. 17(a)-(b), 𝑣𝑙𝑒𝑔 peak value (𝑣𝑐1 + 𝑣𝑐2 ) is depicted during Cycle 4 1989 2780 [15.90, 0.87, 7.52, 0.84] 1
OCF in a switch/leg. The voltage drop across the capacitors Cycle 5 1957 2795 [15.66, 0.85, 7.89, 0.92] 1

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used at the second stage of FD algorithm in the OCF case in Fig. 18(a) are shown in Table IV. 𝑡𝑐𝑎𝑝𝑗 values are calculated

(a) (b)
Fig. 17. The input capacitors voltage (𝑣𝐶1 + 𝑣𝐶2 ); (a) OCF in 𝑆𝑎𝐻 (b) OCF in both 𝑆𝑎𝐻 and 𝑆𝑎𝐿 .

(a) (b)
Fig. 18. PF and DF signals after the OCF (a) OCF in 𝑆𝑎𝐻 (b) OCF in both 𝑆𝑎𝐻 and 𝑆𝑎𝐿 .

(a) (b)

(c) (d)
Fig. 19. The output currents in FT q-ZSI; (a) OCF in 𝑆𝑎𝐻 and replacing the leg “a” in the nominal load; (b) OCF in 𝑆𝑎𝐻 and 𝑆𝑎𝐿 and replacing the
leg “a” in the nominal load; (c) OCF in 𝑆𝑎𝐻 and replacing the leg “a” in 30% of the nominal load; (d) OCF in 𝑆𝑎𝐻 and 𝑆𝑎𝐿 and replacing the leg
“a” in 30% of the nominal load.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2847709, IEEE
Transactions on Industrial Electronics
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constant boost approach for controlling quasi-Z-source-based interlinking Negar Noroozi (S’17) was born in Tabriz,
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With Constant Common-Mode Voltage for Photovoltaic Application," in electrical engineering from Sharif University
IEEE Transactions on Industrial Electronics, vol. 65, no. 6, pp. 4790- of Technology, Tehran, Iran, in 2010. She is
4798, June 2018. currently a Ph.D. candidate at the
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Analysis and Control of Asymmetric Impedance Network-Based Quasi- engineering of Sharif University of
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Quasi-Z-Source Cascade Multilevel Inverter-Based Photovoltaic Power de Grenoble (INPG), Grenoble, France, in
Generation System," in IEEE Transactions on Industrial Electronics, vol. 1997, all in electrical engineering. In 1997 he
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Electronics, vol. 60, no. 10, pp. 4468-4481, Oct. 2013. application of power electronics in energy systems, modeling and
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2014.

Mokhtar Yaghoubi was born in

Kermanshah, Iran, in 1985. He received his
B.S. and M.S. degrees from Sharif University
of Technology, Tehran, Iran, in 2008 and
2011, respectively. He is currently working
toward the Ph.D. degree in Department of
Electrical Engineering at Amirkabir University
of Technology.
His research interests include renewable
energy and design and control of power
electronic converters.

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