Assignment 2
Assignment 2
Instructions:
• The answers and workings must be strictly handwritten on A4 size papers. No electronically
produced, printed, photocopied or scanned version of the answers will be accepted.
The assignment will be graded and will contribute 5% to the final mark for the course.
• Indicate clearly the total number of pages and matriculation number on the first page, and
name and tutorial group on every page of the answer sheets.
• NO late submission is allowed. Zero mark will be given for no or late submission without
valid reasons (MCs, Official Leave, etc.). Students with MC or valid leave on the deadline of
submission have to submit the assignment on the next working day after the MC or official
leave, and contact their respective tutorial group tutors in week 10 to week 12. The original MC
should also be submitted to the EEE undergraduate office within 7 working days after MC for
full-time students, and to Mdm. Yap at S2-B2A-23 for part-time students.
• For full-time students, the completed Homework Assignment 2 must be submitted according
to the following table. Please check your group number, submit your completed assignment to
the lab officers at the corresponding lab as shown in the table below by 10 April 5:00 p.m,
2013 (For example, the students in groups TC01 submit your completed assignments to IC
Design I (S1-B2b-13); the students in groups TA09 submit your completed assignments to VLSI
Lab (S2.1-B3-01), and so on).
• For part-time students, the completed Homework Assignment 2 must be submitted to the
respective tutors during the tutorial session on 10 April, 2013 evening.
Labs Lab Officer Tutorial Professor Students groups
IC Design I (S1- Quek-Gan Siew Kim Asst. Prof. Kim Tae Hyoung TC01, TC02, TC08, TA04,
B2b-13) <[email protected]>; TA05
Hau Wai Ping
<[email protected]>
IC Design I (S1- Seow-Guee Geok Lian Asst. Prof. Arindam Basu/ TC07, TC09, TA01, TA07,
B2b-10) <[email protected]>; Asst. Prof. Chen Shoushun TA08, TA11, TA12
Goh Mia Yong Jimmy
<[email protected]>
Integrated Leong-Tung Wang Why Asst. Prof. Arindam Basu/ TC05, TC06, TC10, TC11,
System <[email protected]>; Asst. Prof. Chen Shoushun TA02, TA03, TA06
Research (S1- Kang Meng Fai
B2a-04) <[email protected]>
VLSI Lab (S2.1- Sia Liang Poo Assoc. Prof. Tan Cher Ming/ TC03, TC04, TA09,
B3-01) <[email protected]>; Asst. Prof. Chen Shoushun TA010
Seow Yong Hing
<[email protected]>
Question
The figure below shows a bipolar current mirror where the current through the resistor is denoted
as Iref and the two transistors, Q1 and Q2 have emitter areas of AE1 and AE2 respectively. Both
transistors have the same Early voltage VA and same current gain β. The power supply, Vdd =
10V and assume VBE = 0.7V.
1. For each of the five cases mentioned below, find both the mirror ratio MR = Iout/Iref and the
ratio of the collector currents IC1/IC2 (i.e. there should be 5x2=10 answers).
3. If you assume VA=∞ (i.e. no Early effect) and β=50, what is the largest mirror ratio you can
obtain from this circuit by increasing the ratio of emitter areas (AE2/AE1) ?
Figure 1