IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-11, NO.

6, DECEMBER 1976 795

,Dynamic Element Matching for High-Accuracy

Monolithic WA Converters
RUDY J. VAN DE PLASSCHE

Abstract–A novel way to obtain a very high accuracy in the bit

weighting required for monolithic di@al-to-analog (D/A) converters
will be deseribed. The new method combines passive division using
snatched elements with a time ditision concept, needs no trimming,
and is insensitive to element aging. A 12-bit monolithic D/A network
with internal referenee sources, built as a test circuit, demonstrates the
versatility of this new technique.
(a)
INTRODUCTION

M
ONOLITHIC
attention
D/A converters have received considerable
due to the rapidly
processing and microprocessor markets.
expanding
Although
digital signal &_@&
RM.e width
there are numerous approaches to obtain a high-performance
(b)
D/A converter, circuit design has settled down around the
R-2R ladder network to obtain the required precision in Fig. 1. (a) Binary weighted currents using an R -2R ladder network.
(b) Pulsewidth modulation D/A converter.
binary weighting of current sources. Here the designer makes
use of the excellent matching characteristics and thermal track-
ing of integrated components. The accuracy of the converter
is determined by the matching of the R-2R resistors and of the
current source transistors. Using no trimming techniques, a
TABLE I
10-bit D/A converter can be designed having ~ LSB linearity

m
COMPARISON OF THREE DIFFERENT RESISTOR FABRICATION PROCESSES
but circuit yield in production is troublesome. Laser trimming
techniques are therefore used to improve yield.
Converters based on time division, such as pulsewidth modu-
lators, for example, require no trimming and have a high
accuracy. The main disadvantage of these converters is the low
conversion speed due to the high degree of filtering required
The matching characteristics of the R-2R resistors in the
to reduce the ripple on the output signal. To break through
ladder network and of the base-emitter voltages of transistors
the barrier of 10-bit accuracy to achieve 12-, 14-, or in the
T1, Tz, and T3 determine the overall accuracy of the converter.
near future, even 16-bit accuracy in a monolithic form, a new
Three different resistor fabrication techniques are available
design procedure is required. A proposal will be described
to the designer as shown in Table I [2]. The data in the
here which basically combines passive division using matched
column giving the standard deviation for resistors with a line-
elements with a time division method [1]. This method
width of 10 Mm and 40 Mm show that 10-bit converters with
allows high accuracy without trimming in a standard IC ~ LSB linearity can be fabricated although production yield
process. A 12-bit D/A network built as a test circuit will be will be low. A simplified form of a pulsewidth modulator
described to demonstrate the versatility of this new technique.
D/A converter is shown in Fig. 1(b). In the digital circuitry a
function is performed giving an output voltage equal to V,.f
STANDARD MONOLITHIC CIRCUIT APPROACHES
for a time Tx which is proportional to the digital input signals
A circuit diagram of the three most significant bits of an
a. to an and zero for the remaining time of the period T- The
R-2R ladder network D/A converter is shown in Fig. 1(a).
low-pass filter averages the pulsewidth-modulated signal result-
The conversion takes place by summing the collector currents
ing in the output voltage Vout = (Tx/ T). I/ref. A high degree
of T1, T2, and T3 through the digitally controlled switches of filtering is required to reduce the ripple on the output
S1, S2, and S3. The binary weighting of the currents through
voltage below the required level. The low overall speed of
T1, T2, and T3 requires a scaling of the emitter geometries
these converter types is a big disadvantage.
resulting in equal base–emitter voltages of these transistors.
NEW DIVIDER CIRCUIT

Manuscript received May 11, 1976; revised July 30, 1976. This paper The basic scheme of the new divider circuit is shown in
was presented at the International Solid-State Circuits Conference, Fig. 2(a). It consists of a passive current divider and a set of
Philadelphia, PA, February 1976.
switches driven by the clock generator ~. The total current
The author is with the Philips Research Laboratories, Eindhoven,
The Netherkmds. 21 is divided by the passive current divider into two nearly
 IEEE JOURNAL OF SOLID-STATE CIRCUITS, DECEMBER 1976

214
L

(a)
v.
t t,=t+dt
+’E $’E
Clcck n
t, t~ ts –At
I
1
I

4+
+t t~-t, = t +21

Fig. 3. Practical current divider stage.

(b)
Fig. 2. (a) New current divider schematic diagram. (b) Time dependence
of various currents in the new divider.

equal parts: 11 = I + AZ and 12 = I – AI. The currents II and

12 are now interchanged for equal time intervals with respect
to the output terminals 3 and 4. At the output terminals cur-
rents will then flow whereby the average values are exactly
equal and have a dc value equal to 1. Fig. 2(b) shows the cur-
rents as a function of time. A small ripple current 2AI of a
(a)
frequency ~ is present on the output currents too. This ripple
is a measure for the matching performance of the passive ‘“1’~z””
divide-by-two stage. With a simple low-pass filter this small
ripple current can be suppressed below the required value and
an exact 1 to 2 current ratio is obtained without using any
accurate element. If the time intervals during which the cur-
rents 11 and 12 are interchanged differ by a value A t [see Fig. 4. (a) Binary weighted current network using different switching
Fig. 2(b)], there is an error in the 1 to 2 division equal to frequencies. (b) Time dependence of currents flowing in the first and
second divider stage.
A13,4 At AI
.—. —
1~,4 t I
stages (T3 to TIO ) interchange the currents 11 and 12 for equal
The total error is the product of two small errors, resulting in a time intervals between the output terminals 3 and 4. The rd-
very high overall accuracy. It is not difficult in practice to ready discussed improvement in division accuracy with respect
make At/t <0.1 percent and AI/I ~ 5 percent, so an overall to the current mirror is now found. In practice the base cur-
accuracy better than 5 X 10-5 can easily be obtained using rents of the Darlington switches limit the division accuracy.
this division stage. The value of the ripple can be reduced by The mdy criterion determining the overall accuracy for the
optimizing the matching characteristics of the passive divide- whole circuit is a high current gain (e g., 62> 104) for the
by-two stage. This reduction of the ripple allows the use of a switching transistors. This is not such a big problem while, if
simple low-pass filter net work consisting of only one RC necessary, a special high current gain process for the transistor
network. fabrication can be used. The value of the ripple depends on
Generally speaking: dynamic element matching can be used the matching characteristics of the current mirror transistors
advantageously in those cases where a network consists of or T1 and T2. This matching can be improved by inserting emit-
can be divided into a number of nearly equal elements. An ter degeneration resistors across which a voltage drop of about
improvement in overall accuracy can be obtained by a continu- $ to ~ V is needed for an optimum matching performance. Ac-
ous and cyclic interchange of these nearly equal elements. cording to Table I a matching better than 0.5 percent for the
The average value of the output signals is a few orders of currents 11 and Iz can be obtained with a reasonable circuit
magnitude more accurate then the accuracy of the basic yield. This results in a ripple current <0.5 percent 1. No ac-
network. curate elements are used and aging of elements has no influence
on the overall accuracy.
PRACTICAL DIVIDER CIRCUIT

The practical divider circuit is shown in Fig. 3. The current BINARY WEIGHTED CURRENT NETWORK

mirror T1, Tz performs the passive division of the total current A binary weighted current network is formed by cascading
21 into two nearly equal parts. Two Darlington differential current-division elements [see Fig. 4(a)]. In the first divider
VAN DE PLASSCHE: DYNAMIC ELEMENT MATCHING 797

stage a combination with a reference current source l,~f and a I/i I/& 1/2 I

current amplifier A o is used as an accurate current mirror. 4JJ4

This mirror circuit will be described later. To avoid interac- f l+b~
JI,#=I
tions between the individual divider stages the switching fre- 1/2
quencies are halved for every following divider stage. In f l+A.2
Fig. 4(b) the output currents of the first two stages are shown
1/2 !%
as a function of time. That no interaction occurs can be ex- + I*
plained as follows. The current 1* shows the inaccuracy Al of f l+A,

the first divider stage [upper diagram of Fig. 4(b)]. In the out- 1/2

put current 1/2 of the second divider stage we can distinguish %

the error L& with the frequency f/2 and the error A ~ of the (a)
first stage with a frequency f [lower diagram of Fig. 4(b)].
I*= Ir@f(l+A@
During a half-period of the f/2 clock the average value of the
I!. *~+A1.A2t(A1 +A2).~]
Current 1/2 does not contain an error term originating from
the first divider stage of frequency f. This means that over the l/&=Z@~-A1
AZ.+AIA,-A,A,+(A, -A2+A3) .$]

total period of the f/2 clock no interactions from the first (b)
divider stage are found. An independent operation of the Fig. 5. (a) Binary weighted current network with equal switching
frequency. (b) Error analysisresults.
stages is thus indeed obtained.
The disadvantages of halving the switching frequencies are
found to be a large increase of the digital circuitry for the
generation of the different clock signals and a more difficult i’;”
Io”~ 1+ ,3J+
suppression of ripple due to the reduction in frequency. An- 1
jh T,g
other solution with switches operating at the same frequency
is therefore used. T!l
T5 % T9 To

fnn
CUF:RENT NETWORK WITH ONE SWITCHING FREQUENCY T3 T4 T’ {1: c

.4* rC, ~ ‘~: ;

A binary weighted current network with every individual
T TZ
divider stage operating at the same frequency f is shown in RC RE
Fig. 5, Now the interactions between individual stages must be {
taken into account. For the error in the first divider stage we (a)

may take the same result as obtained in the calculations in _——

With Glp. C : T&= l,”
L.t= Ii.
Fig. 2. This will be proved in the next section, Wittout COP.C: l.l = I,g(l +A)
Beciiuse the time errors are the same for all the divider O-t,:
Iwt=
Iin(l +A)
t,.tz:lO~= &=lin(l-4+A2) if A-d
stages they can be separated from the stage errors. The error
zisO.5%with Rc+T& ~ -$<<10-’
term of the second stage (1/2) can then be calculated with:
0- tl = t + At and tz - tl = t - At. The average value for the (b)
output current 1/2 becomes Fig. 6. (a) Accurate current mirror. (b) Error analysisresults.

lref(l + AI); (l +Az)(t + At) +Ir.f(l - Al)~(l - AN- At)

I/2 = ‘3+

~L

which results in an error term equal to: A1A2 + (Al + A2) “ this error is found proportional to the bit weight (lr.f/fV).
(At/t). Now the frequency of the error ripple is the same for all the
[f the error terms of the individual stages are made small output currents and (can be chosen high to simplify the filter-
(Al-,, <0.5 percent), then the influence of the interactions ing. A small RC low-pass filter can be incorporated in every
between the individual divider stages on the overall accuracy of switched output terminal, An identical behavior for the new
the D/A network can be kept very low. If averaging capacitors circuit and a very well-trimmed ladder network D/A converter
are applied between subsequent current dividers all Ai Ai errors is then found.
due to interaction would be removed.
In Fig. 5(b) the result of the calculations for the first three ACCURATE CURRENT MIRROR

most important bits is shown. Although an increase of error A detailed circuit diagram of the accurate current mirror is
terms is found with a rising number of the divider stage (e.g., shown in Fig. 6. The basic current mirror consists of the cur-
the I/4 error term is -A1A2 + A1A3 - A2A3) this increase can rent sources T, and Tz with the Darlington stage Tlz T13 to
be tolerated because in the overall performance a reduction of form the feedback loop. The Darlington differential stages
798 IEEE JOURNAL OF SOLID-STATE CIRCUITS, DECEMBER 1976

TABLE 11 through T1 and T2 can be calculated, resulting in

ERROR TERMS OF 3-Brr D/A CONVERTER

The temperature coefficient of the current 11, with tempera-

1 -A, A2+Aj A3 –A2A2+ 1–A, A2+A1A3 –A2A3+ VZA?+
ture-independent resistors, can be calculated, yielding (1/11) “
-
I 1 1 (aZ1 /aT) = 1/T. Now resistor Rz is inserted. The current
through Rz is determined by the base-emitter voltage VBE, of
transistor Tz so that Iz = VBE, /R2. The temperature coeffi-
cient of the current Iz can be estimated resulting in

and, with

(V8 equals bandgap voltage of silicon).

The output current Z,ef is equal to the sum of 12 + 2Zl = I,ef.
Fig. 7. Schematic diagram of the current reference source.
The temperature coefficient can be adjusted to zero at room
temperature by choosing suitable values for R 1 and Rz. The
T3 to TIO interchange for equal time intervals the currents temperature relation is based on the same principle as in the
lCI and lCZ with respect to the summing point at the base of well-known bandgap voltage sources [3], [4]. Solving the
T13. Two cases can now be distinguished. temperature equations for the reference source, an indepen-
1) An averaging capacitor C is connected between the base dent equation for the resistor R2 can be found. With
terminal of T13 and the negative supply. The average value of i31reJi3T = O at T = TO we obtain
ICI and lCZ being ~q is then made equal to lin. Now because
the average value Tout is equal to 14 as was shown earlier Vg+ ~(n-1)
(Fig. 2), the complete circuit results in an accurate current R2 =
mirror 10Ut = li~. I,ef
2) The capacitor C is deleted. During the first half-period with
of the clock the current Iez is then made equal to lin resulting
with an error A between the transistors T1 and Tz in an output
current loUt = lin (1 + A). In the second half clock period lC1 and
and ICZ are interchanged so now lin = ICI which results in an
output current lout = lin/ 1 + A. If A is made small (A<< 1) Vg = 1.205 V.
then this division can be approximated by a finite expansion With a desired value for I,ef at T = TO the value of R2 can be
resulting in: loUt ~ lin (1 - A + A2 ). After averaging over the
calculated. This value is used in the implicit equation for 11
whole clock period we obtain 10Ut ~ fin (1 + &A2 ). With
giving
A ~ 0.5 percent the error term can be kept very small
(c= 10-5 ). Table II summarizes the results of the error calcula- kTO
211 + — In Z = I,.f.
tions for a 3-bit network incorporating an accurate current qR * 102
mirror. Without the capacitor C a slight decrease in overall
Here ioz is the base-emitter diode reverse current of transistor
accuracy is found.
T2 at T = TO. Then R I can be calculated from
CURRENT REFERENCE SOURCE kTO
R1=— in p.
An important part of a D/A converter is the reference qI1
source. Because the whole converter operates with currents
a current source was taken as a reference source. The simpli- These equations are derived from a simplified model for the
fied circuit diagram is shown in Fig. 7. If the resistor Rz is reference source.
deleted, the circuit behaves like a simple current stabilizer.
PRACTICAL DIAGRAM OF THE REFERENCE
The operation of the circuit is as follows. The resistors R with
CURRENT SOURCE
the operational amplifier A ~ permit equal collector currents to
flow through transistors T1 and Tz. Transistor T1 has a p The circuit diagram of the practical reference source is shown
times larger emitter area than transistor T2. A stable operation in Fig. 8. The operational amplifier consists of a differential
of the circuit will give a voltage drop across resistor R 1 in ac- stage T3, Td with a p-n-p current mirror (T5, T6, T7 ) as an
cordance with this difference in emitter area. Now the current active load and a Darlington stage T8, T9 as an output ampli-
VAN DE PLASSCHE: DYNAMIC ELEMENT MATCHING 799

rtiFF-+vB
WI
r---L--L

Fig. 8. Practical circuit diagram of the reference source.

1/64 1/32
1.000
Iwf,
t~
mA
0

. .. . . I
M
R.=ofl

CIS99L7 I I

Fig. 9. Temperature measurements on the reference source.

fier. In this circuit an additional resistor RC is inserted which

consists of a buried base resistor to compensate for the Fig. 10. Schematic diagram of complete 12-bit D/A converter.

second-order term in the temperature equation. With an ex-

tended model and inserting temperature data for the resistor
RC, an optimum value at I,ef = 1 mA for RC of 170 L? with

““”’+%i!bl
~1 = 160$2 and Rz = 1237 Q is found. (Rl and Rz ate off-
chip resistors). This optimum for RC is rather flat so varia-
tions d.o not have a large influence on the overall temperature
response. Temperature measurements are shown in Fig. 9.
Without the compensation resistor RC the well-known para-
bolic relation with temperature is found, resulting in a tem-
perature coefficient of 4 ppm/°C over AT= 80°C. With the
resistor RC inserted into the -circuit, an improvement of about
a factor of 10 is obtained giving a TC of 0.5 ppm/°C over
AT= 80°C.
At high temperatures (above 80”C) the substrate leakage
currents of the transistors can no longer be ignored so an in-
crease in the temperature coefficient is found.

‘l’L
h I

RE
SCHEMATIC DIAGRAM OF 12-BIT CURRENT NETWORK ‘P-

A schematic diagram of the complete 12-bit current network Fig. 11. Detailed circuit diagram of the three most significant bits.
is shown in Fig. 10. A 5-bit high-accuracy divider with a refer-
ence source ~ref can be distinguished. Furthermore a 7 -bit
less-accurate divider consisting of 4 bits using switched dividers plied after the digital input controlled bit current switching is
and 3 bits using a passive division also with a reference source performed and therefcme not shown in Fig. 10.
I,ef cc~mpletes the 12-bit network. Because both reference An emitter-coupled multivibrator generates the clock fre-
current sources are equal, an additional current divider to set quency required for the dynamic matching procedure. A de- ‘“-
the proper current relationship between the stages for the tailed circuit diagram of the three most significant bits and the
first 5 and last 7 bits is required. This current divider is ap- reference source is shown in Fig. 11. Additional bonding pads
 800 IEEE JOURNAL OF SOLID-STATE CIRCUITS, DECEMBER 1976

Fig. 12. Photomierograph of the test chip.

TABLE 111 ponents. The high accuracy obtained in the test circuit shows
P~RFOR~ANC~ CHARACTERISTICS OF THE MONOLITIiIC
12-BIT D~A TEST CHIP
promise that an increase in the number of bits will be possible.
D/A NETWORKDATA
Using a special process combining MOS with bipolar transis-
Resolution : 12 bit tors, a 16-bit monolithic converter appears to be on the
Accuracy : S1/L L.S.B. or 5.n+
(I,nmtity) horizon in the near future.
output currmt : 7.rnA
TernP. Coeff. of output 5 pp.~ ACKNOWLEDGMENT
c“ ,,,”+ :
Voltcg, Coeff. of output 1 rmdv The author wishes to thank D. Goedhart for breadboarding
current :

Chip size : 2.5x 2.5mrn

and measuring the circuits and A. Schmitz for the processing
TnMax. clcck frea. fcf mn kn. of the circuit.

=LcJ REFERENCES
[1] K. B. Klaassen, “Digitally controlled absolute voltage division,”
allow filtering of the ripple currents per bit with Cext if needed. IEEE Trans. Instrum. Mess.. VOL 24. June 1975.
High-speed applications are therefore possible too. In low- [2] G. Kelson, H. H. Stellrechtj and D. “S. Perloff, “A monolithic10-b
digital-to-analog converter using ion implantation,” IEEE J. Solid-
speed applications filtering at tlhe output summing amplifier State Circuits, vol. SC-8, Dec. 1973.
can be used, requiring only one capacitor. The voltage drop [3] K. E. Kuyk, “A precision reference voltage source,” IEEE J.
across the reference current soumce is stabilized by the Zener Solid-State Circuits, vol. SC-8, June 1973.
[4] A. P. Brokaw, ZSSCC Dig. Tech. Papers, pp. 188,189, Feb. 1974.
diode Dz. In this way the sensitivity of the reference current
to supply variations [(1 /lref) (t) Zref/i3VB) s 10-4/V], already
low, is further improved. A photornicrograph of the test chip
is shown in Fig, 12. Table III gives the restilts of measurements Rudy J. van de Plassche was born in IJzendijke,
on these test chips. The Netherlands, on September 24, 1941. He
received the Ir. degree from the University of
Technology, Delft, The Netherlands, in 1964.
CONCLUSION In 1965 he joined the N. V. Philips Research
The dynamic element matching method gives a simple, Laboratories, Eindhoven, The Netherlands,
where he was engaged in circuit design for in-
strumentation and control. Since 1967 he has
been involved with research in circuit design for
linear integrated circuits.