Introduction to Microprocessors

Chapter 1 - 8086 Software Model

Dr. Adnan Ismail Al-Sulaifanie

Department of Electrical and Computer Engineering

University of Duhok, Iraq

2021 - 2022

Outline

• Introduction to Microcomputer & Microprocessor.

• 8086 Microprocessor: definition and internal architecture.

• 8086 registers.

• Logical address versus physical address.

• 8086 instruction cycle

References

1. Brey, The Intel Microprocessors, Brey, chapters 1 & 2.

2. Bhurchandi, Advanced microprocessors and peripherals, chapter 1

3. Triebel, The 8088 and 8086 Microprocessors, , chapters 1 & 2.

4. Mazidi, 80X86 IBM PC and Compatible Computers Assembly Language, Design, and
Interfacing, chapter 1.

5. Rafiquzzaman, Fundamentals of Digital Logic and Microcomputer Design , chapter 9.

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1 Computers

• A computer is an information processor that is able to perform substantial computations

with little or no intervention of human.

• A computer consists of two parts:

1. Hardware: refers to all physical and mechanical components that forming the com-
puter, such as CPU, memory, display, etc.
2. Software: A computer program is a collection of instructions that performs a specific
task when executed by a computer. There are two type of software: system software
and application software.

1.1 Computer Hardware: Von Numman Architecture

1.2 Computer Components

The basic architecture of a digital computer is based on Von Neumann model. It Consists of four
parts:

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 • Microprocessor is integrated circuit device that can be programmed with a series of in-
structions to perform specified functions on data.

• Main memory: is a storage unit used to store program and data.

• Input/Output devices: input devices are used to transfer data between the user and
the computer, such as keyboard and mouse. Output device converts data of the computer
into a form that the human can understand or use. For example, screen and printer.

• System bus: is a common group of wires that interconnect components to transfer infor-
mation between them. There are three type of buses:

1. Address bus: is uni-directional and used to carry address from the CPU to different
parts of computer system.
2. Data bus: is bi-directional bus, carries data between different parts.
3. Control bus: special type type of bus which coordinate the operation of computer
components.

2 Processor-Memory Interface

• Each processor has n bit address bus, it can access 2n memory locations.

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 • The number of address bus defines the maximum memory size that can be connected to
the processor.

n Memory size
8 256 byte A0 − A7
16 64 K byte A0 − A15
32 4 G byte A0 − A31

• The number of data lines defines how much data can be transferred in each memory access.

m Data size
8 one byte D0 − D7
16 two byte (word) D0 − D15
32 four byte (double word) D0 − A31
64 eight byte (quad word) D0 − A63

• The size of registers inside processor is equal to the size of data bus (m)

3 Microprocessors

• A Microprocessor is a multipurpose programmable logic device which reads the binary in-
structions from memory. Also, it accepts binary data as input and process data according
to the instructions and gives the results as output.

• It understand and execute a limited number of instructions (instruction set).

• Instruction set are different for each microprocessor.

• The 8086 microprocessor represents the foundation upon which all the 80x86 family of
processors have been built.

• It has 20 bit address bus (1 M byte memory) and 16 bit data bus (can transfer 2 byte in
each memory access).

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3.1 8086 Internal Architecture

8086 is divided internally into two independent units:

• Bus Interface Unit: Interfaces the microprocessor to external memory and I/O devices.

• Execution Unit: executes instructions already fetched by the BIU.

Bus Interface Unit (BIU)

• BIU is responsible for communicating with the outside of microprocessor.

• It has three functions: reads (fetches) instructions, reads operands, and writes results.

• BIU consists of instruction queue, instruction pointer, segment registers, special adder, and
control unit.

• The instruction queue uses 6 bytes FIFO (first-in-first-out) memory. It is used to speed up
program execution.

• Instruction pointer is used to index next instruction to be fetched.

• The control unit generates all control signals necessary for read/write operations, such as
MRDC, MWTC, IORC, and IOWC.

• Special adder is used to generate the required address to access memory.

• Memory bus cycle (read/write):

1. BIU generates the required address and send it to the memory through address bus.

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 2. BIU generate the required control signals

Read (MRDC) ==> the processor reads data from memory location that indexed by
the address.

Write (MWTC) ==> the processor send data to the memory to be stored in specified
location indexed by the address.

Execution Unit (EU)

• EU consists of: Arithmetic Logic Unit (ALU) and many registers with different functionality.

• ALU is a digital circuit which performs arithmetic and logic operations on two m-bit digital
numbers. The value of m can be 4, 8, 16, 32, or 64 bits (16 bit in 8086).

• The size of the ALU defines the size of the computer. For example, a 32-bit computer
contains a 32-bit ALU.

3.2 Parallel Processing: Pipeline

• In 8085, the EU and BIU are combined in single unit, and the execution cycle is performed
in sequence.

• 8086 architecture employs parallel processing i.e., both the units (BIU and EU) work at the
same time.

• This type of design is called a pipeline. It speeds up program execution up to three times
when compared with non-pipeline architecture.

Nonpipelined 8085
fetch1 exe1 fetch2 exe2 fetch3 exe3 ....

Pipelined 8086
fetch1 fetch2 fetch3 fetch4 fetch5 fetch6 ....
wait exe1 exe2 exe3 exe4 exe5 ....

4 8086 Registers

• Data registers

• Index registers

• Base registers

• Instruction pointer

• Segment registers

• Flag register

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Data Registers

• Registers: AX, BX, CX, and DX.

• They also called general purpose registers.

• Each register is 16 bit and can be separated into two 8 bit register (for example AH and
AL).

• These registers are used for arithmetic, logic, and transfer operations.

• Each register has a specific functions associated with particular instructions.

Index and Pointer Registers

• Index registers ====> SI and DI

• Pointer registers ====> Sp and Bp

• These registers used as pointer to memory locations.

• Data segment (DS) is the default register used to generate physical address with SI and
DI. Sometimes ES is used instead.

• Stack segment (SS) is the default register used to generate physical address with Sp and
Bp.

Instruction Pointer (IP)

• IP register stores the address of next instruction to be fetched from memory.

• Each time instruction is fetch from memory, IP content will be added so that it always refer
to the next instruction.

• If branch instruction is exuted, the IP content will be loaded with new value which is the
branch address.

• The physical address is generated using CS:IP

Flag Register

Flag register is 16 bit register and contains 9 active flags. They are divided into two groups:

1. Status flags ==> six flags are updated after executing the instruction

2. Control flags ==> are set by the processor or programmer for different purposes.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O D I T S Z A P C

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 • Status flags
Carry flag (C): hold carry out from the most significant bit in any arithmetic operation
(addition or subtraction).

Auxiliary flag (A): holds carry out from b3 to b4 in any arithmetic operation.

Zero flag (Z): is set to one when any arithmetic or logic operation yields zero result.

Sign flag (S): acquire the value of most significant bit of the result in any arithmetic or
logic operation.

Overflow flag (O): it set if the size of the result exceeds the capacity of the destination
location. is set to ’1’ when the carry in and carry out from the most significant bit are
different.

Parity flag (P): is set to ’1’ when the number of 1s in lower byte of the result is even.

Example Determine the content of flag register after adding BA10 + 9F58

5 Memory Segmentation in 8086

• Memory segmentation divides the main memory (1 MB) into 16 segments of 64 KB each.

• Each memory location can be accessed through two addresses: base address (segment)
and offset address (SEG:OFFSET).

• Segment register holds the starting address of the segment.

• The offset address (also called effective address) refers to the displacement from the be-
ginning of the segment.

• There are four segments can be active at any given time (CS, DS, ES, SS).

• Segment size can range from 1 byte to 64 KB.

• The segmentation is useful in time shared system when several users share a microproces-
sor.

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6 Logical Versus Physical Address

• Physical Address is 20 Bits address that is actually put on the address bus of 8086/8088.
The range of the physical address is 00000H to FFFFFH

• The BIU has four 16-bit segment registers: CS, DS, SS, and ES.

• Since the segment register is 16 bit, it can only access first 64 KB of memory. Therefore it
is multiplied by 16 to access entire 1 MB memory.

• Offset address is a location within a 64 KB segment range. It has a range 0000H to FFFFH

• A dedicated adder is used to produce 20-bit address.

Physical address PA = CS * 10h + IP

CS = 2500h, IP = 95F3h ====> PA = 25000 + 95F3 = 2E5F3h

• Logical address consists of a segment starting address and offset value CS:IP, SS:BP, SS:
SP, DS: BX, DS:DI and DS:SI

• Physical Address Calculation:

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7 Instruction Cycle

• Executing an instruction requires three phases: fetch, decode, and execute.

• Fetch cycle:

1. Calculate physical address of next instruction.

2. Read instruction from memory.
3. Store fetched instruction in instruction queue.
4. Update instruction pointer.

• Decode cycle:

1. Translate operand addresses.

2. Fetch operand from memory/register.

• Execution cycle:

1. Perform required operation.

2. Updated flags register.
3. Store result in memory/register.

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