Analog Interfacing Overview

➢ Analog and Digital signals

➢ Analog Interfacing

➢ MKL25Z Analog Modules:

1) Analog to Digital (ADC)

Features
Setup
Example Application
2) Digital to Analog (DAC)
Features
Setup
Example Application
3) Analog Comparator
Features
Setup
Example Application
 Analog Signals and Embedded Systems
▪ Embedded systems often need to measure values of physical parameters
▪ These parameters are usually continuous (analog) and not in a digital form which computers
can process
• Temperature • Pressure
– Thermometer (do you have a fever?) – Blood pressure monitor
– Thermostat for building, fridge, freezer – Altimeter
– Car engine controller – Car engine controller
– Chemical reaction monitor – Scuba dive computer
– Safety (e.g. microprocessor processor thermal – Tsunami detector
management) • Acceleration
• Light (or infrared or ultraviolet) intensity – Air bag controller
– Digital camera
– Vehicle stability
– IR remote control receiver
– Tanning bed
– Video game remote
– UV monitor • Mechanical strain
• Rotary position • Other
– Wind gauge – Touch screen controller
– Knobs – EKG, EEG
– Breathalyzer

2
 Analog & Digital Signals
Q: Why converting signals to digital form?

A: Signals in practice are analog. Digital computers made it possible to apply

sophisticated numerical algorithms in many fields like automatic control
and signal processing that was not possible by analog electronics.

Analog signal x(t):

A function of time t. Defined for all real t.

Discrete-time signal x(n):

Defined only for discrete time instants t = nT, n integer:

x(n) = x(nT), T is the constant sampling period.

Digital signal xd(n):

When x(n) takes only discrete values, i.e. quantized because of the finite
number of digits used, the signal is called digital signal.
Continuous/Discrete-time & Digital Signals
1.25
Discrete
1 Digital
Continuous
0.75

0.5

0.25

-0.25

-0.5

-0.75

-1

-1.25
0 1 2 3 4 5 6 7 8 9 10
k
 Microcontrollers in Control

A digital controller performs the control action through three steps:

1. Sample the system variable(s), usually the output(s), through ATD.

2. Process the measured sample(s) and compute the required control

action according to the built-in control algorithm based on the given
system model and control specifications.

3. Output the control action to the system actuator(s) through DTA.

 ATD/DTA Conversion
Analog Value: Determines the range of operation 𝑉𝐻
Range: 𝑉𝐿 → 𝑉𝐻
Polarity: 𝑉𝐿& 𝑉𝐻 same sign ⎯→ Unipolar
different signs → Bipolar Δ
Digital Value:
Number of bits: 𝑛
Number of levels: 𝑁 = 2𝑛
If bipolar: 2’s complement or sign & magnitude
𝑉𝐿
Resolution ∆:
𝑉𝐻 − 𝑉𝐿 Range
The ability to differentiate between very close values. Δ= 𝑛 =
2 −1 𝑁−1
Measured as: As the resolution is defined relative to the range:
• ATD: The smallest sensed change in the analog Δ
, resolution is defined as the number of
input reflected as a change of ±1 of the output Range
binary value bits used 𝑛.

• DTA: The change in the analog output

corresponding to a change of ±1 of the input binary
value
 ATD Converter
Analog reference
voltages V VL
H
Start
SC Conversion
End of
𝑽+
𝑰𝑵 EOC
Conversion

Analog B0
input
𝑽−
𝑰𝑵
ATD .
. Digital
. output
➢ The SC signal triggers
the conversion Bn-1
process.
➢ When conversion is
Clock
complete, the EOC is
asserted to indicate
that the digital
output is ready.
 DTA Converter
Analog reference voltages
VH VL

Write

8 8

6
B0 6

4
VOUT

Internal Latch
4

0
0 1 2 3 4
k
5 6 7 8 9
DTA .
.
2

0
0 2 4
k
6 8 10

Analog Digital
output . input

Bn-1
Every Write pulse stores
the new binary input
value to the DTA latch,
so its output is held
constant until the next
Write pulse; Zero-Order-
Hold ZOH.
 ATD Conversion Example

Analog input voltage value:

If the digital value from the ATD is D, then its analog input is:

𝑉𝐻 − 𝑉𝐿
𝑉𝐼𝑁 = 𝑉𝐿 + × 𝐷 = 𝑉𝐿 + Δ × 𝐷
2𝑛 − 1
If 𝑉𝐿 is zero, then 𝑉𝐼𝑁 = Δ × 𝐷.

Example:
A 12-bit A/D converter with reference voltages 𝑉𝐿 = 0.5𝑉 and 𝑉𝐻 = 3.5𝑉, what
is the corresponding input voltage for digital value 100?

Solution:
3
𝑉𝐼𝑁 = 0.5 + 12 × 100 = 0.573𝑉
2 −1
 Signal Conditioning Circuit
In many practical cases the sensor output voltage range V1→V2 is different
from the range of the ATD VL→VH , so we need a circuit to translate the sensors
output range to fit that of the ATD to make use of the full dynamic range of the
ATD.
This is the signal conditioning circuit.
In some cases, the sensor’s output comes in the form of a current or charge
so we need to convert it to voltage:

Signal translation formula in general contains gain and bias:

If the signal conditioning circuit input from sensor is 𝑉𝐼𝑁 in the range 𝑉1 → 𝑉2 ,
and its corresponding output is 𝑉𝑜𝑢𝑡 in the range 𝑉𝐿 → 𝑉𝐻 ,
the translation formula should be:
𝑉𝐻 − 𝑉𝐿
𝑉𝑜𝑢𝑡 = 𝑉𝐿 + × (𝑉𝐼𝑁 − 𝑉1 ) = 𝐴𝑉𝐼𝑁 − 𝐴𝑉1 − 𝑉𝐿
𝑉2 − 𝑉1
ATD Range 𝑉𝐻 − 𝑉𝐿
The amplifier gain is: 𝐴 = =
Sensor′s Range 𝑉2 − 𝑉1
and the bias is: 𝐵 = 𝐴𝑉1 − 𝑉𝐿
Signal Conditioning: Amplification & Bias
25
Sensor output
After amplification
After bias
20

15
Volts

10

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Sensed Variable
The Big Picture – A Depth Gauge
V_ref // Your software
Analog to ADC_Code = ADC0->R[0];
Pressure
Digital V_sensor = ADC_code*V_ref/1023;
Sensor
Converter Pressure_kPa = 250 * (V_sensor/V_supply+0.04);
Depth_ft = 33 * (Pressure_kPa – Atmos_Press_kPa)/101.3;
Water
Pressure Voltages ADC
V_sensor ADC_Code V_ref
Output Codes
111..111
111..110
111..101
111..100

V_sensor ADC_Code

000..001
Ground 000..000

1. Sensor detects water pressure and generates a

proportional output voltage V_sensor
2. ADC generates a proportional digital integer (code) based
on V_sensor and V_ref
3. Code can convert that integer to a something more useful
a. first a float representing the voltage,
b. then another float representing pressure,
c. finally another float representing depth
12
What if the Reference Voltage is not known?
▪ Example - running off an unregulated battery (to save power) → 𝑉𝑟𝑒𝑓 is unknown
▪ Measure a known voltage and an unknown voltage

𝑛𝑢𝑛𝑘𝑛𝑜𝑤𝑛
𝑉𝑢𝑛𝑘𝑛𝑜𝑤𝑛 = 𝑉𝑘𝑛𝑜𝑤𝑛
𝑛𝑘𝑛𝑜𝑤𝑛

▪ Many MCUs include an internal fixed voltage source which ADC can measure for this purpose
Can also solve for 𝑉𝑟𝑒𝑓

2𝑁
𝑉𝑟𝑒𝑓 = 𝑉𝑘𝑛𝑜𝑤𝑛
𝑛
My ADC tells me that channel 27 returns a code of 0x6543, so I
can calculate that:
216
𝑉𝑟𝑒𝑓 = 1.0𝑉
0x6543
13
Inputs to ADC

▪ Differential
▪ Use two channels, and compute difference between them
▪ Very good noise immunity
▪ Some sensors offer differential outputs (e.g. Wheatstone Bridge)

▪ Multiplexing
▪ Typically share a single ADC among multiple inputs
▪ Need to select an input, allow time to settle before sampling

▪ Signal Conditioning
▪ Amplify and filter input signal
▪ Protect against out-of-range inputs with clamping diodes

14
 Sample and Hold Devices
Sampling
switch
Output
Signal
Analog Input
Hold
Signal Capacitor

▪ Some A/D converters require the input analog signal to be held constant during
conversion (e.g. successive approximation devices)
▪ In other cases, peak capture or sampling at a specific point in time requires a sampling
device.
▪ A “sample and hold” circuit performs this operation
▪ Many A/D converters include a sample and hold circuit

15
 KL25 ANALOG INTERFACING
PERIPHERALS

16
 MKL25Z Analog Modules

1) One Analog to Digital Converter: ADC0

2) One Digital to Analog Converter: DAC0

3) One Analog Comparator: CMP0

Other microcontrollers from the same family may have:

Two DTA converters; DAC0 and DAC1,

Two ATD converters ADC0 and ADC1, etc

KL25Z Analog Interface Pins

▪ 80-pin QFP
▪ Inputs
▪ 1 16-bit ADC with 14
input channels
▪ 1 comparator with 6
external inputs, one 6-
bit DAC
▪ Output
▪ 1 12-bit DAC

18
Freedom KL25Z Analog I/O

Inputs
14 external ADC channels
6 external comparator channels
Output
1 12-bit DAC

19
Using a Pin for Analog Input or Output
Data Bus Address

▪ Configuration
bit n Bus

▪ Direction Address
Decoder

▪ MUX PDDR select

Port Data
D Direction
▪ Data
Q
Register
Freescale: is the pin
mux location in this
▪ Output (different ways to PDOR select diagram accurate?

access it) PSOR select

PCOR select
Set
Rst Port Data
▪ Input PTOR select
Tgl Output
Pin or
Pad on
D Register Q package

I/O Clock
PDIR select
Port Data Pin Control
D Input Q Register
Register MUX field

20
 Pin Control Register to Select MUX Channel

MUX (bits 10-8) Configuration

000 Digital circuits disabled, analog enabled
▪ MUX field of PCR defines connections 001 Alternative 1 – GPIO
010 Alternative 2
011 Alternative 3
100 Alternative 4
101 Alternative 5
110 Alternative 6
Example: 111 Alternative 7
Configure pin PTC7 for alternative 0; analog functionality:
PORTC->PCR[7] &= ~PORT_PCR_MUX_MASK;
PORTC->PCR[7] |= PORT_PCR_MUX(0);
21
MKL25Z ADC
 MKL25Z ADC

Topic Outlines:

➢ Features

➢ Block diagram & memory map

➢ Initialization & Configuration

➢ Operation

➢ Example application
 MKL25Z ADC
Features
Software selectable Features:
➢ Multiple resolution: 8 to 16 bits using successive approximation.

➢ Reference voltages, VREFSH and VREFSL connected to one of two pairs:

1. External: VREFH and VREFL, or
2. Internal (sometimes external): VALTH (Analog supply 𝑉DDA = 3.3𝑉) and VALTL (Analog ground 𝑉SSA = 0𝑉)
➢ Single-ended or differential analog inputs.
Up to four differential and 24 single-ended input channels selectable by amplifier plus-input multiplexer and
minus-input multiplexer. The number of channels depends on the pinout of the package.
– Output in right-justified unsigned format for single-ended.
– Output format in 2's complement 16-bit sign extended for differential inputs.
 MKL25Z ADC
Features

➢ Software-or-hardware trigger:
– Hardware (SC2[ADTRG=1]): Caused by a timer, the analog comparator, or external pin signal.
– Software (SC2[ADTRG=0]): Conversion is initiated following a write to SC1A.

➢ End of Conversion (EOC):

− Conversion complete flag and interrupt
− Hardware average complete flag and interrupt (if hardware average is used)

➢ Additional features:
• Compare logic can discard results within (or outside) a specified range.
• Configurable sample-and-hold time, and conversion speed/power.
• A hardware average function enabled by SC3[AVGE=1], compare function enabled by SC2[ACFE]=1.

The ADC should be calibrated by the calibration instructions in Calibration Function in the manual.
MKL25Z ADC
Block Diagram

Trigger Control

Clock Selection

Result registers

Input Multiplexers

Vref Selection

Compare Function

Calibration Function

Averaging Function

Result Formatting
 MKL25Z ADC
Memory Map
The ADC module occupies 27 memory words, 13 of them are listed in the partial
list below. The unlisted 14 are used by the calibration function.
Partial Memory Map:
Using the ADC

▪ ADC initialization
▪ Configure clock
▪ Select voltage reference
▪ Select trigger source
▪ Select input channel
▪ Select other parameters

▪ Trigger conversion

▪ Read results

28
 MKL25Z ADC
Functional Description: Configuration
The ADC can be used with the default configuration settings, or in case these settings are not
satisfactory, they can be changed by program via the proper configuration and control registers.
Configuration Parameter Default Options
Input clock source and Bus clock Bus clock/2, ALTCLK, ADACK
divide ratio used for ADCK. Divide ratio is 1 2, 4, 8
Single-input or Differential Single ended Differential

Trigger Select Software Hardware

Resolution 8-bit SE and 9-bit Differential 12/13, 10/11, 16/16

Continuous Conversion Disabled Enabled

VREFSH & VREFSL Select External VREFH and VREFL Alternate VALTH and VALTL (Internal/External)

Sample Time Short Long (for high impedance inputs)

20/12/6/2 extra ADCK cycles.
Interrupt Disabled Enabled

DMA Disabled Enabled

Power Mode Normal power mode Low power mode

Hardware Average Disabled Enabled

Hardware Compare Disabled Enabled

 MKL25Z ADC
Functional Description: Initialization
Gate the clock to the ADC Module: Set SCGC6[ADC0] = 1

SIM->SCGC6 |= SIM->SCGC6_ADC0_MASK

Note: You may find the following definition line in the MCU header file:
#define SIM_SCGC6_ADC0_MASK 0x08000000u

System Clock Gating Control Register 6 (SIM_SCGC6)

 MKL25Z ADC
Functional Description: Operation

➢ The ADC module is disabled:

▪ After reset
▪ In Low-Power Stop mode
▪ When SC1n[ADCH] are all high

Starting a conversion
➢ A conversion is initiated by one of the following ways:
1) Software SC2[ADTRG]=0: By a write to SC1A.
2) Hardware SC2[ADTRG]=1: By ADHWT event, and a hardware trigger select event, ADHWTSn’s occurred.
3) The transfer of the result to the data registers when continuous conversion is enabled, SC3[ADCO]=1.

(The analog input channel is selected by SC1n[ADCH] ≠ 11111)

 MKL25Z ADC
Functional Description: Operation

Reading the result

➢ When the conversion is completed:(or the average of multiple samples, SC3[AVGE]=1, is ready)

– The result is placed in the ADCx_Rn data result register.

– The respective conversion complete flag SC1n[COCO] is set.

❖ An interrupt is generated if ADC respective interrupt is enabled by SC1n[AIEN] = 1.

– The code reads the result from the ADCx_Rn data result register.

➢ The 16-bit result is right-justified.

For conversion formats shorter than 16 bits, the upper unused bits need to be filled with:
– All zeros (unsigned format) in single-ended conversions.

– Two’s complement (sign extend) format in differential conversions.

 MKL25Z ADC
Functional Description: Conversion Trigger Sources
1. Software: Selected by setting SC2[ADTRG]=0
Conversion is triggered by writing to register SC1A. Analog channel is selected by
SC1n[ADCH]

2. Hardware: Selected by setting SC2[ADTRG]=1

Conversion is triggered by a signal indicating an event from a hardware source.
These events include timer signals, comparator output, and an external trigger.
The trigger source is selected by SIM_SOPT7[ADC0TRGSEL].
ADC0TRGSEL Trigger selected for ADC0
0000 External trigger pin input
0001 HSCMP0 (comparator) output
0100 PIT (timer) trigger 0
0101 PIT (timer) trigger 1
1000 TPM0 (timer) overflow
1001 TPM1 (timer) overflow
1010 TPM2 (timer) overflow
1100 RTC (real-time clock) alarm
1101 RTC (real-time clock) seconds
1110 LPTMR0 (timer) trigger
other Reserved
 MKL25Z ADC
Functional Description: Clocking
The conversion clock signal ADCK determines how quickly the ADC samples and then
converts input data.
Slower sampling gives more accurate results.

Depending on the ADC’s configuration

– a sample can take from 4 to 26 ADCK cycles, and
– a conversion can take from 20 to 71 ADCK clock cycles.
The ADCK signal frequency must be:
• between 1 and 18 MHz when the ADC is operating with the resolution of up to 13 bits, or
• between 2 and 12 MHz for higher resolutions.
There are four possible inputs to the conversion clock, selected with ADCx_CFG1[ADICLK]:
1. The bus clock (24 MHz)
ADIV Clock division
2. The bus clock divided by two factor
3. ADACK (a local clock that can keep running 00 1
when the rest of the CPU is stopped) 01 2
4. ALTCLK (an alternate clock source) 10 4
11 8
The input clock is divided by a factor specified by
ADCx_CFG1[ADIV].
 MKL25Z ADC
Configuration & Operation Example
Example: SC1A = 0x41 (%01000001)
Configure the ADC module with: Bit 7 COCO 0 Set when a conversion completes.
Bit 6 AIEN 0 Conversion complete interrupt disabled.
1) Input on channel 1
Bit 5 DIFF 0 Single-ended conversion selected.
2) Single-ended 10-bit conversion Bit 4:0 ADCH 00001 Input channel 1 selected.

SC2 = 0x00 (%00000000)

3) Use software trigger
Bit 7 ADACT 0 Flag indicates a conversion is in progress.
Bit 6 ADTRG 0 Software trigger selected.
4) Use low-power with a long sample time
Bit 5 ACFE 0 Compare function disabled.

5) Don’t use interrupts Bit 4 ACFGT 0 Not used in this example.

Bit 3 ACREN 0 Compare range disabled.
6) Don’t use DMA Bit 2 DMAEN 0 Default DMA request disabled.
Bit 1:0 REFSEL 00 Default voltage reference pin pair
(External VREFH and VREFL).
7) ADCK is derived from the bus clock divided by 1
 MKL25Z ADC
Configuration & Operation Example
Example: (continued)
Configure the ADC module with :

1) Input on channel 1

2) Single-ended 10-bit conversion CFG1 = 0x98 (%10011000)

Bit 7 ADLPC 1 Low power, lowers maximum clock speed

3) Use software trigger Bit 6:5 ADIV 00 ADCK = the input clock ÷ 1
Bit 4 ADLSMP 1 Long sample time
4) Use low-power with a long sample time Bit 3:2 MODE 10 Single-ended 10-bit/differential 11-bit result
Bit 1:0 ADICLK 00 Bus clock
5) Don’t use interrupts

6) Don’t use DMA

7) ADCK is derived from the bus clock divided by 1

 MKL25Z ADC
Configuration & Operation Example

SC1A = 0x41 (%01000001)

Bit 7 COCO 0 Set when a conversion completes.
Bit 6 AIEN 0 Conversion complete interrupt disabled.
Bit 5 DIFF 0 Single-ended conversion selected.
Bit 4:0 ADCH 00001 Input channel 1 selected.

RA = 0xxx
Holds results of conversion.
 MKL25Z ADC
Functional Description: Input Connections
➢ The MCU family data sheet provides information on connections between ADC
channels and MCU pins, whereas
➢ the FREEDOM-KL25Z manual explains how MCU pins are connected to the board’s
header connectors.
ADC channel MCU signal (with ALT0 Freedom KL25Z
(single-ended) multiplexer setting) connector and pin
number
0 PTE20 J10 1
3 PTE22 J10 5
4 PTE21 (a), PTB29 (b) J10 3 (a), J10 9 (b)
5 PTD1 (b) J2 12 (b)
6 PTD5 (b) J2 4 (b)
7 PTE23 (a), PTD6 (b) J10 7 (a), J2 17(b)
8 PTB0 J10 2
9 PTB1 J10 4
11 PTC2 J10 10
12 PTB2 J10 6
13 PTB3 J10 8
14 PTC0 J1 3
15 PTC1 J10 12
23 PTE30 J10 11
 MKL25Z ADC
Example Application: Hot Plate Sensor (Sensor Characteristic)
The temperature of the hotplate is measured using a thermistor whose resistance varies
with temperature. One type of thermistor (called negative temperature coefficient, or
NTC) has a resistance that falls with increasing temperature as shown:

The NTC resistance at 25°C is 33 kΩ. The manufacturer provides this information in the
device’s data sheet. We can create a voltage divider with an NTC thermistor and a fixed
resistor. The output voltage VTemp will depend on the temperature as shown:
 MKL25Z ADC
Example Application: Hot Plate Sensor (Linearization)

We need to linearization the sensor’s input-output characteristic in order to get its output
proportional to the input if the sensor is nonlinear.

Linearization can be done either by:

• A lookup table … Consumes memory space
or
• A linearizing formula … Consumes execution time

The linearizing formula for the given temperature sensor is obtained by curve fitting as:

𝑇
= − 1.1309010−25 𝑛2 + 2.3265610−20 𝑛2 − 1.846310−15 𝑛2
+ 7.1864110−11 𝑛2 − 1.4321610−6 𝑛2 + 0.01555762𝑛 − 36.9861
 MKL25Z ADC
Example Application: Hot Plate Sensor
Initialization:
Assume connecting VTemp to pin one of connector J10, which will send the signal through
PTE20 to ADC channel 0:

0x00
// Enable clock to ADC0 Module
// Enable clock to Port E Module
 MKL25Z ADC
Example Application: Hot Plate Sensor
Operation:
The code to read the ADC and calculate the temperature:
➢ The code starts a conversion on channel 0 and uses polling to determine when the
conversion is complete.
➢ Then it reads the ADC result and calculates the temperature using a polynomial
approximation. The equation given is reorganized to reduce the complexity and
speed execution.
0x00
MKL25Z DAC
 MKL25Z DAC
Features
➢ Digital input 12 bits.
➢ Selectable Reference voltage:
– 𝑉+𝑅𝑒𝑓 can be connected to either DACREF_1 (VREFH) or DAC_REF2 (VDDA).
– The lower reference voltage is connected to ground.
➢ Selectable software or hardware conversion trigger
𝑉+𝑅𝑒𝑓
➢ Analog output range to 𝑉+𝑅𝑒𝑓 :
4096
𝑛+1
Transfer Function: 𝑉𝑜𝑢𝑡 = 4096 𝑉+𝑅𝑒𝑓 (Note: an offset of 1 is added to 𝑛 !)
➢ An amplifier buffers the voltage output signal.

➢ The analog output of the DAC is available:

1. on an external pin (PTE30)
2. as an input to the analog comparator and the ADC.

➢ Data for the DAC (12 bits) is written to the DACDAT register:
– The data’s upper four bits are written to DACx_DAT0H.
– The lower byte is written to DACx_DAT0L … x is the DAC number 0 or 1.
➢ DMA support
 MKL25Z DAC
Block Diagram

▪ Load DACDAT with 12-bit

data 𝑁 𝑉+𝑅𝑒𝑓 Select

▪ MUX selects a node from

resistor divider network to
create
𝑉𝑜 = (𝑁 + 1) ∗ 𝑉𝑖𝑛/212
▪ 𝑉𝑜 is buffered by output Analog Output
amplifier to create 𝑉𝑜𝑢𝑡
▪ 𝑉𝑜
=
𝑉𝑜𝑢𝑡 but 𝑉𝑜 is high
impedance - can’t drive
much of a load, so need to
buffer it Digital Input
 MKL25Z DAC
Memory Map

➢ Four 8-bit DATA registers: DAC0_DATxL and DAC0_DATxH, x=0,1

➢ One 8-bit STATUS register: DAC0_SR
➢ Three 8-bit CONTROL registers: DAC0_Cx, x=0,1,2

STATUS
 MKL25Z DAC
Functional Description: Initialization
The following DAC initialization steps are made before it can be used:

1. Gate the clock to the DAC module:

DAC0 Clock Gate Control (bit31 in the SIM_SCGC6 register) controls the clock
gate to the DAC0 module:
0 Clock disabled
1 Clock enabled

2. In case the analog output should be made available at an MCU pin: (PTE30)
– Enable clock to PORTE module:
Port E Clock Gate Control (bit13 in the SIM_SCGC5 register) controls the clock gate
to the Port E module.
0 Clock disabled
1 Clock enabled
– Connect the DAC output to pin PTE30:
Set the MUX field (bit8-bit10) in the pin control register PCR 30 of PORTE
(PORTE_PCR30) to the binary value 000.

After initialization, the DAC should be enabled and configured by selecting parameters
such as 𝑉+𝑅𝑒𝑓 , buffer mode, and power level mode via the proper control registers.
DAC Operating Modes

▪ Normal
▪ DAT0 is converted to voltage immediately

▪ Buffered
▪ Data to output is stored in 16-word buffer
▪ Next data item is sent to DAC when a selectable trigger event occurs
◦ Software Trigger - write to DACSWTRG field in DACx_C0
◦ Hardware Trigger - from PIT timer peripheral
▪ Normal Mode
◦ Circular buffer
▪ One-time Scan Mode
◦ Pointer advances until reaching upper limit of buffer, then stops
▪ Status flags in DACx_SR

57
 MKL25Z DAC
Functional Description: Configuration

➢ The DAC should be enabled by setting DACEN=1 in DACx_C0 register.

➢ After being enabled, the DAC can be used with the default configuration settings,
or in case these settings are not satisfactory, they can be changed via the DAC
control registers.

Configuration Default Options

Parameter

DAC input source DAC Data register DACDAT[11:0] DAC data buffer

Reference Voltage 𝑉+𝑅𝑒𝑓 to DACREF_1 = 𝑉DDA 𝑉+𝑅𝑒𝑓 to DACREF_2 (External VREFH)

Trigger Source Hardware Software

Power Leve High-power mode Low-power mode

Interrupt Enable No interrupts Interrupts on buffer pointer limits

DMA Enable No DMA DMA enabled

 MKL25Z DAC
Control Register DACx_C0

It controls various aspects of the DAC.

There are other control registers, DACx_C1 and DACx_C2 that enable other operation modes using DMA.

DAC control register 0, DACx_C0

➢ DACEN: DAC Enabled ➢ LPEN: DAC Low Power Control
0 High-Power mode
0 The DAC system is disabled.
1 Low-Power mode
1 The DAC system is enabled.
➢ DACBTIEN: DAC Buffer Read
➢ DACRFS: DAC 𝑉+𝑅𝑒𝑓 Select
Pointer Top Flag Interrupt Enable
0 connect 𝑉+𝑅𝑒𝑓 to DACREF_1 (𝑉DDA ).
0 DAC buffer read pointer top flag
1 connect 𝑉+𝑅𝑒𝑓 to DACREF_2 (External interrupt is disabled.
VREFH). 1 DAC buffer read pointer top flag
➢ DACTRGSEL: DAC Trigger Select interrupt is enabled.
0 DAC hardware trigger is selected. ➢ DACBBIEN: DAC Buffer Read
1 DAC software trigger is selected.
Pointer Bottom Flag Interrupt
➢ DACSWTRG: DAC Software Trigger Enable
If DAC software trigger is selected and 0 DAC buffer read pointer bottom flag
buffer is enabled, writing 1 to this field interrupt is disabled.
advances the buffer read pointer once. 1 DAC buffer read pointer bottom flag
0 DAC soft trigger is not valid. interrupt is enabled.
1 DAC soft trigger is valid.
 MKL25Z DAC
Example: Waveform Generator
Example: Waveform Generator

▪ Supply clock to DAC0 module

▪ Bit 31 of SIM SCGC6
▪ Set Pin Mux to Analog (0)
▪ Enable DAC
▪ Configure DAC
▪ Reference voltage
▪ Low power mode?
▪ Normal mode (not buffered)
▪ Write to DAC data register

63
 MKL25Z DAC
Example: Waveform Generator

Function Init_DAC to initialize and configure DAC:

 MKL25Z DAC
Example: Waveform Generator
Function Triangle_Output sweeps the DAC output voltage up and down repeatedly.
Two macros (DAC_DATL_DATA0 and DAC_DATH_DATA1, defined in MKL25Z4.H) are used to
format the output data for the upper and lower output data registers.
We still need to shift the data to the right by eight positions to position the upper four bits
correctly for the macro.