Practical Test 20 %: School of Computer Science Degree Programme

SCHOOL OF COMPUTER SCIENCE
DEGREE PROGRAMME
PRACTICAL TEST 20 %
JAN 2023 SEMESTER

MODULE NAME : COMPUTER ARCHITECTURE AND ORGANIZATION
MODULE CODE : IT
PRESENTAION DATE :
SUBMISSION DATE : 31 MARCH,2023.
ACTION : Submission of Practical Test Paper (Group)
GROUP MEMBER’S NAME :

Sagar Budhathoki
Sajan Amatya
Pratik Chaudhary
Sanjeev Magar
Avinab K.C
Part 1/2
Part A
a)
A B X
0 0 0
0 1 1
1 0 1
1 1 0
A’B+AB’ This gives (A XOR B)
b)
A B X
0 0 0
0 1 0
1 0 0
1 1 1
AB This gives (A AND B)
c)
A B X
0 0 1
0 1 1
1 0 1
1 1 0
A’B’ + A’ B + AB’ This gives ( A NAND B)
d)
A B X
0 0 0
0 1 1
1 0 1
1 1 0
A’B + AB’ This gives A XOR B
PART B:
Demonstrating in Tinkercad :
Fig: XOR Gate

Fig: AND Gate
Fig: NAND Gate

Fig: XOR Gate
PART C
a)
Truth table :
A B C X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Circuit diagram:
Figure 1: Part C (a)
b)
Truth table:
A B C X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
Circuit diagram:
Half Adder gate 2/2

Part A :
Circuit Diagram :
The truth table of half adder is:
Expected outcome Actual outcome

A B
Sum Carry Sum Carry
0 0 0 0 0 0
0 1 1 0 1 0
1 0 1 0 1 0
1 1 0 1 0 1
Part C
1. What is the use of Half adder?

A half adder is a kind of adder, an electronic circuit that plays out the expansion
of numbers. A half adder is utilized to add two single-digit parallel numbers and
results into a two-digit yield. It is named as such in light of the fact that assembling
two half adders with the utilization of an OR entryway brings about a full adder. All
in all, it just accomplishes a portion of crafted by a full adder.
The adder works by joining the tasks of essential rationale entryways, with the
easiest structure utilizing just a XOR and an AND door. This can likewise be changed
over into a circuit that just has AND, OR and NOT entryways. This is particularly
valuable since these three easier rationale door ICs (coordinated circuits) are more
normal and accessible than the XOR IC, however this could bring about a greater
circuit since three unique chips are utilized rather than only one.
1. What are the limitations of Half adder?

The limitations of Half adder are.
• Cannot handle multiple bits: A half adder can only add two single binary
digits together. It cannot handle multiple bits or numbers.
• Can produce an incorrect output for some inputs: If both inputs to the half
adder are 1, the output of the sum bit will be 0, and the carry bit will be 1.
This is an incorrect output because the sum of two 1s should be 10 in binary
notation.
• Cannot handle carry-in: A half adder does not have a carry-in input. It can
only produce a carry-out bit if both inputs are 1.
• A half-adder cannot perform subtraction: it can only perform addition. It

cannot perform subtraction without additional circuitry.
• Limited scope: A half adder is a very basic and fundamental building block
for digital circuits. While it is essential for designing more complex circuits,
it has limited functionality on its own.
2. In the output of half adder, what can be observed?

The output of a half adder comprises of two bits: a sum bit (S) and a carry bit
(C).
The sum bit addresses the result of adding the two information bits, disregarding
any carry from a past option. The sum spot can have a worth of one or the other
0 or 1.
On other hand, the carry bit addresses the carry that results from adding the two
information bits. The carry spot can have a worth of one or the other 0 or 1. In
the event that both info bits are 1, the carry touch will be 1, showing that a carry
will be required for the following expansion.
In summary, the output of a half adder gives data about the result of adding two
single parallel digits, and whether a carry will be required for the following
option.
3. How many AND gate required to make a Half adder?

To make a half adder only 1 AND gate is required. Though 2 logic gates are
required to make a half adder the other one is XOR gate.
4. What is the use of a Full adder?

A digital circuit that performs addition is called a full adder. Two binary values and a
carry or overflow bit are required by a full adder. An additional carry bit and a total are
the outputs. Hardware XOR, AND, and OR gates are used to build full adders. To add bits
to any number of bits, such as 32 or 64 bits, full adders are frequently coupled to one
another. A full adder is really two half adders joined by an OR gate, an XOR gate, and an
AND gate.

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SCHOOL OF COMPUTER SCIENCE

JAN 2023 SEMESTER

GROUP MEMBER’S NAME :

A’B + AB’ This gives A XOR B

Fig: XOR Gate

Fig: NAND Gate

Half Adder gate 2/2

Expected outcome Actual outcome

1. What is the use of Half adder?

1. What are the limitations of Half adder?

• A half-adder cannot perform subtraction: it can only perform addition. It

2. In the output of half adder, what can be observed?

3. How many AND gate required to make a Half adder?

4. What is the use of a Full adder?

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